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Added emscripten (emcc) support to build system and some build fixes
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int() const
96 {
97 int ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 return ret;
102 }
103
104 std::string RTLIL::Const::as_string() const
105 {
106 std::string ret;
107 for (size_t i = bits.size(); i > 0; i--)
108 switch (bits[i-1]) {
109 case S0: ret += "0"; break;
110 case S1: ret += "1"; break;
111 case Sx: ret += "x"; break;
112 case Sz: ret += "z"; break;
113 case Sa: ret += "-"; break;
114 case Sm: ret += "m"; break;
115 }
116 return ret;
117 }
118
119 std::string RTLIL::Const::decode_string() const
120 {
121 std::string string;
122 std::vector <char> string_chars;
123 for (int i = 0; i < int (bits.size()); i += 8) {
124 char ch = 0;
125 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
126 if (bits[i + j] == RTLIL::State::S1)
127 ch |= 1 << j;
128 if (ch != 0)
129 string_chars.push_back(ch);
130 }
131 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
132 string += string_chars[i];
133 return string;
134 }
135
136 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
137 {
138 if (full_selection)
139 return true;
140 if (selected_modules.count(mod_name) > 0)
141 return true;
142 if (selected_members.count(mod_name) > 0)
143 return true;
144 return false;
145 }
146
147 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
148 {
149 if (full_selection)
150 return true;
151 if (selected_modules.count(mod_name) > 0)
152 return true;
153 return false;
154 }
155
156 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
157 {
158 if (full_selection)
159 return true;
160 if (selected_modules.count(mod_name) > 0)
161 return true;
162 if (selected_members.count(mod_name) > 0)
163 if (selected_members.at(mod_name).count(memb_name) > 0)
164 return true;
165 return false;
166 }
167
168 void RTLIL::Selection::optimize(RTLIL::Design *design)
169 {
170 if (full_selection) {
171 selected_modules.clear();
172 selected_members.clear();
173 return;
174 }
175
176 std::vector<RTLIL::IdString> del_list, add_list;
177
178 del_list.clear();
179 for (auto mod_name : selected_modules) {
180 if (design->modules_.count(mod_name) == 0)
181 del_list.push_back(mod_name);
182 selected_members.erase(mod_name);
183 }
184 for (auto mod_name : del_list)
185 selected_modules.erase(mod_name);
186
187 del_list.clear();
188 for (auto &it : selected_members)
189 if (design->modules_.count(it.first) == 0)
190 del_list.push_back(it.first);
191 for (auto mod_name : del_list)
192 selected_members.erase(mod_name);
193
194 for (auto &it : selected_members) {
195 del_list.clear();
196 for (auto memb_name : it.second)
197 if (design->modules_[it.first]->count_id(memb_name) == 0)
198 del_list.push_back(memb_name);
199 for (auto memb_name : del_list)
200 it.second.erase(memb_name);
201 }
202
203 del_list.clear();
204 add_list.clear();
205 for (auto &it : selected_members)
206 if (it.second.size() == 0)
207 del_list.push_back(it.first);
208 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
209 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
210 add_list.push_back(it.first);
211 for (auto mod_name : del_list)
212 selected_members.erase(mod_name);
213 for (auto mod_name : add_list) {
214 selected_members.erase(mod_name);
215 selected_modules.insert(mod_name);
216 }
217
218 if (selected_modules.size() == design->modules_.size()) {
219 full_selection = true;
220 selected_modules.clear();
221 selected_members.clear();
222 }
223 }
224
225 RTLIL::Design::Design()
226 {
227 refcount_modules_ = 0;
228 }
229
230 RTLIL::Design::~Design()
231 {
232 for (auto it = modules_.begin(); it != modules_.end(); it++)
233 delete it->second;
234 }
235
236 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
237 {
238 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
239 }
240
241 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
242 {
243 return modules_.count(name) ? modules_.at(name) : NULL;
244 }
245
246 void RTLIL::Design::add(RTLIL::Module *module)
247 {
248 log_assert(modules_.count(module->name) == 0);
249 log_assert(refcount_modules_ == 0);
250 modules_[module->name] = module;
251 module->design = this;
252
253 for (auto mon : monitors)
254 mon->notify_module_add(module);
255 }
256
257 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
258 {
259 log_assert(modules_.count(name) == 0);
260 log_assert(refcount_modules_ == 0);
261
262 RTLIL::Module *module = new RTLIL::Module;
263 modules_[name] = module;
264 module->design = this;
265 module->name = name;
266
267 for (auto mon : monitors)
268 mon->notify_module_add(module);
269
270 return module;
271 }
272
273 void RTLIL::Design::remove(RTLIL::Module *module)
274 {
275 for (auto mon : monitors)
276 mon->notify_module_del(module);
277
278 log_assert(modules_.at(module->name) == module);
279 modules_.erase(module->name);
280 delete module;
281 }
282
283 void RTLIL::Design::check()
284 {
285 #ifndef NDEBUG
286 for (auto &it : modules_) {
287 log_assert(this == it.second->design);
288 log_assert(it.first == it.second->name);
289 log_assert(!it.first.empty());
290 it.second->check();
291 }
292 #endif
293 }
294
295 void RTLIL::Design::optimize()
296 {
297 for (auto &it : modules_)
298 it.second->optimize();
299 for (auto &it : selection_stack)
300 it.optimize(this);
301 for (auto &it : selection_vars)
302 it.second.optimize(this);
303 }
304
305 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
306 {
307 if (!selected_active_module.empty() && mod_name != selected_active_module)
308 return false;
309 if (selection_stack.size() == 0)
310 return true;
311 return selection_stack.back().selected_module(mod_name);
312 }
313
314 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
315 {
316 if (!selected_active_module.empty() && mod_name != selected_active_module)
317 return false;
318 if (selection_stack.size() == 0)
319 return true;
320 return selection_stack.back().selected_whole_module(mod_name);
321 }
322
323 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
324 {
325 if (!selected_active_module.empty() && mod_name != selected_active_module)
326 return false;
327 if (selection_stack.size() == 0)
328 return true;
329 return selection_stack.back().selected_member(mod_name, memb_name);
330 }
331
332 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
333 {
334 return selected_module(mod->name);
335 }
336
337 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
338 {
339 return selected_whole_module(mod->name);
340 }
341
342 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
343 {
344 std::vector<RTLIL::Module*> result;
345 result.reserve(modules_.size());
346 for (auto &it : modules_)
347 if (selected_module(it.first))
348 result.push_back(it.second);
349 return result;
350 }
351
352 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
353 {
354 std::vector<RTLIL::Module*> result;
355 result.reserve(modules_.size());
356 for (auto &it : modules_)
357 if (selected_whole_module(it.first))
358 result.push_back(it.second);
359 return result;
360 }
361
362 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
363 {
364 std::vector<RTLIL::Module*> result;
365 result.reserve(modules_.size());
366 for (auto &it : modules_)
367 if (selected_whole_module(it.first))
368 result.push_back(it.second);
369 else if (selected_module(it.first))
370 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
371 return result;
372 }
373
374 RTLIL::Module::Module()
375 {
376 design = nullptr;
377 refcount_wires_ = 0;
378 refcount_cells_ = 0;
379 }
380
381 RTLIL::Module::~Module()
382 {
383 for (auto it = wires_.begin(); it != wires_.end(); it++)
384 delete it->second;
385 for (auto it = memories.begin(); it != memories.end(); it++)
386 delete it->second;
387 for (auto it = cells_.begin(); it != cells_.end(); it++)
388 delete it->second;
389 for (auto it = processes.begin(); it != processes.end(); it++)
390 delete it->second;
391 }
392
393 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
394 {
395 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
396 }
397
398 size_t RTLIL::Module::count_id(RTLIL::IdString id)
399 {
400 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
401 }
402
403 #ifndef NDEBUG
404 namespace {
405 struct InternalCellChecker
406 {
407 RTLIL::Module *module;
408 RTLIL::Cell *cell;
409 std::set<RTLIL::IdString> expected_params, expected_ports;
410
411 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
412
413 void error(int linenr)
414 {
415 char *ptr;
416 size_t size;
417
418 FILE *f = open_memstream(&ptr, &size);
419 ILANG_BACKEND::dump_cell(f, " ", cell);
420 fputc(0, f);
421 fclose(f);
422
423 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
424 module ? module->name.c_str() : "", module ? "." : "",
425 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
426 }
427
428 int param(const char *name)
429 {
430 if (cell->parameters.count(name) == 0)
431 error(__LINE__);
432 expected_params.insert(name);
433 return cell->parameters.at(name).as_int();
434 }
435
436 int param_bool(const char *name)
437 {
438 int v = param(name);
439 if (cell->parameters.at(name).bits.size() > 32)
440 error(__LINE__);
441 if (v != 0 && v != 1)
442 error(__LINE__);
443 return v;
444 }
445
446 void param_bits(const char *name, int width)
447 {
448 param(name);
449 if (int(cell->parameters.at(name).bits.size()) != width)
450 error(__LINE__);
451 }
452
453 void port(const char *name, int width)
454 {
455 if (!cell->hasPort(name))
456 error(__LINE__);
457 if (cell->getPort(name).size() != width)
458 error(__LINE__);
459 expected_ports.insert(name);
460 }
461
462 void check_expected(bool check_matched_sign = true)
463 {
464 for (auto &para : cell->parameters)
465 if (expected_params.count(para.first) == 0)
466 error(__LINE__);
467 for (auto &conn : cell->connections())
468 if (expected_ports.count(conn.first) == 0)
469 error(__LINE__);
470
471 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
472 bool a_is_signed = param("\\A_SIGNED") != 0;
473 bool b_is_signed = param("\\B_SIGNED") != 0;
474 if (a_is_signed != b_is_signed)
475 error(__LINE__);
476 }
477 }
478
479 void check_gate(const char *ports)
480 {
481 if (cell->parameters.size() != 0)
482 error(__LINE__);
483
484 for (const char *p = ports; *p; p++) {
485 char portname[3] = { '\\', *p, 0 };
486 if (!cell->hasPort(portname))
487 error(__LINE__);
488 if (cell->getPort(portname).size() != 1)
489 error(__LINE__);
490 }
491
492 for (auto &conn : cell->connections()) {
493 if (conn.first.size() != 2 || conn.first[0] != '\\')
494 error(__LINE__);
495 if (strchr(ports, conn.first[1]) == NULL)
496 error(__LINE__);
497 }
498 }
499
500 void check()
501 {
502 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
503 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
504 return;
505
506 if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
507 param_bool("\\A_SIGNED");
508 port("\\A", param("\\A_WIDTH"));
509 port("\\Y", param("\\Y_WIDTH"));
510 check_expected();
511 return;
512 }
513
514 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
515 param_bool("\\A_SIGNED");
516 param_bool("\\B_SIGNED");
517 port("\\A", param("\\A_WIDTH"));
518 port("\\B", param("\\B_WIDTH"));
519 port("\\Y", param("\\Y_WIDTH"));
520 check_expected();
521 return;
522 }
523
524 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
525 param_bool("\\A_SIGNED");
526 port("\\A", param("\\A_WIDTH"));
527 port("\\Y", param("\\Y_WIDTH"));
528 check_expected();
529 return;
530 }
531
532 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
533 param_bool("\\A_SIGNED");
534 param_bool("\\B_SIGNED");
535 port("\\A", param("\\A_WIDTH"));
536 port("\\B", param("\\B_WIDTH"));
537 port("\\Y", param("\\Y_WIDTH"));
538 check_expected(false);
539 return;
540 }
541
542 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
543 param_bool("\\A_SIGNED");
544 param_bool("\\B_SIGNED");
545 port("\\A", param("\\A_WIDTH"));
546 port("\\B", param("\\B_WIDTH"));
547 port("\\Y", param("\\Y_WIDTH"));
548 check_expected();
549 return;
550 }
551
552 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
553 param_bool("\\A_SIGNED");
554 param_bool("\\B_SIGNED");
555 port("\\A", param("\\A_WIDTH"));
556 port("\\B", param("\\B_WIDTH"));
557 port("\\Y", param("\\Y_WIDTH"));
558 check_expected(cell->type != "$pow");
559 return;
560 }
561
562 if (cell->type == "$logic_not") {
563 param_bool("\\A_SIGNED");
564 port("\\A", param("\\A_WIDTH"));
565 port("\\Y", param("\\Y_WIDTH"));
566 check_expected();
567 return;
568 }
569
570 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
571 param_bool("\\A_SIGNED");
572 param_bool("\\B_SIGNED");
573 port("\\A", param("\\A_WIDTH"));
574 port("\\B", param("\\B_WIDTH"));
575 port("\\Y", param("\\Y_WIDTH"));
576 check_expected(false);
577 return;
578 }
579
580 if (cell->type == "$slice") {
581 param("\\OFFSET");
582 port("\\A", param("\\A_WIDTH"));
583 port("\\Y", param("\\Y_WIDTH"));
584 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
585 error(__LINE__);
586 check_expected();
587 return;
588 }
589
590 if (cell->type == "$concat") {
591 port("\\A", param("\\A_WIDTH"));
592 port("\\B", param("\\B_WIDTH"));
593 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
594 check_expected();
595 return;
596 }
597
598 if (cell->type == "$mux") {
599 port("\\A", param("\\WIDTH"));
600 port("\\B", param("\\WIDTH"));
601 port("\\S", 1);
602 port("\\Y", param("\\WIDTH"));
603 check_expected();
604 return;
605 }
606
607 if (cell->type == "$pmux") {
608 port("\\A", param("\\WIDTH"));
609 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
610 port("\\S", param("\\S_WIDTH"));
611 port("\\Y", param("\\WIDTH"));
612 check_expected();
613 return;
614 }
615
616 if (cell->type == "$lut") {
617 param("\\LUT");
618 port("\\A", param("\\WIDTH"));
619 port("\\Y", 1);
620 check_expected();
621 return;
622 }
623
624 if (cell->type == "$sr") {
625 param_bool("\\SET_POLARITY");
626 param_bool("\\CLR_POLARITY");
627 port("\\SET", param("\\WIDTH"));
628 port("\\CLR", param("\\WIDTH"));
629 port("\\Q", param("\\WIDTH"));
630 check_expected();
631 return;
632 }
633
634 if (cell->type == "$dff") {
635 param_bool("\\CLK_POLARITY");
636 port("\\CLK", 1);
637 port("\\D", param("\\WIDTH"));
638 port("\\Q", param("\\WIDTH"));
639 check_expected();
640 return;
641 }
642
643 if (cell->type == "$dffsr") {
644 param_bool("\\CLK_POLARITY");
645 param_bool("\\SET_POLARITY");
646 param_bool("\\CLR_POLARITY");
647 port("\\CLK", 1);
648 port("\\SET", param("\\WIDTH"));
649 port("\\CLR", param("\\WIDTH"));
650 port("\\D", param("\\WIDTH"));
651 port("\\Q", param("\\WIDTH"));
652 check_expected();
653 return;
654 }
655
656 if (cell->type == "$adff") {
657 param_bool("\\CLK_POLARITY");
658 param_bool("\\ARST_POLARITY");
659 param_bits("\\ARST_VALUE", param("\\WIDTH"));
660 port("\\CLK", 1);
661 port("\\ARST", 1);
662 port("\\D", param("\\WIDTH"));
663 port("\\Q", param("\\WIDTH"));
664 check_expected();
665 return;
666 }
667
668 if (cell->type == "$dlatch") {
669 param_bool("\\EN_POLARITY");
670 port("\\EN", 1);
671 port("\\D", param("\\WIDTH"));
672 port("\\Q", param("\\WIDTH"));
673 check_expected();
674 return;
675 }
676
677 if (cell->type == "$dlatchsr") {
678 param_bool("\\EN_POLARITY");
679 param_bool("\\SET_POLARITY");
680 param_bool("\\CLR_POLARITY");
681 port("\\EN", 1);
682 port("\\SET", param("\\WIDTH"));
683 port("\\CLR", param("\\WIDTH"));
684 port("\\D", param("\\WIDTH"));
685 port("\\Q", param("\\WIDTH"));
686 check_expected();
687 return;
688 }
689
690 if (cell->type == "$fsm") {
691 param("\\NAME");
692 param_bool("\\CLK_POLARITY");
693 param_bool("\\ARST_POLARITY");
694 param("\\STATE_BITS");
695 param("\\STATE_NUM");
696 param("\\STATE_NUM_LOG2");
697 param("\\STATE_RST");
698 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
699 param("\\TRANS_NUM");
700 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
701 port("\\CLK", 1);
702 port("\\ARST", 1);
703 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
704 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
705 check_expected();
706 return;
707 }
708
709 if (cell->type == "$memrd") {
710 param("\\MEMID");
711 param_bool("\\CLK_ENABLE");
712 param_bool("\\CLK_POLARITY");
713 param_bool("\\TRANSPARENT");
714 port("\\CLK", 1);
715 port("\\ADDR", param("\\ABITS"));
716 port("\\DATA", param("\\WIDTH"));
717 check_expected();
718 return;
719 }
720
721 if (cell->type == "$memwr") {
722 param("\\MEMID");
723 param_bool("\\CLK_ENABLE");
724 param_bool("\\CLK_POLARITY");
725 param("\\PRIORITY");
726 port("\\CLK", 1);
727 port("\\EN", param("\\WIDTH"));
728 port("\\ADDR", param("\\ABITS"));
729 port("\\DATA", param("\\WIDTH"));
730 check_expected();
731 return;
732 }
733
734 if (cell->type == "$mem") {
735 param("\\MEMID");
736 param("\\SIZE");
737 param("\\OFFSET");
738 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
739 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
740 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
741 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
742 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
743 port("\\RD_CLK", param("\\RD_PORTS"));
744 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
745 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
746 port("\\WR_CLK", param("\\WR_PORTS"));
747 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
748 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
749 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
750 check_expected();
751 return;
752 }
753
754 if (cell->type == "$assert") {
755 port("\\A", 1);
756 port("\\EN", 1);
757 check_expected();
758 return;
759 }
760
761 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
762 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
763 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
764 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
765 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
766 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
767 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
768 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
769 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
770 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
771 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
772 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
773
774 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
775 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
776 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
777 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
778
779 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
780 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
781
782 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
783 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
784 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
785 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
786 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
787 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
788 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
789 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
790
791 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
792 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
793 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
794 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
795 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
796 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
797 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
798 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
799
800 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
801 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
802
803 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
804 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
805 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
806 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
807 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
808 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
809 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
810 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
811
812 error(__LINE__);
813 }
814 };
815 }
816 #endif
817
818 void RTLIL::Module::check()
819 {
820 #ifndef NDEBUG
821 std::vector<bool> ports_declared;
822 for (auto &it : wires_) {
823 log_assert(this == it.second->module);
824 log_assert(it.first == it.second->name);
825 log_assert(!it.first.empty());
826 log_assert(it.second->width >= 0);
827 log_assert(it.second->port_id >= 0);
828 for (auto &it2 : it.second->attributes)
829 log_assert(!it2.first.empty());
830 if (it.second->port_id) {
831 log_assert(SIZE(ports) >= it.second->port_id);
832 log_assert(ports.at(it.second->port_id-1) == it.first);
833 log_assert(it.second->port_input || it.second->port_output);
834 if (SIZE(ports_declared) < it.second->port_id)
835 ports_declared.resize(it.second->port_id);
836 log_assert(ports_declared[it.second->port_id-1] == false);
837 ports_declared[it.second->port_id-1] = true;
838 } else
839 log_assert(!it.second->port_input && !it.second->port_output);
840 }
841 for (auto port_declared : ports_declared)
842 log_assert(port_declared == true);
843 log_assert(SIZE(ports) == SIZE(ports_declared));
844
845 for (auto &it : memories) {
846 log_assert(it.first == it.second->name);
847 log_assert(!it.first.empty());
848 log_assert(it.second->width >= 0);
849 log_assert(it.second->size >= 0);
850 for (auto &it2 : it.second->attributes)
851 log_assert(!it2.first.empty());
852 }
853
854 for (auto &it : cells_) {
855 log_assert(this == it.second->module);
856 log_assert(it.first == it.second->name);
857 log_assert(!it.first.empty());
858 log_assert(!it.second->type.empty());
859 for (auto &it2 : it.second->connections()) {
860 log_assert(!it2.first.empty());
861 it2.second.check();
862 }
863 for (auto &it2 : it.second->attributes)
864 log_assert(!it2.first.empty());
865 for (auto &it2 : it.second->parameters)
866 log_assert(!it2.first.empty());
867 InternalCellChecker checker(this, it.second);
868 checker.check();
869 }
870
871 for (auto &it : processes) {
872 log_assert(it.first == it.second->name);
873 log_assert(!it.first.empty());
874 // FIXME: More checks here..
875 }
876
877 for (auto &it : connections_) {
878 log_assert(it.first.size() == it.second.size());
879 it.first.check();
880 it.second.check();
881 }
882
883 for (auto &it : attributes)
884 log_assert(!it.first.empty());
885 #endif
886 }
887
888 void RTLIL::Module::optimize()
889 {
890 }
891
892 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
893 {
894 log_assert(new_mod->refcount_wires_ == 0);
895 log_assert(new_mod->refcount_cells_ == 0);
896
897 new_mod->connections_ = connections_;
898 new_mod->attributes = attributes;
899
900 for (auto &it : wires_)
901 new_mod->addWire(it.first, it.second);
902
903 for (auto &it : memories)
904 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
905
906 for (auto &it : cells_)
907 new_mod->addCell(it.first, it.second);
908
909 for (auto &it : processes)
910 new_mod->processes[it.first] = it.second->clone();
911
912 struct RewriteSigSpecWorker
913 {
914 RTLIL::Module *mod;
915 void operator()(RTLIL::SigSpec &sig)
916 {
917 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
918 for (auto &c : chunks)
919 if (c.wire != NULL)
920 c.wire = mod->wires_.at(c.wire->name);
921 sig = chunks;
922 }
923 };
924
925 RewriteSigSpecWorker rewriteSigSpecWorker;
926 rewriteSigSpecWorker.mod = new_mod;
927 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
928 new_mod->fixup_ports();
929 }
930
931 RTLIL::Module *RTLIL::Module::clone() const
932 {
933 RTLIL::Module *new_mod = new RTLIL::Module;
934 new_mod->name = name;
935 cloneInto(new_mod);
936 return new_mod;
937 }
938
939 bool RTLIL::Module::has_memories() const
940 {
941 return !memories.empty();
942 }
943
944 bool RTLIL::Module::has_processes() const
945 {
946 return !processes.empty();
947 }
948
949 bool RTLIL::Module::has_memories_warn() const
950 {
951 if (!memories.empty())
952 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
953 return !memories.empty();
954 }
955
956 bool RTLIL::Module::has_processes_warn() const
957 {
958 if (!processes.empty())
959 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
960 return !processes.empty();
961 }
962
963 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
964 {
965 std::vector<RTLIL::Wire*> result;
966 result.reserve(wires_.size());
967 for (auto &it : wires_)
968 if (design->selected(this, it.second))
969 result.push_back(it.second);
970 return result;
971 }
972
973 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
974 {
975 std::vector<RTLIL::Cell*> result;
976 result.reserve(wires_.size());
977 for (auto &it : cells_)
978 if (design->selected(this, it.second))
979 result.push_back(it.second);
980 return result;
981 }
982
983 void RTLIL::Module::add(RTLIL::Wire *wire)
984 {
985 log_assert(!wire->name.empty());
986 log_assert(count_id(wire->name) == 0);
987 log_assert(refcount_wires_ == 0);
988 wires_[wire->name] = wire;
989 wire->module = this;
990 }
991
992 void RTLIL::Module::add(RTLIL::Cell *cell)
993 {
994 log_assert(!cell->name.empty());
995 log_assert(count_id(cell->name) == 0);
996 log_assert(refcount_cells_ == 0);
997 cells_[cell->name] = cell;
998 cell->module = this;
999 }
1000
1001 namespace {
1002 struct DeleteWireWorker
1003 {
1004 RTLIL::Module *module;
1005 const std::set<RTLIL::Wire*> *wires_p;
1006
1007 void operator()(RTLIL::SigSpec &sig) {
1008 std::vector<RTLIL::SigChunk> chunks = sig;
1009 for (auto &c : chunks)
1010 if (c.wire != NULL && wires_p->count(c.wire)) {
1011 c.wire = module->addWire(NEW_ID, c.width);
1012 c.offset = 0;
1013 }
1014 sig = chunks;
1015 }
1016 };
1017 }
1018
1019 #if 0
1020 void RTLIL::Module::remove(RTLIL::Wire *wire)
1021 {
1022 std::setPort<RTLIL::Wire*> wires_;
1023 wires_.insert(wire);
1024 remove(wires_);
1025 }
1026 #endif
1027
1028 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1029 {
1030 log_assert(refcount_wires_ == 0);
1031
1032 DeleteWireWorker delete_wire_worker;
1033 delete_wire_worker.module = this;
1034 delete_wire_worker.wires_p = &wires;
1035 rewrite_sigspecs(delete_wire_worker);
1036
1037 for (auto &it : wires) {
1038 log_assert(wires_.count(it->name) != 0);
1039 wires_.erase(it->name);
1040 delete it;
1041 }
1042 }
1043
1044 void RTLIL::Module::remove(RTLIL::Cell *cell)
1045 {
1046 log_assert(cells_.count(cell->name) != 0);
1047 log_assert(refcount_cells_ == 0);
1048 cells_.erase(cell->name);
1049 delete cell;
1050 }
1051
1052 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1053 {
1054 log_assert(wires_[wire->name] == wire);
1055 log_assert(refcount_wires_ == 0);
1056 wires_.erase(wire->name);
1057 wire->name = new_name;
1058 add(wire);
1059 }
1060
1061 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1062 {
1063 log_assert(cells_[cell->name] == cell);
1064 log_assert(refcount_wires_ == 0);
1065 cells_.erase(cell->name);
1066 cell->name = new_name;
1067 add(cell);
1068 }
1069
1070 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1071 {
1072 log_assert(count_id(old_name) != 0);
1073 if (wires_.count(old_name))
1074 rename(wires_.at(old_name), new_name);
1075 else if (cells_.count(old_name))
1076 rename(cells_.at(old_name), new_name);
1077 else
1078 log_abort();
1079 }
1080
1081 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1082 {
1083 log_assert(wires_[w1->name] == w1);
1084 log_assert(wires_[w2->name] == w2);
1085 log_assert(refcount_wires_ == 0);
1086
1087 wires_.erase(w1->name);
1088 wires_.erase(w2->name);
1089
1090 std::swap(w1->name, w2->name);
1091
1092 wires_[w1->name] = w1;
1093 wires_[w2->name] = w2;
1094 }
1095
1096 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1097 {
1098 log_assert(cells_[c1->name] == c1);
1099 log_assert(cells_[c2->name] == c2);
1100 log_assert(refcount_cells_ == 0);
1101
1102 cells_.erase(c1->name);
1103 cells_.erase(c2->name);
1104
1105 std::swap(c1->name, c2->name);
1106
1107 cells_[c1->name] = c1;
1108 cells_[c2->name] = c2;
1109 }
1110
1111 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1112 {
1113 int index = 0;
1114 return uniquify(name, index);
1115 }
1116
1117 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1118 {
1119 if (index == 0) {
1120 if (count_id(name) == 0)
1121 return name;
1122 index++;
1123 }
1124
1125 while (1) {
1126 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1127 if (count_id(new_name) == 0)
1128 return new_name;
1129 index++;
1130 }
1131 }
1132
1133 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1134 {
1135 if (a->port_id && !b->port_id)
1136 return true;
1137 if (!a->port_id && b->port_id)
1138 return false;
1139
1140 if (a->port_id == b->port_id)
1141 return a->name < b->name;
1142 return a->port_id < b->port_id;
1143 }
1144
1145 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1146 {
1147 for (auto mon : monitors)
1148 mon->notify_connect(this, conn);
1149
1150 if (design)
1151 for (auto mon : design->monitors)
1152 mon->notify_connect(this, conn);
1153
1154 connections_.push_back(conn);
1155 }
1156
1157 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1158 {
1159 connect(RTLIL::SigSig(lhs, rhs));
1160 }
1161
1162 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1163 {
1164 for (auto mon : monitors)
1165 mon->notify_connect(this, new_conn);
1166
1167 if (design)
1168 for (auto mon : design->monitors)
1169 mon->notify_connect(this, new_conn);
1170
1171 connections_ = new_conn;
1172 }
1173
1174 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1175 {
1176 return connections_;
1177 }
1178
1179 void RTLIL::Module::fixup_ports()
1180 {
1181 std::vector<RTLIL::Wire*> all_ports;
1182
1183 for (auto &w : wires_)
1184 if (w.second->port_input || w.second->port_output)
1185 all_ports.push_back(w.second);
1186 else
1187 w.second->port_id = 0;
1188
1189 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1190
1191 ports.clear();
1192 for (size_t i = 0; i < all_ports.size(); i++) {
1193 ports.push_back(all_ports[i]->name);
1194 all_ports[i]->port_id = i+1;
1195 }
1196 }
1197
1198 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1199 {
1200 RTLIL::Wire *wire = new RTLIL::Wire;
1201 wire->name = name;
1202 wire->width = width;
1203 add(wire);
1204 return wire;
1205 }
1206
1207 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1208 {
1209 RTLIL::Wire *wire = addWire(name);
1210 wire->width = other->width;
1211 wire->start_offset = other->start_offset;
1212 wire->port_id = other->port_id;
1213 wire->port_input = other->port_input;
1214 wire->port_output = other->port_output;
1215 wire->upto = other->upto;
1216 wire->attributes = other->attributes;
1217 return wire;
1218 }
1219
1220 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1221 {
1222 RTLIL::Cell *cell = new RTLIL::Cell;
1223 cell->name = name;
1224 cell->type = type;
1225 add(cell);
1226 return cell;
1227 }
1228
1229 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1230 {
1231 RTLIL::Cell *cell = addCell(name, other->type);
1232 cell->connections_ = other->connections_;
1233 cell->parameters = other->parameters;
1234 cell->attributes = other->attributes;
1235 return cell;
1236 }
1237
1238 #define DEF_METHOD(_func, _y_size, _type) \
1239 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1240 RTLIL::Cell *cell = addCell(name, _type); \
1241 cell->parameters["\\A_SIGNED"] = is_signed; \
1242 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1243 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1244 cell->setPort("\\A", sig_a); \
1245 cell->setPort("\\Y", sig_y); \
1246 return cell; \
1247 } \
1248 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1249 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1250 add ## _func(name, sig_a, sig_y, is_signed); \
1251 return sig_y; \
1252 }
1253 DEF_METHOD(Not, sig_a.size(), "$not")
1254 DEF_METHOD(Pos, sig_a.size(), "$pos")
1255 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1256 DEF_METHOD(Neg, sig_a.size(), "$neg")
1257 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1258 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1259 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1260 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1261 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1262 DEF_METHOD(LogicNot, 1, "$logic_not")
1263 #undef DEF_METHOD
1264
1265 #define DEF_METHOD(_func, _y_size, _type) \
1266 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1267 RTLIL::Cell *cell = addCell(name, _type); \
1268 cell->parameters["\\A_SIGNED"] = is_signed; \
1269 cell->parameters["\\B_SIGNED"] = is_signed; \
1270 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1271 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1272 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1273 cell->setPort("\\A", sig_a); \
1274 cell->setPort("\\B", sig_b); \
1275 cell->setPort("\\Y", sig_y); \
1276 return cell; \
1277 } \
1278 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1279 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1280 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1281 return sig_y; \
1282 }
1283 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1284 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1285 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1286 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1287 DEF_METHOD(Shl, sig_a.size(), "$shl")
1288 DEF_METHOD(Shr, sig_a.size(), "$shr")
1289 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1290 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1291 DEF_METHOD(Shift, sig_a.size(), "$shift")
1292 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1293 DEF_METHOD(Lt, 1, "$lt")
1294 DEF_METHOD(Le, 1, "$le")
1295 DEF_METHOD(Eq, 1, "$eq")
1296 DEF_METHOD(Ne, 1, "$ne")
1297 DEF_METHOD(Eqx, 1, "$eqx")
1298 DEF_METHOD(Nex, 1, "$nex")
1299 DEF_METHOD(Ge, 1, "$ge")
1300 DEF_METHOD(Gt, 1, "$gt")
1301 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1302 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1303 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1304 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1305 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1306 DEF_METHOD(LogicAnd, 1, "$logic_and")
1307 DEF_METHOD(LogicOr, 1, "$logic_or")
1308 #undef DEF_METHOD
1309
1310 #define DEF_METHOD(_func, _type, _pmux) \
1311 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1312 RTLIL::Cell *cell = addCell(name, _type); \
1313 cell->parameters["\\WIDTH"] = sig_a.size(); \
1314 cell->parameters["\\WIDTH"] = sig_b.size(); \
1315 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1316 cell->setPort("\\A", sig_a); \
1317 cell->setPort("\\B", sig_b); \
1318 cell->setPort("\\S", sig_s); \
1319 cell->setPort("\\Y", sig_y); \
1320 return cell; \
1321 } \
1322 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1323 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1324 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1325 return sig_y; \
1326 }
1327 DEF_METHOD(Mux, "$mux", 0)
1328 DEF_METHOD(Pmux, "$pmux", 1)
1329 #undef DEF_METHOD
1330
1331 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1332 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1333 RTLIL::Cell *cell = addCell(name, _type); \
1334 cell->setPort("\\" #_P1, sig1); \
1335 cell->setPort("\\" #_P2, sig2); \
1336 return cell; \
1337 } \
1338 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1339 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1340 add ## _func(name, sig1, sig2); \
1341 return sig2; \
1342 }
1343 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1344 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1345 RTLIL::Cell *cell = addCell(name, _type); \
1346 cell->setPort("\\" #_P1, sig1); \
1347 cell->setPort("\\" #_P2, sig2); \
1348 cell->setPort("\\" #_P3, sig3); \
1349 return cell; \
1350 } \
1351 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1352 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1353 add ## _func(name, sig1, sig2, sig3); \
1354 return sig3; \
1355 }
1356 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1357 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1358 RTLIL::Cell *cell = addCell(name, _type); \
1359 cell->setPort("\\" #_P1, sig1); \
1360 cell->setPort("\\" #_P2, sig2); \
1361 cell->setPort("\\" #_P3, sig3); \
1362 cell->setPort("\\" #_P4, sig4); \
1363 return cell; \
1364 } \
1365 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1366 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1367 add ## _func(name, sig1, sig2, sig3, sig4); \
1368 return sig4; \
1369 }
1370 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1371 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1372 RTLIL::Cell *cell = addCell(name, _type); \
1373 cell->setPort("\\" #_P1, sig1); \
1374 cell->setPort("\\" #_P2, sig2); \
1375 cell->setPort("\\" #_P3, sig3); \
1376 cell->setPort("\\" #_P4, sig4); \
1377 cell->setPort("\\" #_P5, sig5); \
1378 return cell; \
1379 } \
1380 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1381 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1382 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1383 return sig5; \
1384 }
1385 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1386 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1387 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1388 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1389 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1390 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1391 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1392 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1393 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1394 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1395 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1396 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1397 #undef DEF_METHOD_2
1398 #undef DEF_METHOD_3
1399 #undef DEF_METHOD_4
1400 #undef DEF_METHOD_5
1401
1402 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1403 {
1404 RTLIL::Cell *cell = addCell(name, "$pow");
1405 cell->parameters["\\A_SIGNED"] = a_signed;
1406 cell->parameters["\\B_SIGNED"] = b_signed;
1407 cell->parameters["\\A_WIDTH"] = sig_a.size();
1408 cell->parameters["\\B_WIDTH"] = sig_b.size();
1409 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1410 cell->setPort("\\A", sig_a);
1411 cell->setPort("\\B", sig_b);
1412 cell->setPort("\\Y", sig_y);
1413 return cell;
1414 }
1415
1416 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1417 {
1418 RTLIL::Cell *cell = addCell(name, "$slice");
1419 cell->parameters["\\A_WIDTH"] = sig_a.size();
1420 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1421 cell->parameters["\\OFFSET"] = offset;
1422 cell->setPort("\\A", sig_a);
1423 cell->setPort("\\Y", sig_y);
1424 return cell;
1425 }
1426
1427 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1428 {
1429 RTLIL::Cell *cell = addCell(name, "$concat");
1430 cell->parameters["\\A_WIDTH"] = sig_a.size();
1431 cell->parameters["\\B_WIDTH"] = sig_b.size();
1432 cell->setPort("\\A", sig_a);
1433 cell->setPort("\\B", sig_b);
1434 cell->setPort("\\Y", sig_y);
1435 return cell;
1436 }
1437
1438 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1439 {
1440 RTLIL::Cell *cell = addCell(name, "$lut");
1441 cell->parameters["\\LUT"] = lut;
1442 cell->parameters["\\WIDTH"] = sig_i.size();
1443 cell->setPort("\\A", sig_i);
1444 cell->setPort("\\Y", sig_o);
1445 return cell;
1446 }
1447
1448 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1449 {
1450 RTLIL::Cell *cell = addCell(name, "$assert");
1451 cell->setPort("\\A", sig_a);
1452 cell->setPort("\\EN", sig_en);
1453 return cell;
1454 }
1455
1456 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1457 {
1458 RTLIL::Cell *cell = addCell(name, "$sr");
1459 cell->parameters["\\SET_POLARITY"] = set_polarity;
1460 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1461 cell->parameters["\\WIDTH"] = sig_q.size();
1462 cell->setPort("\\SET", sig_set);
1463 cell->setPort("\\CLR", sig_clr);
1464 cell->setPort("\\Q", sig_q);
1465 return cell;
1466 }
1467
1468 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1469 {
1470 RTLIL::Cell *cell = addCell(name, "$dff");
1471 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1472 cell->parameters["\\WIDTH"] = sig_q.size();
1473 cell->setPort("\\CLK", sig_clk);
1474 cell->setPort("\\D", sig_d);
1475 cell->setPort("\\Q", sig_q);
1476 return cell;
1477 }
1478
1479 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1480 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1481 {
1482 RTLIL::Cell *cell = addCell(name, "$dffsr");
1483 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1484 cell->parameters["\\SET_POLARITY"] = set_polarity;
1485 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1486 cell->parameters["\\WIDTH"] = sig_q.size();
1487 cell->setPort("\\CLK", sig_clk);
1488 cell->setPort("\\SET", sig_set);
1489 cell->setPort("\\CLR", sig_clr);
1490 cell->setPort("\\D", sig_d);
1491 cell->setPort("\\Q", sig_q);
1492 return cell;
1493 }
1494
1495 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1496 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1497 {
1498 RTLIL::Cell *cell = addCell(name, "$adff");
1499 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1500 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1501 cell->parameters["\\ARST_VALUE"] = arst_value;
1502 cell->parameters["\\WIDTH"] = sig_q.size();
1503 cell->setPort("\\CLK", sig_clk);
1504 cell->setPort("\\ARST", sig_arst);
1505 cell->setPort("\\D", sig_d);
1506 cell->setPort("\\Q", sig_q);
1507 return cell;
1508 }
1509
1510 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1511 {
1512 RTLIL::Cell *cell = addCell(name, "$dlatch");
1513 cell->parameters["\\EN_POLARITY"] = en_polarity;
1514 cell->parameters["\\WIDTH"] = sig_q.size();
1515 cell->setPort("\\EN", sig_en);
1516 cell->setPort("\\D", sig_d);
1517 cell->setPort("\\Q", sig_q);
1518 return cell;
1519 }
1520
1521 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1522 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1523 {
1524 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1525 cell->parameters["\\EN_POLARITY"] = en_polarity;
1526 cell->parameters["\\SET_POLARITY"] = set_polarity;
1527 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1528 cell->parameters["\\WIDTH"] = sig_q.size();
1529 cell->setPort("\\EN", sig_en);
1530 cell->setPort("\\SET", sig_set);
1531 cell->setPort("\\CLR", sig_clr);
1532 cell->setPort("\\D", sig_d);
1533 cell->setPort("\\Q", sig_q);
1534 return cell;
1535 }
1536
1537 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1538 {
1539 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1540 cell->setPort("\\C", sig_clk);
1541 cell->setPort("\\D", sig_d);
1542 cell->setPort("\\Q", sig_q);
1543 return cell;
1544 }
1545
1546 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1547 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1548 {
1549 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1550 cell->setPort("\\C", sig_clk);
1551 cell->setPort("\\S", sig_set);
1552 cell->setPort("\\R", sig_clr);
1553 cell->setPort("\\D", sig_d);
1554 cell->setPort("\\Q", sig_q);
1555 return cell;
1556 }
1557
1558 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1559 bool arst_value, bool clk_polarity, bool arst_polarity)
1560 {
1561 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1562 cell->setPort("\\C", sig_clk);
1563 cell->setPort("\\R", sig_arst);
1564 cell->setPort("\\D", sig_d);
1565 cell->setPort("\\Q", sig_q);
1566 return cell;
1567 }
1568
1569 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1570 {
1571 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1572 cell->setPort("\\E", sig_en);
1573 cell->setPort("\\D", sig_d);
1574 cell->setPort("\\Q", sig_q);
1575 return cell;
1576 }
1577
1578 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1579 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1580 {
1581 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1582 cell->setPort("\\E", sig_en);
1583 cell->setPort("\\S", sig_set);
1584 cell->setPort("\\R", sig_clr);
1585 cell->setPort("\\D", sig_d);
1586 cell->setPort("\\Q", sig_q);
1587 return cell;
1588 }
1589
1590
1591 RTLIL::Wire::Wire()
1592 {
1593 module = nullptr;
1594 width = 1;
1595 start_offset = 0;
1596 port_id = 0;
1597 port_input = false;
1598 port_output = false;
1599 upto = false;
1600 }
1601
1602 RTLIL::Memory::Memory()
1603 {
1604 width = 1;
1605 size = 0;
1606 }
1607
1608 RTLIL::Cell::Cell() : module(nullptr)
1609 {
1610 }
1611
1612 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1613 {
1614 return connections_.count(portname) != 0;
1615 }
1616
1617 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1618 {
1619 RTLIL::SigSpec signal;
1620 auto conn_it = connections_.find(portname);
1621
1622 if (conn_it != connections_.end())
1623 {
1624 for (auto mon : module->monitors)
1625 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1626
1627 if (module->design)
1628 for (auto mon : module->design->monitors)
1629 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1630
1631 connections_.erase(conn_it);
1632 }
1633 }
1634
1635 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1636 {
1637 auto conn_it = connections_.find(portname);
1638
1639 if (conn_it == connections_.end()) {
1640 connections_[portname] = RTLIL::SigSpec();
1641 conn_it = connections_.find(portname);
1642 log_assert(conn_it != connections_.end());
1643 }
1644
1645 for (auto mon : module->monitors)
1646 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1647
1648 if (module->design)
1649 for (auto mon : module->design->monitors)
1650 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1651
1652 conn_it->second = signal;
1653 }
1654
1655 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1656 {
1657 return connections_.at(portname);
1658 }
1659
1660 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1661 {
1662 return connections_;
1663 }
1664
1665 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1666 {
1667 return parameters.count(paramname);
1668 }
1669
1670 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1671 {
1672 parameters.erase(paramname);
1673 }
1674
1675 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1676 {
1677 parameters[paramname] = value;
1678 }
1679
1680 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1681 {
1682 return parameters.at(paramname);
1683 }
1684
1685 void RTLIL::Cell::check()
1686 {
1687 #ifndef NDEBUG
1688 InternalCellChecker checker(NULL, this);
1689 checker.check();
1690 #endif
1691 }
1692
1693 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1694 {
1695 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1696 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1697 return;
1698
1699 if (type == "$mux" || type == "$pmux")
1700 {
1701 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1702 if (type == "$pmux")
1703 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1704 check();
1705 return;
1706 }
1707
1708 bool signedness_ab = type != "$slice" && type != "$concat";
1709
1710 if (connections_.count("\\A")) {
1711 if (signedness_ab) {
1712 if (set_a_signed)
1713 parameters["\\A_SIGNED"] = true;
1714 else if (parameters.count("\\A_SIGNED") == 0)
1715 parameters["\\A_SIGNED"] = false;
1716 }
1717 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1718 }
1719
1720 if (connections_.count("\\B")) {
1721 if (signedness_ab) {
1722 if (set_b_signed)
1723 parameters["\\B_SIGNED"] = true;
1724 else if (parameters.count("\\B_SIGNED") == 0)
1725 parameters["\\B_SIGNED"] = false;
1726 }
1727 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1728 }
1729
1730 if (connections_.count("\\Y"))
1731 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1732
1733 check();
1734 }
1735
1736 RTLIL::SigChunk::SigChunk()
1737 {
1738 wire = NULL;
1739 width = 0;
1740 offset = 0;
1741 }
1742
1743 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1744 {
1745 wire = NULL;
1746 data = value;
1747 width = data.bits.size();
1748 offset = 0;
1749 }
1750
1751 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1752 {
1753 log_assert(wire != nullptr);
1754 this->wire = wire;
1755 this->width = wire->width;
1756 this->offset = 0;
1757 }
1758
1759 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1760 {
1761 log_assert(wire != nullptr);
1762 this->wire = wire;
1763 this->width = width;
1764 this->offset = offset;
1765 }
1766
1767 RTLIL::SigChunk::SigChunk(const std::string &str)
1768 {
1769 wire = NULL;
1770 data = RTLIL::Const(str);
1771 width = data.bits.size();
1772 offset = 0;
1773 }
1774
1775 RTLIL::SigChunk::SigChunk(int val, int width)
1776 {
1777 wire = NULL;
1778 data = RTLIL::Const(val, width);
1779 this->width = data.bits.size();
1780 offset = 0;
1781 }
1782
1783 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1784 {
1785 wire = NULL;
1786 data = RTLIL::Const(bit, width);
1787 this->width = data.bits.size();
1788 offset = 0;
1789 }
1790
1791 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1792 {
1793 wire = bit.wire;
1794 offset = 0;
1795 if (wire == NULL)
1796 data = RTLIL::Const(bit.data);
1797 else
1798 offset = bit.offset;
1799 width = 1;
1800 }
1801
1802 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1803 {
1804 RTLIL::SigChunk ret;
1805 if (wire) {
1806 ret.wire = wire;
1807 ret.offset = this->offset + offset;
1808 ret.width = length;
1809 } else {
1810 for (int i = 0; i < length; i++)
1811 ret.data.bits.push_back(data.bits[offset+i]);
1812 ret.width = length;
1813 }
1814 return ret;
1815 }
1816
1817 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1818 {
1819 if (wire && other.wire)
1820 if (wire->name != other.wire->name)
1821 return wire->name < other.wire->name;
1822
1823 if (wire != other.wire)
1824 return wire < other.wire;
1825
1826 if (offset != other.offset)
1827 return offset < other.offset;
1828
1829 if (width != other.width)
1830 return width < other.width;
1831
1832 return data.bits < other.data.bits;
1833 }
1834
1835 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1836 {
1837 if (wire != other.wire || width != other.width || offset != other.offset)
1838 return false;
1839 if (data.bits != other.data.bits)
1840 return false;
1841 return true;
1842 }
1843
1844 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1845 {
1846 if (*this == other)
1847 return false;
1848 return true;
1849 }
1850
1851 RTLIL::SigSpec::SigSpec()
1852 {
1853 width_ = 0;
1854 hash_ = 0;
1855 }
1856
1857 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1858 {
1859 *this = other;
1860 }
1861
1862 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1863 {
1864 cover("kernel.rtlil.sigspec.init.list");
1865
1866 width_ = 0;
1867 hash_ = 0;
1868
1869 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1870 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1871 append(*it);
1872 }
1873
1874 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1875 {
1876 cover("kernel.rtlil.sigspec.assign");
1877
1878 width_ = other.width_;
1879 hash_ = other.hash_;
1880 chunks_ = other.chunks_;
1881 bits_.clear();
1882
1883 if (!other.bits_.empty())
1884 {
1885 RTLIL::SigChunk *last = NULL;
1886 int last_end_offset = 0;
1887
1888 for (auto &bit : other.bits_) {
1889 if (last && bit.wire == last->wire) {
1890 if (bit.wire == NULL) {
1891 last->data.bits.push_back(bit.data);
1892 last->width++;
1893 continue;
1894 } else if (last_end_offset == bit.offset) {
1895 last_end_offset++;
1896 last->width++;
1897 continue;
1898 }
1899 }
1900 chunks_.push_back(bit);
1901 last = &chunks_.back();
1902 last_end_offset = bit.offset + 1;
1903 }
1904
1905 check();
1906 }
1907
1908 return *this;
1909 }
1910
1911 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1912 {
1913 cover("kernel.rtlil.sigspec.init.const");
1914
1915 chunks_.push_back(RTLIL::SigChunk(value));
1916 width_ = chunks_.back().width;
1917 hash_ = 0;
1918 check();
1919 }
1920
1921 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1922 {
1923 cover("kernel.rtlil.sigspec.init.chunk");
1924
1925 chunks_.push_back(chunk);
1926 width_ = chunks_.back().width;
1927 hash_ = 0;
1928 check();
1929 }
1930
1931 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1932 {
1933 cover("kernel.rtlil.sigspec.init.wire");
1934
1935 chunks_.push_back(RTLIL::SigChunk(wire));
1936 width_ = chunks_.back().width;
1937 hash_ = 0;
1938 check();
1939 }
1940
1941 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1942 {
1943 cover("kernel.rtlil.sigspec.init.wire_part");
1944
1945 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1946 width_ = chunks_.back().width;
1947 hash_ = 0;
1948 check();
1949 }
1950
1951 RTLIL::SigSpec::SigSpec(const std::string &str)
1952 {
1953 cover("kernel.rtlil.sigspec.init.str");
1954
1955 chunks_.push_back(RTLIL::SigChunk(str));
1956 width_ = chunks_.back().width;
1957 hash_ = 0;
1958 check();
1959 }
1960
1961 RTLIL::SigSpec::SigSpec(int val, int width)
1962 {
1963 cover("kernel.rtlil.sigspec.init.int");
1964
1965 chunks_.push_back(RTLIL::SigChunk(val, width));
1966 width_ = width;
1967 hash_ = 0;
1968 check();
1969 }
1970
1971 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1972 {
1973 cover("kernel.rtlil.sigspec.init.state");
1974
1975 chunks_.push_back(RTLIL::SigChunk(bit, width));
1976 width_ = width;
1977 hash_ = 0;
1978 check();
1979 }
1980
1981 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1982 {
1983 cover("kernel.rtlil.sigspec.init.bit");
1984
1985 if (bit.wire == NULL)
1986 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1987 else
1988 for (int i = 0; i < width; i++)
1989 chunks_.push_back(bit);
1990 width_ = width;
1991 hash_ = 0;
1992 check();
1993 }
1994
1995 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1996 {
1997 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1998
1999 width_ = 0;
2000 hash_ = 0;
2001 for (auto &c : chunks)
2002 append(c);
2003 check();
2004 }
2005
2006 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2007 {
2008 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2009
2010 width_ = 0;
2011 hash_ = 0;
2012 for (auto &bit : bits)
2013 append_bit(bit);
2014 check();
2015 }
2016
2017 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2018 {
2019 cover("kernel.rtlil.sigspec.init.stdset_bits");
2020
2021 width_ = 0;
2022 hash_ = 0;
2023 for (auto &bit : bits)
2024 append_bit(bit);
2025 check();
2026 }
2027
2028 void RTLIL::SigSpec::pack() const
2029 {
2030 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2031
2032 if (that->bits_.empty())
2033 return;
2034
2035 cover("kernel.rtlil.sigspec.convert.pack");
2036 log_assert(that->chunks_.empty());
2037
2038 std::vector<RTLIL::SigBit> old_bits;
2039 old_bits.swap(that->bits_);
2040
2041 RTLIL::SigChunk *last = NULL;
2042 int last_end_offset = 0;
2043
2044 for (auto &bit : old_bits) {
2045 if (last && bit.wire == last->wire) {
2046 if (bit.wire == NULL) {
2047 last->data.bits.push_back(bit.data);
2048 last->width++;
2049 continue;
2050 } else if (last_end_offset == bit.offset) {
2051 last_end_offset++;
2052 last->width++;
2053 continue;
2054 }
2055 }
2056 that->chunks_.push_back(bit);
2057 last = &that->chunks_.back();
2058 last_end_offset = bit.offset + 1;
2059 }
2060
2061 check();
2062 }
2063
2064 void RTLIL::SigSpec::unpack() const
2065 {
2066 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2067
2068 if (that->chunks_.empty())
2069 return;
2070
2071 cover("kernel.rtlil.sigspec.convert.unpack");
2072 log_assert(that->bits_.empty());
2073
2074 that->bits_.reserve(that->width_);
2075 for (auto &c : that->chunks_)
2076 for (int i = 0; i < c.width; i++)
2077 that->bits_.push_back(RTLIL::SigBit(c, i));
2078
2079 that->chunks_.clear();
2080 that->hash_ = 0;
2081 }
2082
2083 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2084
2085 void RTLIL::SigSpec::hash() const
2086 {
2087 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2088
2089 if (that->hash_ != 0)
2090 return;
2091
2092 cover("kernel.rtlil.sigspec.hash");
2093 that->pack();
2094
2095 that->hash_ = 5381;
2096 for (auto &c : that->chunks_)
2097 if (c.wire == NULL) {
2098 for (auto &v : c.data.bits)
2099 DJB2(that->hash_, v);
2100 } else {
2101 DJB2(that->hash_, c.wire->name.index_);
2102 DJB2(that->hash_, c.offset);
2103 DJB2(that->hash_, c.width);
2104 }
2105
2106 if (that->hash_ == 0)
2107 that->hash_ = 1;
2108 }
2109
2110 void RTLIL::SigSpec::sort()
2111 {
2112 unpack();
2113 cover("kernel.rtlil.sigspec.sort");
2114 std::sort(bits_.begin(), bits_.end());
2115 }
2116
2117 void RTLIL::SigSpec::sort_and_unify()
2118 {
2119 cover("kernel.rtlil.sigspec.sort_and_unify");
2120 *this = this->to_sigbit_set();
2121 }
2122
2123 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2124 {
2125 replace(pattern, with, this);
2126 }
2127
2128 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2129 {
2130 log_assert(pattern.width_ == with.width_);
2131
2132 pattern.unpack();
2133 with.unpack();
2134
2135 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2136
2137 for (int i = 0; i < SIZE(pattern.bits_); i++)
2138 if (pattern.bits_[i].wire != NULL)
2139 rules[pattern.bits_[i]] = with.bits_[i];
2140
2141 replace(rules, other);
2142 }
2143
2144 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2145 {
2146 replace(rules, this);
2147 }
2148
2149 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2150 {
2151 cover("kernel.rtlil.sigspec.replace");
2152
2153 log_assert(other != NULL);
2154 log_assert(width_ == other->width_);
2155
2156 unpack();
2157 other->unpack();
2158
2159 for (int i = 0; i < SIZE(bits_); i++) {
2160 auto it = rules.find(bits_[i]);
2161 if (it != rules.end())
2162 other->bits_[i] = it->second;
2163 }
2164
2165 other->check();
2166 }
2167
2168 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2169 {
2170 remove2(pattern, NULL);
2171 }
2172
2173 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2174 {
2175 RTLIL::SigSpec tmp = *this;
2176 tmp.remove2(pattern, other);
2177 }
2178
2179 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2180 {
2181 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2182 remove2(pattern_bits, other);
2183 }
2184
2185 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2186 {
2187 remove2(pattern, NULL);
2188 }
2189
2190 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2191 {
2192 RTLIL::SigSpec tmp = *this;
2193 tmp.remove2(pattern, other);
2194 }
2195
2196 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2197 {
2198 if (other)
2199 cover("kernel.rtlil.sigspec.remove_other");
2200 else
2201 cover("kernel.rtlil.sigspec.remove");
2202
2203 unpack();
2204
2205 if (other != NULL) {
2206 log_assert(width_ == other->width_);
2207 other->unpack();
2208 }
2209
2210 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2211
2212 new_bits.resize(SIZE(bits_));
2213 if (other != NULL)
2214 new_other_bits.resize(SIZE(bits_));
2215
2216 int k = 0;
2217 for (int i = 0; i < SIZE(bits_); i++) {
2218 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2219 continue;
2220 if (other != NULL)
2221 new_other_bits[k] = other->bits_[i];
2222 new_bits[k++] = bits_[i];
2223 }
2224
2225 new_bits.resize(k);
2226 if (other != NULL)
2227 new_other_bits.resize(k);
2228
2229 bits_.swap(new_bits);
2230 width_ = SIZE(bits_);
2231
2232 if (other != NULL) {
2233 other->bits_.swap(new_other_bits);
2234 other->width_ = SIZE(other->bits_);
2235 }
2236
2237 check();
2238 }
2239
2240 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2241 {
2242 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2243 return extract(pattern_bits, other);
2244 }
2245
2246 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2247 {
2248 if (other)
2249 cover("kernel.rtlil.sigspec.extract_other");
2250 else
2251 cover("kernel.rtlil.sigspec.extract");
2252
2253 log_assert(other == NULL || width_ == other->width_);
2254
2255 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2256 RTLIL::SigSpec ret;
2257
2258 if (other) {
2259 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2260 for (int i = 0; i < width_; i++)
2261 if (bits_match[i].wire && pattern.count(bits_match[i]))
2262 ret.append_bit(bits_other[i]);
2263 } else {
2264 for (int i = 0; i < width_; i++)
2265 if (bits_match[i].wire && pattern.count(bits_match[i]))
2266 ret.append_bit(bits_match[i]);
2267 }
2268
2269 ret.check();
2270 return ret;
2271 }
2272
2273 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2274 {
2275 cover("kernel.rtlil.sigspec.replace_pos");
2276
2277 unpack();
2278 with.unpack();
2279
2280 log_assert(offset >= 0);
2281 log_assert(with.width_ >= 0);
2282 log_assert(offset+with.width_ <= width_);
2283
2284 for (int i = 0; i < with.width_; i++)
2285 bits_.at(offset + i) = with.bits_.at(i);
2286
2287 check();
2288 }
2289
2290 void RTLIL::SigSpec::remove_const()
2291 {
2292 if (packed())
2293 {
2294 cover("kernel.rtlil.sigspec.remove_const.packed");
2295
2296 std::vector<RTLIL::SigChunk> new_chunks;
2297 new_chunks.reserve(SIZE(chunks_));
2298
2299 width_ = 0;
2300 for (auto &chunk : chunks_)
2301 if (chunk.wire != NULL) {
2302 new_chunks.push_back(chunk);
2303 width_ += chunk.width;
2304 }
2305
2306 chunks_.swap(new_chunks);
2307 }
2308 else
2309 {
2310 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2311
2312 std::vector<RTLIL::SigBit> new_bits;
2313 new_bits.reserve(width_);
2314
2315 for (auto &bit : bits_)
2316 if (bit.wire != NULL)
2317 new_bits.push_back(bit);
2318
2319 bits_.swap(new_bits);
2320 width_ = bits_.size();
2321 }
2322
2323 check();
2324 }
2325
2326 void RTLIL::SigSpec::remove(int offset, int length)
2327 {
2328 cover("kernel.rtlil.sigspec.remove_pos");
2329
2330 unpack();
2331
2332 log_assert(offset >= 0);
2333 log_assert(length >= 0);
2334 log_assert(offset + length <= width_);
2335
2336 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2337 width_ = bits_.size();
2338
2339 check();
2340 }
2341
2342 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2343 {
2344 unpack();
2345 cover("kernel.rtlil.sigspec.extract_pos");
2346 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2347 }
2348
2349 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2350 {
2351 if (signal.width_ == 0)
2352 return;
2353
2354 if (width_ == 0) {
2355 *this = signal;
2356 return;
2357 }
2358
2359 cover("kernel.rtlil.sigspec.append");
2360
2361 if (packed() != signal.packed()) {
2362 pack();
2363 signal.pack();
2364 }
2365
2366 if (packed())
2367 for (auto &other_c : signal.chunks_)
2368 {
2369 auto &my_last_c = chunks_.back();
2370 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2371 auto &this_data = my_last_c.data.bits;
2372 auto &other_data = other_c.data.bits;
2373 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2374 my_last_c.width += other_c.width;
2375 } else
2376 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2377 my_last_c.width += other_c.width;
2378 } else
2379 chunks_.push_back(other_c);
2380 }
2381 else
2382 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2383
2384 width_ += signal.width_;
2385 check();
2386 }
2387
2388 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2389 {
2390 if (packed())
2391 {
2392 cover("kernel.rtlil.sigspec.append_bit.packed");
2393
2394 if (chunks_.size() == 0)
2395 chunks_.push_back(bit);
2396 else
2397 if (bit.wire == NULL)
2398 if (chunks_.back().wire == NULL) {
2399 chunks_.back().data.bits.push_back(bit.data);
2400 chunks_.back().width++;
2401 } else
2402 chunks_.push_back(bit);
2403 else
2404 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2405 chunks_.back().width++;
2406 else
2407 chunks_.push_back(bit);
2408 }
2409 else
2410 {
2411 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2412 bits_.push_back(bit);
2413 }
2414
2415 width_++;
2416 check();
2417 }
2418
2419 void RTLIL::SigSpec::extend(int width, bool is_signed)
2420 {
2421 cover("kernel.rtlil.sigspec.extend");
2422
2423 pack();
2424
2425 if (width_ > width)
2426 remove(width, width_ - width);
2427
2428 if (width_ < width) {
2429 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2430 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2431 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2432 padding = RTLIL::SigSpec(RTLIL::State::S0);
2433 while (width_ < width)
2434 append(padding);
2435 }
2436 }
2437
2438 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2439 {
2440 cover("kernel.rtlil.sigspec.extend_u0");
2441
2442 pack();
2443
2444 if (width_ > width)
2445 remove(width, width_ - width);
2446
2447 if (width_ < width) {
2448 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2449 if (!is_signed)
2450 padding = RTLIL::SigSpec(RTLIL::State::S0);
2451 while (width_ < width)
2452 append(padding);
2453 }
2454
2455 }
2456
2457 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2458 {
2459 cover("kernel.rtlil.sigspec.repeat");
2460
2461 RTLIL::SigSpec sig;
2462 for (int i = 0; i < num; i++)
2463 sig.append(*this);
2464 return sig;
2465 }
2466
2467 #ifndef NDEBUG
2468 void RTLIL::SigSpec::check() const
2469 {
2470 if (width_ > 64)
2471 {
2472 cover("kernel.rtlil.sigspec.check.skip");
2473 }
2474 else if (packed())
2475 {
2476 cover("kernel.rtlil.sigspec.check.packed");
2477
2478 int w = 0;
2479 for (size_t i = 0; i < chunks_.size(); i++) {
2480 const RTLIL::SigChunk chunk = chunks_[i];
2481 if (chunk.wire == NULL) {
2482 if (i > 0)
2483 log_assert(chunks_[i-1].wire != NULL);
2484 log_assert(chunk.offset == 0);
2485 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2486 } else {
2487 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2488 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2489 log_assert(chunk.offset >= 0);
2490 log_assert(chunk.width >= 0);
2491 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2492 log_assert(chunk.data.bits.size() == 0);
2493 }
2494 w += chunk.width;
2495 }
2496 log_assert(w == width_);
2497 log_assert(bits_.empty());
2498 }
2499 else
2500 {
2501 cover("kernel.rtlil.sigspec.check.unpacked");
2502
2503 log_assert(width_ == SIZE(bits_));
2504 log_assert(chunks_.empty());
2505 }
2506 }
2507 #endif
2508
2509 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2510 {
2511 cover("kernel.rtlil.sigspec.comp_lt");
2512
2513 if (this == &other)
2514 return false;
2515
2516 if (width_ != other.width_)
2517 return width_ < other.width_;
2518
2519 pack();
2520 other.pack();
2521
2522 if (chunks_.size() != other.chunks_.size())
2523 return chunks_.size() < other.chunks_.size();
2524
2525 hash();
2526 other.hash();
2527
2528 if (hash_ != other.hash_)
2529 return hash_ < other.hash_;
2530
2531 for (size_t i = 0; i < chunks_.size(); i++)
2532 if (chunks_[i] != other.chunks_[i]) {
2533 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2534 return chunks_[i] < other.chunks_[i];
2535 }
2536
2537 cover("kernel.rtlil.sigspec.comp_lt.equal");
2538 return false;
2539 }
2540
2541 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2542 {
2543 cover("kernel.rtlil.sigspec.comp_eq");
2544
2545 if (this == &other)
2546 return true;
2547
2548 if (width_ != other.width_)
2549 return false;
2550
2551 pack();
2552 other.pack();
2553
2554 if (chunks_.size() != chunks_.size())
2555 return false;
2556
2557 hash();
2558 other.hash();
2559
2560 if (hash_ != other.hash_)
2561 return false;
2562
2563 for (size_t i = 0; i < chunks_.size(); i++)
2564 if (chunks_[i] != other.chunks_[i]) {
2565 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2566 return false;
2567 }
2568
2569 cover("kernel.rtlil.sigspec.comp_eq.equal");
2570 return true;
2571 }
2572
2573 bool RTLIL::SigSpec::is_wire() const
2574 {
2575 cover("kernel.rtlil.sigspec.is_wire");
2576
2577 pack();
2578 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2579 }
2580
2581 bool RTLIL::SigSpec::is_chunk() const
2582 {
2583 cover("kernel.rtlil.sigspec.is_chunk");
2584
2585 pack();
2586 return SIZE(chunks_) == 1;
2587 }
2588
2589 bool RTLIL::SigSpec::is_fully_const() const
2590 {
2591 cover("kernel.rtlil.sigspec.is_fully_const");
2592
2593 pack();
2594 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2595 if (it->width > 0 && it->wire != NULL)
2596 return false;
2597 return true;
2598 }
2599
2600 bool RTLIL::SigSpec::is_fully_def() const
2601 {
2602 cover("kernel.rtlil.sigspec.is_fully_def");
2603
2604 pack();
2605 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2606 if (it->width > 0 && it->wire != NULL)
2607 return false;
2608 for (size_t i = 0; i < it->data.bits.size(); i++)
2609 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2610 return false;
2611 }
2612 return true;
2613 }
2614
2615 bool RTLIL::SigSpec::is_fully_undef() const
2616 {
2617 cover("kernel.rtlil.sigspec.is_fully_undef");
2618
2619 pack();
2620 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2621 if (it->width > 0 && it->wire != NULL)
2622 return false;
2623 for (size_t i = 0; i < it->data.bits.size(); i++)
2624 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2625 return false;
2626 }
2627 return true;
2628 }
2629
2630 bool RTLIL::SigSpec::has_marked_bits() const
2631 {
2632 cover("kernel.rtlil.sigspec.has_marked_bits");
2633
2634 pack();
2635 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2636 if (it->width > 0 && it->wire == NULL) {
2637 for (size_t i = 0; i < it->data.bits.size(); i++)
2638 if (it->data.bits[i] == RTLIL::State::Sm)
2639 return true;
2640 }
2641 return false;
2642 }
2643
2644 bool RTLIL::SigSpec::as_bool() const
2645 {
2646 cover("kernel.rtlil.sigspec.as_bool");
2647
2648 pack();
2649 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2650 if (width_)
2651 return chunks_[0].data.as_bool();
2652 return false;
2653 }
2654
2655 int RTLIL::SigSpec::as_int() const
2656 {
2657 cover("kernel.rtlil.sigspec.as_int");
2658
2659 pack();
2660 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2661 if (width_)
2662 return chunks_[0].data.as_int();
2663 return 0;
2664 }
2665
2666 std::string RTLIL::SigSpec::as_string() const
2667 {
2668 cover("kernel.rtlil.sigspec.as_string");
2669
2670 pack();
2671 std::string str;
2672 for (size_t i = chunks_.size(); i > 0; i--) {
2673 const RTLIL::SigChunk &chunk = chunks_[i-1];
2674 if (chunk.wire != NULL)
2675 for (int j = 0; j < chunk.width; j++)
2676 str += "?";
2677 else
2678 str += chunk.data.as_string();
2679 }
2680 return str;
2681 }
2682
2683 RTLIL::Const RTLIL::SigSpec::as_const() const
2684 {
2685 cover("kernel.rtlil.sigspec.as_const");
2686
2687 pack();
2688 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2689 if (width_)
2690 return chunks_[0].data;
2691 return RTLIL::Const();
2692 }
2693
2694 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2695 {
2696 cover("kernel.rtlil.sigspec.as_wire");
2697
2698 pack();
2699 log_assert(is_wire());
2700 return chunks_[0].wire;
2701 }
2702
2703 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2704 {
2705 cover("kernel.rtlil.sigspec.as_chunk");
2706
2707 pack();
2708 log_assert(is_chunk());
2709 return chunks_[0];
2710 }
2711
2712 bool RTLIL::SigSpec::match(std::string pattern) const
2713 {
2714 cover("kernel.rtlil.sigspec.match");
2715
2716 pack();
2717 std::string str = as_string();
2718 log_assert(pattern.size() == str.size());
2719
2720 for (size_t i = 0; i < pattern.size(); i++) {
2721 if (pattern[i] == ' ')
2722 continue;
2723 if (pattern[i] == '*') {
2724 if (str[i] != 'z' && str[i] != 'x')
2725 return false;
2726 continue;
2727 }
2728 if (pattern[i] != str[i])
2729 return false;
2730 }
2731
2732 return true;
2733 }
2734
2735 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2736 {
2737 cover("kernel.rtlil.sigspec.to_sigbit_set");
2738
2739 pack();
2740 std::set<RTLIL::SigBit> sigbits;
2741 for (auto &c : chunks_)
2742 for (int i = 0; i < c.width; i++)
2743 sigbits.insert(RTLIL::SigBit(c, i));
2744 return sigbits;
2745 }
2746
2747 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2748 {
2749 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2750
2751 unpack();
2752 return bits_;
2753 }
2754
2755 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2756 {
2757 cover("kernel.rtlil.sigspec.to_sigbit_map");
2758
2759 unpack();
2760 other.unpack();
2761
2762 log_assert(width_ == other.width_);
2763
2764 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2765 for (int i = 0; i < width_; i++)
2766 new_map[bits_[i]] = other.bits_[i];
2767
2768 return new_map;
2769 }
2770
2771 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2772 {
2773 cover("kernel.rtlil.sigspec.to_single_sigbit");
2774
2775 pack();
2776 log_assert(width_ == 1);
2777 for (auto &c : chunks_)
2778 if (c.width)
2779 return RTLIL::SigBit(c);
2780 log_abort();
2781 }
2782
2783 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2784 {
2785 size_t start = 0, end = 0;
2786 while ((end = text.find(sep, start)) != std::string::npos) {
2787 tokens.push_back(text.substr(start, end - start));
2788 start = end + 1;
2789 }
2790 tokens.push_back(text.substr(start));
2791 }
2792
2793 static int sigspec_parse_get_dummy_line_num()
2794 {
2795 return 0;
2796 }
2797
2798 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2799 {
2800 cover("kernel.rtlil.sigspec.parse");
2801
2802 std::vector<std::string> tokens;
2803 sigspec_parse_split(tokens, str, ',');
2804
2805 sig = RTLIL::SigSpec();
2806 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2807 {
2808 std::string netname = tokens[tokidx];
2809 std::string indices;
2810
2811 if (netname.size() == 0)
2812 continue;
2813
2814 if ('0' <= netname[0] && netname[0] <= '9') {
2815 cover("kernel.rtlil.sigspec.parse.const");
2816 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2817 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2818 if (ast == NULL)
2819 return false;
2820 sig.append(RTLIL::Const(ast->bits));
2821 delete ast;
2822 continue;
2823 }
2824
2825 if (module == NULL)
2826 return false;
2827
2828 cover("kernel.rtlil.sigspec.parse.net");
2829
2830 if (netname[0] != '$' && netname[0] != '\\')
2831 netname = "\\" + netname;
2832
2833 if (module->wires_.count(netname) == 0) {
2834 size_t indices_pos = netname.size()-1;
2835 if (indices_pos > 2 && netname[indices_pos] == ']')
2836 {
2837 indices_pos--;
2838 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2839 if (indices_pos > 0 && netname[indices_pos] == ':') {
2840 indices_pos--;
2841 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2842 }
2843 if (indices_pos > 0 && netname[indices_pos] == '[') {
2844 indices = netname.substr(indices_pos);
2845 netname = netname.substr(0, indices_pos);
2846 }
2847 }
2848 }
2849
2850 if (module->wires_.count(netname) == 0)
2851 return false;
2852
2853 RTLIL::Wire *wire = module->wires_.at(netname);
2854 if (!indices.empty()) {
2855 std::vector<std::string> index_tokens;
2856 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2857 if (index_tokens.size() == 1) {
2858 cover("kernel.rtlil.sigspec.parse.bit_sel");
2859 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2860 } else {
2861 cover("kernel.rtlil.sigspec.parse.part_sel");
2862 int a = atoi(index_tokens.at(0).c_str());
2863 int b = atoi(index_tokens.at(1).c_str());
2864 if (a > b) {
2865 int tmp = a;
2866 a = b, b = tmp;
2867 }
2868 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2869 }
2870 } else
2871 sig.append(wire);
2872 }
2873
2874 return true;
2875 }
2876
2877 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2878 {
2879 if (str.empty() || str[0] != '@')
2880 return parse(sig, module, str);
2881
2882 cover("kernel.rtlil.sigspec.parse.sel");
2883
2884 str = RTLIL::escape_id(str.substr(1));
2885 if (design->selection_vars.count(str) == 0)
2886 return false;
2887
2888 sig = RTLIL::SigSpec();
2889 RTLIL::Selection &sel = design->selection_vars.at(str);
2890 for (auto &it : module->wires_)
2891 if (sel.selected_member(module->name, it.first))
2892 sig.append(it.second);
2893
2894 return true;
2895 }
2896
2897 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2898 {
2899 if (str == "0") {
2900 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2901 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2902 return true;
2903 }
2904
2905 if (str == "~0") {
2906 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2907 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2908 return true;
2909 }
2910
2911 if (lhs.chunks_.size() == 1) {
2912 char *p = (char*)str.c_str(), *endptr;
2913 long long int val = strtoll(p, &endptr, 10);
2914 if (endptr && endptr != p && *endptr == 0) {
2915 sig = RTLIL::SigSpec(val, lhs.width_);
2916 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2917 return true;
2918 }
2919 }
2920
2921 return parse(sig, module, str);
2922 }
2923
2924 RTLIL::CaseRule::~CaseRule()
2925 {
2926 for (auto it = switches.begin(); it != switches.end(); it++)
2927 delete *it;
2928 }
2929
2930 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2931 {
2932 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2933 new_caserule->compare = compare;
2934 new_caserule->actions = actions;
2935 for (auto &it : switches)
2936 new_caserule->switches.push_back(it->clone());
2937 return new_caserule;
2938 }
2939
2940 RTLIL::SwitchRule::~SwitchRule()
2941 {
2942 for (auto it = cases.begin(); it != cases.end(); it++)
2943 delete *it;
2944 }
2945
2946 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2947 {
2948 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2949 new_switchrule->signal = signal;
2950 new_switchrule->attributes = attributes;
2951 for (auto &it : cases)
2952 new_switchrule->cases.push_back(it->clone());
2953 return new_switchrule;
2954
2955 }
2956
2957 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2958 {
2959 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2960 new_syncrule->type = type;
2961 new_syncrule->signal = signal;
2962 new_syncrule->actions = actions;
2963 return new_syncrule;
2964 }
2965
2966 RTLIL::Process::~Process()
2967 {
2968 for (auto it = syncs.begin(); it != syncs.end(); it++)
2969 delete *it;
2970 }
2971
2972 RTLIL::Process *RTLIL::Process::clone() const
2973 {
2974 RTLIL::Process *new_proc = new RTLIL::Process;
2975
2976 new_proc->name = name;
2977 new_proc->attributes = attributes;
2978
2979 RTLIL::CaseRule *rc_ptr = root_case.clone();
2980 new_proc->root_case = *rc_ptr;
2981 rc_ptr->switches.clear();
2982 delete rc_ptr;
2983
2984 for (auto &it : syncs)
2985 new_proc->syncs.push_back(it->clone());
2986
2987 return new_proc;
2988 }
2989
2990 YOSYS_NAMESPACE_END
2991