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Merge pull request #2128 from whitequark/flatten-processes
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($adff),
58 ID($dlatch),
59 ID($dlatchsr),
60 ID($_DFFE_NN_),
61 ID($_DFFE_NP_),
62 ID($_DFFE_PN_),
63 ID($_DFFE_PP_),
64 ID($_DFFSR_NNN_),
65 ID($_DFFSR_NNP_),
66 ID($_DFFSR_NPN_),
67 ID($_DFFSR_NPP_),
68 ID($_DFFSR_PNN_),
69 ID($_DFFSR_PNP_),
70 ID($_DFFSR_PPN_),
71 ID($_DFFSR_PPP_),
72 ID($_DFF_NN0_),
73 ID($_DFF_NN1_),
74 ID($_DFF_NP0_),
75 ID($_DFF_NP1_),
76 ID($_DFF_N_),
77 ID($_DFF_PN0_),
78 ID($_DFF_PN1_),
79 ID($_DFF_PP0_),
80 ID($_DFF_PP1_),
81 ID($_DFF_P_),
82 ID($_DLATCHSR_NNN_),
83 ID($_DLATCHSR_NNP_),
84 ID($_DLATCHSR_NPN_),
85 ID($_DLATCHSR_NPP_),
86 ID($_DLATCHSR_PNN_),
87 ID($_DLATCHSR_PNP_),
88 ID($_DLATCHSR_PPN_),
89 ID($_DLATCHSR_PPP_),
90 ID($_DLATCH_N_),
91 ID($_DLATCH_P_),
92 ID($_FF_),
93 };
94 return res;
95 }
96
97 RTLIL::Const::Const()
98 {
99 flags = RTLIL::CONST_FLAG_NONE;
100 }
101
102 RTLIL::Const::Const(std::string str)
103 {
104 flags = RTLIL::CONST_FLAG_STRING;
105 for (int i = str.size()-1; i >= 0; i--) {
106 unsigned char ch = str[i];
107 for (int j = 0; j < 8; j++) {
108 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
109 ch = ch >> 1;
110 }
111 }
112 }
113
114 RTLIL::Const::Const(int val, int width)
115 {
116 flags = RTLIL::CONST_FLAG_NONE;
117 for (int i = 0; i < width; i++) {
118 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
119 val = val >> 1;
120 }
121 }
122
123 RTLIL::Const::Const(RTLIL::State bit, int width)
124 {
125 flags = RTLIL::CONST_FLAG_NONE;
126 for (int i = 0; i < width; i++)
127 bits.push_back(bit);
128 }
129
130 RTLIL::Const::Const(const std::vector<bool> &bits)
131 {
132 flags = RTLIL::CONST_FLAG_NONE;
133 for (const auto &b : bits)
134 this->bits.emplace_back(b ? State::S1 : State::S0);
135 }
136
137 RTLIL::Const::Const(const RTLIL::Const &c)
138 {
139 flags = c.flags;
140 for (const auto &b : c.bits)
141 this->bits.push_back(b);
142 }
143
144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
145 {
146 if (bits.size() != other.bits.size())
147 return bits.size() < other.bits.size();
148 for (size_t i = 0; i < bits.size(); i++)
149 if (bits[i] != other.bits[i])
150 return bits[i] < other.bits[i];
151 return false;
152 }
153
154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
155 {
156 return bits == other.bits;
157 }
158
159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
160 {
161 return bits != other.bits;
162 }
163
164 bool RTLIL::Const::as_bool() const
165 {
166 for (size_t i = 0; i < bits.size(); i++)
167 if (bits[i] == State::S1)
168 return true;
169 return false;
170 }
171
172 int RTLIL::Const::as_int(bool is_signed) const
173 {
174 int32_t ret = 0;
175 for (size_t i = 0; i < bits.size() && i < 32; i++)
176 if (bits[i] == State::S1)
177 ret |= 1 << i;
178 if (is_signed && bits.back() == State::S1)
179 for (size_t i = bits.size(); i < 32; i++)
180 ret |= 1 << i;
181 return ret;
182 }
183
184 std::string RTLIL::Const::as_string() const
185 {
186 std::string ret;
187 ret.reserve(bits.size());
188 for (size_t i = bits.size(); i > 0; i--)
189 switch (bits[i-1]) {
190 case S0: ret += "0"; break;
191 case S1: ret += "1"; break;
192 case Sx: ret += "x"; break;
193 case Sz: ret += "z"; break;
194 case Sa: ret += "-"; break;
195 case Sm: ret += "m"; break;
196 }
197 return ret;
198 }
199
200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
201 {
202 Const c;
203 c.bits.reserve(str.size());
204 for (auto it = str.rbegin(); it != str.rend(); it++)
205 switch (*it) {
206 case '0': c.bits.push_back(State::S0); break;
207 case '1': c.bits.push_back(State::S1); break;
208 case 'x': c.bits.push_back(State::Sx); break;
209 case 'z': c.bits.push_back(State::Sz); break;
210 case 'm': c.bits.push_back(State::Sm); break;
211 default: c.bits.push_back(State::Sa);
212 }
213 return c;
214 }
215
216 std::string RTLIL::Const::decode_string() const
217 {
218 std::string string;
219 string.reserve(GetSize(bits)/8);
220 for (int i = 0; i < GetSize(bits); i += 8) {
221 char ch = 0;
222 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
223 if (bits[i + j] == RTLIL::State::S1)
224 ch |= 1 << j;
225 if (ch != 0)
226 string.append({ch});
227 }
228 std::reverse(string.begin(), string.end());
229 return string;
230 }
231
232 bool RTLIL::Const::is_fully_zero() const
233 {
234 cover("kernel.rtlil.const.is_fully_zero");
235
236 for (const auto &bit : bits)
237 if (bit != RTLIL::State::S0)
238 return false;
239
240 return true;
241 }
242
243 bool RTLIL::Const::is_fully_ones() const
244 {
245 cover("kernel.rtlil.const.is_fully_ones");
246
247 for (const auto &bit : bits)
248 if (bit != RTLIL::State::S1)
249 return false;
250
251 return true;
252 }
253
254 bool RTLIL::Const::is_fully_def() const
255 {
256 cover("kernel.rtlil.const.is_fully_def");
257
258 for (const auto &bit : bits)
259 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
260 return false;
261
262 return true;
263 }
264
265 bool RTLIL::Const::is_fully_undef() const
266 {
267 cover("kernel.rtlil.const.is_fully_undef");
268
269 for (const auto &bit : bits)
270 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
271 return false;
272
273 return true;
274 }
275
276 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
277 {
278 return attributes.count(id);
279 }
280
281 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
282 {
283 if (value)
284 attributes[id] = RTLIL::Const(1);
285 else
286 attributes.erase(id);
287 }
288
289 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
290 {
291 const auto it = attributes.find(id);
292 if (it == attributes.end())
293 return false;
294 return it->second.as_bool();
295 }
296
297 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
298 {
299 if (value.empty())
300 attributes.erase(id);
301 else
302 attributes[id] = value;
303 }
304
305 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
306 {
307 std::string value;
308 const auto it = attributes.find(id);
309 if (it != attributes.end())
310 value = it->second.decode_string();
311 return value;
312 }
313
314 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
315 {
316 string attrval;
317 for (const auto &s : data) {
318 if (!attrval.empty())
319 attrval += "|";
320 attrval += s;
321 }
322 set_string_attribute(id, attrval);
323 }
324
325 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
326 {
327 pool<string> union_data = get_strpool_attribute(id);
328 union_data.insert(data.begin(), data.end());
329 if (!union_data.empty())
330 set_strpool_attribute(id, union_data);
331 }
332
333 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
334 {
335 pool<string> data;
336 if (attributes.count(id) != 0)
337 for (auto s : split_tokens(get_string_attribute(id), "|"))
338 data.insert(s);
339 return data;
340 }
341
342 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
343 {
344 string attrval;
345 for (const auto &ident : hierarchy) {
346 if (!attrval.empty())
347 attrval += " ";
348 attrval += ident;
349 }
350 set_string_attribute(ID::hdlname, attrval);
351 }
352
353 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
354 {
355 return split_tokens(get_string_attribute(ID::hdlname), " ");
356 }
357
358 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
359 {
360 if (full_selection)
361 return true;
362 if (selected_modules.count(mod_name) > 0)
363 return true;
364 if (selected_members.count(mod_name) > 0)
365 return true;
366 return false;
367 }
368
369 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
370 {
371 if (full_selection)
372 return true;
373 if (selected_modules.count(mod_name) > 0)
374 return true;
375 return false;
376 }
377
378 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
379 {
380 if (full_selection)
381 return true;
382 if (selected_modules.count(mod_name) > 0)
383 return true;
384 if (selected_members.count(mod_name) > 0)
385 if (selected_members.at(mod_name).count(memb_name) > 0)
386 return true;
387 return false;
388 }
389
390 void RTLIL::Selection::optimize(RTLIL::Design *design)
391 {
392 if (full_selection) {
393 selected_modules.clear();
394 selected_members.clear();
395 return;
396 }
397
398 std::vector<RTLIL::IdString> del_list, add_list;
399
400 del_list.clear();
401 for (auto mod_name : selected_modules) {
402 if (design->modules_.count(mod_name) == 0)
403 del_list.push_back(mod_name);
404 selected_members.erase(mod_name);
405 }
406 for (auto mod_name : del_list)
407 selected_modules.erase(mod_name);
408
409 del_list.clear();
410 for (auto &it : selected_members)
411 if (design->modules_.count(it.first) == 0)
412 del_list.push_back(it.first);
413 for (auto mod_name : del_list)
414 selected_members.erase(mod_name);
415
416 for (auto &it : selected_members) {
417 del_list.clear();
418 for (auto memb_name : it.second)
419 if (design->modules_[it.first]->count_id(memb_name) == 0)
420 del_list.push_back(memb_name);
421 for (auto memb_name : del_list)
422 it.second.erase(memb_name);
423 }
424
425 del_list.clear();
426 add_list.clear();
427 for (auto &it : selected_members)
428 if (it.second.size() == 0)
429 del_list.push_back(it.first);
430 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
431 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
432 add_list.push_back(it.first);
433 for (auto mod_name : del_list)
434 selected_members.erase(mod_name);
435 for (auto mod_name : add_list) {
436 selected_members.erase(mod_name);
437 selected_modules.insert(mod_name);
438 }
439
440 if (selected_modules.size() == design->modules_.size()) {
441 full_selection = true;
442 selected_modules.clear();
443 selected_members.clear();
444 }
445 }
446
447 RTLIL::Design::Design()
448 : verilog_defines (new define_map_t)
449 {
450 static unsigned int hashidx_count = 123456789;
451 hashidx_count = mkhash_xorshift(hashidx_count);
452 hashidx_ = hashidx_count;
453
454 refcount_modules_ = 0;
455 selection_stack.push_back(RTLIL::Selection());
456
457 #ifdef WITH_PYTHON
458 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
459 #endif
460 }
461
462 RTLIL::Design::~Design()
463 {
464 for (auto it = modules_.begin(); it != modules_.end(); ++it)
465 delete it->second;
466 for (auto n : verilog_packages)
467 delete n;
468 for (auto n : verilog_globals)
469 delete n;
470 #ifdef WITH_PYTHON
471 RTLIL::Design::get_all_designs()->erase(hashidx_);
472 #endif
473 }
474
475 #ifdef WITH_PYTHON
476 static std::map<unsigned int, RTLIL::Design*> all_designs;
477 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
478 {
479 return &all_designs;
480 }
481 #endif
482
483 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
484 {
485 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
486 }
487
488 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
489 {
490 return modules_.count(name) ? modules_.at(name) : NULL;
491 }
492
493 RTLIL::Module *RTLIL::Design::top_module()
494 {
495 RTLIL::Module *module = nullptr;
496 int module_count = 0;
497
498 for (auto mod : selected_modules()) {
499 if (mod->get_bool_attribute(ID::top))
500 return mod;
501 module_count++;
502 module = mod;
503 }
504
505 return module_count == 1 ? module : nullptr;
506 }
507
508 void RTLIL::Design::add(RTLIL::Module *module)
509 {
510 log_assert(modules_.count(module->name) == 0);
511 log_assert(refcount_modules_ == 0);
512 modules_[module->name] = module;
513 module->design = this;
514
515 for (auto mon : monitors)
516 mon->notify_module_add(module);
517
518 if (yosys_xtrace) {
519 log("#X# New Module: %s\n", log_id(module));
520 log_backtrace("-X- ", yosys_xtrace-1);
521 }
522 }
523
524 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
525 {
526 log_assert(modules_.count(name) == 0);
527 log_assert(refcount_modules_ == 0);
528
529 RTLIL::Module *module = new RTLIL::Module;
530 modules_[name] = module;
531 module->design = this;
532 module->name = name;
533
534 for (auto mon : monitors)
535 mon->notify_module_add(module);
536
537 if (yosys_xtrace) {
538 log("#X# New Module: %s\n", log_id(module));
539 log_backtrace("-X- ", yosys_xtrace-1);
540 }
541
542 return module;
543 }
544
545 void RTLIL::Design::scratchpad_unset(const std::string &varname)
546 {
547 scratchpad.erase(varname);
548 }
549
550 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
551 {
552 scratchpad[varname] = stringf("%d", value);
553 }
554
555 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
556 {
557 scratchpad[varname] = value ? "true" : "false";
558 }
559
560 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
561 {
562 scratchpad[varname] = std::move(value);
563 }
564
565 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
566 {
567 auto it = scratchpad.find(varname);
568 if (it == scratchpad.end())
569 return default_value;
570
571 const std::string &str = it->second;
572
573 if (str == "0" || str == "false")
574 return 0;
575
576 if (str == "1" || str == "true")
577 return 1;
578
579 char *endptr = nullptr;
580 long int parsed_value = strtol(str.c_str(), &endptr, 10);
581 return *endptr ? default_value : parsed_value;
582 }
583
584 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
585 {
586 auto it = scratchpad.find(varname);
587 if (it == scratchpad.end())
588 return default_value;
589
590 const std::string &str = it->second;
591
592 if (str == "0" || str == "false")
593 return false;
594
595 if (str == "1" || str == "true")
596 return true;
597
598 return default_value;
599 }
600
601 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
602 {
603 auto it = scratchpad.find(varname);
604 if (it == scratchpad.end())
605 return default_value;
606
607 return it->second;
608 }
609
610 void RTLIL::Design::remove(RTLIL::Module *module)
611 {
612 for (auto mon : monitors)
613 mon->notify_module_del(module);
614
615 if (yosys_xtrace) {
616 log("#X# Remove Module: %s\n", log_id(module));
617 log_backtrace("-X- ", yosys_xtrace-1);
618 }
619
620 log_assert(modules_.at(module->name) == module);
621 log_assert(refcount_modules_ == 0);
622 modules_.erase(module->name);
623 delete module;
624 }
625
626 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
627 {
628 modules_.erase(module->name);
629 module->name = new_name;
630 add(module);
631 }
632
633 void RTLIL::Design::sort()
634 {
635 scratchpad.sort();
636 modules_.sort(sort_by_id_str());
637 for (auto &it : modules_)
638 it.second->sort();
639 }
640
641 void RTLIL::Design::check()
642 {
643 #ifndef NDEBUG
644 for (auto &it : modules_) {
645 log_assert(this == it.second->design);
646 log_assert(it.first == it.second->name);
647 log_assert(!it.first.empty());
648 it.second->check();
649 }
650 #endif
651 }
652
653 void RTLIL::Design::optimize()
654 {
655 for (auto &it : modules_)
656 it.second->optimize();
657 for (auto &it : selection_stack)
658 it.optimize(this);
659 for (auto &it : selection_vars)
660 it.second.optimize(this);
661 }
662
663 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
664 {
665 if (!selected_active_module.empty() && mod_name != selected_active_module)
666 return false;
667 if (selection_stack.size() == 0)
668 return true;
669 return selection_stack.back().selected_module(mod_name);
670 }
671
672 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
673 {
674 if (!selected_active_module.empty() && mod_name != selected_active_module)
675 return false;
676 if (selection_stack.size() == 0)
677 return true;
678 return selection_stack.back().selected_whole_module(mod_name);
679 }
680
681 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
682 {
683 if (!selected_active_module.empty() && mod_name != selected_active_module)
684 return false;
685 if (selection_stack.size() == 0)
686 return true;
687 return selection_stack.back().selected_member(mod_name, memb_name);
688 }
689
690 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
691 {
692 return selected_module(mod->name);
693 }
694
695 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
696 {
697 return selected_whole_module(mod->name);
698 }
699
700 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
701 {
702 std::vector<RTLIL::Module*> result;
703 result.reserve(modules_.size());
704 for (auto &it : modules_)
705 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
706 result.push_back(it.second);
707 return result;
708 }
709
710 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
711 {
712 std::vector<RTLIL::Module*> result;
713 result.reserve(modules_.size());
714 for (auto &it : modules_)
715 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
716 result.push_back(it.second);
717 return result;
718 }
719
720 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
721 {
722 std::vector<RTLIL::Module*> result;
723 result.reserve(modules_.size());
724 for (auto &it : modules_)
725 if (it.second->get_blackbox_attribute())
726 continue;
727 else if (selected_whole_module(it.first))
728 result.push_back(it.second);
729 else if (selected_module(it.first))
730 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
731 return result;
732 }
733
734 RTLIL::Module::Module()
735 {
736 static unsigned int hashidx_count = 123456789;
737 hashidx_count = mkhash_xorshift(hashidx_count);
738 hashidx_ = hashidx_count;
739
740 design = nullptr;
741 refcount_wires_ = 0;
742 refcount_cells_ = 0;
743
744 #ifdef WITH_PYTHON
745 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
746 #endif
747 }
748
749 RTLIL::Module::~Module()
750 {
751 for (auto it = wires_.begin(); it != wires_.end(); ++it)
752 delete it->second;
753 for (auto it = memories.begin(); it != memories.end(); ++it)
754 delete it->second;
755 for (auto it = cells_.begin(); it != cells_.end(); ++it)
756 delete it->second;
757 for (auto it = processes.begin(); it != processes.end(); ++it)
758 delete it->second;
759 #ifdef WITH_PYTHON
760 RTLIL::Module::get_all_modules()->erase(hashidx_);
761 #endif
762 }
763
764 #ifdef WITH_PYTHON
765 static std::map<unsigned int, RTLIL::Module*> all_modules;
766 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
767 {
768 return &all_modules;
769 }
770 #endif
771
772 void RTLIL::Module::makeblackbox()
773 {
774 pool<RTLIL::Wire*> delwires;
775
776 for (auto it = wires_.begin(); it != wires_.end(); ++it)
777 if (!it->second->port_input && !it->second->port_output)
778 delwires.insert(it->second);
779
780 for (auto it = memories.begin(); it != memories.end(); ++it)
781 delete it->second;
782 memories.clear();
783
784 for (auto it = cells_.begin(); it != cells_.end(); ++it)
785 delete it->second;
786 cells_.clear();
787
788 for (auto it = processes.begin(); it != processes.end(); ++it)
789 delete it->second;
790 processes.clear();
791
792 connections_.clear();
793
794 remove(delwires);
795 set_bool_attribute(ID::blackbox);
796 }
797
798 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
799 {
800 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
801 }
802
803 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
804 {
805 if (mayfail)
806 return RTLIL::IdString();
807 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
808 }
809
810
811 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
812 {
813 if (mayfail)
814 return RTLIL::IdString();
815 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
816 }
817
818 size_t RTLIL::Module::count_id(RTLIL::IdString id)
819 {
820 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
821 }
822
823 #ifndef NDEBUG
824 namespace {
825 struct InternalCellChecker
826 {
827 RTLIL::Module *module;
828 RTLIL::Cell *cell;
829 pool<RTLIL::IdString> expected_params, expected_ports;
830
831 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
832
833 void error(int linenr)
834 {
835 std::stringstream buf;
836 ILANG_BACKEND::dump_cell(buf, " ", cell);
837
838 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
839 module ? module->name.c_str() : "", module ? "." : "",
840 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
841 }
842
843 int param(RTLIL::IdString name)
844 {
845 auto it = cell->parameters.find(name);
846 if (it == cell->parameters.end())
847 error(__LINE__);
848 expected_params.insert(name);
849 return it->second.as_int();
850 }
851
852 int param_bool(RTLIL::IdString name)
853 {
854 int v = param(name);
855 if (GetSize(cell->parameters.at(name)) > 32)
856 error(__LINE__);
857 if (v != 0 && v != 1)
858 error(__LINE__);
859 return v;
860 }
861
862 int param_bool(RTLIL::IdString name, bool expected)
863 {
864 int v = param_bool(name);
865 if (v != expected)
866 error(__LINE__);
867 return v;
868 }
869
870 void param_bits(RTLIL::IdString name, int width)
871 {
872 param(name);
873 if (GetSize(cell->parameters.at(name).bits) != width)
874 error(__LINE__);
875 }
876
877 void port(RTLIL::IdString name, int width)
878 {
879 auto it = cell->connections_.find(name);
880 if (it == cell->connections_.end())
881 error(__LINE__);
882 if (GetSize(it->second) != width)
883 error(__LINE__);
884 expected_ports.insert(name);
885 }
886
887 void check_expected(bool check_matched_sign = false)
888 {
889 for (auto &para : cell->parameters)
890 if (expected_params.count(para.first) == 0)
891 error(__LINE__);
892 for (auto &conn : cell->connections())
893 if (expected_ports.count(conn.first) == 0)
894 error(__LINE__);
895
896 if (check_matched_sign) {
897 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
898 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
899 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
900 if (a_is_signed != b_is_signed)
901 error(__LINE__);
902 }
903 }
904
905 void check()
906 {
907 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
908 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
909 return;
910
911 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
912 param_bool(ID::A_SIGNED);
913 port(ID::A, param(ID::A_WIDTH));
914 port(ID::Y, param(ID::Y_WIDTH));
915 check_expected();
916 return;
917 }
918
919 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
920 param_bool(ID::A_SIGNED);
921 param_bool(ID::B_SIGNED);
922 port(ID::A, param(ID::A_WIDTH));
923 port(ID::B, param(ID::B_WIDTH));
924 port(ID::Y, param(ID::Y_WIDTH));
925 check_expected(true);
926 return;
927 }
928
929 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
930 param_bool(ID::A_SIGNED);
931 port(ID::A, param(ID::A_WIDTH));
932 port(ID::Y, param(ID::Y_WIDTH));
933 check_expected();
934 return;
935 }
936
937 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
938 param_bool(ID::A_SIGNED);
939 param_bool(ID::B_SIGNED, /*expected=*/false);
940 port(ID::A, param(ID::A_WIDTH));
941 port(ID::B, param(ID::B_WIDTH));
942 port(ID::Y, param(ID::Y_WIDTH));
943 check_expected(/*check_matched_sign=*/false);
944 return;
945 }
946
947 if (cell->type.in(ID($shift), ID($shiftx))) {
948 param_bool(ID::A_SIGNED);
949 param_bool(ID::B_SIGNED);
950 port(ID::A, param(ID::A_WIDTH));
951 port(ID::B, param(ID::B_WIDTH));
952 port(ID::Y, param(ID::Y_WIDTH));
953 check_expected(/*check_matched_sign=*/false);
954 return;
955 }
956
957 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
958 param_bool(ID::A_SIGNED);
959 param_bool(ID::B_SIGNED);
960 port(ID::A, param(ID::A_WIDTH));
961 port(ID::B, param(ID::B_WIDTH));
962 port(ID::Y, param(ID::Y_WIDTH));
963 check_expected(true);
964 return;
965 }
966
967 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
968 param_bool(ID::A_SIGNED);
969 param_bool(ID::B_SIGNED);
970 port(ID::A, param(ID::A_WIDTH));
971 port(ID::B, param(ID::B_WIDTH));
972 port(ID::Y, param(ID::Y_WIDTH));
973 check_expected(cell->type != ID($pow));
974 return;
975 }
976
977 if (cell->type == ID($fa)) {
978 port(ID::A, param(ID::WIDTH));
979 port(ID::B, param(ID::WIDTH));
980 port(ID::C, param(ID::WIDTH));
981 port(ID::X, param(ID::WIDTH));
982 port(ID::Y, param(ID::WIDTH));
983 check_expected();
984 return;
985 }
986
987 if (cell->type == ID($lcu)) {
988 port(ID::P, param(ID::WIDTH));
989 port(ID::G, param(ID::WIDTH));
990 port(ID::CI, 1);
991 port(ID::CO, param(ID::WIDTH));
992 check_expected();
993 return;
994 }
995
996 if (cell->type == ID($alu)) {
997 param_bool(ID::A_SIGNED);
998 param_bool(ID::B_SIGNED);
999 port(ID::A, param(ID::A_WIDTH));
1000 port(ID::B, param(ID::B_WIDTH));
1001 port(ID::CI, 1);
1002 port(ID::BI, 1);
1003 port(ID::X, param(ID::Y_WIDTH));
1004 port(ID::Y, param(ID::Y_WIDTH));
1005 port(ID::CO, param(ID::Y_WIDTH));
1006 check_expected(true);
1007 return;
1008 }
1009
1010 if (cell->type == ID($macc)) {
1011 param(ID::CONFIG);
1012 param(ID::CONFIG_WIDTH);
1013 port(ID::A, param(ID::A_WIDTH));
1014 port(ID::B, param(ID::B_WIDTH));
1015 port(ID::Y, param(ID::Y_WIDTH));
1016 check_expected();
1017 Macc().from_cell(cell);
1018 return;
1019 }
1020
1021 if (cell->type == ID($logic_not)) {
1022 param_bool(ID::A_SIGNED);
1023 port(ID::A, param(ID::A_WIDTH));
1024 port(ID::Y, param(ID::Y_WIDTH));
1025 check_expected();
1026 return;
1027 }
1028
1029 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1030 param_bool(ID::A_SIGNED);
1031 param_bool(ID::B_SIGNED);
1032 port(ID::A, param(ID::A_WIDTH));
1033 port(ID::B, param(ID::B_WIDTH));
1034 port(ID::Y, param(ID::Y_WIDTH));
1035 check_expected(/*check_matched_sign=*/false);
1036 return;
1037 }
1038
1039 if (cell->type == ID($slice)) {
1040 param(ID::OFFSET);
1041 port(ID::A, param(ID::A_WIDTH));
1042 port(ID::Y, param(ID::Y_WIDTH));
1043 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1044 error(__LINE__);
1045 check_expected();
1046 return;
1047 }
1048
1049 if (cell->type == ID($concat)) {
1050 port(ID::A, param(ID::A_WIDTH));
1051 port(ID::B, param(ID::B_WIDTH));
1052 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1053 check_expected();
1054 return;
1055 }
1056
1057 if (cell->type == ID($mux)) {
1058 port(ID::A, param(ID::WIDTH));
1059 port(ID::B, param(ID::WIDTH));
1060 port(ID::S, 1);
1061 port(ID::Y, param(ID::WIDTH));
1062 check_expected();
1063 return;
1064 }
1065
1066 if (cell->type == ID($pmux)) {
1067 port(ID::A, param(ID::WIDTH));
1068 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1069 port(ID::S, param(ID::S_WIDTH));
1070 port(ID::Y, param(ID::WIDTH));
1071 check_expected();
1072 return;
1073 }
1074
1075 if (cell->type == ID($lut)) {
1076 param(ID::LUT);
1077 port(ID::A, param(ID::WIDTH));
1078 port(ID::Y, 1);
1079 check_expected();
1080 return;
1081 }
1082
1083 if (cell->type == ID($sop)) {
1084 param(ID::DEPTH);
1085 param(ID::TABLE);
1086 port(ID::A, param(ID::WIDTH));
1087 port(ID::Y, 1);
1088 check_expected();
1089 return;
1090 }
1091
1092 if (cell->type == ID($sr)) {
1093 param_bool(ID::SET_POLARITY);
1094 param_bool(ID::CLR_POLARITY);
1095 port(ID::SET, param(ID::WIDTH));
1096 port(ID::CLR, param(ID::WIDTH));
1097 port(ID::Q, param(ID::WIDTH));
1098 check_expected();
1099 return;
1100 }
1101
1102 if (cell->type == ID($ff)) {
1103 port(ID::D, param(ID::WIDTH));
1104 port(ID::Q, param(ID::WIDTH));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == ID($dff)) {
1110 param_bool(ID::CLK_POLARITY);
1111 port(ID::CLK, 1);
1112 port(ID::D, param(ID::WIDTH));
1113 port(ID::Q, param(ID::WIDTH));
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == ID($dffe)) {
1119 param_bool(ID::CLK_POLARITY);
1120 param_bool(ID::EN_POLARITY);
1121 port(ID::CLK, 1);
1122 port(ID::EN, 1);
1123 port(ID::D, param(ID::WIDTH));
1124 port(ID::Q, param(ID::WIDTH));
1125 check_expected();
1126 return;
1127 }
1128
1129 if (cell->type == ID($dffsr)) {
1130 param_bool(ID::CLK_POLARITY);
1131 param_bool(ID::SET_POLARITY);
1132 param_bool(ID::CLR_POLARITY);
1133 port(ID::CLK, 1);
1134 port(ID::SET, param(ID::WIDTH));
1135 port(ID::CLR, param(ID::WIDTH));
1136 port(ID::D, param(ID::WIDTH));
1137 port(ID::Q, param(ID::WIDTH));
1138 check_expected();
1139 return;
1140 }
1141
1142 if (cell->type == ID($adff)) {
1143 param_bool(ID::CLK_POLARITY);
1144 param_bool(ID::ARST_POLARITY);
1145 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1146 port(ID::CLK, 1);
1147 port(ID::ARST, 1);
1148 port(ID::D, param(ID::WIDTH));
1149 port(ID::Q, param(ID::WIDTH));
1150 check_expected();
1151 return;
1152 }
1153
1154 if (cell->type == ID($dlatch)) {
1155 param_bool(ID::EN_POLARITY);
1156 port(ID::EN, 1);
1157 port(ID::D, param(ID::WIDTH));
1158 port(ID::Q, param(ID::WIDTH));
1159 check_expected();
1160 return;
1161 }
1162
1163 if (cell->type == ID($dlatchsr)) {
1164 param_bool(ID::EN_POLARITY);
1165 param_bool(ID::SET_POLARITY);
1166 param_bool(ID::CLR_POLARITY);
1167 port(ID::EN, 1);
1168 port(ID::SET, param(ID::WIDTH));
1169 port(ID::CLR, param(ID::WIDTH));
1170 port(ID::D, param(ID::WIDTH));
1171 port(ID::Q, param(ID::WIDTH));
1172 check_expected();
1173 return;
1174 }
1175
1176 if (cell->type == ID($fsm)) {
1177 param(ID::NAME);
1178 param_bool(ID::CLK_POLARITY);
1179 param_bool(ID::ARST_POLARITY);
1180 param(ID::STATE_BITS);
1181 param(ID::STATE_NUM);
1182 param(ID::STATE_NUM_LOG2);
1183 param(ID::STATE_RST);
1184 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1185 param(ID::TRANS_NUM);
1186 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1187 port(ID::CLK, 1);
1188 port(ID::ARST, 1);
1189 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1190 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1191 check_expected();
1192 return;
1193 }
1194
1195 if (cell->type == ID($memrd)) {
1196 param(ID::MEMID);
1197 param_bool(ID::CLK_ENABLE);
1198 param_bool(ID::CLK_POLARITY);
1199 param_bool(ID::TRANSPARENT);
1200 port(ID::CLK, 1);
1201 port(ID::EN, 1);
1202 port(ID::ADDR, param(ID::ABITS));
1203 port(ID::DATA, param(ID::WIDTH));
1204 check_expected();
1205 return;
1206 }
1207
1208 if (cell->type == ID($memwr)) {
1209 param(ID::MEMID);
1210 param_bool(ID::CLK_ENABLE);
1211 param_bool(ID::CLK_POLARITY);
1212 param(ID::PRIORITY);
1213 port(ID::CLK, 1);
1214 port(ID::EN, param(ID::WIDTH));
1215 port(ID::ADDR, param(ID::ABITS));
1216 port(ID::DATA, param(ID::WIDTH));
1217 check_expected();
1218 return;
1219 }
1220
1221 if (cell->type == ID($meminit)) {
1222 param(ID::MEMID);
1223 param(ID::PRIORITY);
1224 port(ID::ADDR, param(ID::ABITS));
1225 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1226 check_expected();
1227 return;
1228 }
1229
1230 if (cell->type == ID($mem)) {
1231 param(ID::MEMID);
1232 param(ID::SIZE);
1233 param(ID::OFFSET);
1234 param(ID::INIT);
1235 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1236 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1237 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1238 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1239 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1240 port(ID::RD_CLK, param(ID::RD_PORTS));
1241 port(ID::RD_EN, param(ID::RD_PORTS));
1242 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1243 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1244 port(ID::WR_CLK, param(ID::WR_PORTS));
1245 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1246 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1247 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1248 check_expected();
1249 return;
1250 }
1251
1252 if (cell->type == ID($tribuf)) {
1253 port(ID::A, param(ID::WIDTH));
1254 port(ID::Y, param(ID::WIDTH));
1255 port(ID::EN, 1);
1256 check_expected();
1257 return;
1258 }
1259
1260 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1261 port(ID::A, 1);
1262 port(ID::EN, 1);
1263 check_expected();
1264 return;
1265 }
1266
1267 if (cell->type == ID($initstate)) {
1268 port(ID::Y, 1);
1269 check_expected();
1270 return;
1271 }
1272
1273 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1274 port(ID::Y, param(ID::WIDTH));
1275 check_expected();
1276 return;
1277 }
1278
1279 if (cell->type == ID($equiv)) {
1280 port(ID::A, 1);
1281 port(ID::B, 1);
1282 port(ID::Y, 1);
1283 check_expected();
1284 return;
1285 }
1286
1287 if (cell->type.in(ID($specify2), ID($specify3))) {
1288 param_bool(ID::FULL);
1289 param_bool(ID::SRC_DST_PEN);
1290 param_bool(ID::SRC_DST_POL);
1291 param(ID::T_RISE_MIN);
1292 param(ID::T_RISE_TYP);
1293 param(ID::T_RISE_MAX);
1294 param(ID::T_FALL_MIN);
1295 param(ID::T_FALL_TYP);
1296 param(ID::T_FALL_MAX);
1297 port(ID::EN, 1);
1298 port(ID::SRC, param(ID::SRC_WIDTH));
1299 port(ID::DST, param(ID::DST_WIDTH));
1300 if (cell->type == ID($specify3)) {
1301 param_bool(ID::EDGE_EN);
1302 param_bool(ID::EDGE_POL);
1303 param_bool(ID::DAT_DST_PEN);
1304 param_bool(ID::DAT_DST_POL);
1305 port(ID::DAT, param(ID::DST_WIDTH));
1306 }
1307 check_expected();
1308 return;
1309 }
1310
1311 if (cell->type == ID($specrule)) {
1312 param(ID::TYPE);
1313 param_bool(ID::SRC_PEN);
1314 param_bool(ID::SRC_POL);
1315 param_bool(ID::DST_PEN);
1316 param_bool(ID::DST_POL);
1317 param(ID::T_LIMIT_MIN);
1318 param(ID::T_LIMIT_TYP);
1319 param(ID::T_LIMIT_MAX);
1320 param(ID::T_LIMIT2_MIN);
1321 param(ID::T_LIMIT2_TYP);
1322 param(ID::T_LIMIT2_MAX);
1323 port(ID::SRC_EN, 1);
1324 port(ID::DST_EN, 1);
1325 port(ID::SRC, param(ID::SRC_WIDTH));
1326 port(ID::DST, param(ID::DST_WIDTH));
1327 check_expected();
1328 return;
1329 }
1330
1331 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1332 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1333 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1334 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1335 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1336 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1337 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1338 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1339 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1340 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1341 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1342 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1343 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1344 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1345 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1346 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1347
1348 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1349
1350 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1351 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1352 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1353
1354 if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1355 if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1356 if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1357 if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1358
1359 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1360 if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1361 if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1362
1363 if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1364 if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1365 if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1366 if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1367
1368 if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1369 if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1370 if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1371 if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1372 if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1373 if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1374 if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1375 if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1376
1377 if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1378 if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1379 if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1380 if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1381 if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1382 if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1383 if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1384 if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1385
1386 if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1387 if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1388
1389 if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1390 if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1391 if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1392 if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1393 if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1394 if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1395 if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1396 if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1397
1398 error(__LINE__);
1399 }
1400 };
1401 }
1402 #endif
1403
1404 void RTLIL::Module::sort()
1405 {
1406 wires_.sort(sort_by_id_str());
1407 cells_.sort(sort_by_id_str());
1408 parameter_default_values.sort(sort_by_id_str());
1409 memories.sort(sort_by_id_str());
1410 processes.sort(sort_by_id_str());
1411 for (auto &it : cells_)
1412 it.second->sort();
1413 for (auto &it : wires_)
1414 it.second->attributes.sort(sort_by_id_str());
1415 for (auto &it : memories)
1416 it.second->attributes.sort(sort_by_id_str());
1417 }
1418
1419 void RTLIL::Module::check()
1420 {
1421 #ifndef NDEBUG
1422 std::vector<bool> ports_declared;
1423 for (auto &it : wires_) {
1424 log_assert(this == it.second->module);
1425 log_assert(it.first == it.second->name);
1426 log_assert(!it.first.empty());
1427 log_assert(it.second->width >= 0);
1428 log_assert(it.second->port_id >= 0);
1429 for (auto &it2 : it.second->attributes)
1430 log_assert(!it2.first.empty());
1431 if (it.second->port_id) {
1432 log_assert(GetSize(ports) >= it.second->port_id);
1433 log_assert(ports.at(it.second->port_id-1) == it.first);
1434 log_assert(it.second->port_input || it.second->port_output);
1435 if (GetSize(ports_declared) < it.second->port_id)
1436 ports_declared.resize(it.second->port_id);
1437 log_assert(ports_declared[it.second->port_id-1] == false);
1438 ports_declared[it.second->port_id-1] = true;
1439 } else
1440 log_assert(!it.second->port_input && !it.second->port_output);
1441 }
1442 for (auto port_declared : ports_declared)
1443 log_assert(port_declared == true);
1444 log_assert(GetSize(ports) == GetSize(ports_declared));
1445
1446 for (auto &it : memories) {
1447 log_assert(it.first == it.second->name);
1448 log_assert(!it.first.empty());
1449 log_assert(it.second->width >= 0);
1450 log_assert(it.second->size >= 0);
1451 for (auto &it2 : it.second->attributes)
1452 log_assert(!it2.first.empty());
1453 }
1454
1455 for (auto &it : cells_) {
1456 log_assert(this == it.second->module);
1457 log_assert(it.first == it.second->name);
1458 log_assert(!it.first.empty());
1459 log_assert(!it.second->type.empty());
1460 for (auto &it2 : it.second->connections()) {
1461 log_assert(!it2.first.empty());
1462 it2.second.check();
1463 }
1464 for (auto &it2 : it.second->attributes)
1465 log_assert(!it2.first.empty());
1466 for (auto &it2 : it.second->parameters)
1467 log_assert(!it2.first.empty());
1468 InternalCellChecker checker(this, it.second);
1469 checker.check();
1470 }
1471
1472 for (auto &it : processes) {
1473 log_assert(it.first == it.second->name);
1474 log_assert(!it.first.empty());
1475 log_assert(it.second->root_case.compare.empty());
1476 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1477 for (size_t i = 0; i < all_cases.size(); i++) {
1478 for (auto &switch_it : all_cases[i]->switches) {
1479 for (auto &case_it : switch_it->cases) {
1480 for (auto &compare_it : case_it->compare) {
1481 log_assert(switch_it->signal.size() == compare_it.size());
1482 }
1483 all_cases.push_back(case_it);
1484 }
1485 }
1486 }
1487 for (auto &sync_it : it.second->syncs) {
1488 switch (sync_it->type) {
1489 case SyncType::ST0:
1490 case SyncType::ST1:
1491 case SyncType::STp:
1492 case SyncType::STn:
1493 case SyncType::STe:
1494 log_assert(!sync_it->signal.empty());
1495 break;
1496 case SyncType::STa:
1497 case SyncType::STg:
1498 case SyncType::STi:
1499 log_assert(sync_it->signal.empty());
1500 break;
1501 }
1502 }
1503 }
1504
1505 for (auto &it : connections_) {
1506 log_assert(it.first.size() == it.second.size());
1507 log_assert(!it.first.has_const());
1508 it.first.check();
1509 it.second.check();
1510 }
1511
1512 for (auto &it : attributes)
1513 log_assert(!it.first.empty());
1514 #endif
1515 }
1516
1517 void RTLIL::Module::optimize()
1518 {
1519 }
1520
1521 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1522 {
1523 log_assert(new_mod->refcount_wires_ == 0);
1524 log_assert(new_mod->refcount_cells_ == 0);
1525
1526 new_mod->avail_parameters = avail_parameters;
1527 new_mod->parameter_default_values = parameter_default_values;
1528
1529 for (auto &conn : connections_)
1530 new_mod->connect(conn);
1531
1532 for (auto &attr : attributes)
1533 new_mod->attributes[attr.first] = attr.second;
1534
1535 for (auto &it : wires_)
1536 new_mod->addWire(it.first, it.second);
1537
1538 for (auto &it : memories)
1539 new_mod->addMemory(it.first, it.second);
1540
1541 for (auto &it : cells_)
1542 new_mod->addCell(it.first, it.second);
1543
1544 for (auto &it : processes)
1545 new_mod->addProcess(it.first, it.second);
1546
1547 struct RewriteSigSpecWorker
1548 {
1549 RTLIL::Module *mod;
1550 void operator()(RTLIL::SigSpec &sig)
1551 {
1552 sig.pack();
1553 for (auto &c : sig.chunks_)
1554 if (c.wire != NULL)
1555 c.wire = mod->wires_.at(c.wire->name);
1556 }
1557 };
1558
1559 RewriteSigSpecWorker rewriteSigSpecWorker;
1560 rewriteSigSpecWorker.mod = new_mod;
1561 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1562 new_mod->fixup_ports();
1563 }
1564
1565 RTLIL::Module *RTLIL::Module::clone() const
1566 {
1567 RTLIL::Module *new_mod = new RTLIL::Module;
1568 new_mod->name = name;
1569 cloneInto(new_mod);
1570 return new_mod;
1571 }
1572
1573 bool RTLIL::Module::has_memories() const
1574 {
1575 return !memories.empty();
1576 }
1577
1578 bool RTLIL::Module::has_processes() const
1579 {
1580 return !processes.empty();
1581 }
1582
1583 bool RTLIL::Module::has_memories_warn() const
1584 {
1585 if (!memories.empty())
1586 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1587 return !memories.empty();
1588 }
1589
1590 bool RTLIL::Module::has_processes_warn() const
1591 {
1592 if (!processes.empty())
1593 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1594 return !processes.empty();
1595 }
1596
1597 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1598 {
1599 std::vector<RTLIL::Wire*> result;
1600 result.reserve(wires_.size());
1601 for (auto &it : wires_)
1602 if (design->selected(this, it.second))
1603 result.push_back(it.second);
1604 return result;
1605 }
1606
1607 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1608 {
1609 std::vector<RTLIL::Cell*> result;
1610 result.reserve(cells_.size());
1611 for (auto &it : cells_)
1612 if (design->selected(this, it.second))
1613 result.push_back(it.second);
1614 return result;
1615 }
1616
1617 void RTLIL::Module::add(RTLIL::Wire *wire)
1618 {
1619 log_assert(!wire->name.empty());
1620 log_assert(count_id(wire->name) == 0);
1621 log_assert(refcount_wires_ == 0);
1622 wires_[wire->name] = wire;
1623 wire->module = this;
1624 }
1625
1626 void RTLIL::Module::add(RTLIL::Cell *cell)
1627 {
1628 log_assert(!cell->name.empty());
1629 log_assert(count_id(cell->name) == 0);
1630 log_assert(refcount_cells_ == 0);
1631 cells_[cell->name] = cell;
1632 cell->module = this;
1633 }
1634
1635 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1636 {
1637 log_assert(refcount_wires_ == 0);
1638
1639 struct DeleteWireWorker
1640 {
1641 RTLIL::Module *module;
1642 const pool<RTLIL::Wire*> *wires_p;
1643
1644 void operator()(RTLIL::SigSpec &sig) {
1645 sig.pack();
1646 for (auto &c : sig.chunks_)
1647 if (c.wire != NULL && wires_p->count(c.wire)) {
1648 c.wire = module->addWire(NEW_ID, c.width);
1649 c.offset = 0;
1650 }
1651 }
1652
1653 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1654 log_assert(GetSize(lhs) == GetSize(rhs));
1655 lhs.unpack();
1656 rhs.unpack();
1657 for (int i = 0; i < GetSize(lhs); i++) {
1658 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1659 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1660 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1661 lhs_bit = State::Sx;
1662 rhs_bit = State::Sx;
1663 }
1664 }
1665 }
1666 };
1667
1668 DeleteWireWorker delete_wire_worker;
1669 delete_wire_worker.module = this;
1670 delete_wire_worker.wires_p = &wires;
1671 rewrite_sigspecs2(delete_wire_worker);
1672
1673 for (auto &it : wires) {
1674 log_assert(wires_.count(it->name) != 0);
1675 wires_.erase(it->name);
1676 delete it;
1677 }
1678 }
1679
1680 void RTLIL::Module::remove(RTLIL::Cell *cell)
1681 {
1682 while (!cell->connections_.empty())
1683 cell->unsetPort(cell->connections_.begin()->first);
1684
1685 log_assert(cells_.count(cell->name) != 0);
1686 log_assert(refcount_cells_ == 0);
1687 cells_.erase(cell->name);
1688 delete cell;
1689 }
1690
1691 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1692 {
1693 log_assert(wires_[wire->name] == wire);
1694 log_assert(refcount_wires_ == 0);
1695 wires_.erase(wire->name);
1696 wire->name = new_name;
1697 add(wire);
1698 }
1699
1700 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1701 {
1702 log_assert(cells_[cell->name] == cell);
1703 log_assert(refcount_wires_ == 0);
1704 cells_.erase(cell->name);
1705 cell->name = new_name;
1706 add(cell);
1707 }
1708
1709 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1710 {
1711 log_assert(count_id(old_name) != 0);
1712 if (wires_.count(old_name))
1713 rename(wires_.at(old_name), new_name);
1714 else if (cells_.count(old_name))
1715 rename(cells_.at(old_name), new_name);
1716 else
1717 log_abort();
1718 }
1719
1720 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1721 {
1722 log_assert(wires_[w1->name] == w1);
1723 log_assert(wires_[w2->name] == w2);
1724 log_assert(refcount_wires_ == 0);
1725
1726 wires_.erase(w1->name);
1727 wires_.erase(w2->name);
1728
1729 std::swap(w1->name, w2->name);
1730
1731 wires_[w1->name] = w1;
1732 wires_[w2->name] = w2;
1733 }
1734
1735 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1736 {
1737 log_assert(cells_[c1->name] == c1);
1738 log_assert(cells_[c2->name] == c2);
1739 log_assert(refcount_cells_ == 0);
1740
1741 cells_.erase(c1->name);
1742 cells_.erase(c2->name);
1743
1744 std::swap(c1->name, c2->name);
1745
1746 cells_[c1->name] = c1;
1747 cells_[c2->name] = c2;
1748 }
1749
1750 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1751 {
1752 int index = 0;
1753 return uniquify(name, index);
1754 }
1755
1756 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1757 {
1758 if (index == 0) {
1759 if (count_id(name) == 0)
1760 return name;
1761 index++;
1762 }
1763
1764 while (1) {
1765 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1766 if (count_id(new_name) == 0)
1767 return new_name;
1768 index++;
1769 }
1770 }
1771
1772 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1773 {
1774 if (a->port_id && !b->port_id)
1775 return true;
1776 if (!a->port_id && b->port_id)
1777 return false;
1778
1779 if (a->port_id == b->port_id)
1780 return a->name < b->name;
1781 return a->port_id < b->port_id;
1782 }
1783
1784 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1785 {
1786 for (auto mon : monitors)
1787 mon->notify_connect(this, conn);
1788
1789 if (design)
1790 for (auto mon : design->monitors)
1791 mon->notify_connect(this, conn);
1792
1793 // ignore all attempts to assign constants to other constants
1794 if (conn.first.has_const()) {
1795 RTLIL::SigSig new_conn;
1796 for (int i = 0; i < GetSize(conn.first); i++)
1797 if (conn.first[i].wire) {
1798 new_conn.first.append(conn.first[i]);
1799 new_conn.second.append(conn.second[i]);
1800 }
1801 if (GetSize(new_conn.first))
1802 connect(new_conn);
1803 return;
1804 }
1805
1806 if (yosys_xtrace) {
1807 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1808 log_backtrace("-X- ", yosys_xtrace-1);
1809 }
1810
1811 log_assert(GetSize(conn.first) == GetSize(conn.second));
1812 connections_.push_back(conn);
1813 }
1814
1815 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1816 {
1817 connect(RTLIL::SigSig(lhs, rhs));
1818 }
1819
1820 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1821 {
1822 for (auto mon : monitors)
1823 mon->notify_connect(this, new_conn);
1824
1825 if (design)
1826 for (auto mon : design->monitors)
1827 mon->notify_connect(this, new_conn);
1828
1829 if (yosys_xtrace) {
1830 log("#X# New connections vector in %s:\n", log_id(this));
1831 for (auto &conn: new_conn)
1832 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1833 log_backtrace("-X- ", yosys_xtrace-1);
1834 }
1835
1836 connections_ = new_conn;
1837 }
1838
1839 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1840 {
1841 return connections_;
1842 }
1843
1844 void RTLIL::Module::fixup_ports()
1845 {
1846 std::vector<RTLIL::Wire*> all_ports;
1847
1848 for (auto &w : wires_)
1849 if (w.second->port_input || w.second->port_output)
1850 all_ports.push_back(w.second);
1851 else
1852 w.second->port_id = 0;
1853
1854 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1855
1856 ports.clear();
1857 for (size_t i = 0; i < all_ports.size(); i++) {
1858 ports.push_back(all_ports[i]->name);
1859 all_ports[i]->port_id = i+1;
1860 }
1861 }
1862
1863 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1864 {
1865 RTLIL::Wire *wire = new RTLIL::Wire;
1866 wire->name = name;
1867 wire->width = width;
1868 add(wire);
1869 return wire;
1870 }
1871
1872 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1873 {
1874 RTLIL::Wire *wire = addWire(name);
1875 wire->width = other->width;
1876 wire->start_offset = other->start_offset;
1877 wire->port_id = other->port_id;
1878 wire->port_input = other->port_input;
1879 wire->port_output = other->port_output;
1880 wire->upto = other->upto;
1881 wire->is_signed = other->is_signed;
1882 wire->attributes = other->attributes;
1883 return wire;
1884 }
1885
1886 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1887 {
1888 RTLIL::Cell *cell = new RTLIL::Cell;
1889 cell->name = name;
1890 cell->type = type;
1891 add(cell);
1892 return cell;
1893 }
1894
1895 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1896 {
1897 RTLIL::Cell *cell = addCell(name, other->type);
1898 cell->connections_ = other->connections_;
1899 cell->parameters = other->parameters;
1900 cell->attributes = other->attributes;
1901 return cell;
1902 }
1903
1904 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
1905 {
1906 RTLIL::Memory *mem = new RTLIL::Memory;
1907 mem->name = name;
1908 mem->width = other->width;
1909 mem->start_offset = other->start_offset;
1910 mem->size = other->size;
1911 mem->attributes = other->attributes;
1912 memories[mem->name] = mem;
1913 return mem;
1914 }
1915
1916 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
1917 {
1918 RTLIL::Process *proc = other->clone();
1919 proc->name = name;
1920 processes[name] = proc;
1921 return proc;
1922 }
1923
1924 #define DEF_METHOD(_func, _y_size, _type) \
1925 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1926 RTLIL::Cell *cell = addCell(name, _type); \
1927 cell->parameters[ID::A_SIGNED] = is_signed; \
1928 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1929 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1930 cell->setPort(ID::A, sig_a); \
1931 cell->setPort(ID::Y, sig_y); \
1932 cell->set_src_attribute(src); \
1933 return cell; \
1934 } \
1935 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1936 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1937 add ## _func(name, sig_a, sig_y, is_signed, src); \
1938 return sig_y; \
1939 }
1940 DEF_METHOD(Not, sig_a.size(), ID($not))
1941 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1942 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1943 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1944 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1945 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1946 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1947 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1948 DEF_METHOD(LogicNot, 1, ID($logic_not))
1949 #undef DEF_METHOD
1950
1951 #define DEF_METHOD(_func, _y_size, _type) \
1952 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1953 RTLIL::Cell *cell = addCell(name, _type); \
1954 cell->parameters[ID::A_SIGNED] = is_signed; \
1955 cell->parameters[ID::B_SIGNED] = is_signed; \
1956 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1957 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1958 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1959 cell->setPort(ID::A, sig_a); \
1960 cell->setPort(ID::B, sig_b); \
1961 cell->setPort(ID::Y, sig_y); \
1962 cell->set_src_attribute(src); \
1963 return cell; \
1964 } \
1965 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1966 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1967 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1968 return sig_y; \
1969 }
1970 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1971 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1972 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1973 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1974 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1975 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1976 DEF_METHOD(Lt, 1, ID($lt))
1977 DEF_METHOD(Le, 1, ID($le))
1978 DEF_METHOD(Eq, 1, ID($eq))
1979 DEF_METHOD(Ne, 1, ID($ne))
1980 DEF_METHOD(Eqx, 1, ID($eqx))
1981 DEF_METHOD(Nex, 1, ID($nex))
1982 DEF_METHOD(Ge, 1, ID($ge))
1983 DEF_METHOD(Gt, 1, ID($gt))
1984 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1985 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1986 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1987 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1988 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1989 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
1990 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
1991 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1992 DEF_METHOD(LogicOr, 1, ID($logic_or))
1993 #undef DEF_METHOD
1994
1995 #define DEF_METHOD(_func, _y_size, _type) \
1996 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1997 RTLIL::Cell *cell = addCell(name, _type); \
1998 cell->parameters[ID::A_SIGNED] = is_signed; \
1999 cell->parameters[ID::B_SIGNED] = false; \
2000 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2001 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2002 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2003 cell->setPort(ID::A, sig_a); \
2004 cell->setPort(ID::B, sig_b); \
2005 cell->setPort(ID::Y, sig_y); \
2006 cell->set_src_attribute(src); \
2007 return cell; \
2008 } \
2009 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2010 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2011 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2012 return sig_y; \
2013 }
2014 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2015 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2016 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2017 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2018 #undef DEF_METHOD
2019
2020 #define DEF_METHOD(_func, _type, _pmux) \
2021 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2022 RTLIL::Cell *cell = addCell(name, _type); \
2023 cell->parameters[ID::WIDTH] = sig_a.size(); \
2024 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2025 cell->setPort(ID::A, sig_a); \
2026 cell->setPort(ID::B, sig_b); \
2027 cell->setPort(ID::S, sig_s); \
2028 cell->setPort(ID::Y, sig_y); \
2029 cell->set_src_attribute(src); \
2030 return cell; \
2031 } \
2032 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2033 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2034 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2035 return sig_y; \
2036 }
2037 DEF_METHOD(Mux, ID($mux), 0)
2038 DEF_METHOD(Pmux, ID($pmux), 1)
2039 #undef DEF_METHOD
2040
2041 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2042 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2043 RTLIL::Cell *cell = addCell(name, _type); \
2044 cell->setPort("\\" #_P1, sig1); \
2045 cell->setPort("\\" #_P2, sig2); \
2046 cell->set_src_attribute(src); \
2047 return cell; \
2048 } \
2049 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2050 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2051 add ## _func(name, sig1, sig2, src); \
2052 return sig2; \
2053 }
2054 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2055 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2056 RTLIL::Cell *cell = addCell(name, _type); \
2057 cell->setPort("\\" #_P1, sig1); \
2058 cell->setPort("\\" #_P2, sig2); \
2059 cell->setPort("\\" #_P3, sig3); \
2060 cell->set_src_attribute(src); \
2061 return cell; \
2062 } \
2063 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2064 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2065 add ## _func(name, sig1, sig2, sig3, src); \
2066 return sig3; \
2067 }
2068 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2069 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2070 RTLIL::Cell *cell = addCell(name, _type); \
2071 cell->setPort("\\" #_P1, sig1); \
2072 cell->setPort("\\" #_P2, sig2); \
2073 cell->setPort("\\" #_P3, sig3); \
2074 cell->setPort("\\" #_P4, sig4); \
2075 cell->set_src_attribute(src); \
2076 return cell; \
2077 } \
2078 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2079 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2080 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2081 return sig4; \
2082 }
2083 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2084 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2085 RTLIL::Cell *cell = addCell(name, _type); \
2086 cell->setPort("\\" #_P1, sig1); \
2087 cell->setPort("\\" #_P2, sig2); \
2088 cell->setPort("\\" #_P3, sig3); \
2089 cell->setPort("\\" #_P4, sig4); \
2090 cell->setPort("\\" #_P5, sig5); \
2091 cell->set_src_attribute(src); \
2092 return cell; \
2093 } \
2094 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2095 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2096 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2097 return sig5; \
2098 }
2099 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2100 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2101 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2102 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2103 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2104 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2105 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2106 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2107 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2108 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2109 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2110 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2111 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2112 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2113 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2114 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2115 #undef DEF_METHOD_2
2116 #undef DEF_METHOD_3
2117 #undef DEF_METHOD_4
2118 #undef DEF_METHOD_5
2119
2120 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2121 {
2122 RTLIL::Cell *cell = addCell(name, ID($pow));
2123 cell->parameters[ID::A_SIGNED] = a_signed;
2124 cell->parameters[ID::B_SIGNED] = b_signed;
2125 cell->parameters[ID::A_WIDTH] = sig_a.size();
2126 cell->parameters[ID::B_WIDTH] = sig_b.size();
2127 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2128 cell->setPort(ID::A, sig_a);
2129 cell->setPort(ID::B, sig_b);
2130 cell->setPort(ID::Y, sig_y);
2131 cell->set_src_attribute(src);
2132 return cell;
2133 }
2134
2135 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2136 {
2137 RTLIL::Cell *cell = addCell(name, ID($slice));
2138 cell->parameters[ID::A_WIDTH] = sig_a.size();
2139 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2140 cell->parameters[ID::OFFSET] = offset;
2141 cell->setPort(ID::A, sig_a);
2142 cell->setPort(ID::Y, sig_y);
2143 cell->set_src_attribute(src);
2144 return cell;
2145 }
2146
2147 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2148 {
2149 RTLIL::Cell *cell = addCell(name, ID($concat));
2150 cell->parameters[ID::A_WIDTH] = sig_a.size();
2151 cell->parameters[ID::B_WIDTH] = sig_b.size();
2152 cell->setPort(ID::A, sig_a);
2153 cell->setPort(ID::B, sig_b);
2154 cell->setPort(ID::Y, sig_y);
2155 cell->set_src_attribute(src);
2156 return cell;
2157 }
2158
2159 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2160 {
2161 RTLIL::Cell *cell = addCell(name, ID($lut));
2162 cell->parameters[ID::LUT] = lut;
2163 cell->parameters[ID::WIDTH] = sig_a.size();
2164 cell->setPort(ID::A, sig_a);
2165 cell->setPort(ID::Y, sig_y);
2166 cell->set_src_attribute(src);
2167 return cell;
2168 }
2169
2170 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2171 {
2172 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2173 cell->parameters[ID::WIDTH] = sig_a.size();
2174 cell->setPort(ID::A, sig_a);
2175 cell->setPort(ID::EN, sig_en);
2176 cell->setPort(ID::Y, sig_y);
2177 cell->set_src_attribute(src);
2178 return cell;
2179 }
2180
2181 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2182 {
2183 RTLIL::Cell *cell = addCell(name, ID($assert));
2184 cell->setPort(ID::A, sig_a);
2185 cell->setPort(ID::EN, sig_en);
2186 cell->set_src_attribute(src);
2187 return cell;
2188 }
2189
2190 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2191 {
2192 RTLIL::Cell *cell = addCell(name, ID($assume));
2193 cell->setPort(ID::A, sig_a);
2194 cell->setPort(ID::EN, sig_en);
2195 cell->set_src_attribute(src);
2196 return cell;
2197 }
2198
2199 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2200 {
2201 RTLIL::Cell *cell = addCell(name, ID($live));
2202 cell->setPort(ID::A, sig_a);
2203 cell->setPort(ID::EN, sig_en);
2204 cell->set_src_attribute(src);
2205 return cell;
2206 }
2207
2208 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2209 {
2210 RTLIL::Cell *cell = addCell(name, ID($fair));
2211 cell->setPort(ID::A, sig_a);
2212 cell->setPort(ID::EN, sig_en);
2213 cell->set_src_attribute(src);
2214 return cell;
2215 }
2216
2217 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2218 {
2219 RTLIL::Cell *cell = addCell(name, ID($cover));
2220 cell->setPort(ID::A, sig_a);
2221 cell->setPort(ID::EN, sig_en);
2222 cell->set_src_attribute(src);
2223 return cell;
2224 }
2225
2226 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2227 {
2228 RTLIL::Cell *cell = addCell(name, ID($equiv));
2229 cell->setPort(ID::A, sig_a);
2230 cell->setPort(ID::B, sig_b);
2231 cell->setPort(ID::Y, sig_y);
2232 cell->set_src_attribute(src);
2233 return cell;
2234 }
2235
2236 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2237 {
2238 RTLIL::Cell *cell = addCell(name, ID($sr));
2239 cell->parameters[ID::SET_POLARITY] = set_polarity;
2240 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2241 cell->parameters[ID::WIDTH] = sig_q.size();
2242 cell->setPort(ID::SET, sig_set);
2243 cell->setPort(ID::CLR, sig_clr);
2244 cell->setPort(ID::Q, sig_q);
2245 cell->set_src_attribute(src);
2246 return cell;
2247 }
2248
2249 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2250 {
2251 RTLIL::Cell *cell = addCell(name, ID($ff));
2252 cell->parameters[ID::WIDTH] = sig_q.size();
2253 cell->setPort(ID::D, sig_d);
2254 cell->setPort(ID::Q, sig_q);
2255 cell->set_src_attribute(src);
2256 return cell;
2257 }
2258
2259 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2260 {
2261 RTLIL::Cell *cell = addCell(name, ID($dff));
2262 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2263 cell->parameters[ID::WIDTH] = sig_q.size();
2264 cell->setPort(ID::CLK, sig_clk);
2265 cell->setPort(ID::D, sig_d);
2266 cell->setPort(ID::Q, sig_q);
2267 cell->set_src_attribute(src);
2268 return cell;
2269 }
2270
2271 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2272 {
2273 RTLIL::Cell *cell = addCell(name, ID($dffe));
2274 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2275 cell->parameters[ID::EN_POLARITY] = en_polarity;
2276 cell->parameters[ID::WIDTH] = sig_q.size();
2277 cell->setPort(ID::CLK, sig_clk);
2278 cell->setPort(ID::EN, sig_en);
2279 cell->setPort(ID::D, sig_d);
2280 cell->setPort(ID::Q, sig_q);
2281 cell->set_src_attribute(src);
2282 return cell;
2283 }
2284
2285 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2286 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2287 {
2288 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2289 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2290 cell->parameters[ID::SET_POLARITY] = set_polarity;
2291 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2292 cell->parameters[ID::WIDTH] = sig_q.size();
2293 cell->setPort(ID::CLK, sig_clk);
2294 cell->setPort(ID::SET, sig_set);
2295 cell->setPort(ID::CLR, sig_clr);
2296 cell->setPort(ID::D, sig_d);
2297 cell->setPort(ID::Q, sig_q);
2298 cell->set_src_attribute(src);
2299 return cell;
2300 }
2301
2302 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2303 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2304 {
2305 RTLIL::Cell *cell = addCell(name, ID($adff));
2306 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2307 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2308 cell->parameters[ID::ARST_VALUE] = arst_value;
2309 cell->parameters[ID::WIDTH] = sig_q.size();
2310 cell->setPort(ID::CLK, sig_clk);
2311 cell->setPort(ID::ARST, sig_arst);
2312 cell->setPort(ID::D, sig_d);
2313 cell->setPort(ID::Q, sig_q);
2314 cell->set_src_attribute(src);
2315 return cell;
2316 }
2317
2318 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2319 {
2320 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2321 cell->parameters[ID::EN_POLARITY] = en_polarity;
2322 cell->parameters[ID::WIDTH] = sig_q.size();
2323 cell->setPort(ID::EN, sig_en);
2324 cell->setPort(ID::D, sig_d);
2325 cell->setPort(ID::Q, sig_q);
2326 cell->set_src_attribute(src);
2327 return cell;
2328 }
2329
2330 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2331 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2332 {
2333 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2334 cell->parameters[ID::EN_POLARITY] = en_polarity;
2335 cell->parameters[ID::SET_POLARITY] = set_polarity;
2336 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2337 cell->parameters[ID::WIDTH] = sig_q.size();
2338 cell->setPort(ID::EN, sig_en);
2339 cell->setPort(ID::SET, sig_set);
2340 cell->setPort(ID::CLR, sig_clr);
2341 cell->setPort(ID::D, sig_d);
2342 cell->setPort(ID::Q, sig_q);
2343 cell->set_src_attribute(src);
2344 return cell;
2345 }
2346
2347 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2348 {
2349 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2350 cell->setPort(ID::D, sig_d);
2351 cell->setPort(ID::Q, sig_q);
2352 cell->set_src_attribute(src);
2353 return cell;
2354 }
2355
2356 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2357 {
2358 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2359 cell->setPort(ID::C, sig_clk);
2360 cell->setPort(ID::D, sig_d);
2361 cell->setPort(ID::Q, sig_q);
2362 cell->set_src_attribute(src);
2363 return cell;
2364 }
2365
2366 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2367 {
2368 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2369 cell->setPort(ID::C, sig_clk);
2370 cell->setPort(ID::E, sig_en);
2371 cell->setPort(ID::D, sig_d);
2372 cell->setPort(ID::Q, sig_q);
2373 cell->set_src_attribute(src);
2374 return cell;
2375 }
2376
2377 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2378 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2379 {
2380 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2381 cell->setPort(ID::C, sig_clk);
2382 cell->setPort(ID::S, sig_set);
2383 cell->setPort(ID::R, sig_clr);
2384 cell->setPort(ID::D, sig_d);
2385 cell->setPort(ID::Q, sig_q);
2386 cell->set_src_attribute(src);
2387 return cell;
2388 }
2389
2390 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2391 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2392 {
2393 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2394 cell->setPort(ID::C, sig_clk);
2395 cell->setPort(ID::R, sig_arst);
2396 cell->setPort(ID::D, sig_d);
2397 cell->setPort(ID::Q, sig_q);
2398 cell->set_src_attribute(src);
2399 return cell;
2400 }
2401
2402 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2403 {
2404 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2405 cell->setPort(ID::E, sig_en);
2406 cell->setPort(ID::D, sig_d);
2407 cell->setPort(ID::Q, sig_q);
2408 cell->set_src_attribute(src);
2409 return cell;
2410 }
2411
2412 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2413 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2414 {
2415 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2416 cell->setPort(ID::E, sig_en);
2417 cell->setPort(ID::S, sig_set);
2418 cell->setPort(ID::R, sig_clr);
2419 cell->setPort(ID::D, sig_d);
2420 cell->setPort(ID::Q, sig_q);
2421 cell->set_src_attribute(src);
2422 return cell;
2423 }
2424
2425 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2426 {
2427 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2428 Cell *cell = addCell(name, ID($anyconst));
2429 cell->setParam(ID::WIDTH, width);
2430 cell->setPort(ID::Y, sig);
2431 cell->set_src_attribute(src);
2432 return sig;
2433 }
2434
2435 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2436 {
2437 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2438 Cell *cell = addCell(name, ID($anyseq));
2439 cell->setParam(ID::WIDTH, width);
2440 cell->setPort(ID::Y, sig);
2441 cell->set_src_attribute(src);
2442 return sig;
2443 }
2444
2445 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2446 {
2447 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2448 Cell *cell = addCell(name, ID($allconst));
2449 cell->setParam(ID::WIDTH, width);
2450 cell->setPort(ID::Y, sig);
2451 cell->set_src_attribute(src);
2452 return sig;
2453 }
2454
2455 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2456 {
2457 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2458 Cell *cell = addCell(name, ID($allseq));
2459 cell->setParam(ID::WIDTH, width);
2460 cell->setPort(ID::Y, sig);
2461 cell->set_src_attribute(src);
2462 return sig;
2463 }
2464
2465 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2466 {
2467 RTLIL::SigSpec sig = addWire(NEW_ID);
2468 Cell *cell = addCell(name, ID($initstate));
2469 cell->setPort(ID::Y, sig);
2470 cell->set_src_attribute(src);
2471 return sig;
2472 }
2473
2474 RTLIL::Wire::Wire()
2475 {
2476 static unsigned int hashidx_count = 123456789;
2477 hashidx_count = mkhash_xorshift(hashidx_count);
2478 hashidx_ = hashidx_count;
2479
2480 module = nullptr;
2481 width = 1;
2482 start_offset = 0;
2483 port_id = 0;
2484 port_input = false;
2485 port_output = false;
2486 upto = false;
2487 is_signed = false;
2488
2489 #ifdef WITH_PYTHON
2490 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2491 #endif
2492 }
2493
2494 RTLIL::Wire::~Wire()
2495 {
2496 #ifdef WITH_PYTHON
2497 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2498 #endif
2499 }
2500
2501 #ifdef WITH_PYTHON
2502 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2503 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2504 {
2505 return &all_wires;
2506 }
2507 #endif
2508
2509 RTLIL::Memory::Memory()
2510 {
2511 static unsigned int hashidx_count = 123456789;
2512 hashidx_count = mkhash_xorshift(hashidx_count);
2513 hashidx_ = hashidx_count;
2514
2515 width = 1;
2516 start_offset = 0;
2517 size = 0;
2518 #ifdef WITH_PYTHON
2519 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2520 #endif
2521 }
2522
2523 RTLIL::Cell::Cell() : module(nullptr)
2524 {
2525 static unsigned int hashidx_count = 123456789;
2526 hashidx_count = mkhash_xorshift(hashidx_count);
2527 hashidx_ = hashidx_count;
2528
2529 // log("#memtrace# %p\n", this);
2530 memhasher();
2531
2532 #ifdef WITH_PYTHON
2533 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2534 #endif
2535 }
2536
2537 RTLIL::Cell::~Cell()
2538 {
2539 #ifdef WITH_PYTHON
2540 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2541 #endif
2542 }
2543
2544 #ifdef WITH_PYTHON
2545 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2546 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2547 {
2548 return &all_cells;
2549 }
2550 #endif
2551
2552 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2553 {
2554 return connections_.count(portname) != 0;
2555 }
2556
2557 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2558 {
2559 RTLIL::SigSpec signal;
2560 auto conn_it = connections_.find(portname);
2561
2562 if (conn_it != connections_.end())
2563 {
2564 for (auto mon : module->monitors)
2565 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2566
2567 if (module->design)
2568 for (auto mon : module->design->monitors)
2569 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2570
2571 if (yosys_xtrace) {
2572 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2573 log_backtrace("-X- ", yosys_xtrace-1);
2574 }
2575
2576 connections_.erase(conn_it);
2577 }
2578 }
2579
2580 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2581 {
2582 auto r = connections_.insert(portname);
2583 auto conn_it = r.first;
2584 if (!r.second && conn_it->second == signal)
2585 return;
2586
2587 for (auto mon : module->monitors)
2588 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2589
2590 if (module->design)
2591 for (auto mon : module->design->monitors)
2592 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2593
2594 if (yosys_xtrace) {
2595 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2596 log_backtrace("-X- ", yosys_xtrace-1);
2597 }
2598
2599 conn_it->second = std::move(signal);
2600 }
2601
2602 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2603 {
2604 return connections_.at(portname);
2605 }
2606
2607 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2608 {
2609 return connections_;
2610 }
2611
2612 bool RTLIL::Cell::known() const
2613 {
2614 if (yosys_celltypes.cell_known(type))
2615 return true;
2616 if (module && module->design && module->design->module(type))
2617 return true;
2618 return false;
2619 }
2620
2621 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2622 {
2623 if (yosys_celltypes.cell_known(type))
2624 return yosys_celltypes.cell_input(type, portname);
2625 if (module && module->design) {
2626 RTLIL::Module *m = module->design->module(type);
2627 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2628 return w && w->port_input;
2629 }
2630 return false;
2631 }
2632
2633 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2634 {
2635 if (yosys_celltypes.cell_known(type))
2636 return yosys_celltypes.cell_output(type, portname);
2637 if (module && module->design) {
2638 RTLIL::Module *m = module->design->module(type);
2639 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2640 return w && w->port_output;
2641 }
2642 return false;
2643 }
2644
2645 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2646 {
2647 return parameters.count(paramname) != 0;
2648 }
2649
2650 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2651 {
2652 parameters.erase(paramname);
2653 }
2654
2655 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2656 {
2657 parameters[paramname] = std::move(value);
2658 }
2659
2660 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2661 {
2662 const auto &it = parameters.find(paramname);
2663 if (it != parameters.end())
2664 return it->second;
2665 if (module && module->design) {
2666 RTLIL::Module *m = module->design->module(type);
2667 if (m)
2668 return m->parameter_default_values.at(paramname);
2669 }
2670 throw std::out_of_range("Cell::getParam()");
2671 }
2672
2673 void RTLIL::Cell::sort()
2674 {
2675 connections_.sort(sort_by_id_str());
2676 parameters.sort(sort_by_id_str());
2677 attributes.sort(sort_by_id_str());
2678 }
2679
2680 void RTLIL::Cell::check()
2681 {
2682 #ifndef NDEBUG
2683 InternalCellChecker checker(NULL, this);
2684 checker.check();
2685 #endif
2686 }
2687
2688 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2689 {
2690 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2691 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2692 return;
2693
2694 if (type == ID($mux) || type == ID($pmux)) {
2695 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2696 if (type == ID($pmux))
2697 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2698 check();
2699 return;
2700 }
2701
2702 if (type == ID($lut) || type == ID($sop)) {
2703 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2704 return;
2705 }
2706
2707 if (type == ID($fa)) {
2708 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2709 return;
2710 }
2711
2712 if (type == ID($lcu)) {
2713 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2714 return;
2715 }
2716
2717 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2718
2719 if (connections_.count(ID::A)) {
2720 if (signedness_ab) {
2721 if (set_a_signed)
2722 parameters[ID::A_SIGNED] = true;
2723 else if (parameters.count(ID::A_SIGNED) == 0)
2724 parameters[ID::A_SIGNED] = false;
2725 }
2726 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2727 }
2728
2729 if (connections_.count(ID::B)) {
2730 if (signedness_ab) {
2731 if (set_b_signed)
2732 parameters[ID::B_SIGNED] = true;
2733 else if (parameters.count(ID::B_SIGNED) == 0)
2734 parameters[ID::B_SIGNED] = false;
2735 }
2736 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2737 }
2738
2739 if (connections_.count(ID::Y))
2740 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2741
2742 if (connections_.count(ID::Q))
2743 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2744
2745 check();
2746 }
2747
2748 RTLIL::SigChunk::SigChunk()
2749 {
2750 wire = NULL;
2751 width = 0;
2752 offset = 0;
2753 }
2754
2755 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2756 {
2757 wire = NULL;
2758 data = value.bits;
2759 width = GetSize(data);
2760 offset = 0;
2761 }
2762
2763 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2764 {
2765 log_assert(wire != nullptr);
2766 this->wire = wire;
2767 this->width = wire->width;
2768 this->offset = 0;
2769 }
2770
2771 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2772 {
2773 log_assert(wire != nullptr);
2774 this->wire = wire;
2775 this->width = width;
2776 this->offset = offset;
2777 }
2778
2779 RTLIL::SigChunk::SigChunk(const std::string &str)
2780 {
2781 wire = NULL;
2782 data = RTLIL::Const(str).bits;
2783 width = GetSize(data);
2784 offset = 0;
2785 }
2786
2787 RTLIL::SigChunk::SigChunk(int val, int width)
2788 {
2789 wire = NULL;
2790 data = RTLIL::Const(val, width).bits;
2791 this->width = GetSize(data);
2792 offset = 0;
2793 }
2794
2795 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2796 {
2797 wire = NULL;
2798 data = RTLIL::Const(bit, width).bits;
2799 this->width = GetSize(data);
2800 offset = 0;
2801 }
2802
2803 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2804 {
2805 wire = bit.wire;
2806 offset = 0;
2807 if (wire == NULL)
2808 data = RTLIL::Const(bit.data).bits;
2809 else
2810 offset = bit.offset;
2811 width = 1;
2812 }
2813
2814 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2815 {
2816 *this = sigchunk;
2817 }
2818
2819 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2820 {
2821 RTLIL::SigChunk ret;
2822 if (wire) {
2823 ret.wire = wire;
2824 ret.offset = this->offset + offset;
2825 ret.width = length;
2826 } else {
2827 for (int i = 0; i < length; i++)
2828 ret.data.push_back(data[offset+i]);
2829 ret.width = length;
2830 }
2831 return ret;
2832 }
2833
2834 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2835 {
2836 if (wire && other.wire)
2837 if (wire->name != other.wire->name)
2838 return wire->name < other.wire->name;
2839
2840 if (wire != other.wire)
2841 return wire < other.wire;
2842
2843 if (offset != other.offset)
2844 return offset < other.offset;
2845
2846 if (width != other.width)
2847 return width < other.width;
2848
2849 return data < other.data;
2850 }
2851
2852 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2853 {
2854 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2855 }
2856
2857 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2858 {
2859 if (*this == other)
2860 return false;
2861 return true;
2862 }
2863
2864 RTLIL::SigSpec::SigSpec()
2865 {
2866 width_ = 0;
2867 hash_ = 0;
2868 }
2869
2870 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2871 {
2872 *this = other;
2873 }
2874
2875 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2876 {
2877 cover("kernel.rtlil.sigspec.init.list");
2878
2879 width_ = 0;
2880 hash_ = 0;
2881
2882 log_assert(parts.size() > 0);
2883 auto ie = parts.begin();
2884 auto it = ie + parts.size() - 1;
2885 while (it >= ie)
2886 append(*it--);
2887 }
2888
2889 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2890 {
2891 cover("kernel.rtlil.sigspec.assign");
2892
2893 width_ = other.width_;
2894 hash_ = other.hash_;
2895 chunks_ = other.chunks_;
2896 bits_ = other.bits_;
2897 return *this;
2898 }
2899
2900 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2901 {
2902 cover("kernel.rtlil.sigspec.init.const");
2903
2904 chunks_.emplace_back(value);
2905 width_ = chunks_.back().width;
2906 hash_ = 0;
2907 check();
2908 }
2909
2910 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2911 {
2912 cover("kernel.rtlil.sigspec.init.chunk");
2913
2914 chunks_.emplace_back(chunk);
2915 width_ = chunks_.back().width;
2916 hash_ = 0;
2917 check();
2918 }
2919
2920 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2921 {
2922 cover("kernel.rtlil.sigspec.init.wire");
2923
2924 chunks_.emplace_back(wire);
2925 width_ = chunks_.back().width;
2926 hash_ = 0;
2927 check();
2928 }
2929
2930 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2931 {
2932 cover("kernel.rtlil.sigspec.init.wire_part");
2933
2934 chunks_.emplace_back(wire, offset, width);
2935 width_ = chunks_.back().width;
2936 hash_ = 0;
2937 check();
2938 }
2939
2940 RTLIL::SigSpec::SigSpec(const std::string &str)
2941 {
2942 cover("kernel.rtlil.sigspec.init.str");
2943
2944 chunks_.emplace_back(str);
2945 width_ = chunks_.back().width;
2946 hash_ = 0;
2947 check();
2948 }
2949
2950 RTLIL::SigSpec::SigSpec(int val, int width)
2951 {
2952 cover("kernel.rtlil.sigspec.init.int");
2953
2954 chunks_.emplace_back(val, width);
2955 width_ = width;
2956 hash_ = 0;
2957 check();
2958 }
2959
2960 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2961 {
2962 cover("kernel.rtlil.sigspec.init.state");
2963
2964 chunks_.emplace_back(bit, width);
2965 width_ = width;
2966 hash_ = 0;
2967 check();
2968 }
2969
2970 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2971 {
2972 cover("kernel.rtlil.sigspec.init.bit");
2973
2974 if (bit.wire == NULL)
2975 chunks_.emplace_back(bit.data, width);
2976 else
2977 for (int i = 0; i < width; i++)
2978 chunks_.push_back(bit);
2979 width_ = width;
2980 hash_ = 0;
2981 check();
2982 }
2983
2984 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2985 {
2986 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2987
2988 width_ = 0;
2989 hash_ = 0;
2990 for (const auto &c : chunks)
2991 append(c);
2992 check();
2993 }
2994
2995 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2996 {
2997 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2998
2999 width_ = 0;
3000 hash_ = 0;
3001 for (const auto &bit : bits)
3002 append(bit);
3003 check();
3004 }
3005
3006 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3007 {
3008 cover("kernel.rtlil.sigspec.init.pool_bits");
3009
3010 width_ = 0;
3011 hash_ = 0;
3012 for (const auto &bit : bits)
3013 append(bit);
3014 check();
3015 }
3016
3017 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3018 {
3019 cover("kernel.rtlil.sigspec.init.stdset_bits");
3020
3021 width_ = 0;
3022 hash_ = 0;
3023 for (const auto &bit : bits)
3024 append(bit);
3025 check();
3026 }
3027
3028 RTLIL::SigSpec::SigSpec(bool bit)
3029 {
3030 cover("kernel.rtlil.sigspec.init.bool");
3031
3032 width_ = 0;
3033 hash_ = 0;
3034 append(SigBit(bit));
3035 check();
3036 }
3037
3038 void RTLIL::SigSpec::pack() const
3039 {
3040 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3041
3042 if (that->bits_.empty())
3043 return;
3044
3045 cover("kernel.rtlil.sigspec.convert.pack");
3046 log_assert(that->chunks_.empty());
3047
3048 std::vector<RTLIL::SigBit> old_bits;
3049 old_bits.swap(that->bits_);
3050
3051 RTLIL::SigChunk *last = NULL;
3052 int last_end_offset = 0;
3053
3054 for (auto &bit : old_bits) {
3055 if (last && bit.wire == last->wire) {
3056 if (bit.wire == NULL) {
3057 last->data.push_back(bit.data);
3058 last->width++;
3059 continue;
3060 } else if (last_end_offset == bit.offset) {
3061 last_end_offset++;
3062 last->width++;
3063 continue;
3064 }
3065 }
3066 that->chunks_.push_back(bit);
3067 last = &that->chunks_.back();
3068 last_end_offset = bit.offset + 1;
3069 }
3070
3071 check();
3072 }
3073
3074 void RTLIL::SigSpec::unpack() const
3075 {
3076 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3077
3078 if (that->chunks_.empty())
3079 return;
3080
3081 cover("kernel.rtlil.sigspec.convert.unpack");
3082 log_assert(that->bits_.empty());
3083
3084 that->bits_.reserve(that->width_);
3085 for (auto &c : that->chunks_)
3086 for (int i = 0; i < c.width; i++)
3087 that->bits_.emplace_back(c, i);
3088
3089 that->chunks_.clear();
3090 that->hash_ = 0;
3091 }
3092
3093 void RTLIL::SigSpec::updhash() const
3094 {
3095 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3096
3097 if (that->hash_ != 0)
3098 return;
3099
3100 cover("kernel.rtlil.sigspec.hash");
3101 that->pack();
3102
3103 that->hash_ = mkhash_init;
3104 for (auto &c : that->chunks_)
3105 if (c.wire == NULL) {
3106 for (auto &v : c.data)
3107 that->hash_ = mkhash(that->hash_, v);
3108 } else {
3109 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3110 that->hash_ = mkhash(that->hash_, c.offset);
3111 that->hash_ = mkhash(that->hash_, c.width);
3112 }
3113
3114 if (that->hash_ == 0)
3115 that->hash_ = 1;
3116 }
3117
3118 void RTLIL::SigSpec::sort()
3119 {
3120 unpack();
3121 cover("kernel.rtlil.sigspec.sort");
3122 std::sort(bits_.begin(), bits_.end());
3123 }
3124
3125 void RTLIL::SigSpec::sort_and_unify()
3126 {
3127 unpack();
3128 cover("kernel.rtlil.sigspec.sort_and_unify");
3129
3130 // A copy of the bits vector is used to prevent duplicating the logic from
3131 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3132 // that isn't showing up as significant in profiles.
3133 std::vector<SigBit> unique_bits = bits_;
3134 std::sort(unique_bits.begin(), unique_bits.end());
3135 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3136 unique_bits.erase(last, unique_bits.end());
3137
3138 *this = unique_bits;
3139 }
3140
3141 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3142 {
3143 replace(pattern, with, this);
3144 }
3145
3146 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3147 {
3148 log_assert(other != NULL);
3149 log_assert(width_ == other->width_);
3150 log_assert(pattern.width_ == with.width_);
3151
3152 pattern.unpack();
3153 with.unpack();
3154 unpack();
3155 other->unpack();
3156
3157 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3158 if (pattern.bits_[i].wire != NULL) {
3159 for (int j = 0; j < GetSize(bits_); j++) {
3160 if (bits_[j] == pattern.bits_[i]) {
3161 other->bits_[j] = with.bits_[i];
3162 }
3163 }
3164 }
3165 }
3166
3167 other->check();
3168 }
3169
3170 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3171 {
3172 replace(rules, this);
3173 }
3174
3175 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3176 {
3177 cover("kernel.rtlil.sigspec.replace_dict");
3178
3179 log_assert(other != NULL);
3180 log_assert(width_ == other->width_);
3181
3182 if (rules.empty()) return;
3183 unpack();
3184 other->unpack();
3185
3186 for (int i = 0; i < GetSize(bits_); i++) {
3187 auto it = rules.find(bits_[i]);
3188 if (it != rules.end())
3189 other->bits_[i] = it->second;
3190 }
3191
3192 other->check();
3193 }
3194
3195 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3196 {
3197 replace(rules, this);
3198 }
3199
3200 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3201 {
3202 cover("kernel.rtlil.sigspec.replace_map");
3203
3204 log_assert(other != NULL);
3205 log_assert(width_ == other->width_);
3206
3207 if (rules.empty()) return;
3208 unpack();
3209 other->unpack();
3210
3211 for (int i = 0; i < GetSize(bits_); i++) {
3212 auto it = rules.find(bits_[i]);
3213 if (it != rules.end())
3214 other->bits_[i] = it->second;
3215 }
3216
3217 other->check();
3218 }
3219
3220 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3221 {
3222 remove2(pattern, NULL);
3223 }
3224
3225 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3226 {
3227 RTLIL::SigSpec tmp = *this;
3228 tmp.remove2(pattern, other);
3229 }
3230
3231 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3232 {
3233 if (other)
3234 cover("kernel.rtlil.sigspec.remove_other");
3235 else
3236 cover("kernel.rtlil.sigspec.remove");
3237
3238 unpack();
3239 if (other != NULL) {
3240 log_assert(width_ == other->width_);
3241 other->unpack();
3242 }
3243
3244 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3245 {
3246 if (bits_[i].wire == NULL) continue;
3247
3248 for (auto &pattern_chunk : pattern.chunks())
3249 if (bits_[i].wire == pattern_chunk.wire &&
3250 bits_[i].offset >= pattern_chunk.offset &&
3251 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3252 bits_.erase(bits_.begin() + i);
3253 width_--;
3254 if (other != NULL) {
3255 other->bits_.erase(other->bits_.begin() + i);
3256 other->width_--;
3257 }
3258 break;
3259 }
3260 }
3261
3262 check();
3263 }
3264
3265 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3266 {
3267 remove2(pattern, NULL);
3268 }
3269
3270 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3271 {
3272 RTLIL::SigSpec tmp = *this;
3273 tmp.remove2(pattern, other);
3274 }
3275
3276 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3277 {
3278 if (other)
3279 cover("kernel.rtlil.sigspec.remove_other");
3280 else
3281 cover("kernel.rtlil.sigspec.remove");
3282
3283 unpack();
3284
3285 if (other != NULL) {
3286 log_assert(width_ == other->width_);
3287 other->unpack();
3288 }
3289
3290 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3291 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3292 bits_.erase(bits_.begin() + i);
3293 width_--;
3294 if (other != NULL) {
3295 other->bits_.erase(other->bits_.begin() + i);
3296 other->width_--;
3297 }
3298 }
3299 }
3300
3301 check();
3302 }
3303
3304 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3305 {
3306 if (other)
3307 cover("kernel.rtlil.sigspec.remove_other");
3308 else
3309 cover("kernel.rtlil.sigspec.remove");
3310
3311 unpack();
3312
3313 if (other != NULL) {
3314 log_assert(width_ == other->width_);
3315 other->unpack();
3316 }
3317
3318 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3319 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3320 bits_.erase(bits_.begin() + i);
3321 width_--;
3322 if (other != NULL) {
3323 other->bits_.erase(other->bits_.begin() + i);
3324 other->width_--;
3325 }
3326 }
3327 }
3328
3329 check();
3330 }
3331
3332 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3333 {
3334 if (other)
3335 cover("kernel.rtlil.sigspec.extract_other");
3336 else
3337 cover("kernel.rtlil.sigspec.extract");
3338
3339 log_assert(other == NULL || width_ == other->width_);
3340
3341 RTLIL::SigSpec ret;
3342 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3343
3344 for (auto& pattern_chunk : pattern.chunks()) {
3345 if (other) {
3346 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3347 for (int i = 0; i < width_; i++)
3348 if (bits_match[i].wire &&
3349 bits_match[i].wire == pattern_chunk.wire &&
3350 bits_match[i].offset >= pattern_chunk.offset &&
3351 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3352 ret.append(bits_other[i]);
3353 } else {
3354 for (int i = 0; i < width_; i++)
3355 if (bits_match[i].wire &&
3356 bits_match[i].wire == pattern_chunk.wire &&
3357 bits_match[i].offset >= pattern_chunk.offset &&
3358 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3359 ret.append(bits_match[i]);
3360 }
3361 }
3362
3363 ret.check();
3364 return ret;
3365 }
3366
3367 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3368 {
3369 if (other)
3370 cover("kernel.rtlil.sigspec.extract_other");
3371 else
3372 cover("kernel.rtlil.sigspec.extract");
3373
3374 log_assert(other == NULL || width_ == other->width_);
3375
3376 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3377 RTLIL::SigSpec ret;
3378
3379 if (other) {
3380 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3381 for (int i = 0; i < width_; i++)
3382 if (bits_match[i].wire && pattern.count(bits_match[i]))
3383 ret.append(bits_other[i]);
3384 } else {
3385 for (int i = 0; i < width_; i++)
3386 if (bits_match[i].wire && pattern.count(bits_match[i]))
3387 ret.append(bits_match[i]);
3388 }
3389
3390 ret.check();
3391 return ret;
3392 }
3393
3394 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3395 {
3396 cover("kernel.rtlil.sigspec.replace_pos");
3397
3398 unpack();
3399 with.unpack();
3400
3401 log_assert(offset >= 0);
3402 log_assert(with.width_ >= 0);
3403 log_assert(offset+with.width_ <= width_);
3404
3405 for (int i = 0; i < with.width_; i++)
3406 bits_.at(offset + i) = with.bits_.at(i);
3407
3408 check();
3409 }
3410
3411 void RTLIL::SigSpec::remove_const()
3412 {
3413 if (packed())
3414 {
3415 cover("kernel.rtlil.sigspec.remove_const.packed");
3416
3417 std::vector<RTLIL::SigChunk> new_chunks;
3418 new_chunks.reserve(GetSize(chunks_));
3419
3420 width_ = 0;
3421 for (auto &chunk : chunks_)
3422 if (chunk.wire != NULL) {
3423 new_chunks.push_back(chunk);
3424 width_ += chunk.width;
3425 }
3426
3427 chunks_.swap(new_chunks);
3428 }
3429 else
3430 {
3431 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3432
3433 std::vector<RTLIL::SigBit> new_bits;
3434 new_bits.reserve(width_);
3435
3436 for (auto &bit : bits_)
3437 if (bit.wire != NULL)
3438 new_bits.push_back(bit);
3439
3440 bits_.swap(new_bits);
3441 width_ = bits_.size();
3442 }
3443
3444 check();
3445 }
3446
3447 void RTLIL::SigSpec::remove(int offset, int length)
3448 {
3449 cover("kernel.rtlil.sigspec.remove_pos");
3450
3451 unpack();
3452
3453 log_assert(offset >= 0);
3454 log_assert(length >= 0);
3455 log_assert(offset + length <= width_);
3456
3457 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3458 width_ = bits_.size();
3459
3460 check();
3461 }
3462
3463 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3464 {
3465 unpack();
3466 cover("kernel.rtlil.sigspec.extract_pos");
3467 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3468 }
3469
3470 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3471 {
3472 if (signal.width_ == 0)
3473 return;
3474
3475 if (width_ == 0) {
3476 *this = signal;
3477 return;
3478 }
3479
3480 cover("kernel.rtlil.sigspec.append");
3481
3482 if (packed() != signal.packed()) {
3483 pack();
3484 signal.pack();
3485 }
3486
3487 if (packed())
3488 for (auto &other_c : signal.chunks_)
3489 {
3490 auto &my_last_c = chunks_.back();
3491 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3492 auto &this_data = my_last_c.data;
3493 auto &other_data = other_c.data;
3494 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3495 my_last_c.width += other_c.width;
3496 } else
3497 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3498 my_last_c.width += other_c.width;
3499 } else
3500 chunks_.push_back(other_c);
3501 }
3502 else
3503 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3504
3505 width_ += signal.width_;
3506 check();
3507 }
3508
3509 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3510 {
3511 if (packed())
3512 {
3513 cover("kernel.rtlil.sigspec.append_bit.packed");
3514
3515 if (chunks_.size() == 0)
3516 chunks_.push_back(bit);
3517 else
3518 if (bit.wire == NULL)
3519 if (chunks_.back().wire == NULL) {
3520 chunks_.back().data.push_back(bit.data);
3521 chunks_.back().width++;
3522 } else
3523 chunks_.push_back(bit);
3524 else
3525 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3526 chunks_.back().width++;
3527 else
3528 chunks_.push_back(bit);
3529 }
3530 else
3531 {
3532 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3533 bits_.push_back(bit);
3534 }
3535
3536 width_++;
3537 check();
3538 }
3539
3540 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3541 {
3542 cover("kernel.rtlil.sigspec.extend_u0");
3543
3544 pack();
3545
3546 if (width_ > width)
3547 remove(width, width_ - width);
3548
3549 if (width_ < width) {
3550 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3551 if (!is_signed)
3552 padding = RTLIL::State::S0;
3553 while (width_ < width)
3554 append(padding);
3555 }
3556
3557 }
3558
3559 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3560 {
3561 cover("kernel.rtlil.sigspec.repeat");
3562
3563 RTLIL::SigSpec sig;
3564 for (int i = 0; i < num; i++)
3565 sig.append(*this);
3566 return sig;
3567 }
3568
3569 #ifndef NDEBUG
3570 void RTLIL::SigSpec::check() const
3571 {
3572 if (width_ > 64)
3573 {
3574 cover("kernel.rtlil.sigspec.check.skip");
3575 }
3576 else if (packed())
3577 {
3578 cover("kernel.rtlil.sigspec.check.packed");
3579
3580 int w = 0;
3581 for (size_t i = 0; i < chunks_.size(); i++) {
3582 const RTLIL::SigChunk &chunk = chunks_[i];
3583 if (chunk.wire == NULL) {
3584 if (i > 0)
3585 log_assert(chunks_[i-1].wire != NULL);
3586 log_assert(chunk.offset == 0);
3587 log_assert(chunk.data.size() == (size_t)chunk.width);
3588 } else {
3589 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3590 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3591 log_assert(chunk.offset >= 0);
3592 log_assert(chunk.width >= 0);
3593 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3594 log_assert(chunk.data.size() == 0);
3595 }
3596 w += chunk.width;
3597 }
3598 log_assert(w == width_);
3599 log_assert(bits_.empty());
3600 }
3601 else
3602 {
3603 cover("kernel.rtlil.sigspec.check.unpacked");
3604
3605 log_assert(width_ == GetSize(bits_));
3606 log_assert(chunks_.empty());
3607 }
3608 }
3609 #endif
3610
3611 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3612 {
3613 cover("kernel.rtlil.sigspec.comp_lt");
3614
3615 if (this == &other)
3616 return false;
3617
3618 if (width_ != other.width_)
3619 return width_ < other.width_;
3620
3621 pack();
3622 other.pack();
3623
3624 if (chunks_.size() != other.chunks_.size())
3625 return chunks_.size() < other.chunks_.size();
3626
3627 updhash();
3628 other.updhash();
3629
3630 if (hash_ != other.hash_)
3631 return hash_ < other.hash_;
3632
3633 for (size_t i = 0; i < chunks_.size(); i++)
3634 if (chunks_[i] != other.chunks_[i]) {
3635 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3636 return chunks_[i] < other.chunks_[i];
3637 }
3638
3639 cover("kernel.rtlil.sigspec.comp_lt.equal");
3640 return false;
3641 }
3642
3643 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3644 {
3645 cover("kernel.rtlil.sigspec.comp_eq");
3646
3647 if (this == &other)
3648 return true;
3649
3650 if (width_ != other.width_)
3651 return false;
3652
3653 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3654 // since the RHS will contain one SigChunk of width 0 causing
3655 // the size check below to fail
3656 if (width_ == 0)
3657 return true;
3658
3659 pack();
3660 other.pack();
3661
3662 if (chunks_.size() != other.chunks_.size())
3663 return false;
3664
3665 updhash();
3666 other.updhash();
3667
3668 if (hash_ != other.hash_)
3669 return false;
3670
3671 for (size_t i = 0; i < chunks_.size(); i++)
3672 if (chunks_[i] != other.chunks_[i]) {
3673 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3674 return false;
3675 }
3676
3677 cover("kernel.rtlil.sigspec.comp_eq.equal");
3678 return true;
3679 }
3680
3681 bool RTLIL::SigSpec::is_wire() const
3682 {
3683 cover("kernel.rtlil.sigspec.is_wire");
3684
3685 pack();
3686 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3687 }
3688
3689 bool RTLIL::SigSpec::is_chunk() const
3690 {
3691 cover("kernel.rtlil.sigspec.is_chunk");
3692
3693 pack();
3694 return GetSize(chunks_) == 1;
3695 }
3696
3697 bool RTLIL::SigSpec::is_fully_const() const
3698 {
3699 cover("kernel.rtlil.sigspec.is_fully_const");
3700
3701 pack();
3702 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3703 if (it->width > 0 && it->wire != NULL)
3704 return false;
3705 return true;
3706 }
3707
3708 bool RTLIL::SigSpec::is_fully_zero() const
3709 {
3710 cover("kernel.rtlil.sigspec.is_fully_zero");
3711
3712 pack();
3713 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3714 if (it->width > 0 && it->wire != NULL)
3715 return false;
3716 for (size_t i = 0; i < it->data.size(); i++)
3717 if (it->data[i] != RTLIL::State::S0)
3718 return false;
3719 }
3720 return true;
3721 }
3722
3723 bool RTLIL::SigSpec::is_fully_ones() const
3724 {
3725 cover("kernel.rtlil.sigspec.is_fully_ones");
3726
3727 pack();
3728 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3729 if (it->width > 0 && it->wire != NULL)
3730 return false;
3731 for (size_t i = 0; i < it->data.size(); i++)
3732 if (it->data[i] != RTLIL::State::S1)
3733 return false;
3734 }
3735 return true;
3736 }
3737
3738 bool RTLIL::SigSpec::is_fully_def() const
3739 {
3740 cover("kernel.rtlil.sigspec.is_fully_def");
3741
3742 pack();
3743 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3744 if (it->width > 0 && it->wire != NULL)
3745 return false;
3746 for (size_t i = 0; i < it->data.size(); i++)
3747 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3748 return false;
3749 }
3750 return true;
3751 }
3752
3753 bool RTLIL::SigSpec::is_fully_undef() const
3754 {
3755 cover("kernel.rtlil.sigspec.is_fully_undef");
3756
3757 pack();
3758 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3759 if (it->width > 0 && it->wire != NULL)
3760 return false;
3761 for (size_t i = 0; i < it->data.size(); i++)
3762 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3763 return false;
3764 }
3765 return true;
3766 }
3767
3768 bool RTLIL::SigSpec::has_const() const
3769 {
3770 cover("kernel.rtlil.sigspec.has_const");
3771
3772 pack();
3773 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3774 if (it->width > 0 && it->wire == NULL)
3775 return true;
3776 return false;
3777 }
3778
3779 bool RTLIL::SigSpec::has_marked_bits() const
3780 {
3781 cover("kernel.rtlil.sigspec.has_marked_bits");
3782
3783 pack();
3784 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3785 if (it->width > 0 && it->wire == NULL) {
3786 for (size_t i = 0; i < it->data.size(); i++)
3787 if (it->data[i] == RTLIL::State::Sm)
3788 return true;
3789 }
3790 return false;
3791 }
3792
3793 bool RTLIL::SigSpec::as_bool() const
3794 {
3795 cover("kernel.rtlil.sigspec.as_bool");
3796
3797 pack();
3798 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3799 if (width_)
3800 return RTLIL::Const(chunks_[0].data).as_bool();
3801 return false;
3802 }
3803
3804 int RTLIL::SigSpec::as_int(bool is_signed) const
3805 {
3806 cover("kernel.rtlil.sigspec.as_int");
3807
3808 pack();
3809 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3810 if (width_)
3811 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3812 return 0;
3813 }
3814
3815 std::string RTLIL::SigSpec::as_string() const
3816 {
3817 cover("kernel.rtlil.sigspec.as_string");
3818
3819 pack();
3820 std::string str;
3821 str.reserve(size());
3822 for (size_t i = chunks_.size(); i > 0; i--) {
3823 const RTLIL::SigChunk &chunk = chunks_[i-1];
3824 if (chunk.wire != NULL)
3825 str.append(chunk.width, '?');
3826 else
3827 str += RTLIL::Const(chunk.data).as_string();
3828 }
3829 return str;
3830 }
3831
3832 RTLIL::Const RTLIL::SigSpec::as_const() const
3833 {
3834 cover("kernel.rtlil.sigspec.as_const");
3835
3836 pack();
3837 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3838 if (width_)
3839 return chunks_[0].data;
3840 return RTLIL::Const();
3841 }
3842
3843 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3844 {
3845 cover("kernel.rtlil.sigspec.as_wire");
3846
3847 pack();
3848 log_assert(is_wire());
3849 return chunks_[0].wire;
3850 }
3851
3852 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3853 {
3854 cover("kernel.rtlil.sigspec.as_chunk");
3855
3856 pack();
3857 log_assert(is_chunk());
3858 return chunks_[0];
3859 }
3860
3861 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3862 {
3863 cover("kernel.rtlil.sigspec.as_bit");
3864
3865 log_assert(width_ == 1);
3866 if (packed())
3867 return RTLIL::SigBit(*chunks_.begin());
3868 else
3869 return bits_[0];
3870 }
3871
3872 bool RTLIL::SigSpec::match(const char* pattern) const
3873 {
3874 cover("kernel.rtlil.sigspec.match");
3875
3876 unpack();
3877 log_assert(int(strlen(pattern)) == GetSize(bits_));
3878
3879 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3880 if (*pattern == ' ')
3881 continue;
3882 if (*pattern == '*') {
3883 if (*it != State::Sz && *it != State::Sx)
3884 return false;
3885 continue;
3886 }
3887 if (*pattern == '0') {
3888 if (*it != State::S0)
3889 return false;
3890 } else
3891 if (*pattern == '1') {
3892 if (*it != State::S1)
3893 return false;
3894 } else
3895 log_abort();
3896 }
3897
3898 return true;
3899 }
3900
3901 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3902 {
3903 cover("kernel.rtlil.sigspec.to_sigbit_set");
3904
3905 pack();
3906 std::set<RTLIL::SigBit> sigbits;
3907 for (auto &c : chunks_)
3908 for (int i = 0; i < c.width; i++)
3909 sigbits.insert(RTLIL::SigBit(c, i));
3910 return sigbits;
3911 }
3912
3913 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3914 {
3915 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3916
3917 pack();
3918 pool<RTLIL::SigBit> sigbits;
3919 sigbits.reserve(size());
3920 for (auto &c : chunks_)
3921 for (int i = 0; i < c.width; i++)
3922 sigbits.insert(RTLIL::SigBit(c, i));
3923 return sigbits;
3924 }
3925
3926 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3927 {
3928 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3929
3930 unpack();
3931 return bits_;
3932 }
3933
3934 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3935 {
3936 cover("kernel.rtlil.sigspec.to_sigbit_map");
3937
3938 unpack();
3939 other.unpack();
3940
3941 log_assert(width_ == other.width_);
3942
3943 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3944 for (int i = 0; i < width_; i++)
3945 new_map[bits_[i]] = other.bits_[i];
3946
3947 return new_map;
3948 }
3949
3950 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3951 {
3952 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3953
3954 unpack();
3955 other.unpack();
3956
3957 log_assert(width_ == other.width_);
3958
3959 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3960 new_map.reserve(size());
3961 for (int i = 0; i < width_; i++)
3962 new_map[bits_[i]] = other.bits_[i];
3963
3964 return new_map;
3965 }
3966
3967 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3968 {
3969 size_t start = 0, end = 0;
3970 while ((end = text.find(sep, start)) != std::string::npos) {
3971 tokens.push_back(text.substr(start, end - start));
3972 start = end + 1;
3973 }
3974 tokens.push_back(text.substr(start));
3975 }
3976
3977 static int sigspec_parse_get_dummy_line_num()
3978 {
3979 return 0;
3980 }
3981
3982 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3983 {
3984 cover("kernel.rtlil.sigspec.parse");
3985
3986 AST::current_filename = "input";
3987
3988 std::vector<std::string> tokens;
3989 sigspec_parse_split(tokens, str, ',');
3990
3991 sig = RTLIL::SigSpec();
3992 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3993 {
3994 std::string netname = tokens[tokidx];
3995 std::string indices;
3996
3997 if (netname.size() == 0)
3998 continue;
3999
4000 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4001 cover("kernel.rtlil.sigspec.parse.const");
4002 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4003 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4004 if (ast == NULL)
4005 return false;
4006 sig.append(RTLIL::Const(ast->bits));
4007 delete ast;
4008 continue;
4009 }
4010
4011 if (module == NULL)
4012 return false;
4013
4014 cover("kernel.rtlil.sigspec.parse.net");
4015
4016 if (netname[0] != '$' && netname[0] != '\\')
4017 netname = "\\" + netname;
4018
4019 if (module->wires_.count(netname) == 0) {
4020 size_t indices_pos = netname.size()-1;
4021 if (indices_pos > 2 && netname[indices_pos] == ']')
4022 {
4023 indices_pos--;
4024 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4025 if (indices_pos > 0 && netname[indices_pos] == ':') {
4026 indices_pos--;
4027 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4028 }
4029 if (indices_pos > 0 && netname[indices_pos] == '[') {
4030 indices = netname.substr(indices_pos);
4031 netname = netname.substr(0, indices_pos);
4032 }
4033 }
4034 }
4035
4036 if (module->wires_.count(netname) == 0)
4037 return false;
4038
4039 RTLIL::Wire *wire = module->wires_.at(netname);
4040 if (!indices.empty()) {
4041 std::vector<std::string> index_tokens;
4042 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4043 if (index_tokens.size() == 1) {
4044 cover("kernel.rtlil.sigspec.parse.bit_sel");
4045 int a = atoi(index_tokens.at(0).c_str());
4046 if (a < 0 || a >= wire->width)
4047 return false;
4048 sig.append(RTLIL::SigSpec(wire, a));
4049 } else {
4050 cover("kernel.rtlil.sigspec.parse.part_sel");
4051 int a = atoi(index_tokens.at(0).c_str());
4052 int b = atoi(index_tokens.at(1).c_str());
4053 if (a > b) {
4054 int tmp = a;
4055 a = b, b = tmp;
4056 }
4057 if (a < 0 || a >= wire->width)
4058 return false;
4059 if (b < 0 || b >= wire->width)
4060 return false;
4061 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4062 }
4063 } else
4064 sig.append(wire);
4065 }
4066
4067 return true;
4068 }
4069
4070 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4071 {
4072 if (str.empty() || str[0] != '@')
4073 return parse(sig, module, str);
4074
4075 cover("kernel.rtlil.sigspec.parse.sel");
4076
4077 str = RTLIL::escape_id(str.substr(1));
4078 if (design->selection_vars.count(str) == 0)
4079 return false;
4080
4081 sig = RTLIL::SigSpec();
4082 RTLIL::Selection &sel = design->selection_vars.at(str);
4083 for (auto &it : module->wires_)
4084 if (sel.selected_member(module->name, it.first))
4085 sig.append(it.second);
4086
4087 return true;
4088 }
4089
4090 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4091 {
4092 if (str == "0") {
4093 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4094 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4095 return true;
4096 }
4097
4098 if (str == "~0") {
4099 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4100 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4101 return true;
4102 }
4103
4104 if (lhs.chunks_.size() == 1) {
4105 char *p = (char*)str.c_str(), *endptr;
4106 long int val = strtol(p, &endptr, 10);
4107 if (endptr && endptr != p && *endptr == 0) {
4108 sig = RTLIL::SigSpec(val, lhs.width_);
4109 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4110 return true;
4111 }
4112 }
4113
4114 return parse(sig, module, str);
4115 }
4116
4117 RTLIL::CaseRule::~CaseRule()
4118 {
4119 for (auto it = switches.begin(); it != switches.end(); it++)
4120 delete *it;
4121 }
4122
4123 bool RTLIL::CaseRule::empty() const
4124 {
4125 return actions.empty() && switches.empty();
4126 }
4127
4128 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4129 {
4130 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4131 new_caserule->compare = compare;
4132 new_caserule->actions = actions;
4133 for (auto &it : switches)
4134 new_caserule->switches.push_back(it->clone());
4135 return new_caserule;
4136 }
4137
4138 RTLIL::SwitchRule::~SwitchRule()
4139 {
4140 for (auto it = cases.begin(); it != cases.end(); it++)
4141 delete *it;
4142 }
4143
4144 bool RTLIL::SwitchRule::empty() const
4145 {
4146 return cases.empty();
4147 }
4148
4149 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4150 {
4151 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4152 new_switchrule->signal = signal;
4153 new_switchrule->attributes = attributes;
4154 for (auto &it : cases)
4155 new_switchrule->cases.push_back(it->clone());
4156 return new_switchrule;
4157
4158 }
4159
4160 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4161 {
4162 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4163 new_syncrule->type = type;
4164 new_syncrule->signal = signal;
4165 new_syncrule->actions = actions;
4166 return new_syncrule;
4167 }
4168
4169 RTLIL::Process::~Process()
4170 {
4171 for (auto it = syncs.begin(); it != syncs.end(); it++)
4172 delete *it;
4173 }
4174
4175 RTLIL::Process *RTLIL::Process::clone() const
4176 {
4177 RTLIL::Process *new_proc = new RTLIL::Process;
4178
4179 new_proc->name = name;
4180 new_proc->attributes = attributes;
4181
4182 RTLIL::CaseRule *rc_ptr = root_case.clone();
4183 new_proc->root_case = *rc_ptr;
4184 rc_ptr->switches.clear();
4185 delete rc_ptr;
4186
4187 for (auto &it : syncs)
4188 new_proc->syncs.push_back(it->clone());
4189
4190 return new_proc;
4191 }
4192
4193 #ifdef WITH_PYTHON
4194 RTLIL::Memory::~Memory()
4195 {
4196 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4197 }
4198 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4199 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4200 {
4201 return &all_memorys;
4202 }
4203 #endif
4204 YOSYS_NAMESPACE_END