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Merge pull request #2330 from antmicro/arrays-fix-multirange-access
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/rtlil/rtlil_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($dffsre),
58 ID($adff),
59 ID($adffe),
60 ID($sdff),
61 ID($sdffe),
62 ID($sdffce),
63 ID($dlatch),
64 ID($adlatch),
65 ID($dlatchsr),
66 ID($_DFFE_NN_),
67 ID($_DFFE_NP_),
68 ID($_DFFE_PN_),
69 ID($_DFFE_PP_),
70 ID($_DFFSR_NNN_),
71 ID($_DFFSR_NNP_),
72 ID($_DFFSR_NPN_),
73 ID($_DFFSR_NPP_),
74 ID($_DFFSR_PNN_),
75 ID($_DFFSR_PNP_),
76 ID($_DFFSR_PPN_),
77 ID($_DFFSR_PPP_),
78 ID($_DFFSRE_NNNN_),
79 ID($_DFFSRE_NNNP_),
80 ID($_DFFSRE_NNPN_),
81 ID($_DFFSRE_NNPP_),
82 ID($_DFFSRE_NPNN_),
83 ID($_DFFSRE_NPNP_),
84 ID($_DFFSRE_NPPN_),
85 ID($_DFFSRE_NPPP_),
86 ID($_DFFSRE_PNNN_),
87 ID($_DFFSRE_PNNP_),
88 ID($_DFFSRE_PNPN_),
89 ID($_DFFSRE_PNPP_),
90 ID($_DFFSRE_PPNN_),
91 ID($_DFFSRE_PPNP_),
92 ID($_DFFSRE_PPPN_),
93 ID($_DFFSRE_PPPP_),
94 ID($_DFF_N_),
95 ID($_DFF_P_),
96 ID($_DFF_NN0_),
97 ID($_DFF_NN1_),
98 ID($_DFF_NP0_),
99 ID($_DFF_NP1_),
100 ID($_DFF_PN0_),
101 ID($_DFF_PN1_),
102 ID($_DFF_PP0_),
103 ID($_DFF_PP1_),
104 ID($_DFFE_NN0N_),
105 ID($_DFFE_NN0P_),
106 ID($_DFFE_NN1N_),
107 ID($_DFFE_NN1P_),
108 ID($_DFFE_NP0N_),
109 ID($_DFFE_NP0P_),
110 ID($_DFFE_NP1N_),
111 ID($_DFFE_NP1P_),
112 ID($_DFFE_PN0N_),
113 ID($_DFFE_PN0P_),
114 ID($_DFFE_PN1N_),
115 ID($_DFFE_PN1P_),
116 ID($_DFFE_PP0N_),
117 ID($_DFFE_PP0P_),
118 ID($_DFFE_PP1N_),
119 ID($_DFFE_PP1P_),
120 ID($_SDFF_NN0_),
121 ID($_SDFF_NN1_),
122 ID($_SDFF_NP0_),
123 ID($_SDFF_NP1_),
124 ID($_SDFF_PN0_),
125 ID($_SDFF_PN1_),
126 ID($_SDFF_PP0_),
127 ID($_SDFF_PP1_),
128 ID($_SDFFE_NN0N_),
129 ID($_SDFFE_NN0P_),
130 ID($_SDFFE_NN1N_),
131 ID($_SDFFE_NN1P_),
132 ID($_SDFFE_NP0N_),
133 ID($_SDFFE_NP0P_),
134 ID($_SDFFE_NP1N_),
135 ID($_SDFFE_NP1P_),
136 ID($_SDFFE_PN0N_),
137 ID($_SDFFE_PN0P_),
138 ID($_SDFFE_PN1N_),
139 ID($_SDFFE_PN1P_),
140 ID($_SDFFE_PP0N_),
141 ID($_SDFFE_PP0P_),
142 ID($_SDFFE_PP1N_),
143 ID($_SDFFE_PP1P_),
144 ID($_SDFFCE_NN0N_),
145 ID($_SDFFCE_NN0P_),
146 ID($_SDFFCE_NN1N_),
147 ID($_SDFFCE_NN1P_),
148 ID($_SDFFCE_NP0N_),
149 ID($_SDFFCE_NP0P_),
150 ID($_SDFFCE_NP1N_),
151 ID($_SDFFCE_NP1P_),
152 ID($_SDFFCE_PN0N_),
153 ID($_SDFFCE_PN0P_),
154 ID($_SDFFCE_PN1N_),
155 ID($_SDFFCE_PN1P_),
156 ID($_SDFFCE_PP0N_),
157 ID($_SDFFCE_PP0P_),
158 ID($_SDFFCE_PP1N_),
159 ID($_SDFFCE_PP1P_),
160 ID($_SR_NN_),
161 ID($_SR_NP_),
162 ID($_SR_PN_),
163 ID($_SR_PP_),
164 ID($_DLATCH_N_),
165 ID($_DLATCH_P_),
166 ID($_DLATCH_NN0_),
167 ID($_DLATCH_NN1_),
168 ID($_DLATCH_NP0_),
169 ID($_DLATCH_NP1_),
170 ID($_DLATCH_PN0_),
171 ID($_DLATCH_PN1_),
172 ID($_DLATCH_PP0_),
173 ID($_DLATCH_PP1_),
174 ID($_DLATCHSR_NNN_),
175 ID($_DLATCHSR_NNP_),
176 ID($_DLATCHSR_NPN_),
177 ID($_DLATCHSR_NPP_),
178 ID($_DLATCHSR_PNN_),
179 ID($_DLATCHSR_PNP_),
180 ID($_DLATCHSR_PPN_),
181 ID($_DLATCHSR_PPP_),
182 ID($_FF_),
183 };
184 return res;
185 }
186
187 RTLIL::Const::Const()
188 {
189 flags = RTLIL::CONST_FLAG_NONE;
190 }
191
192 RTLIL::Const::Const(std::string str)
193 {
194 flags = RTLIL::CONST_FLAG_STRING;
195 for (int i = str.size()-1; i >= 0; i--) {
196 unsigned char ch = str[i];
197 for (int j = 0; j < 8; j++) {
198 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
199 ch = ch >> 1;
200 }
201 }
202 }
203
204 RTLIL::Const::Const(int val, int width)
205 {
206 flags = RTLIL::CONST_FLAG_NONE;
207 for (int i = 0; i < width; i++) {
208 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
209 val = val >> 1;
210 }
211 }
212
213 RTLIL::Const::Const(RTLIL::State bit, int width)
214 {
215 flags = RTLIL::CONST_FLAG_NONE;
216 for (int i = 0; i < width; i++)
217 bits.push_back(bit);
218 }
219
220 RTLIL::Const::Const(const std::vector<bool> &bits)
221 {
222 flags = RTLIL::CONST_FLAG_NONE;
223 for (const auto &b : bits)
224 this->bits.emplace_back(b ? State::S1 : State::S0);
225 }
226
227 RTLIL::Const::Const(const RTLIL::Const &c)
228 {
229 flags = c.flags;
230 for (const auto &b : c.bits)
231 this->bits.push_back(b);
232 }
233
234 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
235 {
236 if (bits.size() != other.bits.size())
237 return bits.size() < other.bits.size();
238 for (size_t i = 0; i < bits.size(); i++)
239 if (bits[i] != other.bits[i])
240 return bits[i] < other.bits[i];
241 return false;
242 }
243
244 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
245 {
246 return bits == other.bits;
247 }
248
249 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
250 {
251 return bits != other.bits;
252 }
253
254 bool RTLIL::Const::as_bool() const
255 {
256 for (size_t i = 0; i < bits.size(); i++)
257 if (bits[i] == State::S1)
258 return true;
259 return false;
260 }
261
262 int RTLIL::Const::as_int(bool is_signed) const
263 {
264 int32_t ret = 0;
265 for (size_t i = 0; i < bits.size() && i < 32; i++)
266 if (bits[i] == State::S1)
267 ret |= 1 << i;
268 if (is_signed && bits.back() == State::S1)
269 for (size_t i = bits.size(); i < 32; i++)
270 ret |= 1 << i;
271 return ret;
272 }
273
274 std::string RTLIL::Const::as_string() const
275 {
276 std::string ret;
277 ret.reserve(bits.size());
278 for (size_t i = bits.size(); i > 0; i--)
279 switch (bits[i-1]) {
280 case S0: ret += "0"; break;
281 case S1: ret += "1"; break;
282 case Sx: ret += "x"; break;
283 case Sz: ret += "z"; break;
284 case Sa: ret += "-"; break;
285 case Sm: ret += "m"; break;
286 }
287 return ret;
288 }
289
290 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
291 {
292 Const c;
293 c.bits.reserve(str.size());
294 for (auto it = str.rbegin(); it != str.rend(); it++)
295 switch (*it) {
296 case '0': c.bits.push_back(State::S0); break;
297 case '1': c.bits.push_back(State::S1); break;
298 case 'x': c.bits.push_back(State::Sx); break;
299 case 'z': c.bits.push_back(State::Sz); break;
300 case 'm': c.bits.push_back(State::Sm); break;
301 default: c.bits.push_back(State::Sa);
302 }
303 return c;
304 }
305
306 std::string RTLIL::Const::decode_string() const
307 {
308 std::string string;
309 string.reserve(GetSize(bits)/8);
310 for (int i = 0; i < GetSize(bits); i += 8) {
311 char ch = 0;
312 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
313 if (bits[i + j] == RTLIL::State::S1)
314 ch |= 1 << j;
315 if (ch != 0)
316 string.append({ch});
317 }
318 std::reverse(string.begin(), string.end());
319 return string;
320 }
321
322 bool RTLIL::Const::is_fully_zero() const
323 {
324 cover("kernel.rtlil.const.is_fully_zero");
325
326 for (const auto &bit : bits)
327 if (bit != RTLIL::State::S0)
328 return false;
329
330 return true;
331 }
332
333 bool RTLIL::Const::is_fully_ones() const
334 {
335 cover("kernel.rtlil.const.is_fully_ones");
336
337 for (const auto &bit : bits)
338 if (bit != RTLIL::State::S1)
339 return false;
340
341 return true;
342 }
343
344 bool RTLIL::Const::is_fully_def() const
345 {
346 cover("kernel.rtlil.const.is_fully_def");
347
348 for (const auto &bit : bits)
349 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
350 return false;
351
352 return true;
353 }
354
355 bool RTLIL::Const::is_fully_undef() const
356 {
357 cover("kernel.rtlil.const.is_fully_undef");
358
359 for (const auto &bit : bits)
360 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
361 return false;
362
363 return true;
364 }
365
366 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
367 {
368 return attributes.count(id);
369 }
370
371 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
372 {
373 if (value)
374 attributes[id] = RTLIL::Const(1);
375 else
376 attributes.erase(id);
377 }
378
379 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
380 {
381 const auto it = attributes.find(id);
382 if (it == attributes.end())
383 return false;
384 return it->second.as_bool();
385 }
386
387 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
388 {
389 if (value.empty())
390 attributes.erase(id);
391 else
392 attributes[id] = value;
393 }
394
395 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
396 {
397 std::string value;
398 const auto it = attributes.find(id);
399 if (it != attributes.end())
400 value = it->second.decode_string();
401 return value;
402 }
403
404 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
405 {
406 string attrval;
407 for (const auto &s : data) {
408 if (!attrval.empty())
409 attrval += "|";
410 attrval += s;
411 }
412 set_string_attribute(id, attrval);
413 }
414
415 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
416 {
417 pool<string> union_data = get_strpool_attribute(id);
418 union_data.insert(data.begin(), data.end());
419 if (!union_data.empty())
420 set_strpool_attribute(id, union_data);
421 }
422
423 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
424 {
425 pool<string> data;
426 if (attributes.count(id) != 0)
427 for (auto s : split_tokens(get_string_attribute(id), "|"))
428 data.insert(s);
429 return data;
430 }
431
432 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
433 {
434 string attrval;
435 for (const auto &ident : hierarchy) {
436 if (!attrval.empty())
437 attrval += " ";
438 attrval += ident;
439 }
440 set_string_attribute(ID::hdlname, attrval);
441 }
442
443 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
444 {
445 return split_tokens(get_string_attribute(ID::hdlname), " ");
446 }
447
448 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
449 {
450 if (full_selection)
451 return true;
452 if (selected_modules.count(mod_name) > 0)
453 return true;
454 if (selected_members.count(mod_name) > 0)
455 return true;
456 return false;
457 }
458
459 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
460 {
461 if (full_selection)
462 return true;
463 if (selected_modules.count(mod_name) > 0)
464 return true;
465 return false;
466 }
467
468 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
469 {
470 if (full_selection)
471 return true;
472 if (selected_modules.count(mod_name) > 0)
473 return true;
474 if (selected_members.count(mod_name) > 0)
475 if (selected_members.at(mod_name).count(memb_name) > 0)
476 return true;
477 return false;
478 }
479
480 void RTLIL::Selection::optimize(RTLIL::Design *design)
481 {
482 if (full_selection) {
483 selected_modules.clear();
484 selected_members.clear();
485 return;
486 }
487
488 std::vector<RTLIL::IdString> del_list, add_list;
489
490 del_list.clear();
491 for (auto mod_name : selected_modules) {
492 if (design->modules_.count(mod_name) == 0)
493 del_list.push_back(mod_name);
494 selected_members.erase(mod_name);
495 }
496 for (auto mod_name : del_list)
497 selected_modules.erase(mod_name);
498
499 del_list.clear();
500 for (auto &it : selected_members)
501 if (design->modules_.count(it.first) == 0)
502 del_list.push_back(it.first);
503 for (auto mod_name : del_list)
504 selected_members.erase(mod_name);
505
506 for (auto &it : selected_members) {
507 del_list.clear();
508 for (auto memb_name : it.second)
509 if (design->modules_[it.first]->count_id(memb_name) == 0)
510 del_list.push_back(memb_name);
511 for (auto memb_name : del_list)
512 it.second.erase(memb_name);
513 }
514
515 del_list.clear();
516 add_list.clear();
517 for (auto &it : selected_members)
518 if (it.second.size() == 0)
519 del_list.push_back(it.first);
520 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
521 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
522 add_list.push_back(it.first);
523 for (auto mod_name : del_list)
524 selected_members.erase(mod_name);
525 for (auto mod_name : add_list) {
526 selected_members.erase(mod_name);
527 selected_modules.insert(mod_name);
528 }
529
530 if (selected_modules.size() == design->modules_.size()) {
531 full_selection = true;
532 selected_modules.clear();
533 selected_members.clear();
534 }
535 }
536
537 RTLIL::Design::Design()
538 : verilog_defines (new define_map_t)
539 {
540 static unsigned int hashidx_count = 123456789;
541 hashidx_count = mkhash_xorshift(hashidx_count);
542 hashidx_ = hashidx_count;
543
544 refcount_modules_ = 0;
545 selection_stack.push_back(RTLIL::Selection());
546
547 #ifdef WITH_PYTHON
548 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
549 #endif
550 }
551
552 RTLIL::Design::~Design()
553 {
554 for (auto it = modules_.begin(); it != modules_.end(); ++it)
555 delete it->second;
556 for (auto n : verilog_packages)
557 delete n;
558 for (auto n : verilog_globals)
559 delete n;
560 #ifdef WITH_PYTHON
561 RTLIL::Design::get_all_designs()->erase(hashidx_);
562 #endif
563 }
564
565 #ifdef WITH_PYTHON
566 static std::map<unsigned int, RTLIL::Design*> all_designs;
567 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
568 {
569 return &all_designs;
570 }
571 #endif
572
573 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
574 {
575 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
576 }
577
578 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
579 {
580 return modules_.count(name) ? modules_.at(name) : NULL;
581 }
582
583 RTLIL::Module *RTLIL::Design::top_module()
584 {
585 RTLIL::Module *module = nullptr;
586 int module_count = 0;
587
588 for (auto mod : selected_modules()) {
589 if (mod->get_bool_attribute(ID::top))
590 return mod;
591 module_count++;
592 module = mod;
593 }
594
595 return module_count == 1 ? module : nullptr;
596 }
597
598 void RTLIL::Design::add(RTLIL::Module *module)
599 {
600 log_assert(modules_.count(module->name) == 0);
601 log_assert(refcount_modules_ == 0);
602 modules_[module->name] = module;
603 module->design = this;
604
605 for (auto mon : monitors)
606 mon->notify_module_add(module);
607
608 if (yosys_xtrace) {
609 log("#X# New Module: %s\n", log_id(module));
610 log_backtrace("-X- ", yosys_xtrace-1);
611 }
612 }
613
614 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
615 {
616 log_assert(modules_.count(name) == 0);
617 log_assert(refcount_modules_ == 0);
618
619 RTLIL::Module *module = new RTLIL::Module;
620 modules_[name] = module;
621 module->design = this;
622 module->name = name;
623
624 for (auto mon : monitors)
625 mon->notify_module_add(module);
626
627 if (yosys_xtrace) {
628 log("#X# New Module: %s\n", log_id(module));
629 log_backtrace("-X- ", yosys_xtrace-1);
630 }
631
632 return module;
633 }
634
635 void RTLIL::Design::scratchpad_unset(const std::string &varname)
636 {
637 scratchpad.erase(varname);
638 }
639
640 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
641 {
642 scratchpad[varname] = stringf("%d", value);
643 }
644
645 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
646 {
647 scratchpad[varname] = value ? "true" : "false";
648 }
649
650 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
651 {
652 scratchpad[varname] = std::move(value);
653 }
654
655 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
656 {
657 auto it = scratchpad.find(varname);
658 if (it == scratchpad.end())
659 return default_value;
660
661 const std::string &str = it->second;
662
663 if (str == "0" || str == "false")
664 return 0;
665
666 if (str == "1" || str == "true")
667 return 1;
668
669 char *endptr = nullptr;
670 long int parsed_value = strtol(str.c_str(), &endptr, 10);
671 return *endptr ? default_value : parsed_value;
672 }
673
674 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
675 {
676 auto it = scratchpad.find(varname);
677 if (it == scratchpad.end())
678 return default_value;
679
680 const std::string &str = it->second;
681
682 if (str == "0" || str == "false")
683 return false;
684
685 if (str == "1" || str == "true")
686 return true;
687
688 return default_value;
689 }
690
691 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
692 {
693 auto it = scratchpad.find(varname);
694 if (it == scratchpad.end())
695 return default_value;
696
697 return it->second;
698 }
699
700 void RTLIL::Design::remove(RTLIL::Module *module)
701 {
702 for (auto mon : monitors)
703 mon->notify_module_del(module);
704
705 if (yosys_xtrace) {
706 log("#X# Remove Module: %s\n", log_id(module));
707 log_backtrace("-X- ", yosys_xtrace-1);
708 }
709
710 log_assert(modules_.at(module->name) == module);
711 log_assert(refcount_modules_ == 0);
712 modules_.erase(module->name);
713 delete module;
714 }
715
716 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
717 {
718 modules_.erase(module->name);
719 module->name = new_name;
720 add(module);
721 }
722
723 void RTLIL::Design::sort()
724 {
725 scratchpad.sort();
726 modules_.sort(sort_by_id_str());
727 for (auto &it : modules_)
728 it.second->sort();
729 }
730
731 void RTLIL::Design::check()
732 {
733 #ifndef NDEBUG
734 for (auto &it : modules_) {
735 log_assert(this == it.second->design);
736 log_assert(it.first == it.second->name);
737 log_assert(!it.first.empty());
738 it.second->check();
739 }
740 #endif
741 }
742
743 void RTLIL::Design::optimize()
744 {
745 for (auto &it : modules_)
746 it.second->optimize();
747 for (auto &it : selection_stack)
748 it.optimize(this);
749 for (auto &it : selection_vars)
750 it.second.optimize(this);
751 }
752
753 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
754 {
755 if (!selected_active_module.empty() && mod_name != selected_active_module)
756 return false;
757 if (selection_stack.size() == 0)
758 return true;
759 return selection_stack.back().selected_module(mod_name);
760 }
761
762 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
763 {
764 if (!selected_active_module.empty() && mod_name != selected_active_module)
765 return false;
766 if (selection_stack.size() == 0)
767 return true;
768 return selection_stack.back().selected_whole_module(mod_name);
769 }
770
771 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
772 {
773 if (!selected_active_module.empty() && mod_name != selected_active_module)
774 return false;
775 if (selection_stack.size() == 0)
776 return true;
777 return selection_stack.back().selected_member(mod_name, memb_name);
778 }
779
780 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
781 {
782 return selected_module(mod->name);
783 }
784
785 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
786 {
787 return selected_whole_module(mod->name);
788 }
789
790 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
791 {
792 std::vector<RTLIL::Module*> result;
793 result.reserve(modules_.size());
794 for (auto &it : modules_)
795 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
796 result.push_back(it.second);
797 return result;
798 }
799
800 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
801 {
802 std::vector<RTLIL::Module*> result;
803 result.reserve(modules_.size());
804 for (auto &it : modules_)
805 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
806 result.push_back(it.second);
807 return result;
808 }
809
810 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
811 {
812 std::vector<RTLIL::Module*> result;
813 result.reserve(modules_.size());
814 for (auto &it : modules_)
815 if (it.second->get_blackbox_attribute())
816 continue;
817 else if (selected_whole_module(it.first))
818 result.push_back(it.second);
819 else if (selected_module(it.first))
820 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
821 return result;
822 }
823
824 RTLIL::Module::Module()
825 {
826 static unsigned int hashidx_count = 123456789;
827 hashidx_count = mkhash_xorshift(hashidx_count);
828 hashidx_ = hashidx_count;
829
830 design = nullptr;
831 refcount_wires_ = 0;
832 refcount_cells_ = 0;
833
834 #ifdef WITH_PYTHON
835 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
836 #endif
837 }
838
839 RTLIL::Module::~Module()
840 {
841 for (auto it = wires_.begin(); it != wires_.end(); ++it)
842 delete it->second;
843 for (auto it = memories.begin(); it != memories.end(); ++it)
844 delete it->second;
845 for (auto it = cells_.begin(); it != cells_.end(); ++it)
846 delete it->second;
847 for (auto it = processes.begin(); it != processes.end(); ++it)
848 delete it->second;
849 #ifdef WITH_PYTHON
850 RTLIL::Module::get_all_modules()->erase(hashidx_);
851 #endif
852 }
853
854 #ifdef WITH_PYTHON
855 static std::map<unsigned int, RTLIL::Module*> all_modules;
856 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
857 {
858 return &all_modules;
859 }
860 #endif
861
862 void RTLIL::Module::makeblackbox()
863 {
864 pool<RTLIL::Wire*> delwires;
865
866 for (auto it = wires_.begin(); it != wires_.end(); ++it)
867 if (!it->second->port_input && !it->second->port_output)
868 delwires.insert(it->second);
869
870 for (auto it = memories.begin(); it != memories.end(); ++it)
871 delete it->second;
872 memories.clear();
873
874 for (auto it = cells_.begin(); it != cells_.end(); ++it)
875 delete it->second;
876 cells_.clear();
877
878 for (auto it = processes.begin(); it != processes.end(); ++it)
879 delete it->second;
880 processes.clear();
881
882 connections_.clear();
883
884 remove(delwires);
885 set_bool_attribute(ID::blackbox);
886 }
887
888 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
889 {
890 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
891 }
892
893 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
894 {
895 if (mayfail)
896 return RTLIL::IdString();
897 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
898 }
899
900
901 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
902 {
903 if (mayfail)
904 return RTLIL::IdString();
905 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
906 }
907
908 size_t RTLIL::Module::count_id(RTLIL::IdString id)
909 {
910 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
911 }
912
913 #ifndef NDEBUG
914 namespace {
915 struct InternalCellChecker
916 {
917 RTLIL::Module *module;
918 RTLIL::Cell *cell;
919 pool<RTLIL::IdString> expected_params, expected_ports;
920
921 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
922
923 void error(int linenr)
924 {
925 std::stringstream buf;
926 RTLIL_BACKEND::dump_cell(buf, " ", cell);
927
928 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
929 module ? module->name.c_str() : "", module ? "." : "",
930 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
931 }
932
933 int param(RTLIL::IdString name)
934 {
935 auto it = cell->parameters.find(name);
936 if (it == cell->parameters.end())
937 error(__LINE__);
938 expected_params.insert(name);
939 return it->second.as_int();
940 }
941
942 int param_bool(RTLIL::IdString name)
943 {
944 int v = param(name);
945 if (GetSize(cell->parameters.at(name)) > 32)
946 error(__LINE__);
947 if (v != 0 && v != 1)
948 error(__LINE__);
949 return v;
950 }
951
952 int param_bool(RTLIL::IdString name, bool expected)
953 {
954 int v = param_bool(name);
955 if (v != expected)
956 error(__LINE__);
957 return v;
958 }
959
960 void param_bits(RTLIL::IdString name, int width)
961 {
962 param(name);
963 if (GetSize(cell->parameters.at(name).bits) != width)
964 error(__LINE__);
965 }
966
967 void port(RTLIL::IdString name, int width)
968 {
969 auto it = cell->connections_.find(name);
970 if (it == cell->connections_.end())
971 error(__LINE__);
972 if (GetSize(it->second) != width)
973 error(__LINE__);
974 expected_ports.insert(name);
975 }
976
977 void check_expected(bool check_matched_sign = false)
978 {
979 for (auto &para : cell->parameters)
980 if (expected_params.count(para.first) == 0)
981 error(__LINE__);
982 for (auto &conn : cell->connections())
983 if (expected_ports.count(conn.first) == 0)
984 error(__LINE__);
985
986 if (check_matched_sign) {
987 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
988 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
989 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
990 if (a_is_signed != b_is_signed)
991 error(__LINE__);
992 }
993 }
994
995 void check()
996 {
997 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
998 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
999 return;
1000
1001 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
1002 param_bool(ID::A_SIGNED);
1003 port(ID::A, param(ID::A_WIDTH));
1004 port(ID::Y, param(ID::Y_WIDTH));
1005 check_expected();
1006 return;
1007 }
1008
1009 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
1010 param_bool(ID::A_SIGNED);
1011 param_bool(ID::B_SIGNED);
1012 port(ID::A, param(ID::A_WIDTH));
1013 port(ID::B, param(ID::B_WIDTH));
1014 port(ID::Y, param(ID::Y_WIDTH));
1015 check_expected(true);
1016 return;
1017 }
1018
1019 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
1020 param_bool(ID::A_SIGNED);
1021 port(ID::A, param(ID::A_WIDTH));
1022 port(ID::Y, param(ID::Y_WIDTH));
1023 check_expected();
1024 return;
1025 }
1026
1027 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
1028 param_bool(ID::A_SIGNED);
1029 param_bool(ID::B_SIGNED, /*expected=*/false);
1030 port(ID::A, param(ID::A_WIDTH));
1031 port(ID::B, param(ID::B_WIDTH));
1032 port(ID::Y, param(ID::Y_WIDTH));
1033 check_expected(/*check_matched_sign=*/false);
1034 return;
1035 }
1036
1037 if (cell->type.in(ID($shift), ID($shiftx))) {
1038 if (cell->type == ID($shiftx)) {
1039 param_bool(ID::A_SIGNED, /*expected=*/false);
1040 } else {
1041 param_bool(ID::A_SIGNED);
1042 }
1043 param_bool(ID::B_SIGNED);
1044 port(ID::A, param(ID::A_WIDTH));
1045 port(ID::B, param(ID::B_WIDTH));
1046 port(ID::Y, param(ID::Y_WIDTH));
1047 check_expected(/*check_matched_sign=*/false);
1048 return;
1049 }
1050
1051 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
1052 param_bool(ID::A_SIGNED);
1053 param_bool(ID::B_SIGNED);
1054 port(ID::A, param(ID::A_WIDTH));
1055 port(ID::B, param(ID::B_WIDTH));
1056 port(ID::Y, param(ID::Y_WIDTH));
1057 check_expected(true);
1058 return;
1059 }
1060
1061 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
1062 param_bool(ID::A_SIGNED);
1063 param_bool(ID::B_SIGNED);
1064 port(ID::A, param(ID::A_WIDTH));
1065 port(ID::B, param(ID::B_WIDTH));
1066 port(ID::Y, param(ID::Y_WIDTH));
1067 check_expected(cell->type != ID($pow));
1068 return;
1069 }
1070
1071 if (cell->type == ID($fa)) {
1072 port(ID::A, param(ID::WIDTH));
1073 port(ID::B, param(ID::WIDTH));
1074 port(ID::C, param(ID::WIDTH));
1075 port(ID::X, param(ID::WIDTH));
1076 port(ID::Y, param(ID::WIDTH));
1077 check_expected();
1078 return;
1079 }
1080
1081 if (cell->type == ID($lcu)) {
1082 port(ID::P, param(ID::WIDTH));
1083 port(ID::G, param(ID::WIDTH));
1084 port(ID::CI, 1);
1085 port(ID::CO, param(ID::WIDTH));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == ID($alu)) {
1091 param_bool(ID::A_SIGNED);
1092 param_bool(ID::B_SIGNED);
1093 port(ID::A, param(ID::A_WIDTH));
1094 port(ID::B, param(ID::B_WIDTH));
1095 port(ID::CI, 1);
1096 port(ID::BI, 1);
1097 port(ID::X, param(ID::Y_WIDTH));
1098 port(ID::Y, param(ID::Y_WIDTH));
1099 port(ID::CO, param(ID::Y_WIDTH));
1100 check_expected(true);
1101 return;
1102 }
1103
1104 if (cell->type == ID($macc)) {
1105 param(ID::CONFIG);
1106 param(ID::CONFIG_WIDTH);
1107 port(ID::A, param(ID::A_WIDTH));
1108 port(ID::B, param(ID::B_WIDTH));
1109 port(ID::Y, param(ID::Y_WIDTH));
1110 check_expected();
1111 Macc().from_cell(cell);
1112 return;
1113 }
1114
1115 if (cell->type == ID($logic_not)) {
1116 param_bool(ID::A_SIGNED);
1117 port(ID::A, param(ID::A_WIDTH));
1118 port(ID::Y, param(ID::Y_WIDTH));
1119 check_expected();
1120 return;
1121 }
1122
1123 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1124 param_bool(ID::A_SIGNED);
1125 param_bool(ID::B_SIGNED);
1126 port(ID::A, param(ID::A_WIDTH));
1127 port(ID::B, param(ID::B_WIDTH));
1128 port(ID::Y, param(ID::Y_WIDTH));
1129 check_expected(/*check_matched_sign=*/false);
1130 return;
1131 }
1132
1133 if (cell->type == ID($slice)) {
1134 param(ID::OFFSET);
1135 port(ID::A, param(ID::A_WIDTH));
1136 port(ID::Y, param(ID::Y_WIDTH));
1137 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1138 error(__LINE__);
1139 check_expected();
1140 return;
1141 }
1142
1143 if (cell->type == ID($concat)) {
1144 port(ID::A, param(ID::A_WIDTH));
1145 port(ID::B, param(ID::B_WIDTH));
1146 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1147 check_expected();
1148 return;
1149 }
1150
1151 if (cell->type == ID($mux)) {
1152 port(ID::A, param(ID::WIDTH));
1153 port(ID::B, param(ID::WIDTH));
1154 port(ID::S, 1);
1155 port(ID::Y, param(ID::WIDTH));
1156 check_expected();
1157 return;
1158 }
1159
1160 if (cell->type == ID($pmux)) {
1161 port(ID::A, param(ID::WIDTH));
1162 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1163 port(ID::S, param(ID::S_WIDTH));
1164 port(ID::Y, param(ID::WIDTH));
1165 check_expected();
1166 return;
1167 }
1168
1169 if (cell->type == ID($lut)) {
1170 param(ID::LUT);
1171 port(ID::A, param(ID::WIDTH));
1172 port(ID::Y, 1);
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == ID($sop)) {
1178 param(ID::DEPTH);
1179 param(ID::TABLE);
1180 port(ID::A, param(ID::WIDTH));
1181 port(ID::Y, 1);
1182 check_expected();
1183 return;
1184 }
1185
1186 if (cell->type == ID($sr)) {
1187 param_bool(ID::SET_POLARITY);
1188 param_bool(ID::CLR_POLARITY);
1189 port(ID::SET, param(ID::WIDTH));
1190 port(ID::CLR, param(ID::WIDTH));
1191 port(ID::Q, param(ID::WIDTH));
1192 check_expected();
1193 return;
1194 }
1195
1196 if (cell->type == ID($ff)) {
1197 port(ID::D, param(ID::WIDTH));
1198 port(ID::Q, param(ID::WIDTH));
1199 check_expected();
1200 return;
1201 }
1202
1203 if (cell->type == ID($dff)) {
1204 param_bool(ID::CLK_POLARITY);
1205 port(ID::CLK, 1);
1206 port(ID::D, param(ID::WIDTH));
1207 port(ID::Q, param(ID::WIDTH));
1208 check_expected();
1209 return;
1210 }
1211
1212 if (cell->type == ID($dffe)) {
1213 param_bool(ID::CLK_POLARITY);
1214 param_bool(ID::EN_POLARITY);
1215 port(ID::CLK, 1);
1216 port(ID::EN, 1);
1217 port(ID::D, param(ID::WIDTH));
1218 port(ID::Q, param(ID::WIDTH));
1219 check_expected();
1220 return;
1221 }
1222
1223 if (cell->type == ID($dffsr)) {
1224 param_bool(ID::CLK_POLARITY);
1225 param_bool(ID::SET_POLARITY);
1226 param_bool(ID::CLR_POLARITY);
1227 port(ID::CLK, 1);
1228 port(ID::SET, param(ID::WIDTH));
1229 port(ID::CLR, param(ID::WIDTH));
1230 port(ID::D, param(ID::WIDTH));
1231 port(ID::Q, param(ID::WIDTH));
1232 check_expected();
1233 return;
1234 }
1235
1236 if (cell->type == ID($dffsre)) {
1237 param_bool(ID::CLK_POLARITY);
1238 param_bool(ID::SET_POLARITY);
1239 param_bool(ID::CLR_POLARITY);
1240 param_bool(ID::EN_POLARITY);
1241 port(ID::CLK, 1);
1242 port(ID::EN, 1);
1243 port(ID::SET, param(ID::WIDTH));
1244 port(ID::CLR, param(ID::WIDTH));
1245 port(ID::D, param(ID::WIDTH));
1246 port(ID::Q, param(ID::WIDTH));
1247 check_expected();
1248 return;
1249 }
1250
1251 if (cell->type == ID($adff)) {
1252 param_bool(ID::CLK_POLARITY);
1253 param_bool(ID::ARST_POLARITY);
1254 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1255 port(ID::CLK, 1);
1256 port(ID::ARST, 1);
1257 port(ID::D, param(ID::WIDTH));
1258 port(ID::Q, param(ID::WIDTH));
1259 check_expected();
1260 return;
1261 }
1262
1263 if (cell->type == ID($sdff)) {
1264 param_bool(ID::CLK_POLARITY);
1265 param_bool(ID::SRST_POLARITY);
1266 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1267 port(ID::CLK, 1);
1268 port(ID::SRST, 1);
1269 port(ID::D, param(ID::WIDTH));
1270 port(ID::Q, param(ID::WIDTH));
1271 check_expected();
1272 return;
1273 }
1274
1275 if (cell->type.in(ID($sdffe), ID($sdffce))) {
1276 param_bool(ID::CLK_POLARITY);
1277 param_bool(ID::EN_POLARITY);
1278 param_bool(ID::SRST_POLARITY);
1279 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1280 port(ID::CLK, 1);
1281 port(ID::EN, 1);
1282 port(ID::SRST, 1);
1283 port(ID::D, param(ID::WIDTH));
1284 port(ID::Q, param(ID::WIDTH));
1285 check_expected();
1286 return;
1287 }
1288
1289 if (cell->type == ID($adffe)) {
1290 param_bool(ID::CLK_POLARITY);
1291 param_bool(ID::EN_POLARITY);
1292 param_bool(ID::ARST_POLARITY);
1293 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1294 port(ID::CLK, 1);
1295 port(ID::EN, 1);
1296 port(ID::ARST, 1);
1297 port(ID::D, param(ID::WIDTH));
1298 port(ID::Q, param(ID::WIDTH));
1299 check_expected();
1300 return;
1301 }
1302
1303 if (cell->type == ID($dlatch)) {
1304 param_bool(ID::EN_POLARITY);
1305 port(ID::EN, 1);
1306 port(ID::D, param(ID::WIDTH));
1307 port(ID::Q, param(ID::WIDTH));
1308 check_expected();
1309 return;
1310 }
1311
1312 if (cell->type == ID($adlatch)) {
1313 param_bool(ID::EN_POLARITY);
1314 param_bool(ID::ARST_POLARITY);
1315 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1316 port(ID::EN, 1);
1317 port(ID::ARST, 1);
1318 port(ID::D, param(ID::WIDTH));
1319 port(ID::Q, param(ID::WIDTH));
1320 check_expected();
1321 return;
1322 }
1323
1324 if (cell->type == ID($dlatchsr)) {
1325 param_bool(ID::EN_POLARITY);
1326 param_bool(ID::SET_POLARITY);
1327 param_bool(ID::CLR_POLARITY);
1328 port(ID::EN, 1);
1329 port(ID::SET, param(ID::WIDTH));
1330 port(ID::CLR, param(ID::WIDTH));
1331 port(ID::D, param(ID::WIDTH));
1332 port(ID::Q, param(ID::WIDTH));
1333 check_expected();
1334 return;
1335 }
1336
1337 if (cell->type == ID($fsm)) {
1338 param(ID::NAME);
1339 param_bool(ID::CLK_POLARITY);
1340 param_bool(ID::ARST_POLARITY);
1341 param(ID::STATE_BITS);
1342 param(ID::STATE_NUM);
1343 param(ID::STATE_NUM_LOG2);
1344 param(ID::STATE_RST);
1345 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1346 param(ID::TRANS_NUM);
1347 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1348 port(ID::CLK, 1);
1349 port(ID::ARST, 1);
1350 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1351 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1352 check_expected();
1353 return;
1354 }
1355
1356 if (cell->type == ID($memrd)) {
1357 param(ID::MEMID);
1358 param_bool(ID::CLK_ENABLE);
1359 param_bool(ID::CLK_POLARITY);
1360 param_bool(ID::TRANSPARENT);
1361 port(ID::CLK, 1);
1362 port(ID::EN, 1);
1363 port(ID::ADDR, param(ID::ABITS));
1364 port(ID::DATA, param(ID::WIDTH));
1365 check_expected();
1366 return;
1367 }
1368
1369 if (cell->type == ID($memwr)) {
1370 param(ID::MEMID);
1371 param_bool(ID::CLK_ENABLE);
1372 param_bool(ID::CLK_POLARITY);
1373 param(ID::PRIORITY);
1374 port(ID::CLK, 1);
1375 port(ID::EN, param(ID::WIDTH));
1376 port(ID::ADDR, param(ID::ABITS));
1377 port(ID::DATA, param(ID::WIDTH));
1378 check_expected();
1379 return;
1380 }
1381
1382 if (cell->type == ID($meminit)) {
1383 param(ID::MEMID);
1384 param(ID::PRIORITY);
1385 port(ID::ADDR, param(ID::ABITS));
1386 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1387 check_expected();
1388 return;
1389 }
1390
1391 if (cell->type == ID($mem)) {
1392 param(ID::MEMID);
1393 param(ID::SIZE);
1394 param(ID::OFFSET);
1395 param(ID::INIT);
1396 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1397 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1398 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1399 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1400 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1401 port(ID::RD_CLK, param(ID::RD_PORTS));
1402 port(ID::RD_EN, param(ID::RD_PORTS));
1403 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1404 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1405 port(ID::WR_CLK, param(ID::WR_PORTS));
1406 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1407 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1408 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1409 check_expected();
1410 return;
1411 }
1412
1413 if (cell->type == ID($tribuf)) {
1414 port(ID::A, param(ID::WIDTH));
1415 port(ID::Y, param(ID::WIDTH));
1416 port(ID::EN, 1);
1417 check_expected();
1418 return;
1419 }
1420
1421 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1422 port(ID::A, 1);
1423 port(ID::EN, 1);
1424 check_expected();
1425 return;
1426 }
1427
1428 if (cell->type == ID($initstate)) {
1429 port(ID::Y, 1);
1430 check_expected();
1431 return;
1432 }
1433
1434 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1435 port(ID::Y, param(ID::WIDTH));
1436 check_expected();
1437 return;
1438 }
1439
1440 if (cell->type == ID($equiv)) {
1441 port(ID::A, 1);
1442 port(ID::B, 1);
1443 port(ID::Y, 1);
1444 check_expected();
1445 return;
1446 }
1447
1448 if (cell->type.in(ID($specify2), ID($specify3))) {
1449 param_bool(ID::FULL);
1450 param_bool(ID::SRC_DST_PEN);
1451 param_bool(ID::SRC_DST_POL);
1452 param(ID::T_RISE_MIN);
1453 param(ID::T_RISE_TYP);
1454 param(ID::T_RISE_MAX);
1455 param(ID::T_FALL_MIN);
1456 param(ID::T_FALL_TYP);
1457 param(ID::T_FALL_MAX);
1458 port(ID::EN, 1);
1459 port(ID::SRC, param(ID::SRC_WIDTH));
1460 port(ID::DST, param(ID::DST_WIDTH));
1461 if (cell->type == ID($specify3)) {
1462 param_bool(ID::EDGE_EN);
1463 param_bool(ID::EDGE_POL);
1464 param_bool(ID::DAT_DST_PEN);
1465 param_bool(ID::DAT_DST_POL);
1466 port(ID::DAT, param(ID::DST_WIDTH));
1467 }
1468 check_expected();
1469 return;
1470 }
1471
1472 if (cell->type == ID($specrule)) {
1473 param(ID::TYPE);
1474 param_bool(ID::SRC_PEN);
1475 param_bool(ID::SRC_POL);
1476 param_bool(ID::DST_PEN);
1477 param_bool(ID::DST_POL);
1478 param(ID::T_LIMIT_MIN);
1479 param(ID::T_LIMIT_TYP);
1480 param(ID::T_LIMIT_MAX);
1481 param(ID::T_LIMIT2_MIN);
1482 param(ID::T_LIMIT2_TYP);
1483 param(ID::T_LIMIT2_MAX);
1484 port(ID::SRC_EN, 1);
1485 port(ID::DST_EN, 1);
1486 port(ID::SRC, param(ID::SRC_WIDTH));
1487 port(ID::DST, param(ID::DST_WIDTH));
1488 check_expected();
1489 return;
1490 }
1491
1492 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1493 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1494 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1495 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1496 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1497 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1498 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1499 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1500 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1501 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1502 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1503 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1504 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1505 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1506 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1507 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1508
1509 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1510
1511 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1512 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1513 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1514
1515 if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
1516 { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1517
1518 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1519
1520 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1521 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1522
1523 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1524 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1525
1526 if (cell->type.in(
1527 ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
1528 ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
1529 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1530
1531 if (cell->type.in(
1532 ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
1533 ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
1534 ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
1535 ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
1536 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1537
1538 if (cell->type.in(
1539 ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
1540 ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
1541 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1542
1543 if (cell->type.in(
1544 ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
1545 ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
1546 ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
1547 ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
1548 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
1549
1550 if (cell->type.in(
1551 ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
1552 ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
1553 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1554
1555 if (cell->type.in(
1556 ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
1557 ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
1558 ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
1559 ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
1560 ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
1561 ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
1562 ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
1563 ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
1564 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1565
1566 if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
1567 { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1568
1569 if (cell->type.in(
1570 ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
1571 ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
1572 { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1573
1574 if (cell->type.in(
1575 ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
1576 ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
1577 { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1578
1579 error(__LINE__);
1580 }
1581 };
1582 }
1583 #endif
1584
1585 void RTLIL::Module::sort()
1586 {
1587 wires_.sort(sort_by_id_str());
1588 cells_.sort(sort_by_id_str());
1589 parameter_default_values.sort(sort_by_id_str());
1590 memories.sort(sort_by_id_str());
1591 processes.sort(sort_by_id_str());
1592 for (auto &it : cells_)
1593 it.second->sort();
1594 for (auto &it : wires_)
1595 it.second->attributes.sort(sort_by_id_str());
1596 for (auto &it : memories)
1597 it.second->attributes.sort(sort_by_id_str());
1598 }
1599
1600 void RTLIL::Module::check()
1601 {
1602 #ifndef NDEBUG
1603 std::vector<bool> ports_declared;
1604 for (auto &it : wires_) {
1605 log_assert(this == it.second->module);
1606 log_assert(it.first == it.second->name);
1607 log_assert(!it.first.empty());
1608 log_assert(it.second->width >= 0);
1609 log_assert(it.second->port_id >= 0);
1610 for (auto &it2 : it.second->attributes)
1611 log_assert(!it2.first.empty());
1612 if (it.second->port_id) {
1613 log_assert(GetSize(ports) >= it.second->port_id);
1614 log_assert(ports.at(it.second->port_id-1) == it.first);
1615 log_assert(it.second->port_input || it.second->port_output);
1616 if (GetSize(ports_declared) < it.second->port_id)
1617 ports_declared.resize(it.second->port_id);
1618 log_assert(ports_declared[it.second->port_id-1] == false);
1619 ports_declared[it.second->port_id-1] = true;
1620 } else
1621 log_assert(!it.second->port_input && !it.second->port_output);
1622 }
1623 for (auto port_declared : ports_declared)
1624 log_assert(port_declared == true);
1625 log_assert(GetSize(ports) == GetSize(ports_declared));
1626
1627 for (auto &it : memories) {
1628 log_assert(it.first == it.second->name);
1629 log_assert(!it.first.empty());
1630 log_assert(it.second->width >= 0);
1631 log_assert(it.second->size >= 0);
1632 for (auto &it2 : it.second->attributes)
1633 log_assert(!it2.first.empty());
1634 }
1635
1636 for (auto &it : cells_) {
1637 log_assert(this == it.second->module);
1638 log_assert(it.first == it.second->name);
1639 log_assert(!it.first.empty());
1640 log_assert(!it.second->type.empty());
1641 for (auto &it2 : it.second->connections()) {
1642 log_assert(!it2.first.empty());
1643 it2.second.check();
1644 }
1645 for (auto &it2 : it.second->attributes)
1646 log_assert(!it2.first.empty());
1647 for (auto &it2 : it.second->parameters)
1648 log_assert(!it2.first.empty());
1649 InternalCellChecker checker(this, it.second);
1650 checker.check();
1651 }
1652
1653 for (auto &it : processes) {
1654 log_assert(it.first == it.second->name);
1655 log_assert(!it.first.empty());
1656 log_assert(it.second->root_case.compare.empty());
1657 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1658 for (size_t i = 0; i < all_cases.size(); i++) {
1659 for (auto &switch_it : all_cases[i]->switches) {
1660 for (auto &case_it : switch_it->cases) {
1661 for (auto &compare_it : case_it->compare) {
1662 log_assert(switch_it->signal.size() == compare_it.size());
1663 }
1664 all_cases.push_back(case_it);
1665 }
1666 }
1667 }
1668 for (auto &sync_it : it.second->syncs) {
1669 switch (sync_it->type) {
1670 case SyncType::ST0:
1671 case SyncType::ST1:
1672 case SyncType::STp:
1673 case SyncType::STn:
1674 case SyncType::STe:
1675 log_assert(!sync_it->signal.empty());
1676 break;
1677 case SyncType::STa:
1678 case SyncType::STg:
1679 case SyncType::STi:
1680 log_assert(sync_it->signal.empty());
1681 break;
1682 }
1683 }
1684 }
1685
1686 for (auto &it : connections_) {
1687 log_assert(it.first.size() == it.second.size());
1688 log_assert(!it.first.has_const());
1689 it.first.check();
1690 it.second.check();
1691 }
1692
1693 for (auto &it : attributes)
1694 log_assert(!it.first.empty());
1695 #endif
1696 }
1697
1698 void RTLIL::Module::optimize()
1699 {
1700 }
1701
1702 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1703 {
1704 log_assert(new_mod->refcount_wires_ == 0);
1705 log_assert(new_mod->refcount_cells_ == 0);
1706
1707 new_mod->avail_parameters = avail_parameters;
1708 new_mod->parameter_default_values = parameter_default_values;
1709
1710 for (auto &conn : connections_)
1711 new_mod->connect(conn);
1712
1713 for (auto &attr : attributes)
1714 new_mod->attributes[attr.first] = attr.second;
1715
1716 for (auto &it : wires_)
1717 new_mod->addWire(it.first, it.second);
1718
1719 for (auto &it : memories)
1720 new_mod->addMemory(it.first, it.second);
1721
1722 for (auto &it : cells_)
1723 new_mod->addCell(it.first, it.second);
1724
1725 for (auto &it : processes)
1726 new_mod->addProcess(it.first, it.second);
1727
1728 struct RewriteSigSpecWorker
1729 {
1730 RTLIL::Module *mod;
1731 void operator()(RTLIL::SigSpec &sig)
1732 {
1733 sig.pack();
1734 for (auto &c : sig.chunks_)
1735 if (c.wire != NULL)
1736 c.wire = mod->wires_.at(c.wire->name);
1737 }
1738 };
1739
1740 RewriteSigSpecWorker rewriteSigSpecWorker;
1741 rewriteSigSpecWorker.mod = new_mod;
1742 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1743 new_mod->fixup_ports();
1744 }
1745
1746 RTLIL::Module *RTLIL::Module::clone() const
1747 {
1748 RTLIL::Module *new_mod = new RTLIL::Module;
1749 new_mod->name = name;
1750 cloneInto(new_mod);
1751 return new_mod;
1752 }
1753
1754 bool RTLIL::Module::has_memories() const
1755 {
1756 return !memories.empty();
1757 }
1758
1759 bool RTLIL::Module::has_processes() const
1760 {
1761 return !processes.empty();
1762 }
1763
1764 bool RTLIL::Module::has_memories_warn() const
1765 {
1766 if (!memories.empty())
1767 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1768 return !memories.empty();
1769 }
1770
1771 bool RTLIL::Module::has_processes_warn() const
1772 {
1773 if (!processes.empty())
1774 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1775 return !processes.empty();
1776 }
1777
1778 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1779 {
1780 std::vector<RTLIL::Wire*> result;
1781 result.reserve(wires_.size());
1782 for (auto &it : wires_)
1783 if (design->selected(this, it.second))
1784 result.push_back(it.second);
1785 return result;
1786 }
1787
1788 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1789 {
1790 std::vector<RTLIL::Cell*> result;
1791 result.reserve(cells_.size());
1792 for (auto &it : cells_)
1793 if (design->selected(this, it.second))
1794 result.push_back(it.second);
1795 return result;
1796 }
1797
1798 void RTLIL::Module::add(RTLIL::Wire *wire)
1799 {
1800 log_assert(!wire->name.empty());
1801 log_assert(count_id(wire->name) == 0);
1802 log_assert(refcount_wires_ == 0);
1803 wires_[wire->name] = wire;
1804 wire->module = this;
1805 }
1806
1807 void RTLIL::Module::add(RTLIL::Cell *cell)
1808 {
1809 log_assert(!cell->name.empty());
1810 log_assert(count_id(cell->name) == 0);
1811 log_assert(refcount_cells_ == 0);
1812 cells_[cell->name] = cell;
1813 cell->module = this;
1814 }
1815
1816 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1817 {
1818 log_assert(refcount_wires_ == 0);
1819
1820 struct DeleteWireWorker
1821 {
1822 RTLIL::Module *module;
1823 const pool<RTLIL::Wire*> *wires_p;
1824
1825 void operator()(RTLIL::SigSpec &sig) {
1826 sig.pack();
1827 for (auto &c : sig.chunks_)
1828 if (c.wire != NULL && wires_p->count(c.wire)) {
1829 c.wire = module->addWire(NEW_ID, c.width);
1830 c.offset = 0;
1831 }
1832 }
1833
1834 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1835 log_assert(GetSize(lhs) == GetSize(rhs));
1836 lhs.unpack();
1837 rhs.unpack();
1838 for (int i = 0; i < GetSize(lhs); i++) {
1839 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1840 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1841 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1842 lhs_bit = State::Sx;
1843 rhs_bit = State::Sx;
1844 }
1845 }
1846 }
1847 };
1848
1849 DeleteWireWorker delete_wire_worker;
1850 delete_wire_worker.module = this;
1851 delete_wire_worker.wires_p = &wires;
1852 rewrite_sigspecs2(delete_wire_worker);
1853
1854 for (auto &it : wires) {
1855 log_assert(wires_.count(it->name) != 0);
1856 wires_.erase(it->name);
1857 delete it;
1858 }
1859 }
1860
1861 void RTLIL::Module::remove(RTLIL::Cell *cell)
1862 {
1863 while (!cell->connections_.empty())
1864 cell->unsetPort(cell->connections_.begin()->first);
1865
1866 log_assert(cells_.count(cell->name) != 0);
1867 log_assert(refcount_cells_ == 0);
1868 cells_.erase(cell->name);
1869 delete cell;
1870 }
1871
1872 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1873 {
1874 log_assert(wires_[wire->name] == wire);
1875 log_assert(refcount_wires_ == 0);
1876 wires_.erase(wire->name);
1877 wire->name = new_name;
1878 add(wire);
1879 }
1880
1881 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1882 {
1883 log_assert(cells_[cell->name] == cell);
1884 log_assert(refcount_wires_ == 0);
1885 cells_.erase(cell->name);
1886 cell->name = new_name;
1887 add(cell);
1888 }
1889
1890 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1891 {
1892 log_assert(count_id(old_name) != 0);
1893 if (wires_.count(old_name))
1894 rename(wires_.at(old_name), new_name);
1895 else if (cells_.count(old_name))
1896 rename(cells_.at(old_name), new_name);
1897 else
1898 log_abort();
1899 }
1900
1901 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1902 {
1903 log_assert(wires_[w1->name] == w1);
1904 log_assert(wires_[w2->name] == w2);
1905 log_assert(refcount_wires_ == 0);
1906
1907 wires_.erase(w1->name);
1908 wires_.erase(w2->name);
1909
1910 std::swap(w1->name, w2->name);
1911
1912 wires_[w1->name] = w1;
1913 wires_[w2->name] = w2;
1914 }
1915
1916 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1917 {
1918 log_assert(cells_[c1->name] == c1);
1919 log_assert(cells_[c2->name] == c2);
1920 log_assert(refcount_cells_ == 0);
1921
1922 cells_.erase(c1->name);
1923 cells_.erase(c2->name);
1924
1925 std::swap(c1->name, c2->name);
1926
1927 cells_[c1->name] = c1;
1928 cells_[c2->name] = c2;
1929 }
1930
1931 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1932 {
1933 int index = 0;
1934 return uniquify(name, index);
1935 }
1936
1937 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1938 {
1939 if (index == 0) {
1940 if (count_id(name) == 0)
1941 return name;
1942 index++;
1943 }
1944
1945 while (1) {
1946 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1947 if (count_id(new_name) == 0)
1948 return new_name;
1949 index++;
1950 }
1951 }
1952
1953 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1954 {
1955 if (a->port_id && !b->port_id)
1956 return true;
1957 if (!a->port_id && b->port_id)
1958 return false;
1959
1960 if (a->port_id == b->port_id)
1961 return a->name < b->name;
1962 return a->port_id < b->port_id;
1963 }
1964
1965 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1966 {
1967 for (auto mon : monitors)
1968 mon->notify_connect(this, conn);
1969
1970 if (design)
1971 for (auto mon : design->monitors)
1972 mon->notify_connect(this, conn);
1973
1974 // ignore all attempts to assign constants to other constants
1975 if (conn.first.has_const()) {
1976 RTLIL::SigSig new_conn;
1977 for (int i = 0; i < GetSize(conn.first); i++)
1978 if (conn.first[i].wire) {
1979 new_conn.first.append(conn.first[i]);
1980 new_conn.second.append(conn.second[i]);
1981 }
1982 if (GetSize(new_conn.first))
1983 connect(new_conn);
1984 return;
1985 }
1986
1987 if (yosys_xtrace) {
1988 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1989 log_backtrace("-X- ", yosys_xtrace-1);
1990 }
1991
1992 log_assert(GetSize(conn.first) == GetSize(conn.second));
1993 connections_.push_back(conn);
1994 }
1995
1996 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1997 {
1998 connect(RTLIL::SigSig(lhs, rhs));
1999 }
2000
2001 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
2002 {
2003 for (auto mon : monitors)
2004 mon->notify_connect(this, new_conn);
2005
2006 if (design)
2007 for (auto mon : design->monitors)
2008 mon->notify_connect(this, new_conn);
2009
2010 if (yosys_xtrace) {
2011 log("#X# New connections vector in %s:\n", log_id(this));
2012 for (auto &conn: new_conn)
2013 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2014 log_backtrace("-X- ", yosys_xtrace-1);
2015 }
2016
2017 connections_ = new_conn;
2018 }
2019
2020 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
2021 {
2022 return connections_;
2023 }
2024
2025 void RTLIL::Module::fixup_ports()
2026 {
2027 std::vector<RTLIL::Wire*> all_ports;
2028
2029 for (auto &w : wires_)
2030 if (w.second->port_input || w.second->port_output)
2031 all_ports.push_back(w.second);
2032 else
2033 w.second->port_id = 0;
2034
2035 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
2036
2037 ports.clear();
2038 for (size_t i = 0; i < all_ports.size(); i++) {
2039 ports.push_back(all_ports[i]->name);
2040 all_ports[i]->port_id = i+1;
2041 }
2042 }
2043
2044 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
2045 {
2046 RTLIL::Wire *wire = new RTLIL::Wire;
2047 wire->name = name;
2048 wire->width = width;
2049 add(wire);
2050 return wire;
2051 }
2052
2053 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
2054 {
2055 RTLIL::Wire *wire = addWire(name);
2056 wire->width = other->width;
2057 wire->start_offset = other->start_offset;
2058 wire->port_id = other->port_id;
2059 wire->port_input = other->port_input;
2060 wire->port_output = other->port_output;
2061 wire->upto = other->upto;
2062 wire->is_signed = other->is_signed;
2063 wire->attributes = other->attributes;
2064 return wire;
2065 }
2066
2067 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
2068 {
2069 RTLIL::Cell *cell = new RTLIL::Cell;
2070 cell->name = name;
2071 cell->type = type;
2072 add(cell);
2073 return cell;
2074 }
2075
2076 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
2077 {
2078 RTLIL::Cell *cell = addCell(name, other->type);
2079 cell->connections_ = other->connections_;
2080 cell->parameters = other->parameters;
2081 cell->attributes = other->attributes;
2082 return cell;
2083 }
2084
2085 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
2086 {
2087 RTLIL::Memory *mem = new RTLIL::Memory;
2088 mem->name = name;
2089 mem->width = other->width;
2090 mem->start_offset = other->start_offset;
2091 mem->size = other->size;
2092 mem->attributes = other->attributes;
2093 memories[mem->name] = mem;
2094 return mem;
2095 }
2096
2097 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
2098 {
2099 RTLIL::Process *proc = other->clone();
2100 proc->name = name;
2101 processes[name] = proc;
2102 return proc;
2103 }
2104
2105 #define DEF_METHOD(_func, _y_size, _type) \
2106 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2107 RTLIL::Cell *cell = addCell(name, _type); \
2108 cell->parameters[ID::A_SIGNED] = is_signed; \
2109 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2110 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2111 cell->setPort(ID::A, sig_a); \
2112 cell->setPort(ID::Y, sig_y); \
2113 cell->set_src_attribute(src); \
2114 return cell; \
2115 } \
2116 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2117 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2118 add ## _func(name, sig_a, sig_y, is_signed, src); \
2119 return sig_y; \
2120 }
2121 DEF_METHOD(Not, sig_a.size(), ID($not))
2122 DEF_METHOD(Pos, sig_a.size(), ID($pos))
2123 DEF_METHOD(Neg, sig_a.size(), ID($neg))
2124 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
2125 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
2126 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
2127 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
2128 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
2129 DEF_METHOD(LogicNot, 1, ID($logic_not))
2130 #undef DEF_METHOD
2131
2132 #define DEF_METHOD(_func, _y_size, _type) \
2133 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2134 RTLIL::Cell *cell = addCell(name, _type); \
2135 cell->parameters[ID::A_SIGNED] = is_signed; \
2136 cell->parameters[ID::B_SIGNED] = is_signed; \
2137 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2138 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2139 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2140 cell->setPort(ID::A, sig_a); \
2141 cell->setPort(ID::B, sig_b); \
2142 cell->setPort(ID::Y, sig_y); \
2143 cell->set_src_attribute(src); \
2144 return cell; \
2145 } \
2146 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2147 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2148 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2149 return sig_y; \
2150 }
2151 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
2152 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
2153 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
2154 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
2155 DEF_METHOD(Shift, sig_a.size(), ID($shift))
2156 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
2157 DEF_METHOD(Lt, 1, ID($lt))
2158 DEF_METHOD(Le, 1, ID($le))
2159 DEF_METHOD(Eq, 1, ID($eq))
2160 DEF_METHOD(Ne, 1, ID($ne))
2161 DEF_METHOD(Eqx, 1, ID($eqx))
2162 DEF_METHOD(Nex, 1, ID($nex))
2163 DEF_METHOD(Ge, 1, ID($ge))
2164 DEF_METHOD(Gt, 1, ID($gt))
2165 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
2166 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
2167 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
2168 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
2169 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
2170 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
2171 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
2172 DEF_METHOD(LogicAnd, 1, ID($logic_and))
2173 DEF_METHOD(LogicOr, 1, ID($logic_or))
2174 #undef DEF_METHOD
2175
2176 #define DEF_METHOD(_func, _y_size, _type) \
2177 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2178 RTLIL::Cell *cell = addCell(name, _type); \
2179 cell->parameters[ID::A_SIGNED] = is_signed; \
2180 cell->parameters[ID::B_SIGNED] = false; \
2181 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2182 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2183 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2184 cell->setPort(ID::A, sig_a); \
2185 cell->setPort(ID::B, sig_b); \
2186 cell->setPort(ID::Y, sig_y); \
2187 cell->set_src_attribute(src); \
2188 return cell; \
2189 } \
2190 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2191 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2192 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2193 return sig_y; \
2194 }
2195 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2196 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2197 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2198 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2199 #undef DEF_METHOD
2200
2201 #define DEF_METHOD(_func, _type, _pmux) \
2202 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2203 RTLIL::Cell *cell = addCell(name, _type); \
2204 cell->parameters[ID::WIDTH] = sig_a.size(); \
2205 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2206 cell->setPort(ID::A, sig_a); \
2207 cell->setPort(ID::B, sig_b); \
2208 cell->setPort(ID::S, sig_s); \
2209 cell->setPort(ID::Y, sig_y); \
2210 cell->set_src_attribute(src); \
2211 return cell; \
2212 } \
2213 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2214 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2215 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2216 return sig_y; \
2217 }
2218 DEF_METHOD(Mux, ID($mux), 0)
2219 DEF_METHOD(Pmux, ID($pmux), 1)
2220 #undef DEF_METHOD
2221
2222 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2223 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2224 RTLIL::Cell *cell = addCell(name, _type); \
2225 cell->setPort("\\" #_P1, sig1); \
2226 cell->setPort("\\" #_P2, sig2); \
2227 cell->set_src_attribute(src); \
2228 return cell; \
2229 } \
2230 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2231 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2232 add ## _func(name, sig1, sig2, src); \
2233 return sig2; \
2234 }
2235 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2236 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2237 RTLIL::Cell *cell = addCell(name, _type); \
2238 cell->setPort("\\" #_P1, sig1); \
2239 cell->setPort("\\" #_P2, sig2); \
2240 cell->setPort("\\" #_P3, sig3); \
2241 cell->set_src_attribute(src); \
2242 return cell; \
2243 } \
2244 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2245 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2246 add ## _func(name, sig1, sig2, sig3, src); \
2247 return sig3; \
2248 }
2249 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2250 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2251 RTLIL::Cell *cell = addCell(name, _type); \
2252 cell->setPort("\\" #_P1, sig1); \
2253 cell->setPort("\\" #_P2, sig2); \
2254 cell->setPort("\\" #_P3, sig3); \
2255 cell->setPort("\\" #_P4, sig4); \
2256 cell->set_src_attribute(src); \
2257 return cell; \
2258 } \
2259 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2260 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2261 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2262 return sig4; \
2263 }
2264 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2265 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2266 RTLIL::Cell *cell = addCell(name, _type); \
2267 cell->setPort("\\" #_P1, sig1); \
2268 cell->setPort("\\" #_P2, sig2); \
2269 cell->setPort("\\" #_P3, sig3); \
2270 cell->setPort("\\" #_P4, sig4); \
2271 cell->setPort("\\" #_P5, sig5); \
2272 cell->set_src_attribute(src); \
2273 return cell; \
2274 } \
2275 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2276 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2277 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2278 return sig5; \
2279 }
2280 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2281 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2282 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2283 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2284 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2285 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2286 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2287 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2288 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2289 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2290 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2291 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2292 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2293 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2294 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2295 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2296 #undef DEF_METHOD_2
2297 #undef DEF_METHOD_3
2298 #undef DEF_METHOD_4
2299 #undef DEF_METHOD_5
2300
2301 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2302 {
2303 RTLIL::Cell *cell = addCell(name, ID($pow));
2304 cell->parameters[ID::A_SIGNED] = a_signed;
2305 cell->parameters[ID::B_SIGNED] = b_signed;
2306 cell->parameters[ID::A_WIDTH] = sig_a.size();
2307 cell->parameters[ID::B_WIDTH] = sig_b.size();
2308 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2309 cell->setPort(ID::A, sig_a);
2310 cell->setPort(ID::B, sig_b);
2311 cell->setPort(ID::Y, sig_y);
2312 cell->set_src_attribute(src);
2313 return cell;
2314 }
2315
2316 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2317 {
2318 RTLIL::Cell *cell = addCell(name, ID($slice));
2319 cell->parameters[ID::A_WIDTH] = sig_a.size();
2320 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2321 cell->parameters[ID::OFFSET] = offset;
2322 cell->setPort(ID::A, sig_a);
2323 cell->setPort(ID::Y, sig_y);
2324 cell->set_src_attribute(src);
2325 return cell;
2326 }
2327
2328 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2329 {
2330 RTLIL::Cell *cell = addCell(name, ID($concat));
2331 cell->parameters[ID::A_WIDTH] = sig_a.size();
2332 cell->parameters[ID::B_WIDTH] = sig_b.size();
2333 cell->setPort(ID::A, sig_a);
2334 cell->setPort(ID::B, sig_b);
2335 cell->setPort(ID::Y, sig_y);
2336 cell->set_src_attribute(src);
2337 return cell;
2338 }
2339
2340 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2341 {
2342 RTLIL::Cell *cell = addCell(name, ID($lut));
2343 cell->parameters[ID::LUT] = lut;
2344 cell->parameters[ID::WIDTH] = sig_a.size();
2345 cell->setPort(ID::A, sig_a);
2346 cell->setPort(ID::Y, sig_y);
2347 cell->set_src_attribute(src);
2348 return cell;
2349 }
2350
2351 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2352 {
2353 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2354 cell->parameters[ID::WIDTH] = sig_a.size();
2355 cell->setPort(ID::A, sig_a);
2356 cell->setPort(ID::EN, sig_en);
2357 cell->setPort(ID::Y, sig_y);
2358 cell->set_src_attribute(src);
2359 return cell;
2360 }
2361
2362 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2363 {
2364 RTLIL::Cell *cell = addCell(name, ID($assert));
2365 cell->setPort(ID::A, sig_a);
2366 cell->setPort(ID::EN, sig_en);
2367 cell->set_src_attribute(src);
2368 return cell;
2369 }
2370
2371 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2372 {
2373 RTLIL::Cell *cell = addCell(name, ID($assume));
2374 cell->setPort(ID::A, sig_a);
2375 cell->setPort(ID::EN, sig_en);
2376 cell->set_src_attribute(src);
2377 return cell;
2378 }
2379
2380 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2381 {
2382 RTLIL::Cell *cell = addCell(name, ID($live));
2383 cell->setPort(ID::A, sig_a);
2384 cell->setPort(ID::EN, sig_en);
2385 cell->set_src_attribute(src);
2386 return cell;
2387 }
2388
2389 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2390 {
2391 RTLIL::Cell *cell = addCell(name, ID($fair));
2392 cell->setPort(ID::A, sig_a);
2393 cell->setPort(ID::EN, sig_en);
2394 cell->set_src_attribute(src);
2395 return cell;
2396 }
2397
2398 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2399 {
2400 RTLIL::Cell *cell = addCell(name, ID($cover));
2401 cell->setPort(ID::A, sig_a);
2402 cell->setPort(ID::EN, sig_en);
2403 cell->set_src_attribute(src);
2404 return cell;
2405 }
2406
2407 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2408 {
2409 RTLIL::Cell *cell = addCell(name, ID($equiv));
2410 cell->setPort(ID::A, sig_a);
2411 cell->setPort(ID::B, sig_b);
2412 cell->setPort(ID::Y, sig_y);
2413 cell->set_src_attribute(src);
2414 return cell;
2415 }
2416
2417 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2418 {
2419 RTLIL::Cell *cell = addCell(name, ID($sr));
2420 cell->parameters[ID::SET_POLARITY] = set_polarity;
2421 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2422 cell->parameters[ID::WIDTH] = sig_q.size();
2423 cell->setPort(ID::SET, sig_set);
2424 cell->setPort(ID::CLR, sig_clr);
2425 cell->setPort(ID::Q, sig_q);
2426 cell->set_src_attribute(src);
2427 return cell;
2428 }
2429
2430 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2431 {
2432 RTLIL::Cell *cell = addCell(name, ID($ff));
2433 cell->parameters[ID::WIDTH] = sig_q.size();
2434 cell->setPort(ID::D, sig_d);
2435 cell->setPort(ID::Q, sig_q);
2436 cell->set_src_attribute(src);
2437 return cell;
2438 }
2439
2440 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2441 {
2442 RTLIL::Cell *cell = addCell(name, ID($dff));
2443 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2444 cell->parameters[ID::WIDTH] = sig_q.size();
2445 cell->setPort(ID::CLK, sig_clk);
2446 cell->setPort(ID::D, sig_d);
2447 cell->setPort(ID::Q, sig_q);
2448 cell->set_src_attribute(src);
2449 return cell;
2450 }
2451
2452 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2453 {
2454 RTLIL::Cell *cell = addCell(name, ID($dffe));
2455 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2456 cell->parameters[ID::EN_POLARITY] = en_polarity;
2457 cell->parameters[ID::WIDTH] = sig_q.size();
2458 cell->setPort(ID::CLK, sig_clk);
2459 cell->setPort(ID::EN, sig_en);
2460 cell->setPort(ID::D, sig_d);
2461 cell->setPort(ID::Q, sig_q);
2462 cell->set_src_attribute(src);
2463 return cell;
2464 }
2465
2466 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2467 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2468 {
2469 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2470 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2471 cell->parameters[ID::SET_POLARITY] = set_polarity;
2472 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2473 cell->parameters[ID::WIDTH] = sig_q.size();
2474 cell->setPort(ID::CLK, sig_clk);
2475 cell->setPort(ID::SET, sig_set);
2476 cell->setPort(ID::CLR, sig_clr);
2477 cell->setPort(ID::D, sig_d);
2478 cell->setPort(ID::Q, sig_q);
2479 cell->set_src_attribute(src);
2480 return cell;
2481 }
2482
2483 RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2484 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2485 {
2486 RTLIL::Cell *cell = addCell(name, ID($dffsre));
2487 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2488 cell->parameters[ID::EN_POLARITY] = en_polarity;
2489 cell->parameters[ID::SET_POLARITY] = set_polarity;
2490 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2491 cell->parameters[ID::WIDTH] = sig_q.size();
2492 cell->setPort(ID::CLK, sig_clk);
2493 cell->setPort(ID::EN, sig_en);
2494 cell->setPort(ID::SET, sig_set);
2495 cell->setPort(ID::CLR, sig_clr);
2496 cell->setPort(ID::D, sig_d);
2497 cell->setPort(ID::Q, sig_q);
2498 cell->set_src_attribute(src);
2499 return cell;
2500 }
2501
2502 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2503 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2504 {
2505 RTLIL::Cell *cell = addCell(name, ID($adff));
2506 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2507 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2508 cell->parameters[ID::ARST_VALUE] = arst_value;
2509 cell->parameters[ID::WIDTH] = sig_q.size();
2510 cell->setPort(ID::CLK, sig_clk);
2511 cell->setPort(ID::ARST, sig_arst);
2512 cell->setPort(ID::D, sig_d);
2513 cell->setPort(ID::Q, sig_q);
2514 cell->set_src_attribute(src);
2515 return cell;
2516 }
2517
2518 RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2519 RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2520 {
2521 RTLIL::Cell *cell = addCell(name, ID($adffe));
2522 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2523 cell->parameters[ID::EN_POLARITY] = en_polarity;
2524 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2525 cell->parameters[ID::ARST_VALUE] = arst_value;
2526 cell->parameters[ID::WIDTH] = sig_q.size();
2527 cell->setPort(ID::CLK, sig_clk);
2528 cell->setPort(ID::EN, sig_en);
2529 cell->setPort(ID::ARST, sig_arst);
2530 cell->setPort(ID::D, sig_d);
2531 cell->setPort(ID::Q, sig_q);
2532 cell->set_src_attribute(src);
2533 return cell;
2534 }
2535
2536 RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2537 RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2538 {
2539 RTLIL::Cell *cell = addCell(name, ID($sdff));
2540 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2541 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2542 cell->parameters[ID::SRST_VALUE] = srst_value;
2543 cell->parameters[ID::WIDTH] = sig_q.size();
2544 cell->setPort(ID::CLK, sig_clk);
2545 cell->setPort(ID::SRST, sig_srst);
2546 cell->setPort(ID::D, sig_d);
2547 cell->setPort(ID::Q, sig_q);
2548 cell->set_src_attribute(src);
2549 return cell;
2550 }
2551
2552 RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2553 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2554 {
2555 RTLIL::Cell *cell = addCell(name, ID($sdffe));
2556 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2557 cell->parameters[ID::EN_POLARITY] = en_polarity;
2558 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2559 cell->parameters[ID::SRST_VALUE] = srst_value;
2560 cell->parameters[ID::WIDTH] = sig_q.size();
2561 cell->setPort(ID::CLK, sig_clk);
2562 cell->setPort(ID::EN, sig_en);
2563 cell->setPort(ID::SRST, sig_srst);
2564 cell->setPort(ID::D, sig_d);
2565 cell->setPort(ID::Q, sig_q);
2566 cell->set_src_attribute(src);
2567 return cell;
2568 }
2569
2570 RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2571 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2572 {
2573 RTLIL::Cell *cell = addCell(name, ID($sdffce));
2574 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2575 cell->parameters[ID::EN_POLARITY] = en_polarity;
2576 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2577 cell->parameters[ID::SRST_VALUE] = srst_value;
2578 cell->parameters[ID::WIDTH] = sig_q.size();
2579 cell->setPort(ID::CLK, sig_clk);
2580 cell->setPort(ID::EN, sig_en);
2581 cell->setPort(ID::SRST, sig_srst);
2582 cell->setPort(ID::D, sig_d);
2583 cell->setPort(ID::Q, sig_q);
2584 cell->set_src_attribute(src);
2585 return cell;
2586 }
2587
2588 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2589 {
2590 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2591 cell->parameters[ID::EN_POLARITY] = en_polarity;
2592 cell->parameters[ID::WIDTH] = sig_q.size();
2593 cell->setPort(ID::EN, sig_en);
2594 cell->setPort(ID::D, sig_d);
2595 cell->setPort(ID::Q, sig_q);
2596 cell->set_src_attribute(src);
2597 return cell;
2598 }
2599
2600 RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2601 RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2602 {
2603 RTLIL::Cell *cell = addCell(name, ID($adlatch));
2604 cell->parameters[ID::EN_POLARITY] = en_polarity;
2605 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2606 cell->parameters[ID::ARST_VALUE] = arst_value;
2607 cell->parameters[ID::WIDTH] = sig_q.size();
2608 cell->setPort(ID::EN, sig_en);
2609 cell->setPort(ID::ARST, sig_arst);
2610 cell->setPort(ID::D, sig_d);
2611 cell->setPort(ID::Q, sig_q);
2612 cell->set_src_attribute(src);
2613 return cell;
2614 }
2615
2616 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2617 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2618 {
2619 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2620 cell->parameters[ID::EN_POLARITY] = en_polarity;
2621 cell->parameters[ID::SET_POLARITY] = set_polarity;
2622 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2623 cell->parameters[ID::WIDTH] = sig_q.size();
2624 cell->setPort(ID::EN, sig_en);
2625 cell->setPort(ID::SET, sig_set);
2626 cell->setPort(ID::CLR, sig_clr);
2627 cell->setPort(ID::D, sig_d);
2628 cell->setPort(ID::Q, sig_q);
2629 cell->set_src_attribute(src);
2630 return cell;
2631 }
2632
2633 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2634 const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2635 {
2636 RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2637 cell->setPort(ID::S, sig_set);
2638 cell->setPort(ID::R, sig_clr);
2639 cell->setPort(ID::Q, sig_q);
2640 cell->set_src_attribute(src);
2641 return cell;
2642 }
2643
2644 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2645 {
2646 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2647 cell->setPort(ID::D, sig_d);
2648 cell->setPort(ID::Q, sig_q);
2649 cell->set_src_attribute(src);
2650 return cell;
2651 }
2652
2653 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2654 {
2655 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2656 cell->setPort(ID::C, sig_clk);
2657 cell->setPort(ID::D, sig_d);
2658 cell->setPort(ID::Q, sig_q);
2659 cell->set_src_attribute(src);
2660 return cell;
2661 }
2662
2663 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2664 {
2665 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2666 cell->setPort(ID::C, sig_clk);
2667 cell->setPort(ID::E, sig_en);
2668 cell->setPort(ID::D, sig_d);
2669 cell->setPort(ID::Q, sig_q);
2670 cell->set_src_attribute(src);
2671 return cell;
2672 }
2673
2674 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2675 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2676 {
2677 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2678 cell->setPort(ID::C, sig_clk);
2679 cell->setPort(ID::S, sig_set);
2680 cell->setPort(ID::R, sig_clr);
2681 cell->setPort(ID::D, sig_d);
2682 cell->setPort(ID::Q, sig_q);
2683 cell->set_src_attribute(src);
2684 return cell;
2685 }
2686
2687 RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2688 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2689 {
2690 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2691 cell->setPort(ID::C, sig_clk);
2692 cell->setPort(ID::S, sig_set);
2693 cell->setPort(ID::R, sig_clr);
2694 cell->setPort(ID::E, sig_en);
2695 cell->setPort(ID::D, sig_d);
2696 cell->setPort(ID::Q, sig_q);
2697 cell->set_src_attribute(src);
2698 return cell;
2699 }
2700
2701 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2702 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2703 {
2704 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2705 cell->setPort(ID::C, sig_clk);
2706 cell->setPort(ID::R, sig_arst);
2707 cell->setPort(ID::D, sig_d);
2708 cell->setPort(ID::Q, sig_q);
2709 cell->set_src_attribute(src);
2710 return cell;
2711 }
2712
2713 RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2714 bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2715 {
2716 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2717 cell->setPort(ID::C, sig_clk);
2718 cell->setPort(ID::R, sig_arst);
2719 cell->setPort(ID::E, sig_en);
2720 cell->setPort(ID::D, sig_d);
2721 cell->setPort(ID::Q, sig_q);
2722 cell->set_src_attribute(src);
2723 return cell;
2724 }
2725
2726 RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2727 bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2728 {
2729 RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
2730 cell->setPort(ID::C, sig_clk);
2731 cell->setPort(ID::R, sig_srst);
2732 cell->setPort(ID::D, sig_d);
2733 cell->setPort(ID::Q, sig_q);
2734 cell->set_src_attribute(src);
2735 return cell;
2736 }
2737
2738 RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2739 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2740 {
2741 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2742 cell->setPort(ID::C, sig_clk);
2743 cell->setPort(ID::R, sig_srst);
2744 cell->setPort(ID::E, sig_en);
2745 cell->setPort(ID::D, sig_d);
2746 cell->setPort(ID::Q, sig_q);
2747 cell->set_src_attribute(src);
2748 return cell;
2749 }
2750
2751 RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2752 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2753 {
2754 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2755 cell->setPort(ID::C, sig_clk);
2756 cell->setPort(ID::R, sig_srst);
2757 cell->setPort(ID::E, sig_en);
2758 cell->setPort(ID::D, sig_d);
2759 cell->setPort(ID::Q, sig_q);
2760 cell->set_src_attribute(src);
2761 return cell;
2762 }
2763
2764 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2765 {
2766 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2767 cell->setPort(ID::E, sig_en);
2768 cell->setPort(ID::D, sig_d);
2769 cell->setPort(ID::Q, sig_q);
2770 cell->set_src_attribute(src);
2771 return cell;
2772 }
2773
2774 RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2775 bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2776 {
2777 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2778 cell->setPort(ID::E, sig_en);
2779 cell->setPort(ID::R, sig_arst);
2780 cell->setPort(ID::D, sig_d);
2781 cell->setPort(ID::Q, sig_q);
2782 cell->set_src_attribute(src);
2783 return cell;
2784 }
2785
2786 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2787 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2788 {
2789 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2790 cell->setPort(ID::E, sig_en);
2791 cell->setPort(ID::S, sig_set);
2792 cell->setPort(ID::R, sig_clr);
2793 cell->setPort(ID::D, sig_d);
2794 cell->setPort(ID::Q, sig_q);
2795 cell->set_src_attribute(src);
2796 return cell;
2797 }
2798
2799 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2800 {
2801 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2802 Cell *cell = addCell(name, ID($anyconst));
2803 cell->setParam(ID::WIDTH, width);
2804 cell->setPort(ID::Y, sig);
2805 cell->set_src_attribute(src);
2806 return sig;
2807 }
2808
2809 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2810 {
2811 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2812 Cell *cell = addCell(name, ID($anyseq));
2813 cell->setParam(ID::WIDTH, width);
2814 cell->setPort(ID::Y, sig);
2815 cell->set_src_attribute(src);
2816 return sig;
2817 }
2818
2819 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2820 {
2821 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2822 Cell *cell = addCell(name, ID($allconst));
2823 cell->setParam(ID::WIDTH, width);
2824 cell->setPort(ID::Y, sig);
2825 cell->set_src_attribute(src);
2826 return sig;
2827 }
2828
2829 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2830 {
2831 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2832 Cell *cell = addCell(name, ID($allseq));
2833 cell->setParam(ID::WIDTH, width);
2834 cell->setPort(ID::Y, sig);
2835 cell->set_src_attribute(src);
2836 return sig;
2837 }
2838
2839 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2840 {
2841 RTLIL::SigSpec sig = addWire(NEW_ID);
2842 Cell *cell = addCell(name, ID($initstate));
2843 cell->setPort(ID::Y, sig);
2844 cell->set_src_attribute(src);
2845 return sig;
2846 }
2847
2848 RTLIL::Wire::Wire()
2849 {
2850 static unsigned int hashidx_count = 123456789;
2851 hashidx_count = mkhash_xorshift(hashidx_count);
2852 hashidx_ = hashidx_count;
2853
2854 module = nullptr;
2855 width = 1;
2856 start_offset = 0;
2857 port_id = 0;
2858 port_input = false;
2859 port_output = false;
2860 upto = false;
2861 is_signed = false;
2862
2863 #ifdef WITH_PYTHON
2864 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2865 #endif
2866 }
2867
2868 RTLIL::Wire::~Wire()
2869 {
2870 #ifdef WITH_PYTHON
2871 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2872 #endif
2873 }
2874
2875 #ifdef WITH_PYTHON
2876 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2877 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2878 {
2879 return &all_wires;
2880 }
2881 #endif
2882
2883 RTLIL::Memory::Memory()
2884 {
2885 static unsigned int hashidx_count = 123456789;
2886 hashidx_count = mkhash_xorshift(hashidx_count);
2887 hashidx_ = hashidx_count;
2888
2889 width = 1;
2890 start_offset = 0;
2891 size = 0;
2892 #ifdef WITH_PYTHON
2893 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2894 #endif
2895 }
2896
2897 RTLIL::Cell::Cell() : module(nullptr)
2898 {
2899 static unsigned int hashidx_count = 123456789;
2900 hashidx_count = mkhash_xorshift(hashidx_count);
2901 hashidx_ = hashidx_count;
2902
2903 // log("#memtrace# %p\n", this);
2904 memhasher();
2905
2906 #ifdef WITH_PYTHON
2907 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2908 #endif
2909 }
2910
2911 RTLIL::Cell::~Cell()
2912 {
2913 #ifdef WITH_PYTHON
2914 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2915 #endif
2916 }
2917
2918 #ifdef WITH_PYTHON
2919 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2920 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2921 {
2922 return &all_cells;
2923 }
2924 #endif
2925
2926 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2927 {
2928 return connections_.count(portname) != 0;
2929 }
2930
2931 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2932 {
2933 RTLIL::SigSpec signal;
2934 auto conn_it = connections_.find(portname);
2935
2936 if (conn_it != connections_.end())
2937 {
2938 for (auto mon : module->monitors)
2939 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2940
2941 if (module->design)
2942 for (auto mon : module->design->monitors)
2943 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2944
2945 if (yosys_xtrace) {
2946 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2947 log_backtrace("-X- ", yosys_xtrace-1);
2948 }
2949
2950 connections_.erase(conn_it);
2951 }
2952 }
2953
2954 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2955 {
2956 auto r = connections_.insert(portname);
2957 auto conn_it = r.first;
2958 if (!r.second && conn_it->second == signal)
2959 return;
2960
2961 for (auto mon : module->monitors)
2962 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2963
2964 if (module->design)
2965 for (auto mon : module->design->monitors)
2966 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2967
2968 if (yosys_xtrace) {
2969 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2970 log_backtrace("-X- ", yosys_xtrace-1);
2971 }
2972
2973 conn_it->second = std::move(signal);
2974 }
2975
2976 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2977 {
2978 return connections_.at(portname);
2979 }
2980
2981 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2982 {
2983 return connections_;
2984 }
2985
2986 bool RTLIL::Cell::known() const
2987 {
2988 if (yosys_celltypes.cell_known(type))
2989 return true;
2990 if (module && module->design && module->design->module(type))
2991 return true;
2992 return false;
2993 }
2994
2995 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2996 {
2997 if (yosys_celltypes.cell_known(type))
2998 return yosys_celltypes.cell_input(type, portname);
2999 if (module && module->design) {
3000 RTLIL::Module *m = module->design->module(type);
3001 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3002 return w && w->port_input;
3003 }
3004 return false;
3005 }
3006
3007 bool RTLIL::Cell::output(RTLIL::IdString portname) const
3008 {
3009 if (yosys_celltypes.cell_known(type))
3010 return yosys_celltypes.cell_output(type, portname);
3011 if (module && module->design) {
3012 RTLIL::Module *m = module->design->module(type);
3013 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3014 return w && w->port_output;
3015 }
3016 return false;
3017 }
3018
3019 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
3020 {
3021 return parameters.count(paramname) != 0;
3022 }
3023
3024 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
3025 {
3026 parameters.erase(paramname);
3027 }
3028
3029 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
3030 {
3031 parameters[paramname] = std::move(value);
3032 }
3033
3034 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
3035 {
3036 const auto &it = parameters.find(paramname);
3037 if (it != parameters.end())
3038 return it->second;
3039 if (module && module->design) {
3040 RTLIL::Module *m = module->design->module(type);
3041 if (m)
3042 return m->parameter_default_values.at(paramname);
3043 }
3044 throw std::out_of_range("Cell::getParam()");
3045 }
3046
3047 void RTLIL::Cell::sort()
3048 {
3049 connections_.sort(sort_by_id_str());
3050 parameters.sort(sort_by_id_str());
3051 attributes.sort(sort_by_id_str());
3052 }
3053
3054 void RTLIL::Cell::check()
3055 {
3056 #ifndef NDEBUG
3057 InternalCellChecker checker(NULL, this);
3058 checker.check();
3059 #endif
3060 }
3061
3062 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
3063 {
3064 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
3065 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
3066 return;
3067
3068 if (type == ID($mux) || type == ID($pmux)) {
3069 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3070 if (type == ID($pmux))
3071 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3072 check();
3073 return;
3074 }
3075
3076 if (type == ID($lut) || type == ID($sop)) {
3077 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3078 return;
3079 }
3080
3081 if (type == ID($fa)) {
3082 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3083 return;
3084 }
3085
3086 if (type == ID($lcu)) {
3087 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
3088 return;
3089 }
3090
3091 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
3092
3093 if (connections_.count(ID::A)) {
3094 if (signedness_ab) {
3095 if (set_a_signed)
3096 parameters[ID::A_SIGNED] = true;
3097 else if (parameters.count(ID::A_SIGNED) == 0)
3098 parameters[ID::A_SIGNED] = false;
3099 }
3100 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
3101 }
3102
3103 if (connections_.count(ID::B)) {
3104 if (signedness_ab) {
3105 if (set_b_signed)
3106 parameters[ID::B_SIGNED] = true;
3107 else if (parameters.count(ID::B_SIGNED) == 0)
3108 parameters[ID::B_SIGNED] = false;
3109 }
3110 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
3111 }
3112
3113 if (connections_.count(ID::Y))
3114 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
3115
3116 if (connections_.count(ID::Q))
3117 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
3118
3119 check();
3120 }
3121
3122 RTLIL::SigChunk::SigChunk()
3123 {
3124 wire = NULL;
3125 width = 0;
3126 offset = 0;
3127 }
3128
3129 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
3130 {
3131 wire = NULL;
3132 data = value.bits;
3133 width = GetSize(data);
3134 offset = 0;
3135 }
3136
3137 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
3138 {
3139 log_assert(wire != nullptr);
3140 this->wire = wire;
3141 this->width = wire->width;
3142 this->offset = 0;
3143 }
3144
3145 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
3146 {
3147 log_assert(wire != nullptr);
3148 this->wire = wire;
3149 this->width = width;
3150 this->offset = offset;
3151 }
3152
3153 RTLIL::SigChunk::SigChunk(const std::string &str)
3154 {
3155 wire = NULL;
3156 data = RTLIL::Const(str).bits;
3157 width = GetSize(data);
3158 offset = 0;
3159 }
3160
3161 RTLIL::SigChunk::SigChunk(int val, int width)
3162 {
3163 wire = NULL;
3164 data = RTLIL::Const(val, width).bits;
3165 this->width = GetSize(data);
3166 offset = 0;
3167 }
3168
3169 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
3170 {
3171 wire = NULL;
3172 data = RTLIL::Const(bit, width).bits;
3173 this->width = GetSize(data);
3174 offset = 0;
3175 }
3176
3177 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
3178 {
3179 wire = bit.wire;
3180 offset = 0;
3181 if (wire == NULL)
3182 data = RTLIL::Const(bit.data).bits;
3183 else
3184 offset = bit.offset;
3185 width = 1;
3186 }
3187
3188 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
3189 {
3190 *this = sigchunk;
3191 }
3192
3193 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
3194 {
3195 RTLIL::SigChunk ret;
3196 if (wire) {
3197 ret.wire = wire;
3198 ret.offset = this->offset + offset;
3199 ret.width = length;
3200 } else {
3201 for (int i = 0; i < length; i++)
3202 ret.data.push_back(data[offset+i]);
3203 ret.width = length;
3204 }
3205 return ret;
3206 }
3207
3208 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
3209 {
3210 if (wire && other.wire)
3211 if (wire->name != other.wire->name)
3212 return wire->name < other.wire->name;
3213
3214 if (wire != other.wire)
3215 return wire < other.wire;
3216
3217 if (offset != other.offset)
3218 return offset < other.offset;
3219
3220 if (width != other.width)
3221 return width < other.width;
3222
3223 return data < other.data;
3224 }
3225
3226 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
3227 {
3228 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
3229 }
3230
3231 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
3232 {
3233 if (*this == other)
3234 return false;
3235 return true;
3236 }
3237
3238 RTLIL::SigSpec::SigSpec()
3239 {
3240 width_ = 0;
3241 hash_ = 0;
3242 }
3243
3244 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
3245 {
3246 *this = other;
3247 }
3248
3249 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
3250 {
3251 cover("kernel.rtlil.sigspec.init.list");
3252
3253 width_ = 0;
3254 hash_ = 0;
3255
3256 log_assert(parts.size() > 0);
3257 auto ie = parts.begin();
3258 auto it = ie + parts.size() - 1;
3259 while (it >= ie)
3260 append(*it--);
3261 }
3262
3263 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
3264 {
3265 cover("kernel.rtlil.sigspec.assign");
3266
3267 width_ = other.width_;
3268 hash_ = other.hash_;
3269 chunks_ = other.chunks_;
3270 bits_ = other.bits_;
3271 return *this;
3272 }
3273
3274 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
3275 {
3276 cover("kernel.rtlil.sigspec.init.const");
3277
3278 chunks_.emplace_back(value);
3279 width_ = chunks_.back().width;
3280 hash_ = 0;
3281 check();
3282 }
3283
3284 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
3285 {
3286 cover("kernel.rtlil.sigspec.init.chunk");
3287
3288 chunks_.emplace_back(chunk);
3289 width_ = chunks_.back().width;
3290 hash_ = 0;
3291 check();
3292 }
3293
3294 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
3295 {
3296 cover("kernel.rtlil.sigspec.init.wire");
3297
3298 chunks_.emplace_back(wire);
3299 width_ = chunks_.back().width;
3300 hash_ = 0;
3301 check();
3302 }
3303
3304 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
3305 {
3306 cover("kernel.rtlil.sigspec.init.wire_part");
3307
3308 chunks_.emplace_back(wire, offset, width);
3309 width_ = chunks_.back().width;
3310 hash_ = 0;
3311 check();
3312 }
3313
3314 RTLIL::SigSpec::SigSpec(const std::string &str)
3315 {
3316 cover("kernel.rtlil.sigspec.init.str");
3317
3318 chunks_.emplace_back(str);
3319 width_ = chunks_.back().width;
3320 hash_ = 0;
3321 check();
3322 }
3323
3324 RTLIL::SigSpec::SigSpec(int val, int width)
3325 {
3326 cover("kernel.rtlil.sigspec.init.int");
3327
3328 chunks_.emplace_back(val, width);
3329 width_ = width;
3330 hash_ = 0;
3331 check();
3332 }
3333
3334 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
3335 {
3336 cover("kernel.rtlil.sigspec.init.state");
3337
3338 chunks_.emplace_back(bit, width);
3339 width_ = width;
3340 hash_ = 0;
3341 check();
3342 }
3343
3344 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
3345 {
3346 cover("kernel.rtlil.sigspec.init.bit");
3347
3348 if (bit.wire == NULL)
3349 chunks_.emplace_back(bit.data, width);
3350 else
3351 for (int i = 0; i < width; i++)
3352 chunks_.push_back(bit);
3353 width_ = width;
3354 hash_ = 0;
3355 check();
3356 }
3357
3358 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
3359 {
3360 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3361
3362 width_ = 0;
3363 hash_ = 0;
3364 for (const auto &c : chunks)
3365 append(c);
3366 check();
3367 }
3368
3369 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
3370 {
3371 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3372
3373 width_ = 0;
3374 hash_ = 0;
3375 for (const auto &bit : bits)
3376 append(bit);
3377 check();
3378 }
3379
3380 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3381 {
3382 cover("kernel.rtlil.sigspec.init.pool_bits");
3383
3384 width_ = 0;
3385 hash_ = 0;
3386 for (const auto &bit : bits)
3387 append(bit);
3388 check();
3389 }
3390
3391 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3392 {
3393 cover("kernel.rtlil.sigspec.init.stdset_bits");
3394
3395 width_ = 0;
3396 hash_ = 0;
3397 for (const auto &bit : bits)
3398 append(bit);
3399 check();
3400 }
3401
3402 RTLIL::SigSpec::SigSpec(bool bit)
3403 {
3404 cover("kernel.rtlil.sigspec.init.bool");
3405
3406 width_ = 0;
3407 hash_ = 0;
3408 append(SigBit(bit));
3409 check();
3410 }
3411
3412 void RTLIL::SigSpec::pack() const
3413 {
3414 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3415
3416 if (that->bits_.empty())
3417 return;
3418
3419 cover("kernel.rtlil.sigspec.convert.pack");
3420 log_assert(that->chunks_.empty());
3421
3422 std::vector<RTLIL::SigBit> old_bits;
3423 old_bits.swap(that->bits_);
3424
3425 RTLIL::SigChunk *last = NULL;
3426 int last_end_offset = 0;
3427
3428 for (auto &bit : old_bits) {
3429 if (last && bit.wire == last->wire) {
3430 if (bit.wire == NULL) {
3431 last->data.push_back(bit.data);
3432 last->width++;
3433 continue;
3434 } else if (last_end_offset == bit.offset) {
3435 last_end_offset++;
3436 last->width++;
3437 continue;
3438 }
3439 }
3440 that->chunks_.push_back(bit);
3441 last = &that->chunks_.back();
3442 last_end_offset = bit.offset + 1;
3443 }
3444
3445 check();
3446 }
3447
3448 void RTLIL::SigSpec::unpack() const
3449 {
3450 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3451
3452 if (that->chunks_.empty())
3453 return;
3454
3455 cover("kernel.rtlil.sigspec.convert.unpack");
3456 log_assert(that->bits_.empty());
3457
3458 that->bits_.reserve(that->width_);
3459 for (auto &c : that->chunks_)
3460 for (int i = 0; i < c.width; i++)
3461 that->bits_.emplace_back(c, i);
3462
3463 that->chunks_.clear();
3464 that->hash_ = 0;
3465 }
3466
3467 void RTLIL::SigSpec::updhash() const
3468 {
3469 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3470
3471 if (that->hash_ != 0)
3472 return;
3473
3474 cover("kernel.rtlil.sigspec.hash");
3475 that->pack();
3476
3477 that->hash_ = mkhash_init;
3478 for (auto &c : that->chunks_)
3479 if (c.wire == NULL) {
3480 for (auto &v : c.data)
3481 that->hash_ = mkhash(that->hash_, v);
3482 } else {
3483 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3484 that->hash_ = mkhash(that->hash_, c.offset);
3485 that->hash_ = mkhash(that->hash_, c.width);
3486 }
3487
3488 if (that->hash_ == 0)
3489 that->hash_ = 1;
3490 }
3491
3492 void RTLIL::SigSpec::sort()
3493 {
3494 unpack();
3495 cover("kernel.rtlil.sigspec.sort");
3496 std::sort(bits_.begin(), bits_.end());
3497 }
3498
3499 void RTLIL::SigSpec::sort_and_unify()
3500 {
3501 unpack();
3502 cover("kernel.rtlil.sigspec.sort_and_unify");
3503
3504 // A copy of the bits vector is used to prevent duplicating the logic from
3505 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3506 // that isn't showing up as significant in profiles.
3507 std::vector<SigBit> unique_bits = bits_;
3508 std::sort(unique_bits.begin(), unique_bits.end());
3509 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3510 unique_bits.erase(last, unique_bits.end());
3511
3512 *this = unique_bits;
3513 }
3514
3515 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3516 {
3517 replace(pattern, with, this);
3518 }
3519
3520 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3521 {
3522 log_assert(other != NULL);
3523 log_assert(width_ == other->width_);
3524 log_assert(pattern.width_ == with.width_);
3525
3526 pattern.unpack();
3527 with.unpack();
3528 unpack();
3529 other->unpack();
3530
3531 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3532 if (pattern.bits_[i].wire != NULL) {
3533 for (int j = 0; j < GetSize(bits_); j++) {
3534 if (bits_[j] == pattern.bits_[i]) {
3535 other->bits_[j] = with.bits_[i];
3536 }
3537 }
3538 }
3539 }
3540
3541 other->check();
3542 }
3543
3544 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3545 {
3546 replace(rules, this);
3547 }
3548
3549 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3550 {
3551 cover("kernel.rtlil.sigspec.replace_dict");
3552
3553 log_assert(other != NULL);
3554 log_assert(width_ == other->width_);
3555
3556 if (rules.empty()) return;
3557 unpack();
3558 other->unpack();
3559
3560 for (int i = 0; i < GetSize(bits_); i++) {
3561 auto it = rules.find(bits_[i]);
3562 if (it != rules.end())
3563 other->bits_[i] = it->second;
3564 }
3565
3566 other->check();
3567 }
3568
3569 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3570 {
3571 replace(rules, this);
3572 }
3573
3574 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3575 {
3576 cover("kernel.rtlil.sigspec.replace_map");
3577
3578 log_assert(other != NULL);
3579 log_assert(width_ == other->width_);
3580
3581 if (rules.empty()) return;
3582 unpack();
3583 other->unpack();
3584
3585 for (int i = 0; i < GetSize(bits_); i++) {
3586 auto it = rules.find(bits_[i]);
3587 if (it != rules.end())
3588 other->bits_[i] = it->second;
3589 }
3590
3591 other->check();
3592 }
3593
3594 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3595 {
3596 remove2(pattern, NULL);
3597 }
3598
3599 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3600 {
3601 RTLIL::SigSpec tmp = *this;
3602 tmp.remove2(pattern, other);
3603 }
3604
3605 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3606 {
3607 if (other)
3608 cover("kernel.rtlil.sigspec.remove_other");
3609 else
3610 cover("kernel.rtlil.sigspec.remove");
3611
3612 unpack();
3613 if (other != NULL) {
3614 log_assert(width_ == other->width_);
3615 other->unpack();
3616 }
3617
3618 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3619 {
3620 if (bits_[i].wire == NULL) continue;
3621
3622 for (auto &pattern_chunk : pattern.chunks())
3623 if (bits_[i].wire == pattern_chunk.wire &&
3624 bits_[i].offset >= pattern_chunk.offset &&
3625 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3626 bits_.erase(bits_.begin() + i);
3627 width_--;
3628 if (other != NULL) {
3629 other->bits_.erase(other->bits_.begin() + i);
3630 other->width_--;
3631 }
3632 break;
3633 }
3634 }
3635
3636 check();
3637 }
3638
3639 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3640 {
3641 remove2(pattern, NULL);
3642 }
3643
3644 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3645 {
3646 RTLIL::SigSpec tmp = *this;
3647 tmp.remove2(pattern, other);
3648 }
3649
3650 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3651 {
3652 if (other)
3653 cover("kernel.rtlil.sigspec.remove_other");
3654 else
3655 cover("kernel.rtlil.sigspec.remove");
3656
3657 unpack();
3658
3659 if (other != NULL) {
3660 log_assert(width_ == other->width_);
3661 other->unpack();
3662 }
3663
3664 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3665 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3666 bits_.erase(bits_.begin() + i);
3667 width_--;
3668 if (other != NULL) {
3669 other->bits_.erase(other->bits_.begin() + i);
3670 other->width_--;
3671 }
3672 }
3673 }
3674
3675 check();
3676 }
3677
3678 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3679 {
3680 if (other)
3681 cover("kernel.rtlil.sigspec.remove_other");
3682 else
3683 cover("kernel.rtlil.sigspec.remove");
3684
3685 unpack();
3686
3687 if (other != NULL) {
3688 log_assert(width_ == other->width_);
3689 other->unpack();
3690 }
3691
3692 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3693 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3694 bits_.erase(bits_.begin() + i);
3695 width_--;
3696 if (other != NULL) {
3697 other->bits_.erase(other->bits_.begin() + i);
3698 other->width_--;
3699 }
3700 }
3701 }
3702
3703 check();
3704 }
3705
3706 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3707 {
3708 if (other)
3709 cover("kernel.rtlil.sigspec.extract_other");
3710 else
3711 cover("kernel.rtlil.sigspec.extract");
3712
3713 log_assert(other == NULL || width_ == other->width_);
3714
3715 RTLIL::SigSpec ret;
3716 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3717
3718 for (auto& pattern_chunk : pattern.chunks()) {
3719 if (other) {
3720 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3721 for (int i = 0; i < width_; i++)
3722 if (bits_match[i].wire &&
3723 bits_match[i].wire == pattern_chunk.wire &&
3724 bits_match[i].offset >= pattern_chunk.offset &&
3725 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3726 ret.append(bits_other[i]);
3727 } else {
3728 for (int i = 0; i < width_; i++)
3729 if (bits_match[i].wire &&
3730 bits_match[i].wire == pattern_chunk.wire &&
3731 bits_match[i].offset >= pattern_chunk.offset &&
3732 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3733 ret.append(bits_match[i]);
3734 }
3735 }
3736
3737 ret.check();
3738 return ret;
3739 }
3740
3741 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3742 {
3743 if (other)
3744 cover("kernel.rtlil.sigspec.extract_other");
3745 else
3746 cover("kernel.rtlil.sigspec.extract");
3747
3748 log_assert(other == NULL || width_ == other->width_);
3749
3750 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3751 RTLIL::SigSpec ret;
3752
3753 if (other) {
3754 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3755 for (int i = 0; i < width_; i++)
3756 if (bits_match[i].wire && pattern.count(bits_match[i]))
3757 ret.append(bits_other[i]);
3758 } else {
3759 for (int i = 0; i < width_; i++)
3760 if (bits_match[i].wire && pattern.count(bits_match[i]))
3761 ret.append(bits_match[i]);
3762 }
3763
3764 ret.check();
3765 return ret;
3766 }
3767
3768 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3769 {
3770 cover("kernel.rtlil.sigspec.replace_pos");
3771
3772 unpack();
3773 with.unpack();
3774
3775 log_assert(offset >= 0);
3776 log_assert(with.width_ >= 0);
3777 log_assert(offset+with.width_ <= width_);
3778
3779 for (int i = 0; i < with.width_; i++)
3780 bits_.at(offset + i) = with.bits_.at(i);
3781
3782 check();
3783 }
3784
3785 void RTLIL::SigSpec::remove_const()
3786 {
3787 if (packed())
3788 {
3789 cover("kernel.rtlil.sigspec.remove_const.packed");
3790
3791 std::vector<RTLIL::SigChunk> new_chunks;
3792 new_chunks.reserve(GetSize(chunks_));
3793
3794 width_ = 0;
3795 for (auto &chunk : chunks_)
3796 if (chunk.wire != NULL) {
3797 new_chunks.push_back(chunk);
3798 width_ += chunk.width;
3799 }
3800
3801 chunks_.swap(new_chunks);
3802 }
3803 else
3804 {
3805 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3806
3807 std::vector<RTLIL::SigBit> new_bits;
3808 new_bits.reserve(width_);
3809
3810 for (auto &bit : bits_)
3811 if (bit.wire != NULL)
3812 new_bits.push_back(bit);
3813
3814 bits_.swap(new_bits);
3815 width_ = bits_.size();
3816 }
3817
3818 check();
3819 }
3820
3821 void RTLIL::SigSpec::remove(int offset, int length)
3822 {
3823 cover("kernel.rtlil.sigspec.remove_pos");
3824
3825 unpack();
3826
3827 log_assert(offset >= 0);
3828 log_assert(length >= 0);
3829 log_assert(offset + length <= width_);
3830
3831 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3832 width_ = bits_.size();
3833
3834 check();
3835 }
3836
3837 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3838 {
3839 unpack();
3840 cover("kernel.rtlil.sigspec.extract_pos");
3841 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3842 }
3843
3844 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3845 {
3846 if (signal.width_ == 0)
3847 return;
3848
3849 if (width_ == 0) {
3850 *this = signal;
3851 return;
3852 }
3853
3854 cover("kernel.rtlil.sigspec.append");
3855
3856 if (packed() != signal.packed()) {
3857 pack();
3858 signal.pack();
3859 }
3860
3861 if (packed())
3862 for (auto &other_c : signal.chunks_)
3863 {
3864 auto &my_last_c = chunks_.back();
3865 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3866 auto &this_data = my_last_c.data;
3867 auto &other_data = other_c.data;
3868 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3869 my_last_c.width += other_c.width;
3870 } else
3871 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3872 my_last_c.width += other_c.width;
3873 } else
3874 chunks_.push_back(other_c);
3875 }
3876 else
3877 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3878
3879 width_ += signal.width_;
3880 check();
3881 }
3882
3883 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3884 {
3885 if (packed())
3886 {
3887 cover("kernel.rtlil.sigspec.append_bit.packed");
3888
3889 if (chunks_.size() == 0)
3890 chunks_.push_back(bit);
3891 else
3892 if (bit.wire == NULL)
3893 if (chunks_.back().wire == NULL) {
3894 chunks_.back().data.push_back(bit.data);
3895 chunks_.back().width++;
3896 } else
3897 chunks_.push_back(bit);
3898 else
3899 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3900 chunks_.back().width++;
3901 else
3902 chunks_.push_back(bit);
3903 }
3904 else
3905 {
3906 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3907 bits_.push_back(bit);
3908 }
3909
3910 width_++;
3911 check();
3912 }
3913
3914 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3915 {
3916 cover("kernel.rtlil.sigspec.extend_u0");
3917
3918 pack();
3919
3920 if (width_ > width)
3921 remove(width, width_ - width);
3922
3923 if (width_ < width) {
3924 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3925 if (!is_signed)
3926 padding = RTLIL::State::S0;
3927 while (width_ < width)
3928 append(padding);
3929 }
3930
3931 }
3932
3933 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3934 {
3935 cover("kernel.rtlil.sigspec.repeat");
3936
3937 RTLIL::SigSpec sig;
3938 for (int i = 0; i < num; i++)
3939 sig.append(*this);
3940 return sig;
3941 }
3942
3943 #ifndef NDEBUG
3944 void RTLIL::SigSpec::check() const
3945 {
3946 if (width_ > 64)
3947 {
3948 cover("kernel.rtlil.sigspec.check.skip");
3949 }
3950 else if (packed())
3951 {
3952 cover("kernel.rtlil.sigspec.check.packed");
3953
3954 int w = 0;
3955 for (size_t i = 0; i < chunks_.size(); i++) {
3956 const RTLIL::SigChunk &chunk = chunks_[i];
3957 if (chunk.wire == NULL) {
3958 if (i > 0)
3959 log_assert(chunks_[i-1].wire != NULL);
3960 log_assert(chunk.offset == 0);
3961 log_assert(chunk.data.size() == (size_t)chunk.width);
3962 } else {
3963 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3964 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3965 log_assert(chunk.offset >= 0);
3966 log_assert(chunk.width >= 0);
3967 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3968 log_assert(chunk.data.size() == 0);
3969 }
3970 w += chunk.width;
3971 }
3972 log_assert(w == width_);
3973 log_assert(bits_.empty());
3974 }
3975 else
3976 {
3977 cover("kernel.rtlil.sigspec.check.unpacked");
3978
3979 log_assert(width_ == GetSize(bits_));
3980 log_assert(chunks_.empty());
3981 }
3982 }
3983 #endif
3984
3985 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3986 {
3987 cover("kernel.rtlil.sigspec.comp_lt");
3988
3989 if (this == &other)
3990 return false;
3991
3992 if (width_ != other.width_)
3993 return width_ < other.width_;
3994
3995 pack();
3996 other.pack();
3997
3998 if (chunks_.size() != other.chunks_.size())
3999 return chunks_.size() < other.chunks_.size();
4000
4001 updhash();
4002 other.updhash();
4003
4004 if (hash_ != other.hash_)
4005 return hash_ < other.hash_;
4006
4007 for (size_t i = 0; i < chunks_.size(); i++)
4008 if (chunks_[i] != other.chunks_[i]) {
4009 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4010 return chunks_[i] < other.chunks_[i];
4011 }
4012
4013 cover("kernel.rtlil.sigspec.comp_lt.equal");
4014 return false;
4015 }
4016
4017 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
4018 {
4019 cover("kernel.rtlil.sigspec.comp_eq");
4020
4021 if (this == &other)
4022 return true;
4023
4024 if (width_ != other.width_)
4025 return false;
4026
4027 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4028 // since the RHS will contain one SigChunk of width 0 causing
4029 // the size check below to fail
4030 if (width_ == 0)
4031 return true;
4032
4033 pack();
4034 other.pack();
4035
4036 if (chunks_.size() != other.chunks_.size())
4037 return false;
4038
4039 updhash();
4040 other.updhash();
4041
4042 if (hash_ != other.hash_)
4043 return false;
4044
4045 for (size_t i = 0; i < chunks_.size(); i++)
4046 if (chunks_[i] != other.chunks_[i]) {
4047 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4048 return false;
4049 }
4050
4051 cover("kernel.rtlil.sigspec.comp_eq.equal");
4052 return true;
4053 }
4054
4055 bool RTLIL::SigSpec::is_wire() const
4056 {
4057 cover("kernel.rtlil.sigspec.is_wire");
4058
4059 pack();
4060 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
4061 }
4062
4063 bool RTLIL::SigSpec::is_chunk() const
4064 {
4065 cover("kernel.rtlil.sigspec.is_chunk");
4066
4067 pack();
4068 return GetSize(chunks_) == 1;
4069 }
4070
4071 bool RTLIL::SigSpec::is_fully_const() const
4072 {
4073 cover("kernel.rtlil.sigspec.is_fully_const");
4074
4075 pack();
4076 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4077 if (it->width > 0 && it->wire != NULL)
4078 return false;
4079 return true;
4080 }
4081
4082 bool RTLIL::SigSpec::is_fully_zero() const
4083 {
4084 cover("kernel.rtlil.sigspec.is_fully_zero");
4085
4086 pack();
4087 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4088 if (it->width > 0 && it->wire != NULL)
4089 return false;
4090 for (size_t i = 0; i < it->data.size(); i++)
4091 if (it->data[i] != RTLIL::State::S0)
4092 return false;
4093 }
4094 return true;
4095 }
4096
4097 bool RTLIL::SigSpec::is_fully_ones() const
4098 {
4099 cover("kernel.rtlil.sigspec.is_fully_ones");
4100
4101 pack();
4102 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4103 if (it->width > 0 && it->wire != NULL)
4104 return false;
4105 for (size_t i = 0; i < it->data.size(); i++)
4106 if (it->data[i] != RTLIL::State::S1)
4107 return false;
4108 }
4109 return true;
4110 }
4111
4112 bool RTLIL::SigSpec::is_fully_def() const
4113 {
4114 cover("kernel.rtlil.sigspec.is_fully_def");
4115
4116 pack();
4117 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4118 if (it->width > 0 && it->wire != NULL)
4119 return false;
4120 for (size_t i = 0; i < it->data.size(); i++)
4121 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
4122 return false;
4123 }
4124 return true;
4125 }
4126
4127 bool RTLIL::SigSpec::is_fully_undef() const
4128 {
4129 cover("kernel.rtlil.sigspec.is_fully_undef");
4130
4131 pack();
4132 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4133 if (it->width > 0 && it->wire != NULL)
4134 return false;
4135 for (size_t i = 0; i < it->data.size(); i++)
4136 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
4137 return false;
4138 }
4139 return true;
4140 }
4141
4142 bool RTLIL::SigSpec::has_const() const
4143 {
4144 cover("kernel.rtlil.sigspec.has_const");
4145
4146 pack();
4147 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4148 if (it->width > 0 && it->wire == NULL)
4149 return true;
4150 return false;
4151 }
4152
4153 bool RTLIL::SigSpec::has_marked_bits() const
4154 {
4155 cover("kernel.rtlil.sigspec.has_marked_bits");
4156
4157 pack();
4158 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4159 if (it->width > 0 && it->wire == NULL) {
4160 for (size_t i = 0; i < it->data.size(); i++)
4161 if (it->data[i] == RTLIL::State::Sm)
4162 return true;
4163 }
4164 return false;
4165 }
4166
4167 bool RTLIL::SigSpec::as_bool() const
4168 {
4169 cover("kernel.rtlil.sigspec.as_bool");
4170
4171 pack();
4172 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4173 if (width_)
4174 return RTLIL::Const(chunks_[0].data).as_bool();
4175 return false;
4176 }
4177
4178 int RTLIL::SigSpec::as_int(bool is_signed) const
4179 {
4180 cover("kernel.rtlil.sigspec.as_int");
4181
4182 pack();
4183 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4184 if (width_)
4185 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
4186 return 0;
4187 }
4188
4189 std::string RTLIL::SigSpec::as_string() const
4190 {
4191 cover("kernel.rtlil.sigspec.as_string");
4192
4193 pack();
4194 std::string str;
4195 str.reserve(size());
4196 for (size_t i = chunks_.size(); i > 0; i--) {
4197 const RTLIL::SigChunk &chunk = chunks_[i-1];
4198 if (chunk.wire != NULL)
4199 str.append(chunk.width, '?');
4200 else
4201 str += RTLIL::Const(chunk.data).as_string();
4202 }
4203 return str;
4204 }
4205
4206 RTLIL::Const RTLIL::SigSpec::as_const() const
4207 {
4208 cover("kernel.rtlil.sigspec.as_const");
4209
4210 pack();
4211 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4212 if (width_)
4213 return chunks_[0].data;
4214 return RTLIL::Const();
4215 }
4216
4217 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
4218 {
4219 cover("kernel.rtlil.sigspec.as_wire");
4220
4221 pack();
4222 log_assert(is_wire());
4223 return chunks_[0].wire;
4224 }
4225
4226 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
4227 {
4228 cover("kernel.rtlil.sigspec.as_chunk");
4229
4230 pack();
4231 log_assert(is_chunk());
4232 return chunks_[0];
4233 }
4234
4235 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
4236 {
4237 cover("kernel.rtlil.sigspec.as_bit");
4238
4239 log_assert(width_ == 1);
4240 if (packed())
4241 return RTLIL::SigBit(*chunks_.begin());
4242 else
4243 return bits_[0];
4244 }
4245
4246 bool RTLIL::SigSpec::match(const char* pattern) const
4247 {
4248 cover("kernel.rtlil.sigspec.match");
4249
4250 unpack();
4251 log_assert(int(strlen(pattern)) == GetSize(bits_));
4252
4253 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
4254 if (*pattern == ' ')
4255 continue;
4256 if (*pattern == '*') {
4257 if (*it != State::Sz && *it != State::Sx)
4258 return false;
4259 continue;
4260 }
4261 if (*pattern == '0') {
4262 if (*it != State::S0)
4263 return false;
4264 } else
4265 if (*pattern == '1') {
4266 if (*it != State::S1)
4267 return false;
4268 } else
4269 log_abort();
4270 }
4271
4272 return true;
4273 }
4274
4275 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
4276 {
4277 cover("kernel.rtlil.sigspec.to_sigbit_set");
4278
4279 pack();
4280 std::set<RTLIL::SigBit> sigbits;
4281 for (auto &c : chunks_)
4282 for (int i = 0; i < c.width; i++)
4283 sigbits.insert(RTLIL::SigBit(c, i));
4284 return sigbits;
4285 }
4286
4287 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
4288 {
4289 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4290
4291 pack();
4292 pool<RTLIL::SigBit> sigbits;
4293 sigbits.reserve(size());
4294 for (auto &c : chunks_)
4295 for (int i = 0; i < c.width; i++)
4296 sigbits.insert(RTLIL::SigBit(c, i));
4297 return sigbits;
4298 }
4299
4300 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
4301 {
4302 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4303
4304 unpack();
4305 return bits_;
4306 }
4307
4308 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
4309 {
4310 cover("kernel.rtlil.sigspec.to_sigbit_map");
4311
4312 unpack();
4313 other.unpack();
4314
4315 log_assert(width_ == other.width_);
4316
4317 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
4318 for (int i = 0; i < width_; i++)
4319 new_map[bits_[i]] = other.bits_[i];
4320
4321 return new_map;
4322 }
4323
4324 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
4325 {
4326 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4327
4328 unpack();
4329 other.unpack();
4330
4331 log_assert(width_ == other.width_);
4332
4333 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
4334 new_map.reserve(size());
4335 for (int i = 0; i < width_; i++)
4336 new_map[bits_[i]] = other.bits_[i];
4337
4338 return new_map;
4339 }
4340
4341 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
4342 {
4343 size_t start = 0, end = 0;
4344 while ((end = text.find(sep, start)) != std::string::npos) {
4345 tokens.push_back(text.substr(start, end - start));
4346 start = end + 1;
4347 }
4348 tokens.push_back(text.substr(start));
4349 }
4350
4351 static int sigspec_parse_get_dummy_line_num()
4352 {
4353 return 0;
4354 }
4355
4356 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4357 {
4358 cover("kernel.rtlil.sigspec.parse");
4359
4360 AST::current_filename = "input";
4361
4362 std::vector<std::string> tokens;
4363 sigspec_parse_split(tokens, str, ',');
4364
4365 sig = RTLIL::SigSpec();
4366 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
4367 {
4368 std::string netname = tokens[tokidx];
4369 std::string indices;
4370
4371 if (netname.size() == 0)
4372 continue;
4373
4374 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4375 cover("kernel.rtlil.sigspec.parse.const");
4376 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4377 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4378 if (ast == NULL)
4379 return false;
4380 sig.append(RTLIL::Const(ast->bits));
4381 delete ast;
4382 continue;
4383 }
4384
4385 if (module == NULL)
4386 return false;
4387
4388 cover("kernel.rtlil.sigspec.parse.net");
4389
4390 if (netname[0] != '$' && netname[0] != '\\')
4391 netname = "\\" + netname;
4392
4393 if (module->wires_.count(netname) == 0) {
4394 size_t indices_pos = netname.size()-1;
4395 if (indices_pos > 2 && netname[indices_pos] == ']')
4396 {
4397 indices_pos--;
4398 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4399 if (indices_pos > 0 && netname[indices_pos] == ':') {
4400 indices_pos--;
4401 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4402 }
4403 if (indices_pos > 0 && netname[indices_pos] == '[') {
4404 indices = netname.substr(indices_pos);
4405 netname = netname.substr(0, indices_pos);
4406 }
4407 }
4408 }
4409
4410 if (module->wires_.count(netname) == 0)
4411 return false;
4412
4413 RTLIL::Wire *wire = module->wires_.at(netname);
4414 if (!indices.empty()) {
4415 std::vector<std::string> index_tokens;
4416 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4417 if (index_tokens.size() == 1) {
4418 cover("kernel.rtlil.sigspec.parse.bit_sel");
4419 int a = atoi(index_tokens.at(0).c_str());
4420 if (a < 0 || a >= wire->width)
4421 return false;
4422 sig.append(RTLIL::SigSpec(wire, a));
4423 } else {
4424 cover("kernel.rtlil.sigspec.parse.part_sel");
4425 int a = atoi(index_tokens.at(0).c_str());
4426 int b = atoi(index_tokens.at(1).c_str());
4427 if (a > b) {
4428 int tmp = a;
4429 a = b, b = tmp;
4430 }
4431 if (a < 0 || a >= wire->width)
4432 return false;
4433 if (b < 0 || b >= wire->width)
4434 return false;
4435 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4436 }
4437 } else
4438 sig.append(wire);
4439 }
4440
4441 return true;
4442 }
4443
4444 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4445 {
4446 if (str.empty() || str[0] != '@')
4447 return parse(sig, module, str);
4448
4449 cover("kernel.rtlil.sigspec.parse.sel");
4450
4451 str = RTLIL::escape_id(str.substr(1));
4452 if (design->selection_vars.count(str) == 0)
4453 return false;
4454
4455 sig = RTLIL::SigSpec();
4456 RTLIL::Selection &sel = design->selection_vars.at(str);
4457 for (auto &it : module->wires_)
4458 if (sel.selected_member(module->name, it.first))
4459 sig.append(it.second);
4460
4461 return true;
4462 }
4463
4464 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4465 {
4466 if (str == "0") {
4467 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4468 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4469 return true;
4470 }
4471
4472 if (str == "~0") {
4473 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4474 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4475 return true;
4476 }
4477
4478 if (lhs.chunks_.size() == 1) {
4479 char *p = (char*)str.c_str(), *endptr;
4480 long int val = strtol(p, &endptr, 10);
4481 if (endptr && endptr != p && *endptr == 0) {
4482 sig = RTLIL::SigSpec(val, lhs.width_);
4483 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4484 return true;
4485 }
4486 }
4487
4488 return parse(sig, module, str);
4489 }
4490
4491 RTLIL::CaseRule::~CaseRule()
4492 {
4493 for (auto it = switches.begin(); it != switches.end(); it++)
4494 delete *it;
4495 }
4496
4497 bool RTLIL::CaseRule::empty() const
4498 {
4499 return actions.empty() && switches.empty();
4500 }
4501
4502 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4503 {
4504 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4505 new_caserule->compare = compare;
4506 new_caserule->actions = actions;
4507 for (auto &it : switches)
4508 new_caserule->switches.push_back(it->clone());
4509 return new_caserule;
4510 }
4511
4512 RTLIL::SwitchRule::~SwitchRule()
4513 {
4514 for (auto it = cases.begin(); it != cases.end(); it++)
4515 delete *it;
4516 }
4517
4518 bool RTLIL::SwitchRule::empty() const
4519 {
4520 return cases.empty();
4521 }
4522
4523 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4524 {
4525 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4526 new_switchrule->signal = signal;
4527 new_switchrule->attributes = attributes;
4528 for (auto &it : cases)
4529 new_switchrule->cases.push_back(it->clone());
4530 return new_switchrule;
4531
4532 }
4533
4534 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4535 {
4536 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4537 new_syncrule->type = type;
4538 new_syncrule->signal = signal;
4539 new_syncrule->actions = actions;
4540 return new_syncrule;
4541 }
4542
4543 RTLIL::Process::~Process()
4544 {
4545 for (auto it = syncs.begin(); it != syncs.end(); it++)
4546 delete *it;
4547 }
4548
4549 RTLIL::Process *RTLIL::Process::clone() const
4550 {
4551 RTLIL::Process *new_proc = new RTLIL::Process;
4552
4553 new_proc->name = name;
4554 new_proc->attributes = attributes;
4555
4556 RTLIL::CaseRule *rc_ptr = root_case.clone();
4557 new_proc->root_case = *rc_ptr;
4558 rc_ptr->switches.clear();
4559 delete rc_ptr;
4560
4561 for (auto &it : syncs)
4562 new_proc->syncs.push_back(it->clone());
4563
4564 return new_proc;
4565 }
4566
4567 #ifdef WITH_PYTHON
4568 RTLIL::Memory::~Memory()
4569 {
4570 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4571 }
4572 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4573 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4574 {
4575 return &all_memorys;
4576 }
4577 #endif
4578 YOSYS_NAMESPACE_END