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Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/binding.h"
24 #include "frontends/verilog/verilog_frontend.h"
25 #include "frontends/verilog/preproc.h"
26 #include "backends/rtlil/rtlil_backend.h"
27
28 #include <string.h>
29 #include <algorithm>
30
31 YOSYS_NAMESPACE_BEGIN
32
33 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
34 std::vector<char*> RTLIL::IdString::global_id_storage_;
35 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
36 #ifndef YOSYS_NO_IDS_REFCNT
37 std::vector<int> RTLIL::IdString::global_refcount_storage_;
38 std::vector<int> RTLIL::IdString::global_free_idx_list_;
39 #endif
40 #ifdef YOSYS_USE_STICKY_IDS
41 int RTLIL::IdString::last_created_idx_[8];
42 int RTLIL::IdString::last_created_idx_ptr_;
43 #endif
44
45 #define X(_id) IdString RTLIL::ID::_id;
46 #include "kernel/constids.inc"
47 #undef X
48
49 dict<std::string, std::string> RTLIL::constpad;
50
51 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
52 static const pool<IdString> res = {
53 ID($sr),
54 ID($ff),
55 ID($dff),
56 ID($dffe),
57 ID($dffsr),
58 ID($dffsre),
59 ID($adff),
60 ID($adffe),
61 ID($aldff),
62 ID($aldffe),
63 ID($sdff),
64 ID($sdffe),
65 ID($sdffce),
66 ID($dlatch),
67 ID($adlatch),
68 ID($dlatchsr),
69 ID($_DFFE_NN_),
70 ID($_DFFE_NP_),
71 ID($_DFFE_PN_),
72 ID($_DFFE_PP_),
73 ID($_DFFSR_NNN_),
74 ID($_DFFSR_NNP_),
75 ID($_DFFSR_NPN_),
76 ID($_DFFSR_NPP_),
77 ID($_DFFSR_PNN_),
78 ID($_DFFSR_PNP_),
79 ID($_DFFSR_PPN_),
80 ID($_DFFSR_PPP_),
81 ID($_DFFSRE_NNNN_),
82 ID($_DFFSRE_NNNP_),
83 ID($_DFFSRE_NNPN_),
84 ID($_DFFSRE_NNPP_),
85 ID($_DFFSRE_NPNN_),
86 ID($_DFFSRE_NPNP_),
87 ID($_DFFSRE_NPPN_),
88 ID($_DFFSRE_NPPP_),
89 ID($_DFFSRE_PNNN_),
90 ID($_DFFSRE_PNNP_),
91 ID($_DFFSRE_PNPN_),
92 ID($_DFFSRE_PNPP_),
93 ID($_DFFSRE_PPNN_),
94 ID($_DFFSRE_PPNP_),
95 ID($_DFFSRE_PPPN_),
96 ID($_DFFSRE_PPPP_),
97 ID($_DFF_N_),
98 ID($_DFF_P_),
99 ID($_DFF_NN0_),
100 ID($_DFF_NN1_),
101 ID($_DFF_NP0_),
102 ID($_DFF_NP1_),
103 ID($_DFF_PN0_),
104 ID($_DFF_PN1_),
105 ID($_DFF_PP0_),
106 ID($_DFF_PP1_),
107 ID($_DFFE_NN0N_),
108 ID($_DFFE_NN0P_),
109 ID($_DFFE_NN1N_),
110 ID($_DFFE_NN1P_),
111 ID($_DFFE_NP0N_),
112 ID($_DFFE_NP0P_),
113 ID($_DFFE_NP1N_),
114 ID($_DFFE_NP1P_),
115 ID($_DFFE_PN0N_),
116 ID($_DFFE_PN0P_),
117 ID($_DFFE_PN1N_),
118 ID($_DFFE_PN1P_),
119 ID($_DFFE_PP0N_),
120 ID($_DFFE_PP0P_),
121 ID($_DFFE_PP1N_),
122 ID($_DFFE_PP1P_),
123 ID($_ALDFF_NN_),
124 ID($_ALDFF_NP_),
125 ID($_ALDFF_PN_),
126 ID($_ALDFF_PP_),
127 ID($_ALDFFE_NNN_),
128 ID($_ALDFFE_NNP_),
129 ID($_ALDFFE_NPN_),
130 ID($_ALDFFE_NPP_),
131 ID($_ALDFFE_PNN_),
132 ID($_ALDFFE_PNP_),
133 ID($_ALDFFE_PPN_),
134 ID($_ALDFFE_PPP_),
135 ID($_SDFF_NN0_),
136 ID($_SDFF_NN1_),
137 ID($_SDFF_NP0_),
138 ID($_SDFF_NP1_),
139 ID($_SDFF_PN0_),
140 ID($_SDFF_PN1_),
141 ID($_SDFF_PP0_),
142 ID($_SDFF_PP1_),
143 ID($_SDFFE_NN0N_),
144 ID($_SDFFE_NN0P_),
145 ID($_SDFFE_NN1N_),
146 ID($_SDFFE_NN1P_),
147 ID($_SDFFE_NP0N_),
148 ID($_SDFFE_NP0P_),
149 ID($_SDFFE_NP1N_),
150 ID($_SDFFE_NP1P_),
151 ID($_SDFFE_PN0N_),
152 ID($_SDFFE_PN0P_),
153 ID($_SDFFE_PN1N_),
154 ID($_SDFFE_PN1P_),
155 ID($_SDFFE_PP0N_),
156 ID($_SDFFE_PP0P_),
157 ID($_SDFFE_PP1N_),
158 ID($_SDFFE_PP1P_),
159 ID($_SDFFCE_NN0N_),
160 ID($_SDFFCE_NN0P_),
161 ID($_SDFFCE_NN1N_),
162 ID($_SDFFCE_NN1P_),
163 ID($_SDFFCE_NP0N_),
164 ID($_SDFFCE_NP0P_),
165 ID($_SDFFCE_NP1N_),
166 ID($_SDFFCE_NP1P_),
167 ID($_SDFFCE_PN0N_),
168 ID($_SDFFCE_PN0P_),
169 ID($_SDFFCE_PN1N_),
170 ID($_SDFFCE_PN1P_),
171 ID($_SDFFCE_PP0N_),
172 ID($_SDFFCE_PP0P_),
173 ID($_SDFFCE_PP1N_),
174 ID($_SDFFCE_PP1P_),
175 ID($_SR_NN_),
176 ID($_SR_NP_),
177 ID($_SR_PN_),
178 ID($_SR_PP_),
179 ID($_DLATCH_N_),
180 ID($_DLATCH_P_),
181 ID($_DLATCH_NN0_),
182 ID($_DLATCH_NN1_),
183 ID($_DLATCH_NP0_),
184 ID($_DLATCH_NP1_),
185 ID($_DLATCH_PN0_),
186 ID($_DLATCH_PN1_),
187 ID($_DLATCH_PP0_),
188 ID($_DLATCH_PP1_),
189 ID($_DLATCHSR_NNN_),
190 ID($_DLATCHSR_NNP_),
191 ID($_DLATCHSR_NPN_),
192 ID($_DLATCHSR_NPP_),
193 ID($_DLATCHSR_PNN_),
194 ID($_DLATCHSR_PNP_),
195 ID($_DLATCHSR_PPN_),
196 ID($_DLATCHSR_PPP_),
197 ID($_FF_),
198 };
199 return res;
200 }
201
202 RTLIL::Const::Const()
203 {
204 flags = RTLIL::CONST_FLAG_NONE;
205 }
206
207 RTLIL::Const::Const(std::string str)
208 {
209 flags = RTLIL::CONST_FLAG_STRING;
210 bits.reserve(str.size() * 8);
211 for (int i = str.size()-1; i >= 0; i--) {
212 unsigned char ch = str[i];
213 for (int j = 0; j < 8; j++) {
214 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
215 ch = ch >> 1;
216 }
217 }
218 }
219
220 RTLIL::Const::Const(int val, int width)
221 {
222 flags = RTLIL::CONST_FLAG_NONE;
223 bits.reserve(width);
224 for (int i = 0; i < width; i++) {
225 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
226 val = val >> 1;
227 }
228 }
229
230 RTLIL::Const::Const(RTLIL::State bit, int width)
231 {
232 flags = RTLIL::CONST_FLAG_NONE;
233 bits.reserve(width);
234 for (int i = 0; i < width; i++)
235 bits.push_back(bit);
236 }
237
238 RTLIL::Const::Const(const std::vector<bool> &bits)
239 {
240 flags = RTLIL::CONST_FLAG_NONE;
241 this->bits.reserve(bits.size());
242 for (const auto &b : bits)
243 this->bits.emplace_back(b ? State::S1 : State::S0);
244 }
245
246 RTLIL::Const::Const(const RTLIL::Const &c)
247 {
248 flags = c.flags;
249 this->bits.reserve(c.size());
250 for (const auto &b : c.bits)
251 this->bits.push_back(b);
252 }
253
254 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
255 {
256 if (bits.size() != other.bits.size())
257 return bits.size() < other.bits.size();
258 for (size_t i = 0; i < bits.size(); i++)
259 if (bits[i] != other.bits[i])
260 return bits[i] < other.bits[i];
261 return false;
262 }
263
264 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
265 {
266 return bits == other.bits;
267 }
268
269 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
270 {
271 return bits != other.bits;
272 }
273
274 bool RTLIL::Const::as_bool() const
275 {
276 for (size_t i = 0; i < bits.size(); i++)
277 if (bits[i] == State::S1)
278 return true;
279 return false;
280 }
281
282 int RTLIL::Const::as_int(bool is_signed) const
283 {
284 int32_t ret = 0;
285 for (size_t i = 0; i < bits.size() && i < 32; i++)
286 if (bits[i] == State::S1)
287 ret |= 1 << i;
288 if (is_signed && bits.back() == State::S1)
289 for (size_t i = bits.size(); i < 32; i++)
290 ret |= 1 << i;
291 return ret;
292 }
293
294 std::string RTLIL::Const::as_string() const
295 {
296 std::string ret;
297 ret.reserve(bits.size());
298 for (size_t i = bits.size(); i > 0; i--)
299 switch (bits[i-1]) {
300 case S0: ret += "0"; break;
301 case S1: ret += "1"; break;
302 case Sx: ret += "x"; break;
303 case Sz: ret += "z"; break;
304 case Sa: ret += "-"; break;
305 case Sm: ret += "m"; break;
306 }
307 return ret;
308 }
309
310 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
311 {
312 Const c;
313 c.bits.reserve(str.size());
314 for (auto it = str.rbegin(); it != str.rend(); it++)
315 switch (*it) {
316 case '0': c.bits.push_back(State::S0); break;
317 case '1': c.bits.push_back(State::S1); break;
318 case 'x': c.bits.push_back(State::Sx); break;
319 case 'z': c.bits.push_back(State::Sz); break;
320 case 'm': c.bits.push_back(State::Sm); break;
321 default: c.bits.push_back(State::Sa);
322 }
323 return c;
324 }
325
326 std::string RTLIL::Const::decode_string() const
327 {
328 std::string string;
329 string.reserve(GetSize(bits)/8);
330 for (int i = 0; i < GetSize(bits); i += 8) {
331 char ch = 0;
332 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
333 if (bits[i + j] == RTLIL::State::S1)
334 ch |= 1 << j;
335 if (ch != 0)
336 string.append({ch});
337 }
338 std::reverse(string.begin(), string.end());
339 return string;
340 }
341
342 bool RTLIL::Const::is_fully_zero() const
343 {
344 cover("kernel.rtlil.const.is_fully_zero");
345
346 for (const auto &bit : bits)
347 if (bit != RTLIL::State::S0)
348 return false;
349
350 return true;
351 }
352
353 bool RTLIL::Const::is_fully_ones() const
354 {
355 cover("kernel.rtlil.const.is_fully_ones");
356
357 for (const auto &bit : bits)
358 if (bit != RTLIL::State::S1)
359 return false;
360
361 return true;
362 }
363
364 bool RTLIL::Const::is_fully_def() const
365 {
366 cover("kernel.rtlil.const.is_fully_def");
367
368 for (const auto &bit : bits)
369 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
370 return false;
371
372 return true;
373 }
374
375 bool RTLIL::Const::is_fully_undef() const
376 {
377 cover("kernel.rtlil.const.is_fully_undef");
378
379 for (const auto &bit : bits)
380 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
381 return false;
382
383 return true;
384 }
385
386 bool RTLIL::Const::is_onehot(int *pos) const
387 {
388 cover("kernel.rtlil.const.is_onehot");
389
390 bool found = false;
391 for (int i = 0; i < GetSize(*this); i++) {
392 auto &bit = bits[i];
393 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
394 return false;
395 if (bit == RTLIL::State::S1) {
396 if (found)
397 return false;
398 if (pos)
399 *pos = i;
400 found = true;
401 }
402 }
403 return found;
404 }
405
406 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
407 {
408 return attributes.count(id);
409 }
410
411 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
412 {
413 if (value)
414 attributes[id] = RTLIL::Const(1);
415 else
416 attributes.erase(id);
417 }
418
419 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
420 {
421 const auto it = attributes.find(id);
422 if (it == attributes.end())
423 return false;
424 return it->second.as_bool();
425 }
426
427 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
428 {
429 if (value.empty())
430 attributes.erase(id);
431 else
432 attributes[id] = value;
433 }
434
435 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
436 {
437 std::string value;
438 const auto it = attributes.find(id);
439 if (it != attributes.end())
440 value = it->second.decode_string();
441 return value;
442 }
443
444 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
445 {
446 string attrval;
447 for (const auto &s : data) {
448 if (!attrval.empty())
449 attrval += "|";
450 attrval += s;
451 }
452 set_string_attribute(id, attrval);
453 }
454
455 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
456 {
457 pool<string> union_data = get_strpool_attribute(id);
458 union_data.insert(data.begin(), data.end());
459 if (!union_data.empty())
460 set_strpool_attribute(id, union_data);
461 }
462
463 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
464 {
465 pool<string> data;
466 if (attributes.count(id) != 0)
467 for (auto s : split_tokens(get_string_attribute(id), "|"))
468 data.insert(s);
469 return data;
470 }
471
472 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
473 {
474 string attrval;
475 for (const auto &ident : hierarchy) {
476 if (!attrval.empty())
477 attrval += " ";
478 attrval += ident;
479 }
480 set_string_attribute(ID::hdlname, attrval);
481 }
482
483 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
484 {
485 return split_tokens(get_string_attribute(ID::hdlname), " ");
486 }
487
488 void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector<int> &data)
489 {
490 std::stringstream attrval;
491 for (auto &i : data) {
492 if (attrval.tellp() > 0)
493 attrval << " ";
494 attrval << i;
495 }
496 attributes[id] = RTLIL::Const(attrval.str());
497 }
498
499 vector<int> RTLIL::AttrObject::get_intvec_attribute(RTLIL::IdString id) const
500 {
501 vector<int> data;
502 auto it = attributes.find(id);
503 if (it != attributes.end())
504 for (const auto &s : split_tokens(attributes.at(id).decode_string())) {
505 char *end = nullptr;
506 errno = 0;
507 long value = strtol(s.c_str(), &end, 10);
508 if (end != s.c_str() + s.size())
509 log_cmd_error("Literal for intvec attribute has invalid format");
510 if (errno == ERANGE || value < INT_MIN || value > INT_MAX)
511 log_cmd_error("Literal for intvec attribute is out of range");
512 data.push_back(value);
513 }
514 return data;
515 }
516
517 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
518 {
519 if (full_selection)
520 return true;
521 if (selected_modules.count(mod_name) > 0)
522 return true;
523 if (selected_members.count(mod_name) > 0)
524 return true;
525 return false;
526 }
527
528 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
529 {
530 if (full_selection)
531 return true;
532 if (selected_modules.count(mod_name) > 0)
533 return true;
534 return false;
535 }
536
537 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
538 {
539 if (full_selection)
540 return true;
541 if (selected_modules.count(mod_name) > 0)
542 return true;
543 if (selected_members.count(mod_name) > 0)
544 if (selected_members.at(mod_name).count(memb_name) > 0)
545 return true;
546 return false;
547 }
548
549 void RTLIL::Selection::optimize(RTLIL::Design *design)
550 {
551 if (full_selection) {
552 selected_modules.clear();
553 selected_members.clear();
554 return;
555 }
556
557 std::vector<RTLIL::IdString> del_list, add_list;
558
559 del_list.clear();
560 for (auto mod_name : selected_modules) {
561 if (design->modules_.count(mod_name) == 0)
562 del_list.push_back(mod_name);
563 selected_members.erase(mod_name);
564 }
565 for (auto mod_name : del_list)
566 selected_modules.erase(mod_name);
567
568 del_list.clear();
569 for (auto &it : selected_members)
570 if (design->modules_.count(it.first) == 0)
571 del_list.push_back(it.first);
572 for (auto mod_name : del_list)
573 selected_members.erase(mod_name);
574
575 for (auto &it : selected_members) {
576 del_list.clear();
577 for (auto memb_name : it.second)
578 if (design->modules_[it.first]->count_id(memb_name) == 0)
579 del_list.push_back(memb_name);
580 for (auto memb_name : del_list)
581 it.second.erase(memb_name);
582 }
583
584 del_list.clear();
585 add_list.clear();
586 for (auto &it : selected_members)
587 if (it.second.size() == 0)
588 del_list.push_back(it.first);
589 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
590 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
591 add_list.push_back(it.first);
592 for (auto mod_name : del_list)
593 selected_members.erase(mod_name);
594 for (auto mod_name : add_list) {
595 selected_members.erase(mod_name);
596 selected_modules.insert(mod_name);
597 }
598
599 if (selected_modules.size() == design->modules_.size()) {
600 full_selection = true;
601 selected_modules.clear();
602 selected_members.clear();
603 }
604 }
605
606 RTLIL::Design::Design()
607 : verilog_defines (new define_map_t)
608 {
609 static unsigned int hashidx_count = 123456789;
610 hashidx_count = mkhash_xorshift(hashidx_count);
611 hashidx_ = hashidx_count;
612
613 refcount_modules_ = 0;
614 selection_stack.push_back(RTLIL::Selection());
615
616 #ifdef WITH_PYTHON
617 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
618 #endif
619 }
620
621 RTLIL::Design::~Design()
622 {
623 for (auto &pr : modules_)
624 delete pr.second;
625 for (auto n : bindings_)
626 delete n;
627 for (auto n : verilog_packages)
628 delete n;
629 for (auto n : verilog_globals)
630 delete n;
631 #ifdef WITH_PYTHON
632 RTLIL::Design::get_all_designs()->erase(hashidx_);
633 #endif
634 }
635
636 #ifdef WITH_PYTHON
637 static std::map<unsigned int, RTLIL::Design*> all_designs;
638 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
639 {
640 return &all_designs;
641 }
642 #endif
643
644 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
645 {
646 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
647 }
648
649 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
650 {
651 return modules_.count(name) ? modules_.at(name) : NULL;
652 }
653
654 const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
655 {
656 return modules_.count(name) ? modules_.at(name) : NULL;
657 }
658
659 RTLIL::Module *RTLIL::Design::top_module()
660 {
661 RTLIL::Module *module = nullptr;
662 int module_count = 0;
663
664 for (auto mod : selected_modules()) {
665 if (mod->get_bool_attribute(ID::top))
666 return mod;
667 module_count++;
668 module = mod;
669 }
670
671 return module_count == 1 ? module : nullptr;
672 }
673
674 void RTLIL::Design::add(RTLIL::Module *module)
675 {
676 log_assert(modules_.count(module->name) == 0);
677 log_assert(refcount_modules_ == 0);
678 modules_[module->name] = module;
679 module->design = this;
680
681 for (auto mon : monitors)
682 mon->notify_module_add(module);
683
684 if (yosys_xtrace) {
685 log("#X# New Module: %s\n", log_id(module));
686 log_backtrace("-X- ", yosys_xtrace-1);
687 }
688 }
689
690 void RTLIL::Design::add(RTLIL::Binding *binding)
691 {
692 log_assert(binding != nullptr);
693 bindings_.push_back(binding);
694 }
695
696 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
697 {
698 if (modules_.count(name) != 0)
699 log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str());
700 log_assert(refcount_modules_ == 0);
701
702 RTLIL::Module *module = new RTLIL::Module;
703 modules_[name] = module;
704 module->design = this;
705 module->name = name;
706
707 for (auto mon : monitors)
708 mon->notify_module_add(module);
709
710 if (yosys_xtrace) {
711 log("#X# New Module: %s\n", log_id(module));
712 log_backtrace("-X- ", yosys_xtrace-1);
713 }
714
715 return module;
716 }
717
718 void RTLIL::Design::scratchpad_unset(const std::string &varname)
719 {
720 scratchpad.erase(varname);
721 }
722
723 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
724 {
725 scratchpad[varname] = stringf("%d", value);
726 }
727
728 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
729 {
730 scratchpad[varname] = value ? "true" : "false";
731 }
732
733 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
734 {
735 scratchpad[varname] = std::move(value);
736 }
737
738 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
739 {
740 auto it = scratchpad.find(varname);
741 if (it == scratchpad.end())
742 return default_value;
743
744 const std::string &str = it->second;
745
746 if (str == "0" || str == "false")
747 return 0;
748
749 if (str == "1" || str == "true")
750 return 1;
751
752 char *endptr = nullptr;
753 long int parsed_value = strtol(str.c_str(), &endptr, 10);
754 return *endptr ? default_value : parsed_value;
755 }
756
757 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
758 {
759 auto it = scratchpad.find(varname);
760 if (it == scratchpad.end())
761 return default_value;
762
763 const std::string &str = it->second;
764
765 if (str == "0" || str == "false")
766 return false;
767
768 if (str == "1" || str == "true")
769 return true;
770
771 return default_value;
772 }
773
774 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
775 {
776 auto it = scratchpad.find(varname);
777 if (it == scratchpad.end())
778 return default_value;
779
780 return it->second;
781 }
782
783 void RTLIL::Design::remove(RTLIL::Module *module)
784 {
785 for (auto mon : monitors)
786 mon->notify_module_del(module);
787
788 if (yosys_xtrace) {
789 log("#X# Remove Module: %s\n", log_id(module));
790 log_backtrace("-X- ", yosys_xtrace-1);
791 }
792
793 log_assert(modules_.at(module->name) == module);
794 log_assert(refcount_modules_ == 0);
795 modules_.erase(module->name);
796 delete module;
797 }
798
799 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
800 {
801 modules_.erase(module->name);
802 module->name = new_name;
803 add(module);
804 }
805
806 void RTLIL::Design::sort()
807 {
808 scratchpad.sort();
809 modules_.sort(sort_by_id_str());
810 for (auto &it : modules_)
811 it.second->sort();
812 }
813
814 void RTLIL::Design::check()
815 {
816 #ifndef NDEBUG
817 for (auto &it : modules_) {
818 log_assert(this == it.second->design);
819 log_assert(it.first == it.second->name);
820 log_assert(!it.first.empty());
821 it.second->check();
822 }
823 #endif
824 }
825
826 void RTLIL::Design::optimize()
827 {
828 for (auto &it : modules_)
829 it.second->optimize();
830 for (auto &it : selection_stack)
831 it.optimize(this);
832 for (auto &it : selection_vars)
833 it.second.optimize(this);
834 }
835
836 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
837 {
838 if (!selected_active_module.empty() && mod_name != selected_active_module)
839 return false;
840 if (selection_stack.size() == 0)
841 return true;
842 return selection_stack.back().selected_module(mod_name);
843 }
844
845 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
846 {
847 if (!selected_active_module.empty() && mod_name != selected_active_module)
848 return false;
849 if (selection_stack.size() == 0)
850 return true;
851 return selection_stack.back().selected_whole_module(mod_name);
852 }
853
854 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
855 {
856 if (!selected_active_module.empty() && mod_name != selected_active_module)
857 return false;
858 if (selection_stack.size() == 0)
859 return true;
860 return selection_stack.back().selected_member(mod_name, memb_name);
861 }
862
863 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
864 {
865 return selected_module(mod->name);
866 }
867
868 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
869 {
870 return selected_whole_module(mod->name);
871 }
872
873 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
874 {
875 std::vector<RTLIL::Module*> result;
876 result.reserve(modules_.size());
877 for (auto &it : modules_)
878 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
879 result.push_back(it.second);
880 return result;
881 }
882
883 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
884 {
885 std::vector<RTLIL::Module*> result;
886 result.reserve(modules_.size());
887 for (auto &it : modules_)
888 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
889 result.push_back(it.second);
890 return result;
891 }
892
893 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
894 {
895 std::vector<RTLIL::Module*> result;
896 result.reserve(modules_.size());
897 for (auto &it : modules_)
898 if (it.second->get_blackbox_attribute(include_wb))
899 continue;
900 else if (selected_whole_module(it.first))
901 result.push_back(it.second);
902 else if (selected_module(it.first))
903 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
904 return result;
905 }
906
907 RTLIL::Module::Module()
908 {
909 static unsigned int hashidx_count = 123456789;
910 hashidx_count = mkhash_xorshift(hashidx_count);
911 hashidx_ = hashidx_count;
912
913 design = nullptr;
914 refcount_wires_ = 0;
915 refcount_cells_ = 0;
916
917 #ifdef WITH_PYTHON
918 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
919 #endif
920 }
921
922 RTLIL::Module::~Module()
923 {
924 for (auto &pr : wires_)
925 delete pr.second;
926 for (auto &pr : memories)
927 delete pr.second;
928 for (auto &pr : cells_)
929 delete pr.second;
930 for (auto &pr : processes)
931 delete pr.second;
932 for (auto binding : bindings_)
933 delete binding;
934 #ifdef WITH_PYTHON
935 RTLIL::Module::get_all_modules()->erase(hashidx_);
936 #endif
937 }
938
939 #ifdef WITH_PYTHON
940 static std::map<unsigned int, RTLIL::Module*> all_modules;
941 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
942 {
943 return &all_modules;
944 }
945 #endif
946
947 void RTLIL::Module::makeblackbox()
948 {
949 pool<RTLIL::Wire*> delwires;
950
951 for (auto it = wires_.begin(); it != wires_.end(); ++it)
952 if (!it->second->port_input && !it->second->port_output)
953 delwires.insert(it->second);
954
955 for (auto it = memories.begin(); it != memories.end(); ++it)
956 delete it->second;
957 memories.clear();
958
959 for (auto it = cells_.begin(); it != cells_.end(); ++it)
960 delete it->second;
961 cells_.clear();
962
963 for (auto it = processes.begin(); it != processes.end(); ++it)
964 delete it->second;
965 processes.clear();
966
967 connections_.clear();
968
969 remove(delwires);
970 set_bool_attribute(ID::blackbox);
971 }
972
973 void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
974 {
975 log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name));
976 }
977
978 bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
979 {
980 return false;
981 }
982
983 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
984 {
985 if (mayfail)
986 return RTLIL::IdString();
987 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
988 }
989
990
991 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
992 {
993 if (mayfail)
994 return RTLIL::IdString();
995 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
996 }
997
998 size_t RTLIL::Module::count_id(RTLIL::IdString id)
999 {
1000 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
1001 }
1002
1003 #ifndef NDEBUG
1004 namespace {
1005 struct InternalCellChecker
1006 {
1007 RTLIL::Module *module;
1008 RTLIL::Cell *cell;
1009 pool<RTLIL::IdString> expected_params, expected_ports;
1010
1011 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
1012
1013 void error(int linenr)
1014 {
1015 std::stringstream buf;
1016 RTLIL_BACKEND::dump_cell(buf, " ", cell);
1017
1018 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
1019 module ? module->name.c_str() : "", module ? "." : "",
1020 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
1021 }
1022
1023 int param(RTLIL::IdString name)
1024 {
1025 auto it = cell->parameters.find(name);
1026 if (it == cell->parameters.end())
1027 error(__LINE__);
1028 expected_params.insert(name);
1029 return it->second.as_int();
1030 }
1031
1032 int param_bool(RTLIL::IdString name)
1033 {
1034 int v = param(name);
1035 if (GetSize(cell->parameters.at(name)) > 32)
1036 error(__LINE__);
1037 if (v != 0 && v != 1)
1038 error(__LINE__);
1039 return v;
1040 }
1041
1042 int param_bool(RTLIL::IdString name, bool expected)
1043 {
1044 int v = param_bool(name);
1045 if (v != expected)
1046 error(__LINE__);
1047 return v;
1048 }
1049
1050 void param_bits(RTLIL::IdString name, int width)
1051 {
1052 param(name);
1053 if (GetSize(cell->parameters.at(name).bits) != width)
1054 error(__LINE__);
1055 }
1056
1057 void port(RTLIL::IdString name, int width)
1058 {
1059 auto it = cell->connections_.find(name);
1060 if (it == cell->connections_.end())
1061 error(__LINE__);
1062 if (GetSize(it->second) != width)
1063 error(__LINE__);
1064 expected_ports.insert(name);
1065 }
1066
1067 void check_expected(bool check_matched_sign = false)
1068 {
1069 for (auto &para : cell->parameters)
1070 if (expected_params.count(para.first) == 0)
1071 error(__LINE__);
1072 for (auto &conn : cell->connections())
1073 if (expected_ports.count(conn.first) == 0)
1074 error(__LINE__);
1075
1076 if (check_matched_sign) {
1077 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
1078 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
1079 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
1080 if (a_is_signed != b_is_signed)
1081 error(__LINE__);
1082 }
1083 }
1084
1085 void check()
1086 {
1087 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
1088 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
1089 return;
1090
1091 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
1092 param_bool(ID::A_SIGNED);
1093 port(ID::A, param(ID::A_WIDTH));
1094 port(ID::Y, param(ID::Y_WIDTH));
1095 check_expected();
1096 return;
1097 }
1098
1099 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
1100 param_bool(ID::A_SIGNED);
1101 param_bool(ID::B_SIGNED);
1102 port(ID::A, param(ID::A_WIDTH));
1103 port(ID::B, param(ID::B_WIDTH));
1104 port(ID::Y, param(ID::Y_WIDTH));
1105 check_expected(true);
1106 return;
1107 }
1108
1109 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
1110 param_bool(ID::A_SIGNED);
1111 port(ID::A, param(ID::A_WIDTH));
1112 port(ID::Y, param(ID::Y_WIDTH));
1113 check_expected();
1114 return;
1115 }
1116
1117 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
1118 param_bool(ID::A_SIGNED);
1119 param_bool(ID::B_SIGNED, /*expected=*/false);
1120 port(ID::A, param(ID::A_WIDTH));
1121 port(ID::B, param(ID::B_WIDTH));
1122 port(ID::Y, param(ID::Y_WIDTH));
1123 check_expected(/*check_matched_sign=*/false);
1124 return;
1125 }
1126
1127 if (cell->type.in(ID($shift), ID($shiftx))) {
1128 if (cell->type == ID($shiftx)) {
1129 param_bool(ID::A_SIGNED, /*expected=*/false);
1130 } else {
1131 param_bool(ID::A_SIGNED);
1132 }
1133 param_bool(ID::B_SIGNED);
1134 port(ID::A, param(ID::A_WIDTH));
1135 port(ID::B, param(ID::B_WIDTH));
1136 port(ID::Y, param(ID::Y_WIDTH));
1137 check_expected(/*check_matched_sign=*/false);
1138 return;
1139 }
1140
1141 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
1142 param_bool(ID::A_SIGNED);
1143 param_bool(ID::B_SIGNED);
1144 port(ID::A, param(ID::A_WIDTH));
1145 port(ID::B, param(ID::B_WIDTH));
1146 port(ID::Y, param(ID::Y_WIDTH));
1147 check_expected(true);
1148 return;
1149 }
1150
1151 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
1152 param_bool(ID::A_SIGNED);
1153 param_bool(ID::B_SIGNED);
1154 port(ID::A, param(ID::A_WIDTH));
1155 port(ID::B, param(ID::B_WIDTH));
1156 port(ID::Y, param(ID::Y_WIDTH));
1157 check_expected(cell->type != ID($pow));
1158 return;
1159 }
1160
1161 if (cell->type == ID($fa)) {
1162 port(ID::A, param(ID::WIDTH));
1163 port(ID::B, param(ID::WIDTH));
1164 port(ID::C, param(ID::WIDTH));
1165 port(ID::X, param(ID::WIDTH));
1166 port(ID::Y, param(ID::WIDTH));
1167 check_expected();
1168 return;
1169 }
1170
1171 if (cell->type == ID($lcu)) {
1172 port(ID::P, param(ID::WIDTH));
1173 port(ID::G, param(ID::WIDTH));
1174 port(ID::CI, 1);
1175 port(ID::CO, param(ID::WIDTH));
1176 check_expected();
1177 return;
1178 }
1179
1180 if (cell->type == ID($alu)) {
1181 param_bool(ID::A_SIGNED);
1182 param_bool(ID::B_SIGNED);
1183 port(ID::A, param(ID::A_WIDTH));
1184 port(ID::B, param(ID::B_WIDTH));
1185 port(ID::CI, 1);
1186 port(ID::BI, 1);
1187 port(ID::X, param(ID::Y_WIDTH));
1188 port(ID::Y, param(ID::Y_WIDTH));
1189 port(ID::CO, param(ID::Y_WIDTH));
1190 check_expected(true);
1191 return;
1192 }
1193
1194 if (cell->type == ID($macc)) {
1195 param(ID::CONFIG);
1196 param(ID::CONFIG_WIDTH);
1197 port(ID::A, param(ID::A_WIDTH));
1198 port(ID::B, param(ID::B_WIDTH));
1199 port(ID::Y, param(ID::Y_WIDTH));
1200 check_expected();
1201 Macc().from_cell(cell);
1202 return;
1203 }
1204
1205 if (cell->type == ID($logic_not)) {
1206 param_bool(ID::A_SIGNED);
1207 port(ID::A, param(ID::A_WIDTH));
1208 port(ID::Y, param(ID::Y_WIDTH));
1209 check_expected();
1210 return;
1211 }
1212
1213 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1214 param_bool(ID::A_SIGNED);
1215 param_bool(ID::B_SIGNED);
1216 port(ID::A, param(ID::A_WIDTH));
1217 port(ID::B, param(ID::B_WIDTH));
1218 port(ID::Y, param(ID::Y_WIDTH));
1219 check_expected(/*check_matched_sign=*/false);
1220 return;
1221 }
1222
1223 if (cell->type == ID($slice)) {
1224 param(ID::OFFSET);
1225 port(ID::A, param(ID::A_WIDTH));
1226 port(ID::Y, param(ID::Y_WIDTH));
1227 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1228 error(__LINE__);
1229 check_expected();
1230 return;
1231 }
1232
1233 if (cell->type == ID($concat)) {
1234 port(ID::A, param(ID::A_WIDTH));
1235 port(ID::B, param(ID::B_WIDTH));
1236 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == ID($mux)) {
1242 port(ID::A, param(ID::WIDTH));
1243 port(ID::B, param(ID::WIDTH));
1244 port(ID::S, 1);
1245 port(ID::Y, param(ID::WIDTH));
1246 check_expected();
1247 return;
1248 }
1249
1250 if (cell->type == ID($pmux)) {
1251 port(ID::A, param(ID::WIDTH));
1252 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1253 port(ID::S, param(ID::S_WIDTH));
1254 port(ID::Y, param(ID::WIDTH));
1255 check_expected();
1256 return;
1257 }
1258
1259 if (cell->type == ID($bmux)) {
1260 port(ID::A, param(ID::WIDTH) << param(ID::S_WIDTH));
1261 port(ID::S, param(ID::S_WIDTH));
1262 port(ID::Y, param(ID::WIDTH));
1263 check_expected();
1264 return;
1265 }
1266
1267 if (cell->type == ID($demux)) {
1268 port(ID::A, param(ID::WIDTH));
1269 port(ID::S, param(ID::S_WIDTH));
1270 port(ID::Y, param(ID::WIDTH) << param(ID::S_WIDTH));
1271 check_expected();
1272 return;
1273 }
1274
1275 if (cell->type == ID($lut)) {
1276 param(ID::LUT);
1277 port(ID::A, param(ID::WIDTH));
1278 port(ID::Y, 1);
1279 check_expected();
1280 return;
1281 }
1282
1283 if (cell->type == ID($sop)) {
1284 param(ID::DEPTH);
1285 param(ID::TABLE);
1286 port(ID::A, param(ID::WIDTH));
1287 port(ID::Y, 1);
1288 check_expected();
1289 return;
1290 }
1291
1292 if (cell->type == ID($sr)) {
1293 param_bool(ID::SET_POLARITY);
1294 param_bool(ID::CLR_POLARITY);
1295 port(ID::SET, param(ID::WIDTH));
1296 port(ID::CLR, param(ID::WIDTH));
1297 port(ID::Q, param(ID::WIDTH));
1298 check_expected();
1299 return;
1300 }
1301
1302 if (cell->type == ID($ff)) {
1303 port(ID::D, param(ID::WIDTH));
1304 port(ID::Q, param(ID::WIDTH));
1305 check_expected();
1306 return;
1307 }
1308
1309 if (cell->type == ID($dff)) {
1310 param_bool(ID::CLK_POLARITY);
1311 port(ID::CLK, 1);
1312 port(ID::D, param(ID::WIDTH));
1313 port(ID::Q, param(ID::WIDTH));
1314 check_expected();
1315 return;
1316 }
1317
1318 if (cell->type == ID($dffe)) {
1319 param_bool(ID::CLK_POLARITY);
1320 param_bool(ID::EN_POLARITY);
1321 port(ID::CLK, 1);
1322 port(ID::EN, 1);
1323 port(ID::D, param(ID::WIDTH));
1324 port(ID::Q, param(ID::WIDTH));
1325 check_expected();
1326 return;
1327 }
1328
1329 if (cell->type == ID($dffsr)) {
1330 param_bool(ID::CLK_POLARITY);
1331 param_bool(ID::SET_POLARITY);
1332 param_bool(ID::CLR_POLARITY);
1333 port(ID::CLK, 1);
1334 port(ID::SET, param(ID::WIDTH));
1335 port(ID::CLR, param(ID::WIDTH));
1336 port(ID::D, param(ID::WIDTH));
1337 port(ID::Q, param(ID::WIDTH));
1338 check_expected();
1339 return;
1340 }
1341
1342 if (cell->type == ID($dffsre)) {
1343 param_bool(ID::CLK_POLARITY);
1344 param_bool(ID::SET_POLARITY);
1345 param_bool(ID::CLR_POLARITY);
1346 param_bool(ID::EN_POLARITY);
1347 port(ID::CLK, 1);
1348 port(ID::EN, 1);
1349 port(ID::SET, param(ID::WIDTH));
1350 port(ID::CLR, param(ID::WIDTH));
1351 port(ID::D, param(ID::WIDTH));
1352 port(ID::Q, param(ID::WIDTH));
1353 check_expected();
1354 return;
1355 }
1356
1357 if (cell->type == ID($adff)) {
1358 param_bool(ID::CLK_POLARITY);
1359 param_bool(ID::ARST_POLARITY);
1360 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1361 port(ID::CLK, 1);
1362 port(ID::ARST, 1);
1363 port(ID::D, param(ID::WIDTH));
1364 port(ID::Q, param(ID::WIDTH));
1365 check_expected();
1366 return;
1367 }
1368
1369 if (cell->type == ID($sdff)) {
1370 param_bool(ID::CLK_POLARITY);
1371 param_bool(ID::SRST_POLARITY);
1372 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1373 port(ID::CLK, 1);
1374 port(ID::SRST, 1);
1375 port(ID::D, param(ID::WIDTH));
1376 port(ID::Q, param(ID::WIDTH));
1377 check_expected();
1378 return;
1379 }
1380
1381 if (cell->type.in(ID($sdffe), ID($sdffce))) {
1382 param_bool(ID::CLK_POLARITY);
1383 param_bool(ID::EN_POLARITY);
1384 param_bool(ID::SRST_POLARITY);
1385 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1386 port(ID::CLK, 1);
1387 port(ID::EN, 1);
1388 port(ID::SRST, 1);
1389 port(ID::D, param(ID::WIDTH));
1390 port(ID::Q, param(ID::WIDTH));
1391 check_expected();
1392 return;
1393 }
1394
1395 if (cell->type == ID($adffe)) {
1396 param_bool(ID::CLK_POLARITY);
1397 param_bool(ID::EN_POLARITY);
1398 param_bool(ID::ARST_POLARITY);
1399 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1400 port(ID::CLK, 1);
1401 port(ID::EN, 1);
1402 port(ID::ARST, 1);
1403 port(ID::D, param(ID::WIDTH));
1404 port(ID::Q, param(ID::WIDTH));
1405 check_expected();
1406 return;
1407 }
1408
1409 if (cell->type == ID($aldff)) {
1410 param_bool(ID::CLK_POLARITY);
1411 param_bool(ID::ALOAD_POLARITY);
1412 port(ID::CLK, 1);
1413 port(ID::ALOAD, 1);
1414 port(ID::D, param(ID::WIDTH));
1415 port(ID::AD, param(ID::WIDTH));
1416 port(ID::Q, param(ID::WIDTH));
1417 check_expected();
1418 return;
1419 }
1420
1421 if (cell->type == ID($aldffe)) {
1422 param_bool(ID::CLK_POLARITY);
1423 param_bool(ID::EN_POLARITY);
1424 param_bool(ID::ALOAD_POLARITY);
1425 port(ID::CLK, 1);
1426 port(ID::EN, 1);
1427 port(ID::ALOAD, 1);
1428 port(ID::D, param(ID::WIDTH));
1429 port(ID::AD, param(ID::WIDTH));
1430 port(ID::Q, param(ID::WIDTH));
1431 check_expected();
1432 return;
1433 }
1434
1435 if (cell->type == ID($dlatch)) {
1436 param_bool(ID::EN_POLARITY);
1437 port(ID::EN, 1);
1438 port(ID::D, param(ID::WIDTH));
1439 port(ID::Q, param(ID::WIDTH));
1440 check_expected();
1441 return;
1442 }
1443
1444 if (cell->type == ID($adlatch)) {
1445 param_bool(ID::EN_POLARITY);
1446 param_bool(ID::ARST_POLARITY);
1447 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1448 port(ID::EN, 1);
1449 port(ID::ARST, 1);
1450 port(ID::D, param(ID::WIDTH));
1451 port(ID::Q, param(ID::WIDTH));
1452 check_expected();
1453 return;
1454 }
1455
1456 if (cell->type == ID($dlatchsr)) {
1457 param_bool(ID::EN_POLARITY);
1458 param_bool(ID::SET_POLARITY);
1459 param_bool(ID::CLR_POLARITY);
1460 port(ID::EN, 1);
1461 port(ID::SET, param(ID::WIDTH));
1462 port(ID::CLR, param(ID::WIDTH));
1463 port(ID::D, param(ID::WIDTH));
1464 port(ID::Q, param(ID::WIDTH));
1465 check_expected();
1466 return;
1467 }
1468
1469 if (cell->type == ID($fsm)) {
1470 param(ID::NAME);
1471 param_bool(ID::CLK_POLARITY);
1472 param_bool(ID::ARST_POLARITY);
1473 param(ID::STATE_BITS);
1474 param(ID::STATE_NUM);
1475 param(ID::STATE_NUM_LOG2);
1476 param(ID::STATE_RST);
1477 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1478 param(ID::TRANS_NUM);
1479 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1480 port(ID::CLK, 1);
1481 port(ID::ARST, 1);
1482 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1483 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1484 check_expected();
1485 return;
1486 }
1487
1488 if (cell->type == ID($memrd)) {
1489 param(ID::MEMID);
1490 param_bool(ID::CLK_ENABLE);
1491 param_bool(ID::CLK_POLARITY);
1492 param_bool(ID::TRANSPARENT);
1493 port(ID::CLK, 1);
1494 port(ID::EN, 1);
1495 port(ID::ADDR, param(ID::ABITS));
1496 port(ID::DATA, param(ID::WIDTH));
1497 check_expected();
1498 return;
1499 }
1500
1501 if (cell->type == ID($memrd_v2)) {
1502 param(ID::MEMID);
1503 param_bool(ID::CLK_ENABLE);
1504 param_bool(ID::CLK_POLARITY);
1505 param(ID::TRANSPARENCY_MASK);
1506 param(ID::COLLISION_X_MASK);
1507 param_bool(ID::CE_OVER_SRST);
1508 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1509 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1510 param_bits(ID::INIT_VALUE, param(ID::WIDTH));
1511 port(ID::CLK, 1);
1512 port(ID::EN, 1);
1513 port(ID::ARST, 1);
1514 port(ID::SRST, 1);
1515 port(ID::ADDR, param(ID::ABITS));
1516 port(ID::DATA, param(ID::WIDTH));
1517 check_expected();
1518 return;
1519 }
1520
1521 if (cell->type == ID($memwr)) {
1522 param(ID::MEMID);
1523 param_bool(ID::CLK_ENABLE);
1524 param_bool(ID::CLK_POLARITY);
1525 param(ID::PRIORITY);
1526 port(ID::CLK, 1);
1527 port(ID::EN, param(ID::WIDTH));
1528 port(ID::ADDR, param(ID::ABITS));
1529 port(ID::DATA, param(ID::WIDTH));
1530 check_expected();
1531 return;
1532 }
1533
1534 if (cell->type == ID($memwr_v2)) {
1535 param(ID::MEMID);
1536 param_bool(ID::CLK_ENABLE);
1537 param_bool(ID::CLK_POLARITY);
1538 param(ID::PORTID);
1539 param(ID::PRIORITY_MASK);
1540 port(ID::CLK, 1);
1541 port(ID::EN, param(ID::WIDTH));
1542 port(ID::ADDR, param(ID::ABITS));
1543 port(ID::DATA, param(ID::WIDTH));
1544 check_expected();
1545 return;
1546 }
1547
1548 if (cell->type == ID($meminit)) {
1549 param(ID::MEMID);
1550 param(ID::PRIORITY);
1551 port(ID::ADDR, param(ID::ABITS));
1552 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1553 check_expected();
1554 return;
1555 }
1556
1557 if (cell->type == ID($meminit_v2)) {
1558 param(ID::MEMID);
1559 param(ID::PRIORITY);
1560 port(ID::ADDR, param(ID::ABITS));
1561 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1562 port(ID::EN, param(ID::WIDTH));
1563 check_expected();
1564 return;
1565 }
1566
1567 if (cell->type == ID($mem)) {
1568 param(ID::MEMID);
1569 param(ID::SIZE);
1570 param(ID::OFFSET);
1571 param(ID::INIT);
1572 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1573 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1574 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1575 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1576 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1577 port(ID::RD_CLK, param(ID::RD_PORTS));
1578 port(ID::RD_EN, param(ID::RD_PORTS));
1579 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1580 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1581 port(ID::WR_CLK, param(ID::WR_PORTS));
1582 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1583 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1584 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1585 check_expected();
1586 return;
1587 }
1588
1589 if (cell->type == ID($mem_v2)) {
1590 param(ID::MEMID);
1591 param(ID::SIZE);
1592 param(ID::OFFSET);
1593 param(ID::INIT);
1594 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1595 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1596 param_bits(ID::RD_TRANSPARENCY_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
1597 param_bits(ID::RD_COLLISION_X_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
1598 param_bits(ID::RD_WIDE_CONTINUATION, max(1, param(ID::RD_PORTS)));
1599 param_bits(ID::RD_CE_OVER_SRST, max(1, param(ID::RD_PORTS)));
1600 param_bits(ID::RD_ARST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
1601 param_bits(ID::RD_SRST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
1602 param_bits(ID::RD_INIT_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
1603 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1604 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1605 param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS)));
1606 param_bits(ID::WR_PRIORITY_MASK, max(1, param(ID::WR_PORTS) * param(ID::WR_PORTS)));
1607 port(ID::RD_CLK, param(ID::RD_PORTS));
1608 port(ID::RD_EN, param(ID::RD_PORTS));
1609 port(ID::RD_ARST, param(ID::RD_PORTS));
1610 port(ID::RD_SRST, param(ID::RD_PORTS));
1611 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1612 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1613 port(ID::WR_CLK, param(ID::WR_PORTS));
1614 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1615 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1616 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1617 check_expected();
1618 return;
1619 }
1620
1621 if (cell->type == ID($tribuf)) {
1622 port(ID::A, param(ID::WIDTH));
1623 port(ID::Y, param(ID::WIDTH));
1624 port(ID::EN, 1);
1625 check_expected();
1626 return;
1627 }
1628
1629 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1630 port(ID::A, 1);
1631 port(ID::EN, 1);
1632 check_expected();
1633 return;
1634 }
1635
1636 if (cell->type == ID($initstate)) {
1637 port(ID::Y, 1);
1638 check_expected();
1639 return;
1640 }
1641
1642 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1643 port(ID::Y, param(ID::WIDTH));
1644 check_expected();
1645 return;
1646 }
1647
1648 if (cell->type == ID($equiv)) {
1649 port(ID::A, 1);
1650 port(ID::B, 1);
1651 port(ID::Y, 1);
1652 check_expected();
1653 return;
1654 }
1655
1656 if (cell->type.in(ID($specify2), ID($specify3))) {
1657 param_bool(ID::FULL);
1658 param_bool(ID::SRC_DST_PEN);
1659 param_bool(ID::SRC_DST_POL);
1660 param(ID::T_RISE_MIN);
1661 param(ID::T_RISE_TYP);
1662 param(ID::T_RISE_MAX);
1663 param(ID::T_FALL_MIN);
1664 param(ID::T_FALL_TYP);
1665 param(ID::T_FALL_MAX);
1666 port(ID::EN, 1);
1667 port(ID::SRC, param(ID::SRC_WIDTH));
1668 port(ID::DST, param(ID::DST_WIDTH));
1669 if (cell->type == ID($specify3)) {
1670 param_bool(ID::EDGE_EN);
1671 param_bool(ID::EDGE_POL);
1672 param_bool(ID::DAT_DST_PEN);
1673 param_bool(ID::DAT_DST_POL);
1674 port(ID::DAT, param(ID::DST_WIDTH));
1675 }
1676 check_expected();
1677 return;
1678 }
1679
1680 if (cell->type == ID($specrule)) {
1681 param(ID::TYPE);
1682 param_bool(ID::SRC_PEN);
1683 param_bool(ID::SRC_POL);
1684 param_bool(ID::DST_PEN);
1685 param_bool(ID::DST_POL);
1686 param(ID::T_LIMIT_MIN);
1687 param(ID::T_LIMIT_TYP);
1688 param(ID::T_LIMIT_MAX);
1689 param(ID::T_LIMIT2_MIN);
1690 param(ID::T_LIMIT2_TYP);
1691 param(ID::T_LIMIT2_MAX);
1692 port(ID::SRC_EN, 1);
1693 port(ID::DST_EN, 1);
1694 port(ID::SRC, param(ID::SRC_WIDTH));
1695 port(ID::DST, param(ID::DST_WIDTH));
1696 check_expected();
1697 return;
1698 }
1699
1700 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1701 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1702 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1703 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1704 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1705 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1706 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1707 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1708 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1709 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1710 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1711 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1712 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1713 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1714 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1715 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1716
1717 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1718
1719 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1720 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1721 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1722
1723 if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
1724 { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1725
1726 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1727
1728 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1729 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1730
1731 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1732 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1733
1734 if (cell->type.in(
1735 ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
1736 ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
1737 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1738
1739 if (cell->type.in(
1740 ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
1741 ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
1742 ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
1743 ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
1744 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1745
1746 if (cell->type.in(
1747 ID($_ALDFF_NN_), ID($_ALDFF_NP_), ID($_ALDFF_PN_), ID($_ALDFF_PP_)))
1748 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::L,1); port(ID::AD,1); check_expected(); return; }
1749
1750 if (cell->type.in(
1751 ID($_ALDFFE_NNN_), ID($_ALDFFE_NNP_), ID($_ALDFFE_NPN_), ID($_ALDFFE_NPP_),
1752 ID($_ALDFFE_PNN_), ID($_ALDFFE_PNP_), ID($_ALDFFE_PPN_), ID($_ALDFFE_PPP_)))
1753 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::L,1); port(ID::AD,1); port(ID::E,1); check_expected(); return; }
1754
1755 if (cell->type.in(
1756 ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
1757 ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
1758 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1759
1760 if (cell->type.in(
1761 ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
1762 ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
1763 ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
1764 ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
1765 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
1766
1767 if (cell->type.in(
1768 ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
1769 ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
1770 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1771
1772 if (cell->type.in(
1773 ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
1774 ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
1775 ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
1776 ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
1777 ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
1778 ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
1779 ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
1780 ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
1781 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1782
1783 if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
1784 { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1785
1786 if (cell->type.in(
1787 ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
1788 ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
1789 { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1790
1791 if (cell->type.in(
1792 ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
1793 ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
1794 { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1795
1796 error(__LINE__);
1797 }
1798 };
1799 }
1800 #endif
1801
1802 void RTLIL::Module::sort()
1803 {
1804 wires_.sort(sort_by_id_str());
1805 cells_.sort(sort_by_id_str());
1806 parameter_default_values.sort(sort_by_id_str());
1807 memories.sort(sort_by_id_str());
1808 processes.sort(sort_by_id_str());
1809 for (auto &it : cells_)
1810 it.second->sort();
1811 for (auto &it : wires_)
1812 it.second->attributes.sort(sort_by_id_str());
1813 for (auto &it : memories)
1814 it.second->attributes.sort(sort_by_id_str());
1815 }
1816
1817 void RTLIL::Module::check()
1818 {
1819 #ifndef NDEBUG
1820 std::vector<bool> ports_declared;
1821 for (auto &it : wires_) {
1822 log_assert(this == it.second->module);
1823 log_assert(it.first == it.second->name);
1824 log_assert(!it.first.empty());
1825 log_assert(it.second->width >= 0);
1826 log_assert(it.second->port_id >= 0);
1827 for (auto &it2 : it.second->attributes)
1828 log_assert(!it2.first.empty());
1829 if (it.second->port_id) {
1830 log_assert(GetSize(ports) >= it.second->port_id);
1831 log_assert(ports.at(it.second->port_id-1) == it.first);
1832 log_assert(it.second->port_input || it.second->port_output);
1833 if (GetSize(ports_declared) < it.second->port_id)
1834 ports_declared.resize(it.second->port_id);
1835 log_assert(ports_declared[it.second->port_id-1] == false);
1836 ports_declared[it.second->port_id-1] = true;
1837 } else
1838 log_assert(!it.second->port_input && !it.second->port_output);
1839 }
1840 for (auto port_declared : ports_declared)
1841 log_assert(port_declared == true);
1842 log_assert(GetSize(ports) == GetSize(ports_declared));
1843
1844 for (auto &it : memories) {
1845 log_assert(it.first == it.second->name);
1846 log_assert(!it.first.empty());
1847 log_assert(it.second->width >= 0);
1848 log_assert(it.second->size >= 0);
1849 for (auto &it2 : it.second->attributes)
1850 log_assert(!it2.first.empty());
1851 }
1852
1853 for (auto &it : cells_) {
1854 log_assert(this == it.second->module);
1855 log_assert(it.first == it.second->name);
1856 log_assert(!it.first.empty());
1857 log_assert(!it.second->type.empty());
1858 for (auto &it2 : it.second->connections()) {
1859 log_assert(!it2.first.empty());
1860 it2.second.check(this);
1861 }
1862 for (auto &it2 : it.second->attributes)
1863 log_assert(!it2.first.empty());
1864 for (auto &it2 : it.second->parameters)
1865 log_assert(!it2.first.empty());
1866 InternalCellChecker checker(this, it.second);
1867 checker.check();
1868 }
1869
1870 for (auto &it : processes) {
1871 log_assert(it.first == it.second->name);
1872 log_assert(!it.first.empty());
1873 log_assert(it.second->root_case.compare.empty());
1874 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1875 for (size_t i = 0; i < all_cases.size(); i++) {
1876 for (auto &switch_it : all_cases[i]->switches) {
1877 for (auto &case_it : switch_it->cases) {
1878 for (auto &compare_it : case_it->compare) {
1879 log_assert(switch_it->signal.size() == compare_it.size());
1880 }
1881 all_cases.push_back(case_it);
1882 }
1883 }
1884 }
1885 for (auto &sync_it : it.second->syncs) {
1886 switch (sync_it->type) {
1887 case SyncType::ST0:
1888 case SyncType::ST1:
1889 case SyncType::STp:
1890 case SyncType::STn:
1891 case SyncType::STe:
1892 log_assert(!sync_it->signal.empty());
1893 break;
1894 case SyncType::STa:
1895 case SyncType::STg:
1896 case SyncType::STi:
1897 log_assert(sync_it->signal.empty());
1898 break;
1899 }
1900 }
1901 }
1902
1903 for (auto &it : connections_) {
1904 log_assert(it.first.size() == it.second.size());
1905 log_assert(!it.first.has_const());
1906 it.first.check(this);
1907 it.second.check(this);
1908 }
1909
1910 for (auto &it : attributes)
1911 log_assert(!it.first.empty());
1912 #endif
1913 }
1914
1915 void RTLIL::Module::optimize()
1916 {
1917 }
1918
1919 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1920 {
1921 log_assert(new_mod->refcount_wires_ == 0);
1922 log_assert(new_mod->refcount_cells_ == 0);
1923
1924 new_mod->avail_parameters = avail_parameters;
1925 new_mod->parameter_default_values = parameter_default_values;
1926
1927 for (auto &conn : connections_)
1928 new_mod->connect(conn);
1929
1930 for (auto &attr : attributes)
1931 new_mod->attributes[attr.first] = attr.second;
1932
1933 for (auto &it : wires_)
1934 new_mod->addWire(it.first, it.second);
1935
1936 for (auto &it : memories)
1937 new_mod->addMemory(it.first, it.second);
1938
1939 for (auto &it : cells_)
1940 new_mod->addCell(it.first, it.second);
1941
1942 for (auto &it : processes)
1943 new_mod->addProcess(it.first, it.second);
1944
1945 struct RewriteSigSpecWorker
1946 {
1947 RTLIL::Module *mod;
1948 void operator()(RTLIL::SigSpec &sig)
1949 {
1950 sig.pack();
1951 for (auto &c : sig.chunks_)
1952 if (c.wire != NULL)
1953 c.wire = mod->wires_.at(c.wire->name);
1954 }
1955 };
1956
1957 RewriteSigSpecWorker rewriteSigSpecWorker;
1958 rewriteSigSpecWorker.mod = new_mod;
1959 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1960 new_mod->fixup_ports();
1961 }
1962
1963 RTLIL::Module *RTLIL::Module::clone() const
1964 {
1965 RTLIL::Module *new_mod = new RTLIL::Module;
1966 new_mod->name = name;
1967 cloneInto(new_mod);
1968 return new_mod;
1969 }
1970
1971 bool RTLIL::Module::has_memories() const
1972 {
1973 return !memories.empty();
1974 }
1975
1976 bool RTLIL::Module::has_processes() const
1977 {
1978 return !processes.empty();
1979 }
1980
1981 bool RTLIL::Module::has_memories_warn() const
1982 {
1983 if (!memories.empty())
1984 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1985 return !memories.empty();
1986 }
1987
1988 bool RTLIL::Module::has_processes_warn() const
1989 {
1990 if (!processes.empty())
1991 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1992 return !processes.empty();
1993 }
1994
1995 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1996 {
1997 std::vector<RTLIL::Wire*> result;
1998 result.reserve(wires_.size());
1999 for (auto &it : wires_)
2000 if (design->selected(this, it.second))
2001 result.push_back(it.second);
2002 return result;
2003 }
2004
2005 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
2006 {
2007 std::vector<RTLIL::Cell*> result;
2008 result.reserve(cells_.size());
2009 for (auto &it : cells_)
2010 if (design->selected(this, it.second))
2011 result.push_back(it.second);
2012 return result;
2013 }
2014
2015 void RTLIL::Module::add(RTLIL::Wire *wire)
2016 {
2017 log_assert(!wire->name.empty());
2018 log_assert(count_id(wire->name) == 0);
2019 log_assert(refcount_wires_ == 0);
2020 wires_[wire->name] = wire;
2021 wire->module = this;
2022 }
2023
2024 void RTLIL::Module::add(RTLIL::Cell *cell)
2025 {
2026 log_assert(!cell->name.empty());
2027 log_assert(count_id(cell->name) == 0);
2028 log_assert(refcount_cells_ == 0);
2029 cells_[cell->name] = cell;
2030 cell->module = this;
2031 }
2032
2033 void RTLIL::Module::add(RTLIL::Process *process)
2034 {
2035 log_assert(!process->name.empty());
2036 log_assert(count_id(process->name) == 0);
2037 processes[process->name] = process;
2038 process->module = this;
2039 }
2040
2041 void RTLIL::Module::add(RTLIL::Binding *binding)
2042 {
2043 log_assert(binding != nullptr);
2044 bindings_.push_back(binding);
2045 }
2046
2047 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
2048 {
2049 log_assert(refcount_wires_ == 0);
2050
2051 struct DeleteWireWorker
2052 {
2053 RTLIL::Module *module;
2054 const pool<RTLIL::Wire*> *wires_p;
2055
2056 void operator()(RTLIL::SigSpec &sig) {
2057 sig.pack();
2058 for (auto &c : sig.chunks_)
2059 if (c.wire != NULL && wires_p->count(c.wire)) {
2060 c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
2061 c.offset = 0;
2062 }
2063 }
2064
2065 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
2066 log_assert(GetSize(lhs) == GetSize(rhs));
2067 lhs.unpack();
2068 rhs.unpack();
2069 for (int i = 0; i < GetSize(lhs); i++) {
2070 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
2071 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
2072 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
2073 lhs_bit = State::Sx;
2074 rhs_bit = State::Sx;
2075 }
2076 }
2077 }
2078 };
2079
2080 DeleteWireWorker delete_wire_worker;
2081 delete_wire_worker.module = this;
2082 delete_wire_worker.wires_p = &wires;
2083 rewrite_sigspecs2(delete_wire_worker);
2084
2085 for (auto &it : wires) {
2086 log_assert(wires_.count(it->name) != 0);
2087 wires_.erase(it->name);
2088 delete it;
2089 }
2090 }
2091
2092 void RTLIL::Module::remove(RTLIL::Cell *cell)
2093 {
2094 while (!cell->connections_.empty())
2095 cell->unsetPort(cell->connections_.begin()->first);
2096
2097 log_assert(cells_.count(cell->name) != 0);
2098 log_assert(refcount_cells_ == 0);
2099 cells_.erase(cell->name);
2100 delete cell;
2101 }
2102
2103 void RTLIL::Module::remove(RTLIL::Process *process)
2104 {
2105 log_assert(processes.count(process->name) != 0);
2106 processes.erase(process->name);
2107 delete process;
2108 }
2109
2110 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
2111 {
2112 log_assert(wires_[wire->name] == wire);
2113 log_assert(refcount_wires_ == 0);
2114 wires_.erase(wire->name);
2115 wire->name = new_name;
2116 add(wire);
2117 }
2118
2119 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
2120 {
2121 log_assert(cells_[cell->name] == cell);
2122 log_assert(refcount_wires_ == 0);
2123 cells_.erase(cell->name);
2124 cell->name = new_name;
2125 add(cell);
2126 }
2127
2128 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
2129 {
2130 log_assert(count_id(old_name) != 0);
2131 if (wires_.count(old_name))
2132 rename(wires_.at(old_name), new_name);
2133 else if (cells_.count(old_name))
2134 rename(cells_.at(old_name), new_name);
2135 else
2136 log_abort();
2137 }
2138
2139 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
2140 {
2141 log_assert(wires_[w1->name] == w1);
2142 log_assert(wires_[w2->name] == w2);
2143 log_assert(refcount_wires_ == 0);
2144
2145 wires_.erase(w1->name);
2146 wires_.erase(w2->name);
2147
2148 std::swap(w1->name, w2->name);
2149
2150 wires_[w1->name] = w1;
2151 wires_[w2->name] = w2;
2152 }
2153
2154 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
2155 {
2156 log_assert(cells_[c1->name] == c1);
2157 log_assert(cells_[c2->name] == c2);
2158 log_assert(refcount_cells_ == 0);
2159
2160 cells_.erase(c1->name);
2161 cells_.erase(c2->name);
2162
2163 std::swap(c1->name, c2->name);
2164
2165 cells_[c1->name] = c1;
2166 cells_[c2->name] = c2;
2167 }
2168
2169 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
2170 {
2171 int index = 0;
2172 return uniquify(name, index);
2173 }
2174
2175 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
2176 {
2177 if (index == 0) {
2178 if (count_id(name) == 0)
2179 return name;
2180 index++;
2181 }
2182
2183 while (1) {
2184 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
2185 if (count_id(new_name) == 0)
2186 return new_name;
2187 index++;
2188 }
2189 }
2190
2191 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
2192 {
2193 if (a->port_id && !b->port_id)
2194 return true;
2195 if (!a->port_id && b->port_id)
2196 return false;
2197
2198 if (a->port_id == b->port_id)
2199 return a->name < b->name;
2200 return a->port_id < b->port_id;
2201 }
2202
2203 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
2204 {
2205 for (auto mon : monitors)
2206 mon->notify_connect(this, conn);
2207
2208 if (design)
2209 for (auto mon : design->monitors)
2210 mon->notify_connect(this, conn);
2211
2212 // ignore all attempts to assign constants to other constants
2213 if (conn.first.has_const()) {
2214 RTLIL::SigSig new_conn;
2215 for (int i = 0; i < GetSize(conn.first); i++)
2216 if (conn.first[i].wire) {
2217 new_conn.first.append(conn.first[i]);
2218 new_conn.second.append(conn.second[i]);
2219 }
2220 if (GetSize(new_conn.first))
2221 connect(new_conn);
2222 return;
2223 }
2224
2225 if (yosys_xtrace) {
2226 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2227 log_backtrace("-X- ", yosys_xtrace-1);
2228 }
2229
2230 log_assert(GetSize(conn.first) == GetSize(conn.second));
2231 connections_.push_back(conn);
2232 }
2233
2234 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
2235 {
2236 connect(RTLIL::SigSig(lhs, rhs));
2237 }
2238
2239 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
2240 {
2241 for (auto mon : monitors)
2242 mon->notify_connect(this, new_conn);
2243
2244 if (design)
2245 for (auto mon : design->monitors)
2246 mon->notify_connect(this, new_conn);
2247
2248 if (yosys_xtrace) {
2249 log("#X# New connections vector in %s:\n", log_id(this));
2250 for (auto &conn: new_conn)
2251 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2252 log_backtrace("-X- ", yosys_xtrace-1);
2253 }
2254
2255 connections_ = new_conn;
2256 }
2257
2258 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
2259 {
2260 return connections_;
2261 }
2262
2263 void RTLIL::Module::fixup_ports()
2264 {
2265 std::vector<RTLIL::Wire*> all_ports;
2266
2267 for (auto &w : wires_)
2268 if (w.second->port_input || w.second->port_output)
2269 all_ports.push_back(w.second);
2270 else
2271 w.second->port_id = 0;
2272
2273 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
2274
2275 ports.clear();
2276 for (size_t i = 0; i < all_ports.size(); i++) {
2277 ports.push_back(all_ports[i]->name);
2278 all_ports[i]->port_id = i+1;
2279 }
2280 }
2281
2282 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
2283 {
2284 RTLIL::Wire *wire = new RTLIL::Wire;
2285 wire->name = name;
2286 wire->width = width;
2287 add(wire);
2288 return wire;
2289 }
2290
2291 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
2292 {
2293 RTLIL::Wire *wire = addWire(name);
2294 wire->width = other->width;
2295 wire->start_offset = other->start_offset;
2296 wire->port_id = other->port_id;
2297 wire->port_input = other->port_input;
2298 wire->port_output = other->port_output;
2299 wire->upto = other->upto;
2300 wire->is_signed = other->is_signed;
2301 wire->attributes = other->attributes;
2302 return wire;
2303 }
2304
2305 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
2306 {
2307 RTLIL::Cell *cell = new RTLIL::Cell;
2308 cell->name = name;
2309 cell->type = type;
2310 add(cell);
2311 return cell;
2312 }
2313
2314 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
2315 {
2316 RTLIL::Cell *cell = addCell(name, other->type);
2317 cell->connections_ = other->connections_;
2318 cell->parameters = other->parameters;
2319 cell->attributes = other->attributes;
2320 return cell;
2321 }
2322
2323 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
2324 {
2325 RTLIL::Memory *mem = new RTLIL::Memory;
2326 mem->name = name;
2327 mem->width = other->width;
2328 mem->start_offset = other->start_offset;
2329 mem->size = other->size;
2330 mem->attributes = other->attributes;
2331 memories[mem->name] = mem;
2332 return mem;
2333 }
2334
2335 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name)
2336 {
2337 RTLIL::Process *proc = new RTLIL::Process;
2338 proc->name = name;
2339 add(proc);
2340 return proc;
2341 }
2342
2343 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
2344 {
2345 RTLIL::Process *proc = other->clone();
2346 proc->name = name;
2347 add(proc);
2348 return proc;
2349 }
2350
2351 #define DEF_METHOD(_func, _y_size, _type) \
2352 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2353 RTLIL::Cell *cell = addCell(name, _type); \
2354 cell->parameters[ID::A_SIGNED] = is_signed; \
2355 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2356 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2357 cell->setPort(ID::A, sig_a); \
2358 cell->setPort(ID::Y, sig_y); \
2359 cell->set_src_attribute(src); \
2360 return cell; \
2361 } \
2362 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2363 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2364 add ## _func(name, sig_a, sig_y, is_signed, src); \
2365 return sig_y; \
2366 }
2367 DEF_METHOD(Not, sig_a.size(), ID($not))
2368 DEF_METHOD(Pos, sig_a.size(), ID($pos))
2369 DEF_METHOD(Neg, sig_a.size(), ID($neg))
2370 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
2371 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
2372 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
2373 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
2374 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
2375 DEF_METHOD(LogicNot, 1, ID($logic_not))
2376 #undef DEF_METHOD
2377
2378 #define DEF_METHOD(_func, _y_size, _type) \
2379 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2380 RTLIL::Cell *cell = addCell(name, _type); \
2381 cell->parameters[ID::A_SIGNED] = is_signed; \
2382 cell->parameters[ID::B_SIGNED] = is_signed; \
2383 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2384 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2385 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2386 cell->setPort(ID::A, sig_a); \
2387 cell->setPort(ID::B, sig_b); \
2388 cell->setPort(ID::Y, sig_y); \
2389 cell->set_src_attribute(src); \
2390 return cell; \
2391 } \
2392 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2393 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2394 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2395 return sig_y; \
2396 }
2397 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
2398 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
2399 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
2400 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
2401 DEF_METHOD(Shift, sig_a.size(), ID($shift))
2402 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
2403 DEF_METHOD(Lt, 1, ID($lt))
2404 DEF_METHOD(Le, 1, ID($le))
2405 DEF_METHOD(Eq, 1, ID($eq))
2406 DEF_METHOD(Ne, 1, ID($ne))
2407 DEF_METHOD(Eqx, 1, ID($eqx))
2408 DEF_METHOD(Nex, 1, ID($nex))
2409 DEF_METHOD(Ge, 1, ID($ge))
2410 DEF_METHOD(Gt, 1, ID($gt))
2411 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
2412 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
2413 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
2414 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
2415 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
2416 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
2417 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
2418 DEF_METHOD(LogicAnd, 1, ID($logic_and))
2419 DEF_METHOD(LogicOr, 1, ID($logic_or))
2420 #undef DEF_METHOD
2421
2422 #define DEF_METHOD(_func, _y_size, _type) \
2423 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2424 RTLIL::Cell *cell = addCell(name, _type); \
2425 cell->parameters[ID::A_SIGNED] = is_signed; \
2426 cell->parameters[ID::B_SIGNED] = false; \
2427 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2428 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2429 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2430 cell->setPort(ID::A, sig_a); \
2431 cell->setPort(ID::B, sig_b); \
2432 cell->setPort(ID::Y, sig_y); \
2433 cell->set_src_attribute(src); \
2434 return cell; \
2435 } \
2436 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2437 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2438 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2439 return sig_y; \
2440 }
2441 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2442 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2443 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2444 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2445 #undef DEF_METHOD
2446
2447 #define DEF_METHOD(_func, _type, _pmux) \
2448 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2449 RTLIL::Cell *cell = addCell(name, _type); \
2450 cell->parameters[ID::WIDTH] = sig_a.size(); \
2451 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2452 cell->setPort(ID::A, sig_a); \
2453 cell->setPort(ID::B, sig_b); \
2454 cell->setPort(ID::S, sig_s); \
2455 cell->setPort(ID::Y, sig_y); \
2456 cell->set_src_attribute(src); \
2457 return cell; \
2458 } \
2459 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2460 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2461 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2462 return sig_y; \
2463 }
2464 DEF_METHOD(Mux, ID($mux), 0)
2465 DEF_METHOD(Pmux, ID($pmux), 1)
2466 #undef DEF_METHOD
2467
2468 #define DEF_METHOD(_func, _type, _demux) \
2469 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2470 RTLIL::Cell *cell = addCell(name, _type); \
2471 cell->parameters[ID::WIDTH] = _demux ? sig_a.size() : sig_y.size(); \
2472 cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2473 cell->setPort(ID::A, sig_a); \
2474 cell->setPort(ID::S, sig_s); \
2475 cell->setPort(ID::Y, sig_y); \
2476 cell->set_src_attribute(src); \
2477 return cell; \
2478 } \
2479 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2480 RTLIL::SigSpec sig_y = addWire(NEW_ID, _demux ? sig_a.size() << sig_s.size() : sig_a.size() >> sig_s.size()); \
2481 add ## _func(name, sig_a, sig_s, sig_y, src); \
2482 return sig_y; \
2483 }
2484 DEF_METHOD(Bmux, ID($bmux), 0)
2485 DEF_METHOD(Demux, ID($demux), 1)
2486 #undef DEF_METHOD
2487
2488 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2489 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2490 RTLIL::Cell *cell = addCell(name, _type); \
2491 cell->setPort("\\" #_P1, sig1); \
2492 cell->setPort("\\" #_P2, sig2); \
2493 cell->set_src_attribute(src); \
2494 return cell; \
2495 } \
2496 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2497 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2498 add ## _func(name, sig1, sig2, src); \
2499 return sig2; \
2500 }
2501 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2502 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2503 RTLIL::Cell *cell = addCell(name, _type); \
2504 cell->setPort("\\" #_P1, sig1); \
2505 cell->setPort("\\" #_P2, sig2); \
2506 cell->setPort("\\" #_P3, sig3); \
2507 cell->set_src_attribute(src); \
2508 return cell; \
2509 } \
2510 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2511 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2512 add ## _func(name, sig1, sig2, sig3, src); \
2513 return sig3; \
2514 }
2515 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2516 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2517 RTLIL::Cell *cell = addCell(name, _type); \
2518 cell->setPort("\\" #_P1, sig1); \
2519 cell->setPort("\\" #_P2, sig2); \
2520 cell->setPort("\\" #_P3, sig3); \
2521 cell->setPort("\\" #_P4, sig4); \
2522 cell->set_src_attribute(src); \
2523 return cell; \
2524 } \
2525 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2526 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2527 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2528 return sig4; \
2529 }
2530 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2531 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2532 RTLIL::Cell *cell = addCell(name, _type); \
2533 cell->setPort("\\" #_P1, sig1); \
2534 cell->setPort("\\" #_P2, sig2); \
2535 cell->setPort("\\" #_P3, sig3); \
2536 cell->setPort("\\" #_P4, sig4); \
2537 cell->setPort("\\" #_P5, sig5); \
2538 cell->set_src_attribute(src); \
2539 return cell; \
2540 } \
2541 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2542 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2543 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2544 return sig5; \
2545 }
2546 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2547 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2548 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2549 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2550 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2551 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2552 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2553 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2554 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2555 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2556 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2557 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2558 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2559 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2560 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2561 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2562 #undef DEF_METHOD_2
2563 #undef DEF_METHOD_3
2564 #undef DEF_METHOD_4
2565 #undef DEF_METHOD_5
2566
2567 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2568 {
2569 RTLIL::Cell *cell = addCell(name, ID($pow));
2570 cell->parameters[ID::A_SIGNED] = a_signed;
2571 cell->parameters[ID::B_SIGNED] = b_signed;
2572 cell->parameters[ID::A_WIDTH] = sig_a.size();
2573 cell->parameters[ID::B_WIDTH] = sig_b.size();
2574 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2575 cell->setPort(ID::A, sig_a);
2576 cell->setPort(ID::B, sig_b);
2577 cell->setPort(ID::Y, sig_y);
2578 cell->set_src_attribute(src);
2579 return cell;
2580 }
2581
2582 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2583 {
2584 RTLIL::Cell *cell = addCell(name, ID($slice));
2585 cell->parameters[ID::A_WIDTH] = sig_a.size();
2586 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2587 cell->parameters[ID::OFFSET] = offset;
2588 cell->setPort(ID::A, sig_a);
2589 cell->setPort(ID::Y, sig_y);
2590 cell->set_src_attribute(src);
2591 return cell;
2592 }
2593
2594 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2595 {
2596 RTLIL::Cell *cell = addCell(name, ID($concat));
2597 cell->parameters[ID::A_WIDTH] = sig_a.size();
2598 cell->parameters[ID::B_WIDTH] = sig_b.size();
2599 cell->setPort(ID::A, sig_a);
2600 cell->setPort(ID::B, sig_b);
2601 cell->setPort(ID::Y, sig_y);
2602 cell->set_src_attribute(src);
2603 return cell;
2604 }
2605
2606 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2607 {
2608 RTLIL::Cell *cell = addCell(name, ID($lut));
2609 cell->parameters[ID::LUT] = lut;
2610 cell->parameters[ID::WIDTH] = sig_a.size();
2611 cell->setPort(ID::A, sig_a);
2612 cell->setPort(ID::Y, sig_y);
2613 cell->set_src_attribute(src);
2614 return cell;
2615 }
2616
2617 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2618 {
2619 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2620 cell->parameters[ID::WIDTH] = sig_a.size();
2621 cell->setPort(ID::A, sig_a);
2622 cell->setPort(ID::EN, sig_en);
2623 cell->setPort(ID::Y, sig_y);
2624 cell->set_src_attribute(src);
2625 return cell;
2626 }
2627
2628 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2629 {
2630 RTLIL::Cell *cell = addCell(name, ID($assert));
2631 cell->setPort(ID::A, sig_a);
2632 cell->setPort(ID::EN, sig_en);
2633 cell->set_src_attribute(src);
2634 return cell;
2635 }
2636
2637 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2638 {
2639 RTLIL::Cell *cell = addCell(name, ID($assume));
2640 cell->setPort(ID::A, sig_a);
2641 cell->setPort(ID::EN, sig_en);
2642 cell->set_src_attribute(src);
2643 return cell;
2644 }
2645
2646 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2647 {
2648 RTLIL::Cell *cell = addCell(name, ID($live));
2649 cell->setPort(ID::A, sig_a);
2650 cell->setPort(ID::EN, sig_en);
2651 cell->set_src_attribute(src);
2652 return cell;
2653 }
2654
2655 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2656 {
2657 RTLIL::Cell *cell = addCell(name, ID($fair));
2658 cell->setPort(ID::A, sig_a);
2659 cell->setPort(ID::EN, sig_en);
2660 cell->set_src_attribute(src);
2661 return cell;
2662 }
2663
2664 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2665 {
2666 RTLIL::Cell *cell = addCell(name, ID($cover));
2667 cell->setPort(ID::A, sig_a);
2668 cell->setPort(ID::EN, sig_en);
2669 cell->set_src_attribute(src);
2670 return cell;
2671 }
2672
2673 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2674 {
2675 RTLIL::Cell *cell = addCell(name, ID($equiv));
2676 cell->setPort(ID::A, sig_a);
2677 cell->setPort(ID::B, sig_b);
2678 cell->setPort(ID::Y, sig_y);
2679 cell->set_src_attribute(src);
2680 return cell;
2681 }
2682
2683 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2684 {
2685 RTLIL::Cell *cell = addCell(name, ID($sr));
2686 cell->parameters[ID::SET_POLARITY] = set_polarity;
2687 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2688 cell->parameters[ID::WIDTH] = sig_q.size();
2689 cell->setPort(ID::SET, sig_set);
2690 cell->setPort(ID::CLR, sig_clr);
2691 cell->setPort(ID::Q, sig_q);
2692 cell->set_src_attribute(src);
2693 return cell;
2694 }
2695
2696 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2697 {
2698 RTLIL::Cell *cell = addCell(name, ID($ff));
2699 cell->parameters[ID::WIDTH] = sig_q.size();
2700 cell->setPort(ID::D, sig_d);
2701 cell->setPort(ID::Q, sig_q);
2702 cell->set_src_attribute(src);
2703 return cell;
2704 }
2705
2706 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2707 {
2708 RTLIL::Cell *cell = addCell(name, ID($dff));
2709 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2710 cell->parameters[ID::WIDTH] = sig_q.size();
2711 cell->setPort(ID::CLK, sig_clk);
2712 cell->setPort(ID::D, sig_d);
2713 cell->setPort(ID::Q, sig_q);
2714 cell->set_src_attribute(src);
2715 return cell;
2716 }
2717
2718 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2719 {
2720 RTLIL::Cell *cell = addCell(name, ID($dffe));
2721 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2722 cell->parameters[ID::EN_POLARITY] = en_polarity;
2723 cell->parameters[ID::WIDTH] = sig_q.size();
2724 cell->setPort(ID::CLK, sig_clk);
2725 cell->setPort(ID::EN, sig_en);
2726 cell->setPort(ID::D, sig_d);
2727 cell->setPort(ID::Q, sig_q);
2728 cell->set_src_attribute(src);
2729 return cell;
2730 }
2731
2732 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2733 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2734 {
2735 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2736 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2737 cell->parameters[ID::SET_POLARITY] = set_polarity;
2738 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2739 cell->parameters[ID::WIDTH] = sig_q.size();
2740 cell->setPort(ID::CLK, sig_clk);
2741 cell->setPort(ID::SET, sig_set);
2742 cell->setPort(ID::CLR, sig_clr);
2743 cell->setPort(ID::D, sig_d);
2744 cell->setPort(ID::Q, sig_q);
2745 cell->set_src_attribute(src);
2746 return cell;
2747 }
2748
2749 RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2750 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2751 {
2752 RTLIL::Cell *cell = addCell(name, ID($dffsre));
2753 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2754 cell->parameters[ID::EN_POLARITY] = en_polarity;
2755 cell->parameters[ID::SET_POLARITY] = set_polarity;
2756 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2757 cell->parameters[ID::WIDTH] = sig_q.size();
2758 cell->setPort(ID::CLK, sig_clk);
2759 cell->setPort(ID::EN, sig_en);
2760 cell->setPort(ID::SET, sig_set);
2761 cell->setPort(ID::CLR, sig_clr);
2762 cell->setPort(ID::D, sig_d);
2763 cell->setPort(ID::Q, sig_q);
2764 cell->set_src_attribute(src);
2765 return cell;
2766 }
2767
2768 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2769 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2770 {
2771 RTLIL::Cell *cell = addCell(name, ID($adff));
2772 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2773 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2774 cell->parameters[ID::ARST_VALUE] = arst_value;
2775 cell->parameters[ID::WIDTH] = sig_q.size();
2776 cell->setPort(ID::CLK, sig_clk);
2777 cell->setPort(ID::ARST, sig_arst);
2778 cell->setPort(ID::D, sig_d);
2779 cell->setPort(ID::Q, sig_q);
2780 cell->set_src_attribute(src);
2781 return cell;
2782 }
2783
2784 RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2785 RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2786 {
2787 RTLIL::Cell *cell = addCell(name, ID($adffe));
2788 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2789 cell->parameters[ID::EN_POLARITY] = en_polarity;
2790 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2791 cell->parameters[ID::ARST_VALUE] = arst_value;
2792 cell->parameters[ID::WIDTH] = sig_q.size();
2793 cell->setPort(ID::CLK, sig_clk);
2794 cell->setPort(ID::EN, sig_en);
2795 cell->setPort(ID::ARST, sig_arst);
2796 cell->setPort(ID::D, sig_d);
2797 cell->setPort(ID::Q, sig_q);
2798 cell->set_src_attribute(src);
2799 return cell;
2800 }
2801
2802 RTLIL::Cell* RTLIL::Module::addAldff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2803 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const std::string &src)
2804 {
2805 RTLIL::Cell *cell = addCell(name, ID($aldff));
2806 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2807 cell->parameters[ID::ALOAD_POLARITY] = aload_polarity;
2808 cell->parameters[ID::WIDTH] = sig_q.size();
2809 cell->setPort(ID::CLK, sig_clk);
2810 cell->setPort(ID::ALOAD, sig_aload);
2811 cell->setPort(ID::D, sig_d);
2812 cell->setPort(ID::AD, sig_ad);
2813 cell->setPort(ID::Q, sig_q);
2814 cell->set_src_attribute(src);
2815 return cell;
2816 }
2817
2818 RTLIL::Cell* RTLIL::Module::addAldffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2819 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const std::string &src)
2820 {
2821 RTLIL::Cell *cell = addCell(name, ID($aldffe));
2822 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2823 cell->parameters[ID::EN_POLARITY] = en_polarity;
2824 cell->parameters[ID::ALOAD_POLARITY] = aload_polarity;
2825 cell->parameters[ID::WIDTH] = sig_q.size();
2826 cell->setPort(ID::CLK, sig_clk);
2827 cell->setPort(ID::EN, sig_en);
2828 cell->setPort(ID::ALOAD, sig_aload);
2829 cell->setPort(ID::D, sig_d);
2830 cell->setPort(ID::AD, sig_ad);
2831 cell->setPort(ID::Q, sig_q);
2832 cell->set_src_attribute(src);
2833 return cell;
2834 }
2835
2836 RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2837 RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2838 {
2839 RTLIL::Cell *cell = addCell(name, ID($sdff));
2840 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2841 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2842 cell->parameters[ID::SRST_VALUE] = srst_value;
2843 cell->parameters[ID::WIDTH] = sig_q.size();
2844 cell->setPort(ID::CLK, sig_clk);
2845 cell->setPort(ID::SRST, sig_srst);
2846 cell->setPort(ID::D, sig_d);
2847 cell->setPort(ID::Q, sig_q);
2848 cell->set_src_attribute(src);
2849 return cell;
2850 }
2851
2852 RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2853 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2854 {
2855 RTLIL::Cell *cell = addCell(name, ID($sdffe));
2856 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2857 cell->parameters[ID::EN_POLARITY] = en_polarity;
2858 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2859 cell->parameters[ID::SRST_VALUE] = srst_value;
2860 cell->parameters[ID::WIDTH] = sig_q.size();
2861 cell->setPort(ID::CLK, sig_clk);
2862 cell->setPort(ID::EN, sig_en);
2863 cell->setPort(ID::SRST, sig_srst);
2864 cell->setPort(ID::D, sig_d);
2865 cell->setPort(ID::Q, sig_q);
2866 cell->set_src_attribute(src);
2867 return cell;
2868 }
2869
2870 RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2871 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2872 {
2873 RTLIL::Cell *cell = addCell(name, ID($sdffce));
2874 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2875 cell->parameters[ID::EN_POLARITY] = en_polarity;
2876 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2877 cell->parameters[ID::SRST_VALUE] = srst_value;
2878 cell->parameters[ID::WIDTH] = sig_q.size();
2879 cell->setPort(ID::CLK, sig_clk);
2880 cell->setPort(ID::EN, sig_en);
2881 cell->setPort(ID::SRST, sig_srst);
2882 cell->setPort(ID::D, sig_d);
2883 cell->setPort(ID::Q, sig_q);
2884 cell->set_src_attribute(src);
2885 return cell;
2886 }
2887
2888 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2889 {
2890 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2891 cell->parameters[ID::EN_POLARITY] = en_polarity;
2892 cell->parameters[ID::WIDTH] = sig_q.size();
2893 cell->setPort(ID::EN, sig_en);
2894 cell->setPort(ID::D, sig_d);
2895 cell->setPort(ID::Q, sig_q);
2896 cell->set_src_attribute(src);
2897 return cell;
2898 }
2899
2900 RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2901 RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2902 {
2903 RTLIL::Cell *cell = addCell(name, ID($adlatch));
2904 cell->parameters[ID::EN_POLARITY] = en_polarity;
2905 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2906 cell->parameters[ID::ARST_VALUE] = arst_value;
2907 cell->parameters[ID::WIDTH] = sig_q.size();
2908 cell->setPort(ID::EN, sig_en);
2909 cell->setPort(ID::ARST, sig_arst);
2910 cell->setPort(ID::D, sig_d);
2911 cell->setPort(ID::Q, sig_q);
2912 cell->set_src_attribute(src);
2913 return cell;
2914 }
2915
2916 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2917 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2918 {
2919 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2920 cell->parameters[ID::EN_POLARITY] = en_polarity;
2921 cell->parameters[ID::SET_POLARITY] = set_polarity;
2922 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2923 cell->parameters[ID::WIDTH] = sig_q.size();
2924 cell->setPort(ID::EN, sig_en);
2925 cell->setPort(ID::SET, sig_set);
2926 cell->setPort(ID::CLR, sig_clr);
2927 cell->setPort(ID::D, sig_d);
2928 cell->setPort(ID::Q, sig_q);
2929 cell->set_src_attribute(src);
2930 return cell;
2931 }
2932
2933 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2934 const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2935 {
2936 RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2937 cell->setPort(ID::S, sig_set);
2938 cell->setPort(ID::R, sig_clr);
2939 cell->setPort(ID::Q, sig_q);
2940 cell->set_src_attribute(src);
2941 return cell;
2942 }
2943
2944 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2945 {
2946 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2947 cell->setPort(ID::D, sig_d);
2948 cell->setPort(ID::Q, sig_q);
2949 cell->set_src_attribute(src);
2950 return cell;
2951 }
2952
2953 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2954 {
2955 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2956 cell->setPort(ID::C, sig_clk);
2957 cell->setPort(ID::D, sig_d);
2958 cell->setPort(ID::Q, sig_q);
2959 cell->set_src_attribute(src);
2960 return cell;
2961 }
2962
2963 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2964 {
2965 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2966 cell->setPort(ID::C, sig_clk);
2967 cell->setPort(ID::E, sig_en);
2968 cell->setPort(ID::D, sig_d);
2969 cell->setPort(ID::Q, sig_q);
2970 cell->set_src_attribute(src);
2971 return cell;
2972 }
2973
2974 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2975 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2976 {
2977 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2978 cell->setPort(ID::C, sig_clk);
2979 cell->setPort(ID::S, sig_set);
2980 cell->setPort(ID::R, sig_clr);
2981 cell->setPort(ID::D, sig_d);
2982 cell->setPort(ID::Q, sig_q);
2983 cell->set_src_attribute(src);
2984 return cell;
2985 }
2986
2987 RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2988 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2989 {
2990 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2991 cell->setPort(ID::C, sig_clk);
2992 cell->setPort(ID::S, sig_set);
2993 cell->setPort(ID::R, sig_clr);
2994 cell->setPort(ID::E, sig_en);
2995 cell->setPort(ID::D, sig_d);
2996 cell->setPort(ID::Q, sig_q);
2997 cell->set_src_attribute(src);
2998 return cell;
2999 }
3000
3001 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3002 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
3003 {
3004 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
3005 cell->setPort(ID::C, sig_clk);
3006 cell->setPort(ID::R, sig_arst);
3007 cell->setPort(ID::D, sig_d);
3008 cell->setPort(ID::Q, sig_q);
3009 cell->set_src_attribute(src);
3010 return cell;
3011 }
3012
3013 RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3014 bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
3015 {
3016 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
3017 cell->setPort(ID::C, sig_clk);
3018 cell->setPort(ID::R, sig_arst);
3019 cell->setPort(ID::E, sig_en);
3020 cell->setPort(ID::D, sig_d);
3021 cell->setPort(ID::Q, sig_q);
3022 cell->set_src_attribute(src);
3023 return cell;
3024 }
3025
3026 RTLIL::Cell* RTLIL::Module::addAldffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3027 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const std::string &src)
3028 {
3029 RTLIL::Cell *cell = addCell(name, stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N'));
3030 cell->setPort(ID::C, sig_clk);
3031 cell->setPort(ID::L, sig_aload);
3032 cell->setPort(ID::D, sig_d);
3033 cell->setPort(ID::AD, sig_ad);
3034 cell->setPort(ID::Q, sig_q);
3035 cell->set_src_attribute(src);
3036 return cell;
3037 }
3038
3039 RTLIL::Cell* RTLIL::Module::addAldffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3040 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const std::string &src)
3041 {
3042 RTLIL::Cell *cell = addCell(name, stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
3043 cell->setPort(ID::C, sig_clk);
3044 cell->setPort(ID::L, sig_aload);
3045 cell->setPort(ID::E, sig_en);
3046 cell->setPort(ID::D, sig_d);
3047 cell->setPort(ID::AD, sig_ad);
3048 cell->setPort(ID::Q, sig_q);
3049 cell->set_src_attribute(src);
3050 return cell;
3051 }
3052
3053 RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3054 bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
3055 {
3056 RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
3057 cell->setPort(ID::C, sig_clk);
3058 cell->setPort(ID::R, sig_srst);
3059 cell->setPort(ID::D, sig_d);
3060 cell->setPort(ID::Q, sig_q);
3061 cell->set_src_attribute(src);
3062 return cell;
3063 }
3064
3065 RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3066 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
3067 {
3068 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
3069 cell->setPort(ID::C, sig_clk);
3070 cell->setPort(ID::R, sig_srst);
3071 cell->setPort(ID::E, sig_en);
3072 cell->setPort(ID::D, sig_d);
3073 cell->setPort(ID::Q, sig_q);
3074 cell->set_src_attribute(src);
3075 return cell;
3076 }
3077
3078 RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3079 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
3080 {
3081 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
3082 cell->setPort(ID::C, sig_clk);
3083 cell->setPort(ID::R, sig_srst);
3084 cell->setPort(ID::E, sig_en);
3085 cell->setPort(ID::D, sig_d);
3086 cell->setPort(ID::Q, sig_q);
3087 cell->set_src_attribute(src);
3088 return cell;
3089 }
3090
3091 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
3092 {
3093 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
3094 cell->setPort(ID::E, sig_en);
3095 cell->setPort(ID::D, sig_d);
3096 cell->setPort(ID::Q, sig_q);
3097 cell->set_src_attribute(src);
3098 return cell;
3099 }
3100
3101 RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3102 bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
3103 {
3104 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
3105 cell->setPort(ID::E, sig_en);
3106 cell->setPort(ID::R, sig_arst);
3107 cell->setPort(ID::D, sig_d);
3108 cell->setPort(ID::Q, sig_q);
3109 cell->set_src_attribute(src);
3110 return cell;
3111 }
3112
3113 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
3114 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
3115 {
3116 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
3117 cell->setPort(ID::E, sig_en);
3118 cell->setPort(ID::S, sig_set);
3119 cell->setPort(ID::R, sig_clr);
3120 cell->setPort(ID::D, sig_d);
3121 cell->setPort(ID::Q, sig_q);
3122 cell->set_src_attribute(src);
3123 return cell;
3124 }
3125
3126 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
3127 {
3128 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3129 Cell *cell = addCell(name, ID($anyconst));
3130 cell->setParam(ID::WIDTH, width);
3131 cell->setPort(ID::Y, sig);
3132 cell->set_src_attribute(src);
3133 return sig;
3134 }
3135
3136 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
3137 {
3138 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3139 Cell *cell = addCell(name, ID($anyseq));
3140 cell->setParam(ID::WIDTH, width);
3141 cell->setPort(ID::Y, sig);
3142 cell->set_src_attribute(src);
3143 return sig;
3144 }
3145
3146 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
3147 {
3148 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3149 Cell *cell = addCell(name, ID($allconst));
3150 cell->setParam(ID::WIDTH, width);
3151 cell->setPort(ID::Y, sig);
3152 cell->set_src_attribute(src);
3153 return sig;
3154 }
3155
3156 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
3157 {
3158 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3159 Cell *cell = addCell(name, ID($allseq));
3160 cell->setParam(ID::WIDTH, width);
3161 cell->setPort(ID::Y, sig);
3162 cell->set_src_attribute(src);
3163 return sig;
3164 }
3165
3166 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
3167 {
3168 RTLIL::SigSpec sig = addWire(NEW_ID);
3169 Cell *cell = addCell(name, ID($initstate));
3170 cell->setPort(ID::Y, sig);
3171 cell->set_src_attribute(src);
3172 return sig;
3173 }
3174
3175 RTLIL::Wire::Wire()
3176 {
3177 static unsigned int hashidx_count = 123456789;
3178 hashidx_count = mkhash_xorshift(hashidx_count);
3179 hashidx_ = hashidx_count;
3180
3181 module = nullptr;
3182 width = 1;
3183 start_offset = 0;
3184 port_id = 0;
3185 port_input = false;
3186 port_output = false;
3187 upto = false;
3188 is_signed = false;
3189
3190 #ifdef WITH_PYTHON
3191 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
3192 #endif
3193 }
3194
3195 RTLIL::Wire::~Wire()
3196 {
3197 #ifdef WITH_PYTHON
3198 RTLIL::Wire::get_all_wires()->erase(hashidx_);
3199 #endif
3200 }
3201
3202 #ifdef WITH_PYTHON
3203 static std::map<unsigned int, RTLIL::Wire*> all_wires;
3204 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
3205 {
3206 return &all_wires;
3207 }
3208 #endif
3209
3210 RTLIL::Memory::Memory()
3211 {
3212 static unsigned int hashidx_count = 123456789;
3213 hashidx_count = mkhash_xorshift(hashidx_count);
3214 hashidx_ = hashidx_count;
3215
3216 width = 1;
3217 start_offset = 0;
3218 size = 0;
3219 #ifdef WITH_PYTHON
3220 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
3221 #endif
3222 }
3223
3224 RTLIL::Process::Process() : module(nullptr)
3225 {
3226 static unsigned int hashidx_count = 123456789;
3227 hashidx_count = mkhash_xorshift(hashidx_count);
3228 hashidx_ = hashidx_count;
3229 }
3230
3231 RTLIL::Cell::Cell() : module(nullptr)
3232 {
3233 static unsigned int hashidx_count = 123456789;
3234 hashidx_count = mkhash_xorshift(hashidx_count);
3235 hashidx_ = hashidx_count;
3236
3237 // log("#memtrace# %p\n", this);
3238 memhasher();
3239
3240 #ifdef WITH_PYTHON
3241 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
3242 #endif
3243 }
3244
3245 RTLIL::Cell::~Cell()
3246 {
3247 #ifdef WITH_PYTHON
3248 RTLIL::Cell::get_all_cells()->erase(hashidx_);
3249 #endif
3250 }
3251
3252 #ifdef WITH_PYTHON
3253 static std::map<unsigned int, RTLIL::Cell*> all_cells;
3254 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
3255 {
3256 return &all_cells;
3257 }
3258 #endif
3259
3260 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
3261 {
3262 return connections_.count(portname) != 0;
3263 }
3264
3265 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
3266 {
3267 RTLIL::SigSpec signal;
3268 auto conn_it = connections_.find(portname);
3269
3270 if (conn_it != connections_.end())
3271 {
3272 for (auto mon : module->monitors)
3273 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3274
3275 if (module->design)
3276 for (auto mon : module->design->monitors)
3277 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3278
3279 if (yosys_xtrace) {
3280 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
3281 log_backtrace("-X- ", yosys_xtrace-1);
3282 }
3283
3284 connections_.erase(conn_it);
3285 }
3286 }
3287
3288 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
3289 {
3290 auto r = connections_.insert(portname);
3291 auto conn_it = r.first;
3292 if (!r.second && conn_it->second == signal)
3293 return;
3294
3295 for (auto mon : module->monitors)
3296 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3297
3298 if (module->design)
3299 for (auto mon : module->design->monitors)
3300 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3301
3302 if (yosys_xtrace) {
3303 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
3304 log_backtrace("-X- ", yosys_xtrace-1);
3305 }
3306
3307 conn_it->second = std::move(signal);
3308 }
3309
3310 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
3311 {
3312 return connections_.at(portname);
3313 }
3314
3315 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
3316 {
3317 return connections_;
3318 }
3319
3320 bool RTLIL::Cell::known() const
3321 {
3322 if (yosys_celltypes.cell_known(type))
3323 return true;
3324 if (module && module->design && module->design->module(type))
3325 return true;
3326 return false;
3327 }
3328
3329 bool RTLIL::Cell::input(RTLIL::IdString portname) const
3330 {
3331 if (yosys_celltypes.cell_known(type))
3332 return yosys_celltypes.cell_input(type, portname);
3333 if (module && module->design) {
3334 RTLIL::Module *m = module->design->module(type);
3335 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3336 return w && w->port_input;
3337 }
3338 return false;
3339 }
3340
3341 bool RTLIL::Cell::output(RTLIL::IdString portname) const
3342 {
3343 if (yosys_celltypes.cell_known(type))
3344 return yosys_celltypes.cell_output(type, portname);
3345 if (module && module->design) {
3346 RTLIL::Module *m = module->design->module(type);
3347 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3348 return w && w->port_output;
3349 }
3350 return false;
3351 }
3352
3353 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
3354 {
3355 return parameters.count(paramname) != 0;
3356 }
3357
3358 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
3359 {
3360 parameters.erase(paramname);
3361 }
3362
3363 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
3364 {
3365 parameters[paramname] = std::move(value);
3366 }
3367
3368 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
3369 {
3370 const auto &it = parameters.find(paramname);
3371 if (it != parameters.end())
3372 return it->second;
3373 if (module && module->design) {
3374 RTLIL::Module *m = module->design->module(type);
3375 if (m)
3376 return m->parameter_default_values.at(paramname);
3377 }
3378 throw std::out_of_range("Cell::getParam()");
3379 }
3380
3381 void RTLIL::Cell::sort()
3382 {
3383 connections_.sort(sort_by_id_str());
3384 parameters.sort(sort_by_id_str());
3385 attributes.sort(sort_by_id_str());
3386 }
3387
3388 void RTLIL::Cell::check()
3389 {
3390 #ifndef NDEBUG
3391 InternalCellChecker checker(NULL, this);
3392 checker.check();
3393 #endif
3394 }
3395
3396 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
3397 {
3398 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
3399 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
3400 return;
3401
3402 if (type == ID($mux) || type == ID($pmux) || type == ID($bmux)) {
3403 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3404 if (type != ID($mux))
3405 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3406 check();
3407 return;
3408 }
3409
3410 if (type == ID($demux)) {
3411 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3412 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3413 check();
3414 return;
3415 }
3416
3417 if (type == ID($lut) || type == ID($sop)) {
3418 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3419 return;
3420 }
3421
3422 if (type == ID($fa)) {
3423 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3424 return;
3425 }
3426
3427 if (type == ID($lcu)) {
3428 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
3429 return;
3430 }
3431
3432 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
3433
3434 if (connections_.count(ID::A)) {
3435 if (signedness_ab) {
3436 if (set_a_signed)
3437 parameters[ID::A_SIGNED] = true;
3438 else if (parameters.count(ID::A_SIGNED) == 0)
3439 parameters[ID::A_SIGNED] = false;
3440 }
3441 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
3442 }
3443
3444 if (connections_.count(ID::B)) {
3445 if (signedness_ab) {
3446 if (set_b_signed)
3447 parameters[ID::B_SIGNED] = true;
3448 else if (parameters.count(ID::B_SIGNED) == 0)
3449 parameters[ID::B_SIGNED] = false;
3450 }
3451 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
3452 }
3453
3454 if (connections_.count(ID::Y))
3455 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
3456
3457 if (connections_.count(ID::Q))
3458 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
3459
3460 check();
3461 }
3462
3463 bool RTLIL::Cell::has_memid() const
3464 {
3465 return type.in(ID($memwr), ID($memwr_v2), ID($memrd), ID($memrd_v2), ID($meminit), ID($meminit_v2));
3466 }
3467
3468 bool RTLIL::Cell::is_mem_cell() const
3469 {
3470 return type.in(ID($mem), ID($mem_v2)) || has_memid();
3471 }
3472
3473 RTLIL::SigChunk::SigChunk()
3474 {
3475 wire = NULL;
3476 width = 0;
3477 offset = 0;
3478 }
3479
3480 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
3481 {
3482 wire = NULL;
3483 data = value.bits;
3484 width = GetSize(data);
3485 offset = 0;
3486 }
3487
3488 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
3489 {
3490 log_assert(wire != nullptr);
3491 this->wire = wire;
3492 this->width = wire->width;
3493 this->offset = 0;
3494 }
3495
3496 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
3497 {
3498 log_assert(wire != nullptr);
3499 this->wire = wire;
3500 this->width = width;
3501 this->offset = offset;
3502 }
3503
3504 RTLIL::SigChunk::SigChunk(const std::string &str)
3505 {
3506 wire = NULL;
3507 data = RTLIL::Const(str).bits;
3508 width = GetSize(data);
3509 offset = 0;
3510 }
3511
3512 RTLIL::SigChunk::SigChunk(int val, int width)
3513 {
3514 wire = NULL;
3515 data = RTLIL::Const(val, width).bits;
3516 this->width = GetSize(data);
3517 offset = 0;
3518 }
3519
3520 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
3521 {
3522 wire = NULL;
3523 data = RTLIL::Const(bit, width).bits;
3524 this->width = GetSize(data);
3525 offset = 0;
3526 }
3527
3528 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
3529 {
3530 wire = bit.wire;
3531 offset = 0;
3532 if (wire == NULL)
3533 data = RTLIL::Const(bit.data).bits;
3534 else
3535 offset = bit.offset;
3536 width = 1;
3537 }
3538
3539 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
3540 {
3541 *this = sigchunk;
3542 }
3543
3544 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
3545 {
3546 RTLIL::SigChunk ret;
3547 if (wire) {
3548 ret.wire = wire;
3549 ret.offset = this->offset + offset;
3550 ret.width = length;
3551 } else {
3552 for (int i = 0; i < length; i++)
3553 ret.data.push_back(data[offset+i]);
3554 ret.width = length;
3555 }
3556 return ret;
3557 }
3558
3559 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
3560 {
3561 if (wire && other.wire)
3562 if (wire->name != other.wire->name)
3563 return wire->name < other.wire->name;
3564
3565 if (wire != other.wire)
3566 return wire < other.wire;
3567
3568 if (offset != other.offset)
3569 return offset < other.offset;
3570
3571 if (width != other.width)
3572 return width < other.width;
3573
3574 return data < other.data;
3575 }
3576
3577 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
3578 {
3579 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
3580 }
3581
3582 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
3583 {
3584 if (*this == other)
3585 return false;
3586 return true;
3587 }
3588
3589 RTLIL::SigSpec::SigSpec()
3590 {
3591 width_ = 0;
3592 hash_ = 0;
3593 }
3594
3595 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
3596 {
3597 *this = other;
3598 }
3599
3600 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
3601 {
3602 cover("kernel.rtlil.sigspec.init.list");
3603
3604 width_ = 0;
3605 hash_ = 0;
3606
3607 log_assert(parts.size() > 0);
3608 auto ie = parts.begin();
3609 auto it = ie + parts.size() - 1;
3610 while (it >= ie)
3611 append(*it--);
3612 }
3613
3614 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
3615 {
3616 cover("kernel.rtlil.sigspec.assign");
3617
3618 width_ = other.width_;
3619 hash_ = other.hash_;
3620 chunks_ = other.chunks_;
3621 bits_ = other.bits_;
3622 return *this;
3623 }
3624
3625 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
3626 {
3627 cover("kernel.rtlil.sigspec.init.const");
3628
3629 if (GetSize(value) != 0) {
3630 chunks_.emplace_back(value);
3631 width_ = chunks_.back().width;
3632 } else {
3633 width_ = 0;
3634 }
3635 hash_ = 0;
3636 check();
3637 }
3638
3639 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
3640 {
3641 cover("kernel.rtlil.sigspec.init.chunk");
3642
3643 if (chunk.width != 0) {
3644 chunks_.emplace_back(chunk);
3645 width_ = chunks_.back().width;
3646 } else {
3647 width_ = 0;
3648 }
3649 hash_ = 0;
3650 check();
3651 }
3652
3653 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
3654 {
3655 cover("kernel.rtlil.sigspec.init.wire");
3656
3657 if (wire->width != 0) {
3658 chunks_.emplace_back(wire);
3659 width_ = chunks_.back().width;
3660 } else {
3661 width_ = 0;
3662 }
3663 hash_ = 0;
3664 check();
3665 }
3666
3667 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
3668 {
3669 cover("kernel.rtlil.sigspec.init.wire_part");
3670
3671 if (width != 0) {
3672 chunks_.emplace_back(wire, offset, width);
3673 width_ = chunks_.back().width;
3674 } else {
3675 width_ = 0;
3676 }
3677 hash_ = 0;
3678 check();
3679 }
3680
3681 RTLIL::SigSpec::SigSpec(const std::string &str)
3682 {
3683 cover("kernel.rtlil.sigspec.init.str");
3684
3685 if (str.size() != 0) {
3686 chunks_.emplace_back(str);
3687 width_ = chunks_.back().width;
3688 } else {
3689 width_ = 0;
3690 }
3691 hash_ = 0;
3692 check();
3693 }
3694
3695 RTLIL::SigSpec::SigSpec(int val, int width)
3696 {
3697 cover("kernel.rtlil.sigspec.init.int");
3698
3699 if (width != 0)
3700 chunks_.emplace_back(val, width);
3701 width_ = width;
3702 hash_ = 0;
3703 check();
3704 }
3705
3706 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
3707 {
3708 cover("kernel.rtlil.sigspec.init.state");
3709
3710 if (width != 0)
3711 chunks_.emplace_back(bit, width);
3712 width_ = width;
3713 hash_ = 0;
3714 check();
3715 }
3716
3717 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
3718 {
3719 cover("kernel.rtlil.sigspec.init.bit");
3720
3721 if (width != 0) {
3722 if (bit.wire == NULL)
3723 chunks_.emplace_back(bit.data, width);
3724 else
3725 for (int i = 0; i < width; i++)
3726 chunks_.push_back(bit);
3727 }
3728 width_ = width;
3729 hash_ = 0;
3730 check();
3731 }
3732
3733 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
3734 {
3735 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3736
3737 width_ = 0;
3738 hash_ = 0;
3739 for (const auto &c : chunks)
3740 append(c);
3741 check();
3742 }
3743
3744 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
3745 {
3746 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3747
3748 width_ = 0;
3749 hash_ = 0;
3750 for (const auto &bit : bits)
3751 append(bit);
3752 check();
3753 }
3754
3755 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3756 {
3757 cover("kernel.rtlil.sigspec.init.pool_bits");
3758
3759 width_ = 0;
3760 hash_ = 0;
3761 for (const auto &bit : bits)
3762 append(bit);
3763 check();
3764 }
3765
3766 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3767 {
3768 cover("kernel.rtlil.sigspec.init.stdset_bits");
3769
3770 width_ = 0;
3771 hash_ = 0;
3772 for (const auto &bit : bits)
3773 append(bit);
3774 check();
3775 }
3776
3777 RTLIL::SigSpec::SigSpec(bool bit)
3778 {
3779 cover("kernel.rtlil.sigspec.init.bool");
3780
3781 width_ = 0;
3782 hash_ = 0;
3783 append(SigBit(bit));
3784 check();
3785 }
3786
3787 void RTLIL::SigSpec::pack() const
3788 {
3789 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3790
3791 if (that->bits_.empty())
3792 return;
3793
3794 cover("kernel.rtlil.sigspec.convert.pack");
3795 log_assert(that->chunks_.empty());
3796
3797 std::vector<RTLIL::SigBit> old_bits;
3798 old_bits.swap(that->bits_);
3799
3800 RTLIL::SigChunk *last = NULL;
3801 int last_end_offset = 0;
3802
3803 for (auto &bit : old_bits) {
3804 if (last && bit.wire == last->wire) {
3805 if (bit.wire == NULL) {
3806 last->data.push_back(bit.data);
3807 last->width++;
3808 continue;
3809 } else if (last_end_offset == bit.offset) {
3810 last_end_offset++;
3811 last->width++;
3812 continue;
3813 }
3814 }
3815 that->chunks_.push_back(bit);
3816 last = &that->chunks_.back();
3817 last_end_offset = bit.offset + 1;
3818 }
3819
3820 check();
3821 }
3822
3823 void RTLIL::SigSpec::unpack() const
3824 {
3825 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3826
3827 if (that->chunks_.empty())
3828 return;
3829
3830 cover("kernel.rtlil.sigspec.convert.unpack");
3831 log_assert(that->bits_.empty());
3832
3833 that->bits_.reserve(that->width_);
3834 for (auto &c : that->chunks_)
3835 for (int i = 0; i < c.width; i++)
3836 that->bits_.emplace_back(c, i);
3837
3838 that->chunks_.clear();
3839 that->hash_ = 0;
3840 }
3841
3842 void RTLIL::SigSpec::updhash() const
3843 {
3844 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3845
3846 if (that->hash_ != 0)
3847 return;
3848
3849 cover("kernel.rtlil.sigspec.hash");
3850 that->pack();
3851
3852 that->hash_ = mkhash_init;
3853 for (auto &c : that->chunks_)
3854 if (c.wire == NULL) {
3855 for (auto &v : c.data)
3856 that->hash_ = mkhash(that->hash_, v);
3857 } else {
3858 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3859 that->hash_ = mkhash(that->hash_, c.offset);
3860 that->hash_ = mkhash(that->hash_, c.width);
3861 }
3862
3863 if (that->hash_ == 0)
3864 that->hash_ = 1;
3865 }
3866
3867 void RTLIL::SigSpec::sort()
3868 {
3869 unpack();
3870 cover("kernel.rtlil.sigspec.sort");
3871 std::sort(bits_.begin(), bits_.end());
3872 }
3873
3874 void RTLIL::SigSpec::sort_and_unify()
3875 {
3876 unpack();
3877 cover("kernel.rtlil.sigspec.sort_and_unify");
3878
3879 // A copy of the bits vector is used to prevent duplicating the logic from
3880 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3881 // that isn't showing up as significant in profiles.
3882 std::vector<SigBit> unique_bits = bits_;
3883 std::sort(unique_bits.begin(), unique_bits.end());
3884 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3885 unique_bits.erase(last, unique_bits.end());
3886
3887 *this = unique_bits;
3888 }
3889
3890 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3891 {
3892 replace(pattern, with, this);
3893 }
3894
3895 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3896 {
3897 log_assert(other != NULL);
3898 log_assert(width_ == other->width_);
3899 log_assert(pattern.width_ == with.width_);
3900
3901 pattern.unpack();
3902 with.unpack();
3903 unpack();
3904 other->unpack();
3905
3906 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3907 if (pattern.bits_[i].wire != NULL) {
3908 for (int j = 0; j < GetSize(bits_); j++) {
3909 if (bits_[j] == pattern.bits_[i]) {
3910 other->bits_[j] = with.bits_[i];
3911 }
3912 }
3913 }
3914 }
3915
3916 other->check();
3917 }
3918
3919 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3920 {
3921 replace(rules, this);
3922 }
3923
3924 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3925 {
3926 cover("kernel.rtlil.sigspec.replace_dict");
3927
3928 log_assert(other != NULL);
3929 log_assert(width_ == other->width_);
3930
3931 if (rules.empty()) return;
3932 unpack();
3933 other->unpack();
3934
3935 for (int i = 0; i < GetSize(bits_); i++) {
3936 auto it = rules.find(bits_[i]);
3937 if (it != rules.end())
3938 other->bits_[i] = it->second;
3939 }
3940
3941 other->check();
3942 }
3943
3944 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3945 {
3946 replace(rules, this);
3947 }
3948
3949 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3950 {
3951 cover("kernel.rtlil.sigspec.replace_map");
3952
3953 log_assert(other != NULL);
3954 log_assert(width_ == other->width_);
3955
3956 if (rules.empty()) return;
3957 unpack();
3958 other->unpack();
3959
3960 for (int i = 0; i < GetSize(bits_); i++) {
3961 auto it = rules.find(bits_[i]);
3962 if (it != rules.end())
3963 other->bits_[i] = it->second;
3964 }
3965
3966 other->check();
3967 }
3968
3969 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3970 {
3971 remove2(pattern, NULL);
3972 }
3973
3974 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3975 {
3976 RTLIL::SigSpec tmp = *this;
3977 tmp.remove2(pattern, other);
3978 }
3979
3980 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3981 {
3982 if (other)
3983 cover("kernel.rtlil.sigspec.remove_other");
3984 else
3985 cover("kernel.rtlil.sigspec.remove");
3986
3987 unpack();
3988 if (other != NULL) {
3989 log_assert(width_ == other->width_);
3990 other->unpack();
3991 }
3992
3993 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3994 {
3995 if (bits_[i].wire == NULL) continue;
3996
3997 for (auto &pattern_chunk : pattern.chunks())
3998 if (bits_[i].wire == pattern_chunk.wire &&
3999 bits_[i].offset >= pattern_chunk.offset &&
4000 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
4001 bits_.erase(bits_.begin() + i);
4002 width_--;
4003 if (other != NULL) {
4004 other->bits_.erase(other->bits_.begin() + i);
4005 other->width_--;
4006 }
4007 break;
4008 }
4009 }
4010
4011 check();
4012 }
4013
4014 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
4015 {
4016 remove2(pattern, NULL);
4017 }
4018
4019 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
4020 {
4021 RTLIL::SigSpec tmp = *this;
4022 tmp.remove2(pattern, other);
4023 }
4024
4025 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
4026 {
4027 if (other)
4028 cover("kernel.rtlil.sigspec.remove_other");
4029 else
4030 cover("kernel.rtlil.sigspec.remove");
4031
4032 unpack();
4033
4034 if (other != NULL) {
4035 log_assert(width_ == other->width_);
4036 other->unpack();
4037 }
4038
4039 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
4040 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
4041 bits_.erase(bits_.begin() + i);
4042 width_--;
4043 if (other != NULL) {
4044 other->bits_.erase(other->bits_.begin() + i);
4045 other->width_--;
4046 }
4047 }
4048 }
4049
4050 check();
4051 }
4052
4053 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
4054 {
4055 if (other)
4056 cover("kernel.rtlil.sigspec.remove_other");
4057 else
4058 cover("kernel.rtlil.sigspec.remove");
4059
4060 unpack();
4061
4062 if (other != NULL) {
4063 log_assert(width_ == other->width_);
4064 other->unpack();
4065 }
4066
4067 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
4068 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
4069 bits_.erase(bits_.begin() + i);
4070 width_--;
4071 if (other != NULL) {
4072 other->bits_.erase(other->bits_.begin() + i);
4073 other->width_--;
4074 }
4075 }
4076 }
4077
4078 check();
4079 }
4080
4081 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
4082 {
4083 if (other)
4084 cover("kernel.rtlil.sigspec.extract_other");
4085 else
4086 cover("kernel.rtlil.sigspec.extract");
4087
4088 log_assert(other == NULL || width_ == other->width_);
4089
4090 RTLIL::SigSpec ret;
4091 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
4092
4093 for (auto& pattern_chunk : pattern.chunks()) {
4094 if (other) {
4095 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
4096 for (int i = 0; i < width_; i++)
4097 if (bits_match[i].wire &&
4098 bits_match[i].wire == pattern_chunk.wire &&
4099 bits_match[i].offset >= pattern_chunk.offset &&
4100 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
4101 ret.append(bits_other[i]);
4102 } else {
4103 for (int i = 0; i < width_; i++)
4104 if (bits_match[i].wire &&
4105 bits_match[i].wire == pattern_chunk.wire &&
4106 bits_match[i].offset >= pattern_chunk.offset &&
4107 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
4108 ret.append(bits_match[i]);
4109 }
4110 }
4111
4112 ret.check();
4113 return ret;
4114 }
4115
4116 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
4117 {
4118 if (other)
4119 cover("kernel.rtlil.sigspec.extract_other");
4120 else
4121 cover("kernel.rtlil.sigspec.extract");
4122
4123 log_assert(other == NULL || width_ == other->width_);
4124
4125 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
4126 RTLIL::SigSpec ret;
4127
4128 if (other) {
4129 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
4130 for (int i = 0; i < width_; i++)
4131 if (bits_match[i].wire && pattern.count(bits_match[i]))
4132 ret.append(bits_other[i]);
4133 } else {
4134 for (int i = 0; i < width_; i++)
4135 if (bits_match[i].wire && pattern.count(bits_match[i]))
4136 ret.append(bits_match[i]);
4137 }
4138
4139 ret.check();
4140 return ret;
4141 }
4142
4143 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
4144 {
4145 cover("kernel.rtlil.sigspec.replace_pos");
4146
4147 unpack();
4148 with.unpack();
4149
4150 log_assert(offset >= 0);
4151 log_assert(with.width_ >= 0);
4152 log_assert(offset+with.width_ <= width_);
4153
4154 for (int i = 0; i < with.width_; i++)
4155 bits_.at(offset + i) = with.bits_.at(i);
4156
4157 check();
4158 }
4159
4160 void RTLIL::SigSpec::remove_const()
4161 {
4162 if (packed())
4163 {
4164 cover("kernel.rtlil.sigspec.remove_const.packed");
4165
4166 std::vector<RTLIL::SigChunk> new_chunks;
4167 new_chunks.reserve(GetSize(chunks_));
4168
4169 width_ = 0;
4170 for (auto &chunk : chunks_)
4171 if (chunk.wire != NULL) {
4172 if (!new_chunks.empty() &&
4173 new_chunks.back().wire == chunk.wire &&
4174 new_chunks.back().offset + new_chunks.back().width == chunk.offset) {
4175 new_chunks.back().width += chunk.width;
4176 } else {
4177 new_chunks.push_back(chunk);
4178 }
4179 width_ += chunk.width;
4180 }
4181
4182 chunks_.swap(new_chunks);
4183 }
4184 else
4185 {
4186 cover("kernel.rtlil.sigspec.remove_const.unpacked");
4187
4188 std::vector<RTLIL::SigBit> new_bits;
4189 new_bits.reserve(width_);
4190
4191 for (auto &bit : bits_)
4192 if (bit.wire != NULL)
4193 new_bits.push_back(bit);
4194
4195 bits_.swap(new_bits);
4196 width_ = bits_.size();
4197 }
4198
4199 check();
4200 }
4201
4202 void RTLIL::SigSpec::remove(int offset, int length)
4203 {
4204 cover("kernel.rtlil.sigspec.remove_pos");
4205
4206 unpack();
4207
4208 log_assert(offset >= 0);
4209 log_assert(length >= 0);
4210 log_assert(offset + length <= width_);
4211
4212 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
4213 width_ = bits_.size();
4214
4215 check();
4216 }
4217
4218 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
4219 {
4220 unpack();
4221 cover("kernel.rtlil.sigspec.extract_pos");
4222 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
4223 }
4224
4225 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
4226 {
4227 if (signal.width_ == 0)
4228 return;
4229
4230 if (width_ == 0) {
4231 *this = signal;
4232 return;
4233 }
4234
4235 cover("kernel.rtlil.sigspec.append");
4236
4237 if (packed() != signal.packed()) {
4238 pack();
4239 signal.pack();
4240 }
4241
4242 if (packed())
4243 for (auto &other_c : signal.chunks_)
4244 {
4245 auto &my_last_c = chunks_.back();
4246 if (my_last_c.wire == NULL && other_c.wire == NULL) {
4247 auto &this_data = my_last_c.data;
4248 auto &other_data = other_c.data;
4249 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
4250 my_last_c.width += other_c.width;
4251 } else
4252 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
4253 my_last_c.width += other_c.width;
4254 } else
4255 chunks_.push_back(other_c);
4256 }
4257 else
4258 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
4259
4260 width_ += signal.width_;
4261 check();
4262 }
4263
4264 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
4265 {
4266 if (packed())
4267 {
4268 cover("kernel.rtlil.sigspec.append_bit.packed");
4269
4270 if (chunks_.size() == 0)
4271 chunks_.push_back(bit);
4272 else
4273 if (bit.wire == NULL)
4274 if (chunks_.back().wire == NULL) {
4275 chunks_.back().data.push_back(bit.data);
4276 chunks_.back().width++;
4277 } else
4278 chunks_.push_back(bit);
4279 else
4280 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
4281 chunks_.back().width++;
4282 else
4283 chunks_.push_back(bit);
4284 }
4285 else
4286 {
4287 cover("kernel.rtlil.sigspec.append_bit.unpacked");
4288 bits_.push_back(bit);
4289 }
4290
4291 width_++;
4292 check();
4293 }
4294
4295 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
4296 {
4297 cover("kernel.rtlil.sigspec.extend_u0");
4298
4299 pack();
4300
4301 if (width_ > width)
4302 remove(width, width_ - width);
4303
4304 if (width_ < width) {
4305 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
4306 if (!is_signed)
4307 padding = RTLIL::State::S0;
4308 while (width_ < width)
4309 append(padding);
4310 }
4311
4312 }
4313
4314 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
4315 {
4316 cover("kernel.rtlil.sigspec.repeat");
4317
4318 RTLIL::SigSpec sig;
4319 for (int i = 0; i < num; i++)
4320 sig.append(*this);
4321 return sig;
4322 }
4323
4324 #ifndef NDEBUG
4325 void RTLIL::SigSpec::check(Module *mod) const
4326 {
4327 if (width_ > 64)
4328 {
4329 cover("kernel.rtlil.sigspec.check.skip");
4330 }
4331 else if (packed())
4332 {
4333 cover("kernel.rtlil.sigspec.check.packed");
4334
4335 int w = 0;
4336 for (size_t i = 0; i < chunks_.size(); i++) {
4337 const RTLIL::SigChunk &chunk = chunks_[i];
4338 log_assert(chunk.width != 0);
4339 if (chunk.wire == NULL) {
4340 if (i > 0)
4341 log_assert(chunks_[i-1].wire != NULL);
4342 log_assert(chunk.offset == 0);
4343 log_assert(chunk.data.size() == (size_t)chunk.width);
4344 } else {
4345 if (i > 0 && chunks_[i-1].wire == chunk.wire)
4346 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
4347 log_assert(chunk.offset >= 0);
4348 log_assert(chunk.width >= 0);
4349 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
4350 log_assert(chunk.data.size() == 0);
4351 if (mod != nullptr)
4352 log_assert(chunk.wire->module == mod);
4353 }
4354 w += chunk.width;
4355 }
4356 log_assert(w == width_);
4357 log_assert(bits_.empty());
4358 }
4359 else
4360 {
4361 cover("kernel.rtlil.sigspec.check.unpacked");
4362
4363 if (mod != nullptr) {
4364 for (size_t i = 0; i < bits_.size(); i++)
4365 if (bits_[i].wire != nullptr)
4366 log_assert(bits_[i].wire->module == mod);
4367 }
4368
4369 log_assert(width_ == GetSize(bits_));
4370 log_assert(chunks_.empty());
4371 }
4372 }
4373 #endif
4374
4375 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
4376 {
4377 cover("kernel.rtlil.sigspec.comp_lt");
4378
4379 if (this == &other)
4380 return false;
4381
4382 if (width_ != other.width_)
4383 return width_ < other.width_;
4384
4385 pack();
4386 other.pack();
4387
4388 if (chunks_.size() != other.chunks_.size())
4389 return chunks_.size() < other.chunks_.size();
4390
4391 updhash();
4392 other.updhash();
4393
4394 if (hash_ != other.hash_)
4395 return hash_ < other.hash_;
4396
4397 for (size_t i = 0; i < chunks_.size(); i++)
4398 if (chunks_[i] != other.chunks_[i]) {
4399 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4400 return chunks_[i] < other.chunks_[i];
4401 }
4402
4403 cover("kernel.rtlil.sigspec.comp_lt.equal");
4404 return false;
4405 }
4406
4407 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
4408 {
4409 cover("kernel.rtlil.sigspec.comp_eq");
4410
4411 if (this == &other)
4412 return true;
4413
4414 if (width_ != other.width_)
4415 return false;
4416
4417 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4418 // since the RHS will contain one SigChunk of width 0 causing
4419 // the size check below to fail
4420 if (width_ == 0)
4421 return true;
4422
4423 pack();
4424 other.pack();
4425
4426 if (chunks_.size() != other.chunks_.size())
4427 return false;
4428
4429 updhash();
4430 other.updhash();
4431
4432 if (hash_ != other.hash_)
4433 return false;
4434
4435 for (size_t i = 0; i < chunks_.size(); i++)
4436 if (chunks_[i] != other.chunks_[i]) {
4437 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4438 return false;
4439 }
4440
4441 cover("kernel.rtlil.sigspec.comp_eq.equal");
4442 return true;
4443 }
4444
4445 bool RTLIL::SigSpec::is_wire() const
4446 {
4447 cover("kernel.rtlil.sigspec.is_wire");
4448
4449 pack();
4450 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
4451 }
4452
4453 bool RTLIL::SigSpec::is_chunk() const
4454 {
4455 cover("kernel.rtlil.sigspec.is_chunk");
4456
4457 pack();
4458 return GetSize(chunks_) == 1;
4459 }
4460
4461 bool RTLIL::SigSpec::is_fully_const() const
4462 {
4463 cover("kernel.rtlil.sigspec.is_fully_const");
4464
4465 pack();
4466 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4467 if (it->width > 0 && it->wire != NULL)
4468 return false;
4469 return true;
4470 }
4471
4472 bool RTLIL::SigSpec::is_fully_zero() const
4473 {
4474 cover("kernel.rtlil.sigspec.is_fully_zero");
4475
4476 pack();
4477 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4478 if (it->width > 0 && it->wire != NULL)
4479 return false;
4480 for (size_t i = 0; i < it->data.size(); i++)
4481 if (it->data[i] != RTLIL::State::S0)
4482 return false;
4483 }
4484 return true;
4485 }
4486
4487 bool RTLIL::SigSpec::is_fully_ones() const
4488 {
4489 cover("kernel.rtlil.sigspec.is_fully_ones");
4490
4491 pack();
4492 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4493 if (it->width > 0 && it->wire != NULL)
4494 return false;
4495 for (size_t i = 0; i < it->data.size(); i++)
4496 if (it->data[i] != RTLIL::State::S1)
4497 return false;
4498 }
4499 return true;
4500 }
4501
4502 bool RTLIL::SigSpec::is_fully_def() const
4503 {
4504 cover("kernel.rtlil.sigspec.is_fully_def");
4505
4506 pack();
4507 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4508 if (it->width > 0 && it->wire != NULL)
4509 return false;
4510 for (size_t i = 0; i < it->data.size(); i++)
4511 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
4512 return false;
4513 }
4514 return true;
4515 }
4516
4517 bool RTLIL::SigSpec::is_fully_undef() const
4518 {
4519 cover("kernel.rtlil.sigspec.is_fully_undef");
4520
4521 pack();
4522 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4523 if (it->width > 0 && it->wire != NULL)
4524 return false;
4525 for (size_t i = 0; i < it->data.size(); i++)
4526 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
4527 return false;
4528 }
4529 return true;
4530 }
4531
4532 bool RTLIL::SigSpec::has_const() const
4533 {
4534 cover("kernel.rtlil.sigspec.has_const");
4535
4536 pack();
4537 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4538 if (it->width > 0 && it->wire == NULL)
4539 return true;
4540 return false;
4541 }
4542
4543 bool RTLIL::SigSpec::has_marked_bits() const
4544 {
4545 cover("kernel.rtlil.sigspec.has_marked_bits");
4546
4547 pack();
4548 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4549 if (it->width > 0 && it->wire == NULL) {
4550 for (size_t i = 0; i < it->data.size(); i++)
4551 if (it->data[i] == RTLIL::State::Sm)
4552 return true;
4553 }
4554 return false;
4555 }
4556
4557 bool RTLIL::SigSpec::is_onehot(int *pos) const
4558 {
4559 cover("kernel.rtlil.sigspec.is_onehot");
4560
4561 pack();
4562 if (!is_fully_const())
4563 return false;
4564 log_assert(GetSize(chunks_) <= 1);
4565 if (width_)
4566 return RTLIL::Const(chunks_[0].data).is_onehot(pos);
4567 return false;
4568 }
4569
4570 bool RTLIL::SigSpec::as_bool() const
4571 {
4572 cover("kernel.rtlil.sigspec.as_bool");
4573
4574 pack();
4575 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4576 if (width_)
4577 return RTLIL::Const(chunks_[0].data).as_bool();
4578 return false;
4579 }
4580
4581 int RTLIL::SigSpec::as_int(bool is_signed) const
4582 {
4583 cover("kernel.rtlil.sigspec.as_int");
4584
4585 pack();
4586 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4587 if (width_)
4588 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
4589 return 0;
4590 }
4591
4592 std::string RTLIL::SigSpec::as_string() const
4593 {
4594 cover("kernel.rtlil.sigspec.as_string");
4595
4596 pack();
4597 std::string str;
4598 str.reserve(size());
4599 for (size_t i = chunks_.size(); i > 0; i--) {
4600 const RTLIL::SigChunk &chunk = chunks_[i-1];
4601 if (chunk.wire != NULL)
4602 str.append(chunk.width, '?');
4603 else
4604 str += RTLIL::Const(chunk.data).as_string();
4605 }
4606 return str;
4607 }
4608
4609 RTLIL::Const RTLIL::SigSpec::as_const() const
4610 {
4611 cover("kernel.rtlil.sigspec.as_const");
4612
4613 pack();
4614 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4615 if (width_)
4616 return chunks_[0].data;
4617 return RTLIL::Const();
4618 }
4619
4620 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
4621 {
4622 cover("kernel.rtlil.sigspec.as_wire");
4623
4624 pack();
4625 log_assert(is_wire());
4626 return chunks_[0].wire;
4627 }
4628
4629 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
4630 {
4631 cover("kernel.rtlil.sigspec.as_chunk");
4632
4633 pack();
4634 log_assert(is_chunk());
4635 return chunks_[0];
4636 }
4637
4638 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
4639 {
4640 cover("kernel.rtlil.sigspec.as_bit");
4641
4642 log_assert(width_ == 1);
4643 if (packed())
4644 return RTLIL::SigBit(*chunks_.begin());
4645 else
4646 return bits_[0];
4647 }
4648
4649 bool RTLIL::SigSpec::match(const char* pattern) const
4650 {
4651 cover("kernel.rtlil.sigspec.match");
4652
4653 unpack();
4654 log_assert(int(strlen(pattern)) == GetSize(bits_));
4655
4656 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
4657 if (*pattern == ' ')
4658 continue;
4659 if (*pattern == '*') {
4660 if (*it != State::Sz && *it != State::Sx)
4661 return false;
4662 continue;
4663 }
4664 if (*pattern == '0') {
4665 if (*it != State::S0)
4666 return false;
4667 } else
4668 if (*pattern == '1') {
4669 if (*it != State::S1)
4670 return false;
4671 } else
4672 log_abort();
4673 }
4674
4675 return true;
4676 }
4677
4678 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
4679 {
4680 cover("kernel.rtlil.sigspec.to_sigbit_set");
4681
4682 pack();
4683 std::set<RTLIL::SigBit> sigbits;
4684 for (auto &c : chunks_)
4685 for (int i = 0; i < c.width; i++)
4686 sigbits.insert(RTLIL::SigBit(c, i));
4687 return sigbits;
4688 }
4689
4690 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
4691 {
4692 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4693
4694 pack();
4695 pool<RTLIL::SigBit> sigbits;
4696 sigbits.reserve(size());
4697 for (auto &c : chunks_)
4698 for (int i = 0; i < c.width; i++)
4699 sigbits.insert(RTLIL::SigBit(c, i));
4700 return sigbits;
4701 }
4702
4703 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
4704 {
4705 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4706
4707 unpack();
4708 return bits_;
4709 }
4710
4711 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
4712 {
4713 cover("kernel.rtlil.sigspec.to_sigbit_map");
4714
4715 unpack();
4716 other.unpack();
4717
4718 log_assert(width_ == other.width_);
4719
4720 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
4721 for (int i = 0; i < width_; i++)
4722 new_map[bits_[i]] = other.bits_[i];
4723
4724 return new_map;
4725 }
4726
4727 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
4728 {
4729 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4730
4731 unpack();
4732 other.unpack();
4733
4734 log_assert(width_ == other.width_);
4735
4736 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
4737 new_map.reserve(size());
4738 for (int i = 0; i < width_; i++)
4739 new_map[bits_[i]] = other.bits_[i];
4740
4741 return new_map;
4742 }
4743
4744 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
4745 {
4746 size_t start = 0, end = 0;
4747 while ((end = text.find(sep, start)) != std::string::npos) {
4748 tokens.push_back(text.substr(start, end - start));
4749 start = end + 1;
4750 }
4751 tokens.push_back(text.substr(start));
4752 }
4753
4754 static int sigspec_parse_get_dummy_line_num()
4755 {
4756 return 0;
4757 }
4758
4759 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4760 {
4761 cover("kernel.rtlil.sigspec.parse");
4762
4763 AST::current_filename = "input";
4764
4765 std::vector<std::string> tokens;
4766 sigspec_parse_split(tokens, str, ',');
4767
4768 sig = RTLIL::SigSpec();
4769 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
4770 {
4771 std::string netname = tokens[tokidx];
4772 std::string indices;
4773
4774 if (netname.size() == 0)
4775 continue;
4776
4777 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4778 cover("kernel.rtlil.sigspec.parse.const");
4779 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4780 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4781 if (ast == NULL)
4782 return false;
4783 sig.append(RTLIL::Const(ast->bits));
4784 delete ast;
4785 continue;
4786 }
4787
4788 if (module == NULL)
4789 return false;
4790
4791 cover("kernel.rtlil.sigspec.parse.net");
4792
4793 if (netname[0] != '$' && netname[0] != '\\')
4794 netname = "\\" + netname;
4795
4796 if (module->wires_.count(netname) == 0) {
4797 size_t indices_pos = netname.size()-1;
4798 if (indices_pos > 2 && netname[indices_pos] == ']')
4799 {
4800 indices_pos--;
4801 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4802 if (indices_pos > 0 && netname[indices_pos] == ':') {
4803 indices_pos--;
4804 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4805 }
4806 if (indices_pos > 0 && netname[indices_pos] == '[') {
4807 indices = netname.substr(indices_pos);
4808 netname = netname.substr(0, indices_pos);
4809 }
4810 }
4811 }
4812
4813 if (module->wires_.count(netname) == 0)
4814 return false;
4815
4816 RTLIL::Wire *wire = module->wires_.at(netname);
4817 if (!indices.empty()) {
4818 std::vector<std::string> index_tokens;
4819 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4820 if (index_tokens.size() == 1) {
4821 cover("kernel.rtlil.sigspec.parse.bit_sel");
4822 int a = atoi(index_tokens.at(0).c_str());
4823 if (a < 0 || a >= wire->width)
4824 return false;
4825 sig.append(RTLIL::SigSpec(wire, a));
4826 } else {
4827 cover("kernel.rtlil.sigspec.parse.part_sel");
4828 int a = atoi(index_tokens.at(0).c_str());
4829 int b = atoi(index_tokens.at(1).c_str());
4830 if (a > b) {
4831 int tmp = a;
4832 a = b, b = tmp;
4833 }
4834 if (a < 0 || a >= wire->width)
4835 return false;
4836 if (b < 0 || b >= wire->width)
4837 return false;
4838 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4839 }
4840 } else
4841 sig.append(wire);
4842 }
4843
4844 return true;
4845 }
4846
4847 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4848 {
4849 if (str.empty() || str[0] != '@')
4850 return parse(sig, module, str);
4851
4852 cover("kernel.rtlil.sigspec.parse.sel");
4853
4854 str = RTLIL::escape_id(str.substr(1));
4855 if (design->selection_vars.count(str) == 0)
4856 return false;
4857
4858 sig = RTLIL::SigSpec();
4859 RTLIL::Selection &sel = design->selection_vars.at(str);
4860 for (auto &it : module->wires_)
4861 if (sel.selected_member(module->name, it.first))
4862 sig.append(it.second);
4863
4864 return true;
4865 }
4866
4867 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4868 {
4869 if (str == "0") {
4870 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4871 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4872 return true;
4873 }
4874
4875 if (str == "~0") {
4876 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4877 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4878 return true;
4879 }
4880
4881 if (lhs.chunks_.size() == 1) {
4882 char *p = (char*)str.c_str(), *endptr;
4883 long int val = strtol(p, &endptr, 10);
4884 if (endptr && endptr != p && *endptr == 0) {
4885 sig = RTLIL::SigSpec(val, lhs.width_);
4886 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4887 return true;
4888 }
4889 }
4890
4891 return parse(sig, module, str);
4892 }
4893
4894 RTLIL::CaseRule::~CaseRule()
4895 {
4896 for (auto it = switches.begin(); it != switches.end(); it++)
4897 delete *it;
4898 }
4899
4900 bool RTLIL::CaseRule::empty() const
4901 {
4902 return actions.empty() && switches.empty();
4903 }
4904
4905 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4906 {
4907 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4908 new_caserule->compare = compare;
4909 new_caserule->actions = actions;
4910 for (auto &it : switches)
4911 new_caserule->switches.push_back(it->clone());
4912 return new_caserule;
4913 }
4914
4915 RTLIL::SwitchRule::~SwitchRule()
4916 {
4917 for (auto it = cases.begin(); it != cases.end(); it++)
4918 delete *it;
4919 }
4920
4921 bool RTLIL::SwitchRule::empty() const
4922 {
4923 return cases.empty();
4924 }
4925
4926 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4927 {
4928 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4929 new_switchrule->signal = signal;
4930 new_switchrule->attributes = attributes;
4931 for (auto &it : cases)
4932 new_switchrule->cases.push_back(it->clone());
4933 return new_switchrule;
4934
4935 }
4936
4937 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4938 {
4939 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4940 new_syncrule->type = type;
4941 new_syncrule->signal = signal;
4942 new_syncrule->actions = actions;
4943 new_syncrule->mem_write_actions = mem_write_actions;
4944 return new_syncrule;
4945 }
4946
4947 RTLIL::Process::~Process()
4948 {
4949 for (auto it = syncs.begin(); it != syncs.end(); it++)
4950 delete *it;
4951 }
4952
4953 RTLIL::Process *RTLIL::Process::clone() const
4954 {
4955 RTLIL::Process *new_proc = new RTLIL::Process;
4956
4957 new_proc->name = name;
4958 new_proc->attributes = attributes;
4959
4960 RTLIL::CaseRule *rc_ptr = root_case.clone();
4961 new_proc->root_case = *rc_ptr;
4962 rc_ptr->switches.clear();
4963 delete rc_ptr;
4964
4965 for (auto &it : syncs)
4966 new_proc->syncs.push_back(it->clone());
4967
4968 return new_proc;
4969 }
4970
4971 #ifdef WITH_PYTHON
4972 RTLIL::Memory::~Memory()
4973 {
4974 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4975 }
4976 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4977 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4978 {
4979 return &all_memorys;
4980 }
4981 #endif
4982 YOSYS_NAMESPACE_END