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Fix leak removing cells during ABC integration; also preserve attr
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else {
222 const auto it = attributes.find(id);
223 if (it != attributes.end())
224 attributes.erase(it);
225 }
226 }
227
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
229 {
230 const auto it = attributes.find(id);
231 if (it == attributes.end())
232 return false;
233 return it->second.as_bool();
234 }
235
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 string attrval;
239 for (auto &s : data) {
240 if (!attrval.empty())
241 attrval += "|";
242 attrval += s;
243 }
244 attributes[id] = RTLIL::Const(attrval);
245 }
246
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 pool<string> union_data = get_strpool_attribute(id);
250 union_data.insert(data.begin(), data.end());
251 if (!union_data.empty())
252 set_strpool_attribute(id, union_data);
253 }
254
255 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
256 {
257 pool<string> data;
258 if (attributes.count(id) != 0)
259 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
260 data.insert(s);
261 return data;
262 }
263
264 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
265 {
266 if (src.empty())
267 attributes.erase("\\src");
268 else
269 attributes["\\src"] = src;
270 }
271
272 std::string RTLIL::AttrObject::get_src_attribute() const
273 {
274 std::string src;
275 if (attributes.count("\\src"))
276 src = attributes.at("\\src").decode_string();
277 return src;
278 }
279
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 if (selected_members.count(mod_name) > 0)
287 return true;
288 return false;
289 }
290
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 return false;
298 }
299
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (full_selection)
303 return true;
304 if (selected_modules.count(mod_name) > 0)
305 return true;
306 if (selected_members.count(mod_name) > 0)
307 if (selected_members.at(mod_name).count(memb_name) > 0)
308 return true;
309 return false;
310 }
311
312 void RTLIL::Selection::optimize(RTLIL::Design *design)
313 {
314 if (full_selection) {
315 selected_modules.clear();
316 selected_members.clear();
317 return;
318 }
319
320 std::vector<RTLIL::IdString> del_list, add_list;
321
322 del_list.clear();
323 for (auto mod_name : selected_modules) {
324 if (design->modules_.count(mod_name) == 0)
325 del_list.push_back(mod_name);
326 selected_members.erase(mod_name);
327 }
328 for (auto mod_name : del_list)
329 selected_modules.erase(mod_name);
330
331 del_list.clear();
332 for (auto &it : selected_members)
333 if (design->modules_.count(it.first) == 0)
334 del_list.push_back(it.first);
335 for (auto mod_name : del_list)
336 selected_members.erase(mod_name);
337
338 for (auto &it : selected_members) {
339 del_list.clear();
340 for (auto memb_name : it.second)
341 if (design->modules_[it.first]->count_id(memb_name) == 0)
342 del_list.push_back(memb_name);
343 for (auto memb_name : del_list)
344 it.second.erase(memb_name);
345 }
346
347 del_list.clear();
348 add_list.clear();
349 for (auto &it : selected_members)
350 if (it.second.size() == 0)
351 del_list.push_back(it.first);
352 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
353 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
354 add_list.push_back(it.first);
355 for (auto mod_name : del_list)
356 selected_members.erase(mod_name);
357 for (auto mod_name : add_list) {
358 selected_members.erase(mod_name);
359 selected_modules.insert(mod_name);
360 }
361
362 if (selected_modules.size() == design->modules_.size()) {
363 full_selection = true;
364 selected_modules.clear();
365 selected_members.clear();
366 }
367 }
368
369 RTLIL::Design::Design()
370 {
371 static unsigned int hashidx_count = 123456789;
372 hashidx_count = mkhash_xorshift(hashidx_count);
373 hashidx_ = hashidx_count;
374
375 refcount_modules_ = 0;
376 selection_stack.push_back(RTLIL::Selection());
377
378 #ifdef WITH_PYTHON
379 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
380 #endif
381 }
382
383 RTLIL::Design::~Design()
384 {
385 for (auto it = modules_.begin(); it != modules_.end(); ++it)
386 delete it->second;
387 for (auto n : verilog_packages)
388 delete n;
389 for (auto n : verilog_globals)
390 delete n;
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->erase(hashidx_);
393 #endif
394 }
395
396 #ifdef WITH_PYTHON
397 static std::map<unsigned int, RTLIL::Design*> all_designs;
398 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
399 {
400 return &all_designs;
401 }
402 #endif
403
404 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
405 {
406 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
407 }
408
409 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
410 {
411 return modules_.count(name) ? modules_.at(name) : NULL;
412 }
413
414 RTLIL::Module *RTLIL::Design::top_module()
415 {
416 RTLIL::Module *module = nullptr;
417 int module_count = 0;
418
419 for (auto mod : selected_modules()) {
420 if (mod->get_bool_attribute("\\top"))
421 return mod;
422 module_count++;
423 module = mod;
424 }
425
426 return module_count == 1 ? module : nullptr;
427 }
428
429 void RTLIL::Design::add(RTLIL::Module *module)
430 {
431 log_assert(modules_.count(module->name) == 0);
432 log_assert(refcount_modules_ == 0);
433 modules_[module->name] = module;
434 module->design = this;
435
436 for (auto mon : monitors)
437 mon->notify_module_add(module);
438
439 if (yosys_xtrace) {
440 log("#X# New Module: %s\n", log_id(module));
441 log_backtrace("-X- ", yosys_xtrace-1);
442 }
443 }
444
445 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
446 {
447 log_assert(modules_.count(name) == 0);
448 log_assert(refcount_modules_ == 0);
449
450 RTLIL::Module *module = new RTLIL::Module;
451 modules_[name] = module;
452 module->design = this;
453 module->name = name;
454
455 for (auto mon : monitors)
456 mon->notify_module_add(module);
457
458 if (yosys_xtrace) {
459 log("#X# New Module: %s\n", log_id(module));
460 log_backtrace("-X- ", yosys_xtrace-1);
461 }
462
463 return module;
464 }
465
466 void RTLIL::Design::scratchpad_unset(std::string varname)
467 {
468 scratchpad.erase(varname);
469 }
470
471 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
472 {
473 scratchpad[varname] = stringf("%d", value);
474 }
475
476 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
477 {
478 scratchpad[varname] = value ? "true" : "false";
479 }
480
481 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
482 {
483 scratchpad[varname] = value;
484 }
485
486 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
487 {
488 if (scratchpad.count(varname) == 0)
489 return default_value;
490
491 std::string str = scratchpad.at(varname);
492
493 if (str == "0" || str == "false")
494 return 0;
495
496 if (str == "1" || str == "true")
497 return 1;
498
499 char *endptr = nullptr;
500 long int parsed_value = strtol(str.c_str(), &endptr, 10);
501 return *endptr ? default_value : parsed_value;
502 }
503
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
505 {
506 if (scratchpad.count(varname) == 0)
507 return default_value;
508
509 std::string str = scratchpad.at(varname);
510
511 if (str == "0" || str == "false")
512 return false;
513
514 if (str == "1" || str == "true")
515 return true;
516
517 return default_value;
518 }
519
520 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
521 {
522 if (scratchpad.count(varname) == 0)
523 return default_value;
524 return scratchpad.at(varname);
525 }
526
527 void RTLIL::Design::remove(RTLIL::Module *module)
528 {
529 for (auto mon : monitors)
530 mon->notify_module_del(module);
531
532 if (yosys_xtrace) {
533 log("#X# Remove Module: %s\n", log_id(module));
534 log_backtrace("-X- ", yosys_xtrace-1);
535 }
536
537 log_assert(modules_.at(module->name) == module);
538 modules_.erase(module->name);
539 delete module;
540 }
541
542 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
543 {
544 modules_.erase(module->name);
545 module->name = new_name;
546 add(module);
547 }
548
549 void RTLIL::Design::sort()
550 {
551 scratchpad.sort();
552 modules_.sort(sort_by_id_str());
553 for (auto &it : modules_)
554 it.second->sort();
555 }
556
557 void RTLIL::Design::check()
558 {
559 #ifndef NDEBUG
560 for (auto &it : modules_) {
561 log_assert(this == it.second->design);
562 log_assert(it.first == it.second->name);
563 log_assert(!it.first.empty());
564 it.second->check();
565 }
566 #endif
567 }
568
569 void RTLIL::Design::optimize()
570 {
571 for (auto &it : modules_)
572 it.second->optimize();
573 for (auto &it : selection_stack)
574 it.optimize(this);
575 for (auto &it : selection_vars)
576 it.second.optimize(this);
577 }
578
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
580 {
581 if (!selected_active_module.empty() && mod_name != selected_active_module)
582 return false;
583 if (selection_stack.size() == 0)
584 return true;
585 return selection_stack.back().selected_module(mod_name);
586 }
587
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
589 {
590 if (!selected_active_module.empty() && mod_name != selected_active_module)
591 return false;
592 if (selection_stack.size() == 0)
593 return true;
594 return selection_stack.back().selected_whole_module(mod_name);
595 }
596
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
598 {
599 if (!selected_active_module.empty() && mod_name != selected_active_module)
600 return false;
601 if (selection_stack.size() == 0)
602 return true;
603 return selection_stack.back().selected_member(mod_name, memb_name);
604 }
605
606 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
607 {
608 return selected_module(mod->name);
609 }
610
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
612 {
613 return selected_whole_module(mod->name);
614 }
615
616 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
617 {
618 std::vector<RTLIL::Module*> result;
619 result.reserve(modules_.size());
620 for (auto &it : modules_)
621 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
622 result.push_back(it.second);
623 return result;
624 }
625
626 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
627 {
628 std::vector<RTLIL::Module*> result;
629 result.reserve(modules_.size());
630 for (auto &it : modules_)
631 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
632 result.push_back(it.second);
633 return result;
634 }
635
636 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
637 {
638 std::vector<RTLIL::Module*> result;
639 result.reserve(modules_.size());
640 for (auto &it : modules_)
641 if (it.second->get_blackbox_attribute())
642 continue;
643 else if (selected_whole_module(it.first))
644 result.push_back(it.second);
645 else if (selected_module(it.first))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
647 return result;
648 }
649
650 RTLIL::Module::Module()
651 {
652 static unsigned int hashidx_count = 123456789;
653 hashidx_count = mkhash_xorshift(hashidx_count);
654 hashidx_ = hashidx_count;
655
656 design = nullptr;
657 refcount_wires_ = 0;
658 refcount_cells_ = 0;
659
660 #ifdef WITH_PYTHON
661 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
662 #endif
663 }
664
665 RTLIL::Module::~Module()
666 {
667 for (auto it = wires_.begin(); it != wires_.end(); ++it)
668 delete it->second;
669 for (auto it = memories.begin(); it != memories.end(); ++it)
670 delete it->second;
671 for (auto it = cells_.begin(); it != cells_.end(); ++it)
672 delete it->second;
673 for (auto it = processes.begin(); it != processes.end(); ++it)
674 delete it->second;
675 #ifdef WITH_PYTHON
676 RTLIL::Module::get_all_modules()->erase(hashidx_);
677 #endif
678 }
679
680 #ifdef WITH_PYTHON
681 static std::map<unsigned int, RTLIL::Module*> all_modules;
682 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
683 {
684 return &all_modules;
685 }
686 #endif
687
688 void RTLIL::Module::makeblackbox()
689 {
690 pool<RTLIL::Wire*> delwires;
691
692 for (auto it = wires_.begin(); it != wires_.end(); ++it)
693 if (!it->second->port_input && !it->second->port_output)
694 delwires.insert(it->second);
695
696 for (auto it = memories.begin(); it != memories.end(); ++it)
697 delete it->second;
698 memories.clear();
699
700 for (auto it = cells_.begin(); it != cells_.end(); ++it)
701 delete it->second;
702 cells_.clear();
703
704 for (auto it = processes.begin(); it != processes.end(); ++it)
705 delete it->second;
706 processes.clear();
707
708 remove(delwires);
709 set_bool_attribute("\\blackbox");
710 }
711
712 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
713 {
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
715 }
716
717 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
718 {
719 if (mayfail)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
722 }
723
724
725 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
726 {
727 if (mayfail)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
730 }
731
732 size_t RTLIL::Module::count_id(RTLIL::IdString id)
733 {
734 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
735 }
736
737 #ifndef NDEBUG
738 namespace {
739 struct InternalCellChecker
740 {
741 RTLIL::Module *module;
742 RTLIL::Cell *cell;
743 pool<RTLIL::IdString> expected_params, expected_ports;
744
745 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
746
747 void error(int linenr)
748 {
749 std::stringstream buf;
750 ILANG_BACKEND::dump_cell(buf, " ", cell);
751
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module ? module->name.c_str() : "", module ? "." : "",
754 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
755 }
756
757 int param(const char *name)
758 {
759 if (cell->parameters.count(name) == 0)
760 error(__LINE__);
761 expected_params.insert(name);
762 return cell->parameters.at(name).as_int();
763 }
764
765 int param_bool(const char *name)
766 {
767 int v = param(name);
768 if (cell->parameters.at(name).bits.size() > 32)
769 error(__LINE__);
770 if (v != 0 && v != 1)
771 error(__LINE__);
772 return v;
773 }
774
775 void param_bits(const char *name, int width)
776 {
777 param(name);
778 if (int(cell->parameters.at(name).bits.size()) != width)
779 error(__LINE__);
780 }
781
782 void port(const char *name, int width)
783 {
784 if (!cell->hasPort(name))
785 error(__LINE__);
786 if (cell->getPort(name).size() != width)
787 error(__LINE__);
788 expected_ports.insert(name);
789 }
790
791 void check_expected(bool check_matched_sign = true)
792 {
793 for (auto &para : cell->parameters)
794 if (expected_params.count(para.first) == 0)
795 error(__LINE__);
796 for (auto &conn : cell->connections())
797 if (expected_ports.count(conn.first) == 0)
798 error(__LINE__);
799
800 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
801 bool a_is_signed = param("\\A_SIGNED") != 0;
802 bool b_is_signed = param("\\B_SIGNED") != 0;
803 if (a_is_signed != b_is_signed)
804 error(__LINE__);
805 }
806 }
807
808 void check_gate(const char *ports)
809 {
810 if (cell->parameters.size() != 0)
811 error(__LINE__);
812
813 for (const char *p = ports; *p; p++) {
814 char portname[3] = { '\\', *p, 0 };
815 if (!cell->hasPort(portname))
816 error(__LINE__);
817 if (cell->getPort(portname).size() != 1)
818 error(__LINE__);
819 }
820
821 for (auto &conn : cell->connections()) {
822 if (conn.first.size() != 2 || conn.first[0] != '\\')
823 error(__LINE__);
824 if (strchr(ports, conn.first[1]) == NULL)
825 error(__LINE__);
826 }
827 }
828
829 void check()
830 {
831 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
832 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
833 return;
834
835 if (cell->type.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
839 check_expected();
840 return;
841 }
842
843 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
857 check_expected();
858 return;
859 }
860
861 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
868 return;
869 }
870
871 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell->type != "$pow");
888 return;
889 }
890
891 if (cell->type == "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
904 port("\\CI", 1);
905 port("\\CO", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
915 port("\\CI", 1);
916 port("\\BI", 1);
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
920 check_expected();
921 return;
922 }
923
924 if (cell->type == "$macc") {
925 param("\\CONFIG");
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
930 check_expected();
931 Macc().from_cell(cell);
932 return;
933 }
934
935 if (cell->type == "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
939 check_expected();
940 return;
941 }
942
943 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
950 return;
951 }
952
953 if (cell->type == "$slice") {
954 param("\\OFFSET");
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
958 error(__LINE__);
959 check_expected();
960 return;
961 }
962
963 if (cell->type == "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
974 port("\\S", 1);
975 port("\\Y", param("\\WIDTH"));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
985 check_expected();
986 return;
987 }
988
989 if (cell->type == "$lut") {
990 param("\\LUT");
991 port("\\A", param("\\WIDTH"));
992 port("\\Y", 1);
993 check_expected();
994 return;
995 }
996
997 if (cell->type == "$sop") {
998 param("\\DEPTH");
999 param("\\TABLE");
1000 port("\\A", param("\\WIDTH"));
1001 port("\\Y", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1012 check_expected();
1013 return;
1014 }
1015
1016 if (cell->type == "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == "$dff") {
1024 param_bool("\\CLK_POLARITY");
1025 port("\\CLK", 1);
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1028 check_expected();
1029 return;
1030 }
1031
1032 if (cell->type == "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1035 port("\\CLK", 1);
1036 port("\\EN", 1);
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1047 port("\\CLK", 1);
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1070 port("\\EN", 1);
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1081 port("\\EN", 1);
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == "$fsm") {
1091 param("\\NAME");
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1101 port("\\CLK", 1);
1102 port("\\ARST", 1);
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == "$memrd") {
1110 param("\\MEMID");
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1114 port("\\CLK", 1);
1115 port("\\EN", 1);
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == "$memwr") {
1123 param("\\MEMID");
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1127 port("\\CLK", 1);
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1131 check_expected();
1132 return;
1133 }
1134
1135 if (cell->type == "$meminit") {
1136 param("\\MEMID");
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == "$mem") {
1145 param("\\MEMID");
1146 param("\\SIZE");
1147 param("\\OFFSET");
1148 param("\\INIT");
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1169 port("\\EN", 1);
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1175 port("\\A", 1);
1176 port("\\EN", 1);
1177 check_expected();
1178 return;
1179 }
1180
1181 if (cell->type == "$initstate") {
1182 port("\\Y", 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1189 check_expected();
1190 return;
1191 }
1192
1193 if (cell->type == "$equiv") {
1194 port("\\A", 1);
1195 port("\\B", 1);
1196 port("\\Y", 1);
1197 check_expected();
1198 return;
1199 }
1200
1201 if (cell->type.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1211 port("\\EN", 1);
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell->type == "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1220 }
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == "$specrule") {
1226 param("\\TYPE");
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1231 param("\\T_LIMIT");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1242 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1243 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1253 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1254 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1255 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1256
1257 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1258
1259 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1260 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1261 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1262
1263 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1264 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1265 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1266 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1267
1268 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1269 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1270 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1271
1272 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1273 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1274 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1275 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1276
1277 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1281 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1282 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1283 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1284 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1285
1286 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1290 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1291 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1292 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1293 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1294
1295 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1296 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1297
1298 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1302 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1303 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1304 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1305 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1306
1307 error(__LINE__);
1308 }
1309 };
1310 }
1311 #endif
1312
1313 void RTLIL::Module::sort()
1314 {
1315 wires_.sort(sort_by_id_str());
1316 cells_.sort(sort_by_id_str());
1317 avail_parameters.sort(sort_by_id_str());
1318 memories.sort(sort_by_id_str());
1319 processes.sort(sort_by_id_str());
1320 for (auto &it : cells_)
1321 it.second->sort();
1322 for (auto &it : wires_)
1323 it.second->attributes.sort(sort_by_id_str());
1324 for (auto &it : memories)
1325 it.second->attributes.sort(sort_by_id_str());
1326 }
1327
1328 void RTLIL::Module::check()
1329 {
1330 #ifndef NDEBUG
1331 std::vector<bool> ports_declared;
1332 for (auto &it : wires_) {
1333 log_assert(this == it.second->module);
1334 log_assert(it.first == it.second->name);
1335 log_assert(!it.first.empty());
1336 log_assert(it.second->width >= 0);
1337 log_assert(it.second->port_id >= 0);
1338 for (auto &it2 : it.second->attributes)
1339 log_assert(!it2.first.empty());
1340 if (it.second->port_id) {
1341 log_assert(GetSize(ports) >= it.second->port_id);
1342 log_assert(ports.at(it.second->port_id-1) == it.first);
1343 log_assert(it.second->port_input || it.second->port_output);
1344 if (GetSize(ports_declared) < it.second->port_id)
1345 ports_declared.resize(it.second->port_id);
1346 log_assert(ports_declared[it.second->port_id-1] == false);
1347 ports_declared[it.second->port_id-1] = true;
1348 } else
1349 log_assert(!it.second->port_input && !it.second->port_output);
1350 }
1351 for (auto port_declared : ports_declared)
1352 log_assert(port_declared == true);
1353 log_assert(GetSize(ports) == GetSize(ports_declared));
1354
1355 for (auto &it : memories) {
1356 log_assert(it.first == it.second->name);
1357 log_assert(!it.first.empty());
1358 log_assert(it.second->width >= 0);
1359 log_assert(it.second->size >= 0);
1360 for (auto &it2 : it.second->attributes)
1361 log_assert(!it2.first.empty());
1362 }
1363
1364 for (auto &it : cells_) {
1365 log_assert(this == it.second->module);
1366 log_assert(it.first == it.second->name);
1367 log_assert(!it.first.empty());
1368 log_assert(!it.second->type.empty());
1369 for (auto &it2 : it.second->connections()) {
1370 log_assert(!it2.first.empty());
1371 it2.second.check();
1372 }
1373 for (auto &it2 : it.second->attributes)
1374 log_assert(!it2.first.empty());
1375 for (auto &it2 : it.second->parameters)
1376 log_assert(!it2.first.empty());
1377 InternalCellChecker checker(this, it.second);
1378 checker.check();
1379 }
1380
1381 for (auto &it : processes) {
1382 log_assert(it.first == it.second->name);
1383 log_assert(!it.first.empty());
1384 // FIXME: More checks here..
1385 }
1386
1387 for (auto &it : connections_) {
1388 log_assert(it.first.size() == it.second.size());
1389 log_assert(!it.first.has_const());
1390 it.first.check();
1391 it.second.check();
1392 }
1393
1394 for (auto &it : attributes)
1395 log_assert(!it.first.empty());
1396 #endif
1397 }
1398
1399 void RTLIL::Module::optimize()
1400 {
1401 }
1402
1403 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1404 {
1405 log_assert(new_mod->refcount_wires_ == 0);
1406 log_assert(new_mod->refcount_cells_ == 0);
1407
1408 new_mod->avail_parameters = avail_parameters;
1409
1410 for (auto &conn : connections_)
1411 new_mod->connect(conn);
1412
1413 for (auto &attr : attributes)
1414 new_mod->attributes[attr.first] = attr.second;
1415
1416 for (auto &it : wires_)
1417 new_mod->addWire(it.first, it.second);
1418
1419 for (auto &it : memories)
1420 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1421
1422 for (auto &it : cells_)
1423 new_mod->addCell(it.first, it.second);
1424
1425 for (auto &it : processes)
1426 new_mod->processes[it.first] = it.second->clone();
1427
1428 struct RewriteSigSpecWorker
1429 {
1430 RTLIL::Module *mod;
1431 void operator()(RTLIL::SigSpec &sig)
1432 {
1433 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1434 for (auto &c : chunks)
1435 if (c.wire != NULL)
1436 c.wire = mod->wires_.at(c.wire->name);
1437 sig = chunks;
1438 }
1439 };
1440
1441 RewriteSigSpecWorker rewriteSigSpecWorker;
1442 rewriteSigSpecWorker.mod = new_mod;
1443 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1444 new_mod->fixup_ports();
1445 }
1446
1447 RTLIL::Module *RTLIL::Module::clone() const
1448 {
1449 RTLIL::Module *new_mod = new RTLIL::Module;
1450 new_mod->name = name;
1451 cloneInto(new_mod);
1452 return new_mod;
1453 }
1454
1455 bool RTLIL::Module::has_memories() const
1456 {
1457 return !memories.empty();
1458 }
1459
1460 bool RTLIL::Module::has_processes() const
1461 {
1462 return !processes.empty();
1463 }
1464
1465 bool RTLIL::Module::has_memories_warn() const
1466 {
1467 if (!memories.empty())
1468 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1469 return !memories.empty();
1470 }
1471
1472 bool RTLIL::Module::has_processes_warn() const
1473 {
1474 if (!processes.empty())
1475 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1476 return !processes.empty();
1477 }
1478
1479 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1480 {
1481 std::vector<RTLIL::Wire*> result;
1482 result.reserve(wires_.size());
1483 for (auto &it : wires_)
1484 if (design->selected(this, it.second))
1485 result.push_back(it.second);
1486 return result;
1487 }
1488
1489 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1490 {
1491 std::vector<RTLIL::Cell*> result;
1492 result.reserve(wires_.size());
1493 for (auto &it : cells_)
1494 if (design->selected(this, it.second))
1495 result.push_back(it.second);
1496 return result;
1497 }
1498
1499 void RTLIL::Module::add(RTLIL::Wire *wire)
1500 {
1501 log_assert(!wire->name.empty());
1502 log_assert(count_id(wire->name) == 0);
1503 log_assert(refcount_wires_ == 0);
1504 wires_[wire->name] = wire;
1505 wire->module = this;
1506 }
1507
1508 void RTLIL::Module::add(RTLIL::Cell *cell)
1509 {
1510 log_assert(!cell->name.empty());
1511 log_assert(count_id(cell->name) == 0);
1512 log_assert(refcount_cells_ == 0);
1513 cells_[cell->name] = cell;
1514 cell->module = this;
1515 }
1516
1517 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1518 {
1519 log_assert(refcount_wires_ == 0);
1520
1521 struct DeleteWireWorker
1522 {
1523 RTLIL::Module *module;
1524 const pool<RTLIL::Wire*> *wires_p;
1525
1526 void operator()(RTLIL::SigSpec &sig) {
1527 std::vector<RTLIL::SigChunk> chunks = sig;
1528 for (auto &c : chunks)
1529 if (c.wire != NULL && wires_p->count(c.wire)) {
1530 c.wire = module->addWire(NEW_ID, c.width);
1531 c.offset = 0;
1532 }
1533 sig = chunks;
1534 }
1535
1536 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1537 log_assert(GetSize(lhs) == GetSize(rhs));
1538 RTLIL::SigSpec new_lhs, new_rhs;
1539 for (int i = 0; i < GetSize(lhs); i++) {
1540 RTLIL::SigBit lhs_bit = lhs[i];
1541 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1542 continue;
1543 RTLIL::SigBit rhs_bit = rhs[i];
1544 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1545 continue;
1546 new_lhs.append(lhs_bit);
1547 new_rhs.append(rhs_bit);
1548 }
1549 lhs = new_lhs;
1550 rhs = new_rhs;
1551 }
1552 };
1553
1554 DeleteWireWorker delete_wire_worker;
1555 delete_wire_worker.module = this;
1556 delete_wire_worker.wires_p = &wires;
1557 rewrite_sigspecs2(delete_wire_worker);
1558
1559 for (auto &it : wires) {
1560 log_assert(wires_.count(it->name) != 0);
1561 wires_.erase(it->name);
1562 delete it;
1563 }
1564 }
1565
1566 void RTLIL::Module::remove(RTLIL::Cell *cell)
1567 {
1568 auto it = cells_.find(cell->name);
1569 log_assert(it != cells_.end());
1570 remove(it);
1571 }
1572
1573 dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it)
1574 {
1575 RTLIL::Cell *cell = it->second;
1576 while (!cell->connections_.empty())
1577 cell->unsetPort(cell->connections_.begin()->first);
1578
1579 log_assert(refcount_cells_ == 0);
1580 it = cells_.erase(it);
1581 delete cell;
1582 return it;
1583 }
1584
1585 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1586 {
1587 log_assert(wires_[wire->name] == wire);
1588 log_assert(refcount_wires_ == 0);
1589 wires_.erase(wire->name);
1590 wire->name = new_name;
1591 add(wire);
1592 }
1593
1594 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1595 {
1596 log_assert(cells_[cell->name] == cell);
1597 log_assert(refcount_wires_ == 0);
1598 cells_.erase(cell->name);
1599 cell->name = new_name;
1600 add(cell);
1601 }
1602
1603 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1604 {
1605 log_assert(count_id(old_name) != 0);
1606 if (wires_.count(old_name))
1607 rename(wires_.at(old_name), new_name);
1608 else if (cells_.count(old_name))
1609 rename(cells_.at(old_name), new_name);
1610 else
1611 log_abort();
1612 }
1613
1614 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1615 {
1616 log_assert(wires_[w1->name] == w1);
1617 log_assert(wires_[w2->name] == w2);
1618 log_assert(refcount_wires_ == 0);
1619
1620 wires_.erase(w1->name);
1621 wires_.erase(w2->name);
1622
1623 std::swap(w1->name, w2->name);
1624
1625 wires_[w1->name] = w1;
1626 wires_[w2->name] = w2;
1627 }
1628
1629 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1630 {
1631 log_assert(cells_[c1->name] == c1);
1632 log_assert(cells_[c2->name] == c2);
1633 log_assert(refcount_cells_ == 0);
1634
1635 cells_.erase(c1->name);
1636 cells_.erase(c2->name);
1637
1638 std::swap(c1->name, c2->name);
1639
1640 cells_[c1->name] = c1;
1641 cells_[c2->name] = c2;
1642 }
1643
1644 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1645 {
1646 int index = 0;
1647 return uniquify(name, index);
1648 }
1649
1650 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1651 {
1652 if (index == 0) {
1653 if (count_id(name) == 0)
1654 return name;
1655 index++;
1656 }
1657
1658 while (1) {
1659 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1660 if (count_id(new_name) == 0)
1661 return new_name;
1662 index++;
1663 }
1664 }
1665
1666 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1667 {
1668 if (a->port_id && !b->port_id)
1669 return true;
1670 if (!a->port_id && b->port_id)
1671 return false;
1672
1673 if (a->port_id == b->port_id)
1674 return a->name < b->name;
1675 return a->port_id < b->port_id;
1676 }
1677
1678 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1679 {
1680 for (auto mon : monitors)
1681 mon->notify_connect(this, conn);
1682
1683 if (design)
1684 for (auto mon : design->monitors)
1685 mon->notify_connect(this, conn);
1686
1687 // ignore all attempts to assign constants to other constants
1688 if (conn.first.has_const()) {
1689 RTLIL::SigSig new_conn;
1690 for (int i = 0; i < GetSize(conn.first); i++)
1691 if (conn.first[i].wire) {
1692 new_conn.first.append(conn.first[i]);
1693 new_conn.second.append(conn.second[i]);
1694 }
1695 if (GetSize(new_conn.first))
1696 connect(new_conn);
1697 return;
1698 }
1699
1700 if (yosys_xtrace) {
1701 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1702 log_backtrace("-X- ", yosys_xtrace-1);
1703 }
1704
1705 log_assert(GetSize(conn.first) == GetSize(conn.second));
1706 connections_.push_back(conn);
1707 }
1708
1709 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1710 {
1711 connect(RTLIL::SigSig(lhs, rhs));
1712 }
1713
1714 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1715 {
1716 for (auto mon : monitors)
1717 mon->notify_connect(this, new_conn);
1718
1719 if (design)
1720 for (auto mon : design->monitors)
1721 mon->notify_connect(this, new_conn);
1722
1723 if (yosys_xtrace) {
1724 log("#X# New connections vector in %s:\n", log_id(this));
1725 for (auto &conn: new_conn)
1726 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1727 log_backtrace("-X- ", yosys_xtrace-1);
1728 }
1729
1730 connections_ = new_conn;
1731 }
1732
1733 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1734 {
1735 return connections_;
1736 }
1737
1738 void RTLIL::Module::fixup_ports()
1739 {
1740 std::vector<RTLIL::Wire*> all_ports;
1741
1742 for (auto &w : wires_)
1743 if (w.second->port_input || w.second->port_output)
1744 all_ports.push_back(w.second);
1745 else
1746 w.second->port_id = 0;
1747
1748 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1749
1750 ports.clear();
1751 for (size_t i = 0; i < all_ports.size(); i++) {
1752 ports.push_back(all_ports[i]->name);
1753 all_ports[i]->port_id = i+1;
1754 }
1755 }
1756
1757 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1758 {
1759 RTLIL::Wire *wire = new RTLIL::Wire;
1760 wire->name = name;
1761 wire->width = width;
1762 add(wire);
1763 return wire;
1764 }
1765
1766 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1767 {
1768 RTLIL::Wire *wire = addWire(name);
1769 wire->width = other->width;
1770 wire->start_offset = other->start_offset;
1771 wire->port_id = other->port_id;
1772 wire->port_input = other->port_input;
1773 wire->port_output = other->port_output;
1774 wire->upto = other->upto;
1775 wire->attributes = other->attributes;
1776 return wire;
1777 }
1778
1779 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1780 {
1781 RTLIL::Cell *cell = new RTLIL::Cell;
1782 cell->name = name;
1783 cell->type = type;
1784 add(cell);
1785 return cell;
1786 }
1787
1788 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1789 {
1790 RTLIL::Cell *cell = addCell(name, other->type);
1791 cell->connections_ = other->connections_;
1792 cell->parameters = other->parameters;
1793 cell->attributes = other->attributes;
1794 return cell;
1795 }
1796
1797 #define DEF_METHOD(_func, _y_size, _type) \
1798 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1799 RTLIL::Cell *cell = addCell(name, _type); \
1800 cell->parameters["\\A_SIGNED"] = is_signed; \
1801 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1802 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1803 cell->setPort("\\A", sig_a); \
1804 cell->setPort("\\Y", sig_y); \
1805 cell->set_src_attribute(src); \
1806 return cell; \
1807 } \
1808 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1809 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1810 add ## _func(name, sig_a, sig_y, is_signed, src); \
1811 return sig_y; \
1812 }
1813 DEF_METHOD(Not, sig_a.size(), "$not")
1814 DEF_METHOD(Pos, sig_a.size(), "$pos")
1815 DEF_METHOD(Neg, sig_a.size(), "$neg")
1816 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1817 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1818 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1819 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1820 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1821 DEF_METHOD(LogicNot, 1, "$logic_not")
1822 #undef DEF_METHOD
1823
1824 #define DEF_METHOD(_func, _y_size, _type) \
1825 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1826 RTLIL::Cell *cell = addCell(name, _type); \
1827 cell->parameters["\\A_SIGNED"] = is_signed; \
1828 cell->parameters["\\B_SIGNED"] = is_signed; \
1829 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1830 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1831 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1832 cell->setPort("\\A", sig_a); \
1833 cell->setPort("\\B", sig_b); \
1834 cell->setPort("\\Y", sig_y); \
1835 cell->set_src_attribute(src); \
1836 return cell; \
1837 } \
1838 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1839 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1840 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1841 return sig_y; \
1842 }
1843 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1844 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1845 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1846 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1847 DEF_METHOD(Shl, sig_a.size(), "$shl")
1848 DEF_METHOD(Shr, sig_a.size(), "$shr")
1849 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1850 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1851 DEF_METHOD(Shift, sig_a.size(), "$shift")
1852 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1853 DEF_METHOD(Lt, 1, "$lt")
1854 DEF_METHOD(Le, 1, "$le")
1855 DEF_METHOD(Eq, 1, "$eq")
1856 DEF_METHOD(Ne, 1, "$ne")
1857 DEF_METHOD(Eqx, 1, "$eqx")
1858 DEF_METHOD(Nex, 1, "$nex")
1859 DEF_METHOD(Ge, 1, "$ge")
1860 DEF_METHOD(Gt, 1, "$gt")
1861 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1862 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1863 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1864 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1865 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1866 DEF_METHOD(LogicAnd, 1, "$logic_and")
1867 DEF_METHOD(LogicOr, 1, "$logic_or")
1868 #undef DEF_METHOD
1869
1870 #define DEF_METHOD(_func, _type, _pmux) \
1871 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1872 RTLIL::Cell *cell = addCell(name, _type); \
1873 cell->parameters["\\WIDTH"] = sig_a.size(); \
1874 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1875 cell->setPort("\\A", sig_a); \
1876 cell->setPort("\\B", sig_b); \
1877 cell->setPort("\\S", sig_s); \
1878 cell->setPort("\\Y", sig_y); \
1879 cell->set_src_attribute(src); \
1880 return cell; \
1881 } \
1882 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1883 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1884 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1885 return sig_y; \
1886 }
1887 DEF_METHOD(Mux, "$mux", 0)
1888 DEF_METHOD(Pmux, "$pmux", 1)
1889 #undef DEF_METHOD
1890
1891 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1892 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1893 RTLIL::Cell *cell = addCell(name, _type); \
1894 cell->setPort("\\" #_P1, sig1); \
1895 cell->setPort("\\" #_P2, sig2); \
1896 cell->set_src_attribute(src); \
1897 return cell; \
1898 } \
1899 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1900 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1901 add ## _func(name, sig1, sig2, src); \
1902 return sig2; \
1903 }
1904 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1905 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1906 RTLIL::Cell *cell = addCell(name, _type); \
1907 cell->setPort("\\" #_P1, sig1); \
1908 cell->setPort("\\" #_P2, sig2); \
1909 cell->setPort("\\" #_P3, sig3); \
1910 cell->set_src_attribute(src); \
1911 return cell; \
1912 } \
1913 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1914 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1915 add ## _func(name, sig1, sig2, sig3, src); \
1916 return sig3; \
1917 }
1918 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1919 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1920 RTLIL::Cell *cell = addCell(name, _type); \
1921 cell->setPort("\\" #_P1, sig1); \
1922 cell->setPort("\\" #_P2, sig2); \
1923 cell->setPort("\\" #_P3, sig3); \
1924 cell->setPort("\\" #_P4, sig4); \
1925 cell->set_src_attribute(src); \
1926 return cell; \
1927 } \
1928 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1929 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1930 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1931 return sig4; \
1932 }
1933 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1934 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1935 RTLIL::Cell *cell = addCell(name, _type); \
1936 cell->setPort("\\" #_P1, sig1); \
1937 cell->setPort("\\" #_P2, sig2); \
1938 cell->setPort("\\" #_P3, sig3); \
1939 cell->setPort("\\" #_P4, sig4); \
1940 cell->setPort("\\" #_P5, sig5); \
1941 cell->set_src_attribute(src); \
1942 return cell; \
1943 } \
1944 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1945 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1946 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1947 return sig5; \
1948 }
1949 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1950 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1951 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1952 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1953 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1954 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1955 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1956 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1957 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1958 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1959 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1960 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1961 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1962 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1963 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1964 #undef DEF_METHOD_2
1965 #undef DEF_METHOD_3
1966 #undef DEF_METHOD_4
1967 #undef DEF_METHOD_5
1968
1969 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1970 {
1971 RTLIL::Cell *cell = addCell(name, "$pow");
1972 cell->parameters["\\A_SIGNED"] = a_signed;
1973 cell->parameters["\\B_SIGNED"] = b_signed;
1974 cell->parameters["\\A_WIDTH"] = sig_a.size();
1975 cell->parameters["\\B_WIDTH"] = sig_b.size();
1976 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1977 cell->setPort("\\A", sig_a);
1978 cell->setPort("\\B", sig_b);
1979 cell->setPort("\\Y", sig_y);
1980 cell->set_src_attribute(src);
1981 return cell;
1982 }
1983
1984 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1985 {
1986 RTLIL::Cell *cell = addCell(name, "$slice");
1987 cell->parameters["\\A_WIDTH"] = sig_a.size();
1988 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1989 cell->parameters["\\OFFSET"] = offset;
1990 cell->setPort("\\A", sig_a);
1991 cell->setPort("\\Y", sig_y);
1992 cell->set_src_attribute(src);
1993 return cell;
1994 }
1995
1996 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1997 {
1998 RTLIL::Cell *cell = addCell(name, "$concat");
1999 cell->parameters["\\A_WIDTH"] = sig_a.size();
2000 cell->parameters["\\B_WIDTH"] = sig_b.size();
2001 cell->setPort("\\A", sig_a);
2002 cell->setPort("\\B", sig_b);
2003 cell->setPort("\\Y", sig_y);
2004 cell->set_src_attribute(src);
2005 return cell;
2006 }
2007
2008 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2009 {
2010 RTLIL::Cell *cell = addCell(name, "$lut");
2011 cell->parameters["\\LUT"] = lut;
2012 cell->parameters["\\WIDTH"] = sig_a.size();
2013 cell->setPort("\\A", sig_a);
2014 cell->setPort("\\Y", sig_y);
2015 cell->set_src_attribute(src);
2016 return cell;
2017 }
2018
2019 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2020 {
2021 RTLIL::Cell *cell = addCell(name, "$tribuf");
2022 cell->parameters["\\WIDTH"] = sig_a.size();
2023 cell->setPort("\\A", sig_a);
2024 cell->setPort("\\EN", sig_en);
2025 cell->setPort("\\Y", sig_y);
2026 cell->set_src_attribute(src);
2027 return cell;
2028 }
2029
2030 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2031 {
2032 RTLIL::Cell *cell = addCell(name, "$assert");
2033 cell->setPort("\\A", sig_a);
2034 cell->setPort("\\EN", sig_en);
2035 cell->set_src_attribute(src);
2036 return cell;
2037 }
2038
2039 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2040 {
2041 RTLIL::Cell *cell = addCell(name, "$assume");
2042 cell->setPort("\\A", sig_a);
2043 cell->setPort("\\EN", sig_en);
2044 cell->set_src_attribute(src);
2045 return cell;
2046 }
2047
2048 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2049 {
2050 RTLIL::Cell *cell = addCell(name, "$live");
2051 cell->setPort("\\A", sig_a);
2052 cell->setPort("\\EN", sig_en);
2053 cell->set_src_attribute(src);
2054 return cell;
2055 }
2056
2057 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2058 {
2059 RTLIL::Cell *cell = addCell(name, "$fair");
2060 cell->setPort("\\A", sig_a);
2061 cell->setPort("\\EN", sig_en);
2062 cell->set_src_attribute(src);
2063 return cell;
2064 }
2065
2066 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2067 {
2068 RTLIL::Cell *cell = addCell(name, "$cover");
2069 cell->setPort("\\A", sig_a);
2070 cell->setPort("\\EN", sig_en);
2071 cell->set_src_attribute(src);
2072 return cell;
2073 }
2074
2075 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2076 {
2077 RTLIL::Cell *cell = addCell(name, "$equiv");
2078 cell->setPort("\\A", sig_a);
2079 cell->setPort("\\B", sig_b);
2080 cell->setPort("\\Y", sig_y);
2081 cell->set_src_attribute(src);
2082 return cell;
2083 }
2084
2085 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2086 {
2087 RTLIL::Cell *cell = addCell(name, "$sr");
2088 cell->parameters["\\SET_POLARITY"] = set_polarity;
2089 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2090 cell->parameters["\\WIDTH"] = sig_q.size();
2091 cell->setPort("\\SET", sig_set);
2092 cell->setPort("\\CLR", sig_clr);
2093 cell->setPort("\\Q", sig_q);
2094 cell->set_src_attribute(src);
2095 return cell;
2096 }
2097
2098 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2099 {
2100 RTLIL::Cell *cell = addCell(name, "$ff");
2101 cell->parameters["\\WIDTH"] = sig_q.size();
2102 cell->setPort("\\D", sig_d);
2103 cell->setPort("\\Q", sig_q);
2104 cell->set_src_attribute(src);
2105 return cell;
2106 }
2107
2108 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2109 {
2110 RTLIL::Cell *cell = addCell(name, "$dff");
2111 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2112 cell->parameters["\\WIDTH"] = sig_q.size();
2113 cell->setPort("\\CLK", sig_clk);
2114 cell->setPort("\\D", sig_d);
2115 cell->setPort("\\Q", sig_q);
2116 cell->set_src_attribute(src);
2117 return cell;
2118 }
2119
2120 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2121 {
2122 RTLIL::Cell *cell = addCell(name, "$dffe");
2123 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2124 cell->parameters["\\EN_POLARITY"] = en_polarity;
2125 cell->parameters["\\WIDTH"] = sig_q.size();
2126 cell->setPort("\\CLK", sig_clk);
2127 cell->setPort("\\EN", sig_en);
2128 cell->setPort("\\D", sig_d);
2129 cell->setPort("\\Q", sig_q);
2130 cell->set_src_attribute(src);
2131 return cell;
2132 }
2133
2134 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2135 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2136 {
2137 RTLIL::Cell *cell = addCell(name, "$dffsr");
2138 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2139 cell->parameters["\\SET_POLARITY"] = set_polarity;
2140 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2141 cell->parameters["\\WIDTH"] = sig_q.size();
2142 cell->setPort("\\CLK", sig_clk);
2143 cell->setPort("\\SET", sig_set);
2144 cell->setPort("\\CLR", sig_clr);
2145 cell->setPort("\\D", sig_d);
2146 cell->setPort("\\Q", sig_q);
2147 cell->set_src_attribute(src);
2148 return cell;
2149 }
2150
2151 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2152 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2153 {
2154 RTLIL::Cell *cell = addCell(name, "$adff");
2155 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2156 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2157 cell->parameters["\\ARST_VALUE"] = arst_value;
2158 cell->parameters["\\WIDTH"] = sig_q.size();
2159 cell->setPort("\\CLK", sig_clk);
2160 cell->setPort("\\ARST", sig_arst);
2161 cell->setPort("\\D", sig_d);
2162 cell->setPort("\\Q", sig_q);
2163 cell->set_src_attribute(src);
2164 return cell;
2165 }
2166
2167 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2168 {
2169 RTLIL::Cell *cell = addCell(name, "$dlatch");
2170 cell->parameters["\\EN_POLARITY"] = en_polarity;
2171 cell->parameters["\\WIDTH"] = sig_q.size();
2172 cell->setPort("\\EN", sig_en);
2173 cell->setPort("\\D", sig_d);
2174 cell->setPort("\\Q", sig_q);
2175 cell->set_src_attribute(src);
2176 return cell;
2177 }
2178
2179 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2180 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2181 {
2182 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2183 cell->parameters["\\EN_POLARITY"] = en_polarity;
2184 cell->parameters["\\SET_POLARITY"] = set_polarity;
2185 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2186 cell->parameters["\\WIDTH"] = sig_q.size();
2187 cell->setPort("\\EN", sig_en);
2188 cell->setPort("\\SET", sig_set);
2189 cell->setPort("\\CLR", sig_clr);
2190 cell->setPort("\\D", sig_d);
2191 cell->setPort("\\Q", sig_q);
2192 cell->set_src_attribute(src);
2193 return cell;
2194 }
2195
2196 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2197 {
2198 RTLIL::Cell *cell = addCell(name, "$_FF_");
2199 cell->setPort("\\D", sig_d);
2200 cell->setPort("\\Q", sig_q);
2201 cell->set_src_attribute(src);
2202 return cell;
2203 }
2204
2205 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2206 {
2207 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2208 cell->setPort("\\C", sig_clk);
2209 cell->setPort("\\D", sig_d);
2210 cell->setPort("\\Q", sig_q);
2211 cell->set_src_attribute(src);
2212 return cell;
2213 }
2214
2215 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2216 {
2217 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2218 cell->setPort("\\C", sig_clk);
2219 cell->setPort("\\E", sig_en);
2220 cell->setPort("\\D", sig_d);
2221 cell->setPort("\\Q", sig_q);
2222 cell->set_src_attribute(src);
2223 return cell;
2224 }
2225
2226 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2227 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2228 {
2229 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2230 cell->setPort("\\C", sig_clk);
2231 cell->setPort("\\S", sig_set);
2232 cell->setPort("\\R", sig_clr);
2233 cell->setPort("\\D", sig_d);
2234 cell->setPort("\\Q", sig_q);
2235 cell->set_src_attribute(src);
2236 return cell;
2237 }
2238
2239 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2240 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2241 {
2242 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2243 cell->setPort("\\C", sig_clk);
2244 cell->setPort("\\R", sig_arst);
2245 cell->setPort("\\D", sig_d);
2246 cell->setPort("\\Q", sig_q);
2247 cell->set_src_attribute(src);
2248 return cell;
2249 }
2250
2251 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2252 {
2253 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2254 cell->setPort("\\E", sig_en);
2255 cell->setPort("\\D", sig_d);
2256 cell->setPort("\\Q", sig_q);
2257 cell->set_src_attribute(src);
2258 return cell;
2259 }
2260
2261 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2262 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2263 {
2264 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2265 cell->setPort("\\E", sig_en);
2266 cell->setPort("\\S", sig_set);
2267 cell->setPort("\\R", sig_clr);
2268 cell->setPort("\\D", sig_d);
2269 cell->setPort("\\Q", sig_q);
2270 cell->set_src_attribute(src);
2271 return cell;
2272 }
2273
2274 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2275 {
2276 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2277 Cell *cell = addCell(name, "$anyconst");
2278 cell->setParam("\\WIDTH", width);
2279 cell->setPort("\\Y", sig);
2280 cell->set_src_attribute(src);
2281 return sig;
2282 }
2283
2284 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2285 {
2286 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2287 Cell *cell = addCell(name, "$anyseq");
2288 cell->setParam("\\WIDTH", width);
2289 cell->setPort("\\Y", sig);
2290 cell->set_src_attribute(src);
2291 return sig;
2292 }
2293
2294 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2295 {
2296 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2297 Cell *cell = addCell(name, "$allconst");
2298 cell->setParam("\\WIDTH", width);
2299 cell->setPort("\\Y", sig);
2300 cell->set_src_attribute(src);
2301 return sig;
2302 }
2303
2304 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2305 {
2306 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2307 Cell *cell = addCell(name, "$allseq");
2308 cell->setParam("\\WIDTH", width);
2309 cell->setPort("\\Y", sig);
2310 cell->set_src_attribute(src);
2311 return sig;
2312 }
2313
2314 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2315 {
2316 RTLIL::SigSpec sig = addWire(NEW_ID);
2317 Cell *cell = addCell(name, "$initstate");
2318 cell->setPort("\\Y", sig);
2319 cell->set_src_attribute(src);
2320 return sig;
2321 }
2322
2323 RTLIL::Wire::Wire()
2324 {
2325 static unsigned int hashidx_count = 123456789;
2326 hashidx_count = mkhash_xorshift(hashidx_count);
2327 hashidx_ = hashidx_count;
2328
2329 module = nullptr;
2330 width = 1;
2331 start_offset = 0;
2332 port_id = 0;
2333 port_input = false;
2334 port_output = false;
2335 upto = false;
2336
2337 #ifdef WITH_PYTHON
2338 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2339 #endif
2340 }
2341
2342 RTLIL::Wire::~Wire()
2343 {
2344 #ifdef WITH_PYTHON
2345 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2346 #endif
2347 }
2348
2349 #ifdef WITH_PYTHON
2350 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2351 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2352 {
2353 return &all_wires;
2354 }
2355 #endif
2356
2357 RTLIL::Memory::Memory()
2358 {
2359 static unsigned int hashidx_count = 123456789;
2360 hashidx_count = mkhash_xorshift(hashidx_count);
2361 hashidx_ = hashidx_count;
2362
2363 width = 1;
2364 start_offset = 0;
2365 size = 0;
2366 #ifdef WITH_PYTHON
2367 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2368 #endif
2369 }
2370
2371 RTLIL::Cell::Cell() : module(nullptr)
2372 {
2373 static unsigned int hashidx_count = 123456789;
2374 hashidx_count = mkhash_xorshift(hashidx_count);
2375 hashidx_ = hashidx_count;
2376
2377 // log("#memtrace# %p\n", this);
2378 memhasher();
2379
2380 #ifdef WITH_PYTHON
2381 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2382 #endif
2383 }
2384
2385 RTLIL::Cell::~Cell()
2386 {
2387 #ifdef WITH_PYTHON
2388 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2389 #endif
2390 }
2391
2392 #ifdef WITH_PYTHON
2393 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2394 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2395 {
2396 return &all_cells;
2397 }
2398 #endif
2399
2400 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2401 {
2402 return connections_.count(portname) != 0;
2403 }
2404
2405 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2406 {
2407 RTLIL::SigSpec signal;
2408 auto conn_it = connections_.find(portname);
2409
2410 if (conn_it != connections_.end())
2411 {
2412 for (auto mon : module->monitors)
2413 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2414
2415 if (module->design)
2416 for (auto mon : module->design->monitors)
2417 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2418
2419 if (yosys_xtrace) {
2420 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2421 log_backtrace("-X- ", yosys_xtrace-1);
2422 }
2423
2424 connections_.erase(conn_it);
2425 }
2426 }
2427
2428 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2429 {
2430 auto conn_it = connections_.find(portname);
2431
2432 if (conn_it == connections_.end()) {
2433 connections_[portname] = RTLIL::SigSpec();
2434 conn_it = connections_.find(portname);
2435 log_assert(conn_it != connections_.end());
2436 } else
2437 if (conn_it->second == signal)
2438 return;
2439
2440 for (auto mon : module->monitors)
2441 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2442
2443 if (module->design)
2444 for (auto mon : module->design->monitors)
2445 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2446
2447 if (yosys_xtrace) {
2448 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2449 log_backtrace("-X- ", yosys_xtrace-1);
2450 }
2451
2452 conn_it->second = signal;
2453 }
2454
2455 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2456 {
2457 return connections_.at(portname);
2458 }
2459
2460 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2461 {
2462 return connections_;
2463 }
2464
2465 bool RTLIL::Cell::known() const
2466 {
2467 if (yosys_celltypes.cell_known(type))
2468 return true;
2469 if (module && module->design && module->design->module(type))
2470 return true;
2471 return false;
2472 }
2473
2474 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2475 {
2476 if (yosys_celltypes.cell_known(type))
2477 return yosys_celltypes.cell_input(type, portname);
2478 if (module && module->design) {
2479 RTLIL::Module *m = module->design->module(type);
2480 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2481 return w && w->port_input;
2482 }
2483 return false;
2484 }
2485
2486 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2487 {
2488 if (yosys_celltypes.cell_known(type))
2489 return yosys_celltypes.cell_output(type, portname);
2490 if (module && module->design) {
2491 RTLIL::Module *m = module->design->module(type);
2492 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2493 return w && w->port_output;
2494 }
2495 return false;
2496 }
2497
2498 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2499 {
2500 return parameters.count(paramname) != 0;
2501 }
2502
2503 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2504 {
2505 parameters.erase(paramname);
2506 }
2507
2508 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2509 {
2510 parameters[paramname] = value;
2511 }
2512
2513 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2514 {
2515 return parameters.at(paramname);
2516 }
2517
2518 void RTLIL::Cell::sort()
2519 {
2520 connections_.sort(sort_by_id_str());
2521 parameters.sort(sort_by_id_str());
2522 attributes.sort(sort_by_id_str());
2523 }
2524
2525 void RTLIL::Cell::check()
2526 {
2527 #ifndef NDEBUG
2528 InternalCellChecker checker(NULL, this);
2529 checker.check();
2530 #endif
2531 }
2532
2533 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2534 {
2535 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2536 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2537 return;
2538
2539 if (type == "$mux" || type == "$pmux") {
2540 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2541 if (type == "$pmux")
2542 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2543 check();
2544 return;
2545 }
2546
2547 if (type == "$lut" || type == "$sop") {
2548 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2549 return;
2550 }
2551
2552 if (type == "$fa") {
2553 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2554 return;
2555 }
2556
2557 if (type == "$lcu") {
2558 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2559 return;
2560 }
2561
2562 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2563
2564 if (connections_.count("\\A")) {
2565 if (signedness_ab) {
2566 if (set_a_signed)
2567 parameters["\\A_SIGNED"] = true;
2568 else if (parameters.count("\\A_SIGNED") == 0)
2569 parameters["\\A_SIGNED"] = false;
2570 }
2571 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2572 }
2573
2574 if (connections_.count("\\B")) {
2575 if (signedness_ab) {
2576 if (set_b_signed)
2577 parameters["\\B_SIGNED"] = true;
2578 else if (parameters.count("\\B_SIGNED") == 0)
2579 parameters["\\B_SIGNED"] = false;
2580 }
2581 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2582 }
2583
2584 if (connections_.count("\\Y"))
2585 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2586
2587 if (connections_.count("\\Q"))
2588 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2589
2590 check();
2591 }
2592
2593 RTLIL::SigChunk::SigChunk()
2594 {
2595 wire = NULL;
2596 width = 0;
2597 offset = 0;
2598 }
2599
2600 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2601 {
2602 wire = NULL;
2603 data = value.bits;
2604 width = GetSize(data);
2605 offset = 0;
2606 }
2607
2608 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2609 {
2610 log_assert(wire != nullptr);
2611 this->wire = wire;
2612 this->width = wire->width;
2613 this->offset = 0;
2614 }
2615
2616 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2617 {
2618 log_assert(wire != nullptr);
2619 this->wire = wire;
2620 this->width = width;
2621 this->offset = offset;
2622 }
2623
2624 RTLIL::SigChunk::SigChunk(const std::string &str)
2625 {
2626 wire = NULL;
2627 data = RTLIL::Const(str).bits;
2628 width = GetSize(data);
2629 offset = 0;
2630 }
2631
2632 RTLIL::SigChunk::SigChunk(int val, int width)
2633 {
2634 wire = NULL;
2635 data = RTLIL::Const(val, width).bits;
2636 this->width = GetSize(data);
2637 offset = 0;
2638 }
2639
2640 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2641 {
2642 wire = NULL;
2643 data = RTLIL::Const(bit, width).bits;
2644 this->width = GetSize(data);
2645 offset = 0;
2646 }
2647
2648 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2649 {
2650 wire = bit.wire;
2651 offset = 0;
2652 if (wire == NULL)
2653 data = RTLIL::Const(bit.data).bits;
2654 else
2655 offset = bit.offset;
2656 width = 1;
2657 }
2658
2659 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2660 {
2661 wire = sigchunk.wire;
2662 data = sigchunk.data;
2663 width = sigchunk.width;
2664 offset = sigchunk.offset;
2665 }
2666
2667 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2668 {
2669 RTLIL::SigChunk ret;
2670 if (wire) {
2671 ret.wire = wire;
2672 ret.offset = this->offset + offset;
2673 ret.width = length;
2674 } else {
2675 for (int i = 0; i < length; i++)
2676 ret.data.push_back(data[offset+i]);
2677 ret.width = length;
2678 }
2679 return ret;
2680 }
2681
2682 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2683 {
2684 if (wire && other.wire)
2685 if (wire->name != other.wire->name)
2686 return wire->name < other.wire->name;
2687
2688 if (wire != other.wire)
2689 return wire < other.wire;
2690
2691 if (offset != other.offset)
2692 return offset < other.offset;
2693
2694 if (width != other.width)
2695 return width < other.width;
2696
2697 return data < other.data;
2698 }
2699
2700 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2701 {
2702 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2703 }
2704
2705 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2706 {
2707 if (*this == other)
2708 return false;
2709 return true;
2710 }
2711
2712 RTLIL::SigSpec::SigSpec()
2713 {
2714 width_ = 0;
2715 hash_ = 0;
2716 }
2717
2718 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2719 {
2720 *this = other;
2721 }
2722
2723 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2724 {
2725 cover("kernel.rtlil.sigspec.init.list");
2726
2727 width_ = 0;
2728 hash_ = 0;
2729
2730 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2731 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2732 append(*it);
2733 }
2734
2735 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2736 {
2737 cover("kernel.rtlil.sigspec.assign");
2738
2739 width_ = other.width_;
2740 hash_ = other.hash_;
2741 chunks_ = other.chunks_;
2742 bits_.clear();
2743
2744 if (!other.bits_.empty())
2745 {
2746 RTLIL::SigChunk *last = NULL;
2747 int last_end_offset = 0;
2748
2749 for (auto &bit : other.bits_) {
2750 if (last && bit.wire == last->wire) {
2751 if (bit.wire == NULL) {
2752 last->data.push_back(bit.data);
2753 last->width++;
2754 continue;
2755 } else if (last_end_offset == bit.offset) {
2756 last_end_offset++;
2757 last->width++;
2758 continue;
2759 }
2760 }
2761 chunks_.push_back(bit);
2762 last = &chunks_.back();
2763 last_end_offset = bit.offset + 1;
2764 }
2765
2766 check();
2767 }
2768
2769 return *this;
2770 }
2771
2772 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2773 {
2774 cover("kernel.rtlil.sigspec.init.const");
2775
2776 chunks_.push_back(RTLIL::SigChunk(value));
2777 width_ = chunks_.back().width;
2778 hash_ = 0;
2779 check();
2780 }
2781
2782 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2783 {
2784 cover("kernel.rtlil.sigspec.init.chunk");
2785
2786 chunks_.push_back(chunk);
2787 width_ = chunks_.back().width;
2788 hash_ = 0;
2789 check();
2790 }
2791
2792 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2793 {
2794 cover("kernel.rtlil.sigspec.init.wire");
2795
2796 chunks_.push_back(RTLIL::SigChunk(wire));
2797 width_ = chunks_.back().width;
2798 hash_ = 0;
2799 check();
2800 }
2801
2802 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2803 {
2804 cover("kernel.rtlil.sigspec.init.wire_part");
2805
2806 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2807 width_ = chunks_.back().width;
2808 hash_ = 0;
2809 check();
2810 }
2811
2812 RTLIL::SigSpec::SigSpec(const std::string &str)
2813 {
2814 cover("kernel.rtlil.sigspec.init.str");
2815
2816 chunks_.push_back(RTLIL::SigChunk(str));
2817 width_ = chunks_.back().width;
2818 hash_ = 0;
2819 check();
2820 }
2821
2822 RTLIL::SigSpec::SigSpec(int val, int width)
2823 {
2824 cover("kernel.rtlil.sigspec.init.int");
2825
2826 chunks_.push_back(RTLIL::SigChunk(val, width));
2827 width_ = width;
2828 hash_ = 0;
2829 check();
2830 }
2831
2832 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2833 {
2834 cover("kernel.rtlil.sigspec.init.state");
2835
2836 chunks_.push_back(RTLIL::SigChunk(bit, width));
2837 width_ = width;
2838 hash_ = 0;
2839 check();
2840 }
2841
2842 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2843 {
2844 cover("kernel.rtlil.sigspec.init.bit");
2845
2846 if (bit.wire == NULL)
2847 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2848 else
2849 for (int i = 0; i < width; i++)
2850 chunks_.push_back(bit);
2851 width_ = width;
2852 hash_ = 0;
2853 check();
2854 }
2855
2856 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2857 {
2858 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2859
2860 width_ = 0;
2861 hash_ = 0;
2862 for (auto &c : chunks)
2863 append(c);
2864 check();
2865 }
2866
2867 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2868 {
2869 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2870
2871 width_ = 0;
2872 hash_ = 0;
2873 for (auto &bit : bits)
2874 append_bit(bit);
2875 check();
2876 }
2877
2878 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2879 {
2880 cover("kernel.rtlil.sigspec.init.pool_bits");
2881
2882 width_ = 0;
2883 hash_ = 0;
2884 for (auto &bit : bits)
2885 append_bit(bit);
2886 check();
2887 }
2888
2889 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2890 {
2891 cover("kernel.rtlil.sigspec.init.stdset_bits");
2892
2893 width_ = 0;
2894 hash_ = 0;
2895 for (auto &bit : bits)
2896 append_bit(bit);
2897 check();
2898 }
2899
2900 RTLIL::SigSpec::SigSpec(bool bit)
2901 {
2902 cover("kernel.rtlil.sigspec.init.bool");
2903
2904 width_ = 0;
2905 hash_ = 0;
2906 append_bit(bit);
2907 check();
2908 }
2909
2910 void RTLIL::SigSpec::pack() const
2911 {
2912 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2913
2914 if (that->bits_.empty())
2915 return;
2916
2917 cover("kernel.rtlil.sigspec.convert.pack");
2918 log_assert(that->chunks_.empty());
2919
2920 std::vector<RTLIL::SigBit> old_bits;
2921 old_bits.swap(that->bits_);
2922
2923 RTLIL::SigChunk *last = NULL;
2924 int last_end_offset = 0;
2925
2926 for (auto &bit : old_bits) {
2927 if (last && bit.wire == last->wire) {
2928 if (bit.wire == NULL) {
2929 last->data.push_back(bit.data);
2930 last->width++;
2931 continue;
2932 } else if (last_end_offset == bit.offset) {
2933 last_end_offset++;
2934 last->width++;
2935 continue;
2936 }
2937 }
2938 that->chunks_.push_back(bit);
2939 last = &that->chunks_.back();
2940 last_end_offset = bit.offset + 1;
2941 }
2942
2943 check();
2944 }
2945
2946 void RTLIL::SigSpec::unpack() const
2947 {
2948 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2949
2950 if (that->chunks_.empty())
2951 return;
2952
2953 cover("kernel.rtlil.sigspec.convert.unpack");
2954 log_assert(that->bits_.empty());
2955
2956 that->bits_.reserve(that->width_);
2957 for (auto &c : that->chunks_)
2958 for (int i = 0; i < c.width; i++)
2959 that->bits_.push_back(RTLIL::SigBit(c, i));
2960
2961 that->chunks_.clear();
2962 that->hash_ = 0;
2963 }
2964
2965 void RTLIL::SigSpec::updhash() const
2966 {
2967 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2968
2969 if (that->hash_ != 0)
2970 return;
2971
2972 cover("kernel.rtlil.sigspec.hash");
2973 that->pack();
2974
2975 that->hash_ = mkhash_init;
2976 for (auto &c : that->chunks_)
2977 if (c.wire == NULL) {
2978 for (auto &v : c.data)
2979 that->hash_ = mkhash(that->hash_, v);
2980 } else {
2981 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2982 that->hash_ = mkhash(that->hash_, c.offset);
2983 that->hash_ = mkhash(that->hash_, c.width);
2984 }
2985
2986 if (that->hash_ == 0)
2987 that->hash_ = 1;
2988 }
2989
2990 void RTLIL::SigSpec::sort()
2991 {
2992 unpack();
2993 cover("kernel.rtlil.sigspec.sort");
2994 std::sort(bits_.begin(), bits_.end());
2995 }
2996
2997 void RTLIL::SigSpec::sort_and_unify()
2998 {
2999 unpack();
3000 cover("kernel.rtlil.sigspec.sort_and_unify");
3001
3002 // A copy of the bits vector is used to prevent duplicating the logic from
3003 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3004 // that isn't showing up as significant in profiles.
3005 std::vector<SigBit> unique_bits = bits_;
3006 std::sort(unique_bits.begin(), unique_bits.end());
3007 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3008 unique_bits.erase(last, unique_bits.end());
3009
3010 *this = unique_bits;
3011 }
3012
3013 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3014 {
3015 replace(pattern, with, this);
3016 }
3017
3018 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3019 {
3020 log_assert(other != NULL);
3021 log_assert(width_ == other->width_);
3022 log_assert(pattern.width_ == with.width_);
3023
3024 pattern.unpack();
3025 with.unpack();
3026 unpack();
3027 other->unpack();
3028
3029 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3030 if (pattern.bits_[i].wire != NULL) {
3031 for (int j = 0; j < GetSize(bits_); j++) {
3032 if (bits_[j] == pattern.bits_[i]) {
3033 other->bits_[j] = with.bits_[i];
3034 }
3035 }
3036 }
3037 }
3038
3039 other->check();
3040 }
3041
3042 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3043 {
3044 replace(rules, this);
3045 }
3046
3047 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3048 {
3049 cover("kernel.rtlil.sigspec.replace_dict");
3050
3051 log_assert(other != NULL);
3052 log_assert(width_ == other->width_);
3053
3054 unpack();
3055 other->unpack();
3056
3057 for (int i = 0; i < GetSize(bits_); i++) {
3058 auto it = rules.find(bits_[i]);
3059 if (it != rules.end())
3060 other->bits_[i] = it->second;
3061 }
3062
3063 other->check();
3064 }
3065
3066 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3067 {
3068 replace(rules, this);
3069 }
3070
3071 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3072 {
3073 cover("kernel.rtlil.sigspec.replace_map");
3074
3075 log_assert(other != NULL);
3076 log_assert(width_ == other->width_);
3077
3078 unpack();
3079 other->unpack();
3080
3081 for (int i = 0; i < GetSize(bits_); i++) {
3082 auto it = rules.find(bits_[i]);
3083 if (it != rules.end())
3084 other->bits_[i] = it->second;
3085 }
3086
3087 other->check();
3088 }
3089
3090 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3091 {
3092 remove2(pattern, NULL);
3093 }
3094
3095 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3096 {
3097 RTLIL::SigSpec tmp = *this;
3098 tmp.remove2(pattern, other);
3099 }
3100
3101 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3102 {
3103 if (other)
3104 cover("kernel.rtlil.sigspec.remove_other");
3105 else
3106 cover("kernel.rtlil.sigspec.remove");
3107
3108 unpack();
3109 if (other != NULL) {
3110 log_assert(width_ == other->width_);
3111 other->unpack();
3112 }
3113
3114 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3115 {
3116 if (bits_[i].wire == NULL) continue;
3117
3118 for (auto &pattern_chunk : pattern.chunks())
3119 if (bits_[i].wire == pattern_chunk.wire &&
3120 bits_[i].offset >= pattern_chunk.offset &&
3121 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3122 bits_.erase(bits_.begin() + i);
3123 width_--;
3124 if (other != NULL) {
3125 other->bits_.erase(other->bits_.begin() + i);
3126 other->width_--;
3127 }
3128 break;
3129 }
3130 }
3131
3132 check();
3133 }
3134
3135 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3136 {
3137 remove2(pattern, NULL);
3138 }
3139
3140 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3141 {
3142 RTLIL::SigSpec tmp = *this;
3143 tmp.remove2(pattern, other);
3144 }
3145
3146 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3147 {
3148 if (other)
3149 cover("kernel.rtlil.sigspec.remove_other");
3150 else
3151 cover("kernel.rtlil.sigspec.remove");
3152
3153 unpack();
3154
3155 if (other != NULL) {
3156 log_assert(width_ == other->width_);
3157 other->unpack();
3158 }
3159
3160 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3161 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3162 bits_.erase(bits_.begin() + i);
3163 width_--;
3164 if (other != NULL) {
3165 other->bits_.erase(other->bits_.begin() + i);
3166 other->width_--;
3167 }
3168 }
3169 }
3170
3171 check();
3172 }
3173
3174 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3175 {
3176 if (other)
3177 cover("kernel.rtlil.sigspec.remove_other");
3178 else
3179 cover("kernel.rtlil.sigspec.remove");
3180
3181 unpack();
3182
3183 if (other != NULL) {
3184 log_assert(width_ == other->width_);
3185 other->unpack();
3186 }
3187
3188 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3189 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3190 bits_.erase(bits_.begin() + i);
3191 width_--;
3192 if (other != NULL) {
3193 other->bits_.erase(other->bits_.begin() + i);
3194 other->width_--;
3195 }
3196 }
3197 }
3198
3199 check();
3200 }
3201
3202 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3203 {
3204 if (other)
3205 cover("kernel.rtlil.sigspec.extract_other");
3206 else
3207 cover("kernel.rtlil.sigspec.extract");
3208
3209 log_assert(other == NULL || width_ == other->width_);
3210
3211 RTLIL::SigSpec ret;
3212 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3213
3214 for (auto& pattern_chunk : pattern.chunks()) {
3215 if (other) {
3216 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3217 for (int i = 0; i < width_; i++)
3218 if (bits_match[i].wire &&
3219 bits_match[i].wire == pattern_chunk.wire &&
3220 bits_match[i].offset >= pattern_chunk.offset &&
3221 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3222 ret.append_bit(bits_other[i]);
3223 } else {
3224 for (int i = 0; i < width_; i++)
3225 if (bits_match[i].wire &&
3226 bits_match[i].wire == pattern_chunk.wire &&
3227 bits_match[i].offset >= pattern_chunk.offset &&
3228 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3229 ret.append_bit(bits_match[i]);
3230 }
3231 }
3232
3233 ret.check();
3234 return ret;
3235 }
3236
3237 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3238 {
3239 if (other)
3240 cover("kernel.rtlil.sigspec.extract_other");
3241 else
3242 cover("kernel.rtlil.sigspec.extract");
3243
3244 log_assert(other == NULL || width_ == other->width_);
3245
3246 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3247 RTLIL::SigSpec ret;
3248
3249 if (other) {
3250 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3251 for (int i = 0; i < width_; i++)
3252 if (bits_match[i].wire && pattern.count(bits_match[i]))
3253 ret.append_bit(bits_other[i]);
3254 } else {
3255 for (int i = 0; i < width_; i++)
3256 if (bits_match[i].wire && pattern.count(bits_match[i]))
3257 ret.append_bit(bits_match[i]);
3258 }
3259
3260 ret.check();
3261 return ret;
3262 }
3263
3264 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3265 {
3266 cover("kernel.rtlil.sigspec.replace_pos");
3267
3268 unpack();
3269 with.unpack();
3270
3271 log_assert(offset >= 0);
3272 log_assert(with.width_ >= 0);
3273 log_assert(offset+with.width_ <= width_);
3274
3275 for (int i = 0; i < with.width_; i++)
3276 bits_.at(offset + i) = with.bits_.at(i);
3277
3278 check();
3279 }
3280
3281 void RTLIL::SigSpec::remove_const()
3282 {
3283 if (packed())
3284 {
3285 cover("kernel.rtlil.sigspec.remove_const.packed");
3286
3287 std::vector<RTLIL::SigChunk> new_chunks;
3288 new_chunks.reserve(GetSize(chunks_));
3289
3290 width_ = 0;
3291 for (auto &chunk : chunks_)
3292 if (chunk.wire != NULL) {
3293 new_chunks.push_back(chunk);
3294 width_ += chunk.width;
3295 }
3296
3297 chunks_.swap(new_chunks);
3298 }
3299 else
3300 {
3301 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3302
3303 std::vector<RTLIL::SigBit> new_bits;
3304 new_bits.reserve(width_);
3305
3306 for (auto &bit : bits_)
3307 if (bit.wire != NULL)
3308 new_bits.push_back(bit);
3309
3310 bits_.swap(new_bits);
3311 width_ = bits_.size();
3312 }
3313
3314 check();
3315 }
3316
3317 void RTLIL::SigSpec::remove(int offset, int length)
3318 {
3319 cover("kernel.rtlil.sigspec.remove_pos");
3320
3321 unpack();
3322
3323 log_assert(offset >= 0);
3324 log_assert(length >= 0);
3325 log_assert(offset + length <= width_);
3326
3327 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3328 width_ = bits_.size();
3329
3330 check();
3331 }
3332
3333 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3334 {
3335 unpack();
3336 cover("kernel.rtlil.sigspec.extract_pos");
3337 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3338 }
3339
3340 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3341 {
3342 if (signal.width_ == 0)
3343 return;
3344
3345 if (width_ == 0) {
3346 *this = signal;
3347 return;
3348 }
3349
3350 cover("kernel.rtlil.sigspec.append");
3351
3352 if (packed() != signal.packed()) {
3353 pack();
3354 signal.pack();
3355 }
3356
3357 if (packed())
3358 for (auto &other_c : signal.chunks_)
3359 {
3360 auto &my_last_c = chunks_.back();
3361 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3362 auto &this_data = my_last_c.data;
3363 auto &other_data = other_c.data;
3364 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3365 my_last_c.width += other_c.width;
3366 } else
3367 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3368 my_last_c.width += other_c.width;
3369 } else
3370 chunks_.push_back(other_c);
3371 }
3372 else
3373 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3374
3375 width_ += signal.width_;
3376 check();
3377 }
3378
3379 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3380 {
3381 if (packed())
3382 {
3383 cover("kernel.rtlil.sigspec.append_bit.packed");
3384
3385 if (chunks_.size() == 0)
3386 chunks_.push_back(bit);
3387 else
3388 if (bit.wire == NULL)
3389 if (chunks_.back().wire == NULL) {
3390 chunks_.back().data.push_back(bit.data);
3391 chunks_.back().width++;
3392 } else
3393 chunks_.push_back(bit);
3394 else
3395 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3396 chunks_.back().width++;
3397 else
3398 chunks_.push_back(bit);
3399 }
3400 else
3401 {
3402 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3403 bits_.push_back(bit);
3404 }
3405
3406 width_++;
3407 check();
3408 }
3409
3410 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3411 {
3412 cover("kernel.rtlil.sigspec.extend_u0");
3413
3414 pack();
3415
3416 if (width_ > width)
3417 remove(width, width_ - width);
3418
3419 if (width_ < width) {
3420 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3421 if (!is_signed)
3422 padding = RTLIL::State::S0;
3423 while (width_ < width)
3424 append(padding);
3425 }
3426
3427 }
3428
3429 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3430 {
3431 cover("kernel.rtlil.sigspec.repeat");
3432
3433 RTLIL::SigSpec sig;
3434 for (int i = 0; i < num; i++)
3435 sig.append(*this);
3436 return sig;
3437 }
3438
3439 #ifndef NDEBUG
3440 void RTLIL::SigSpec::check() const
3441 {
3442 if (width_ > 64)
3443 {
3444 cover("kernel.rtlil.sigspec.check.skip");
3445 }
3446 else if (packed())
3447 {
3448 cover("kernel.rtlil.sigspec.check.packed");
3449
3450 int w = 0;
3451 for (size_t i = 0; i < chunks_.size(); i++) {
3452 const RTLIL::SigChunk chunk = chunks_[i];
3453 if (chunk.wire == NULL) {
3454 if (i > 0)
3455 log_assert(chunks_[i-1].wire != NULL);
3456 log_assert(chunk.offset == 0);
3457 log_assert(chunk.data.size() == (size_t)chunk.width);
3458 } else {
3459 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3460 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3461 log_assert(chunk.offset >= 0);
3462 log_assert(chunk.width >= 0);
3463 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3464 log_assert(chunk.data.size() == 0);
3465 }
3466 w += chunk.width;
3467 }
3468 log_assert(w == width_);
3469 log_assert(bits_.empty());
3470 }
3471 else
3472 {
3473 cover("kernel.rtlil.sigspec.check.unpacked");
3474
3475 log_assert(width_ == GetSize(bits_));
3476 log_assert(chunks_.empty());
3477 }
3478 }
3479 #endif
3480
3481 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3482 {
3483 cover("kernel.rtlil.sigspec.comp_lt");
3484
3485 if (this == &other)
3486 return false;
3487
3488 if (width_ != other.width_)
3489 return width_ < other.width_;
3490
3491 pack();
3492 other.pack();
3493
3494 if (chunks_.size() != other.chunks_.size())
3495 return chunks_.size() < other.chunks_.size();
3496
3497 updhash();
3498 other.updhash();
3499
3500 if (hash_ != other.hash_)
3501 return hash_ < other.hash_;
3502
3503 for (size_t i = 0; i < chunks_.size(); i++)
3504 if (chunks_[i] != other.chunks_[i]) {
3505 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3506 return chunks_[i] < other.chunks_[i];
3507 }
3508
3509 cover("kernel.rtlil.sigspec.comp_lt.equal");
3510 return false;
3511 }
3512
3513 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3514 {
3515 cover("kernel.rtlil.sigspec.comp_eq");
3516
3517 if (this == &other)
3518 return true;
3519
3520 if (width_ != other.width_)
3521 return false;
3522
3523 pack();
3524 other.pack();
3525
3526 if (chunks_.size() != other.chunks_.size())
3527 return false;
3528
3529 updhash();
3530 other.updhash();
3531
3532 if (hash_ != other.hash_)
3533 return false;
3534
3535 for (size_t i = 0; i < chunks_.size(); i++)
3536 if (chunks_[i] != other.chunks_[i]) {
3537 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3538 return false;
3539 }
3540
3541 cover("kernel.rtlil.sigspec.comp_eq.equal");
3542 return true;
3543 }
3544
3545 bool RTLIL::SigSpec::is_wire() const
3546 {
3547 cover("kernel.rtlil.sigspec.is_wire");
3548
3549 pack();
3550 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3551 }
3552
3553 bool RTLIL::SigSpec::is_chunk() const
3554 {
3555 cover("kernel.rtlil.sigspec.is_chunk");
3556
3557 pack();
3558 return GetSize(chunks_) == 1;
3559 }
3560
3561 bool RTLIL::SigSpec::is_fully_const() const
3562 {
3563 cover("kernel.rtlil.sigspec.is_fully_const");
3564
3565 pack();
3566 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3567 if (it->width > 0 && it->wire != NULL)
3568 return false;
3569 return true;
3570 }
3571
3572 bool RTLIL::SigSpec::is_fully_zero() const
3573 {
3574 cover("kernel.rtlil.sigspec.is_fully_zero");
3575
3576 pack();
3577 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3578 if (it->width > 0 && it->wire != NULL)
3579 return false;
3580 for (size_t i = 0; i < it->data.size(); i++)
3581 if (it->data[i] != RTLIL::State::S0)
3582 return false;
3583 }
3584 return true;
3585 }
3586
3587 bool RTLIL::SigSpec::is_fully_ones() const
3588 {
3589 cover("kernel.rtlil.sigspec.is_fully_ones");
3590
3591 pack();
3592 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3593 if (it->width > 0 && it->wire != NULL)
3594 return false;
3595 for (size_t i = 0; i < it->data.size(); i++)
3596 if (it->data[i] != RTLIL::State::S1)
3597 return false;
3598 }
3599 return true;
3600 }
3601
3602 bool RTLIL::SigSpec::is_fully_def() const
3603 {
3604 cover("kernel.rtlil.sigspec.is_fully_def");
3605
3606 pack();
3607 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3608 if (it->width > 0 && it->wire != NULL)
3609 return false;
3610 for (size_t i = 0; i < it->data.size(); i++)
3611 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3612 return false;
3613 }
3614 return true;
3615 }
3616
3617 bool RTLIL::SigSpec::is_fully_undef() const
3618 {
3619 cover("kernel.rtlil.sigspec.is_fully_undef");
3620
3621 pack();
3622 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3623 if (it->width > 0 && it->wire != NULL)
3624 return false;
3625 for (size_t i = 0; i < it->data.size(); i++)
3626 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3627 return false;
3628 }
3629 return true;
3630 }
3631
3632 bool RTLIL::SigSpec::has_const() const
3633 {
3634 cover("kernel.rtlil.sigspec.has_const");
3635
3636 pack();
3637 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3638 if (it->width > 0 && it->wire == NULL)
3639 return true;
3640 return false;
3641 }
3642
3643 bool RTLIL::SigSpec::has_marked_bits() const
3644 {
3645 cover("kernel.rtlil.sigspec.has_marked_bits");
3646
3647 pack();
3648 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3649 if (it->width > 0 && it->wire == NULL) {
3650 for (size_t i = 0; i < it->data.size(); i++)
3651 if (it->data[i] == RTLIL::State::Sm)
3652 return true;
3653 }
3654 return false;
3655 }
3656
3657 bool RTLIL::SigSpec::as_bool() const
3658 {
3659 cover("kernel.rtlil.sigspec.as_bool");
3660
3661 pack();
3662 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3663 if (width_)
3664 return RTLIL::Const(chunks_[0].data).as_bool();
3665 return false;
3666 }
3667
3668 int RTLIL::SigSpec::as_int(bool is_signed) const
3669 {
3670 cover("kernel.rtlil.sigspec.as_int");
3671
3672 pack();
3673 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3674 if (width_)
3675 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3676 return 0;
3677 }
3678
3679 std::string RTLIL::SigSpec::as_string() const
3680 {
3681 cover("kernel.rtlil.sigspec.as_string");
3682
3683 pack();
3684 std::string str;
3685 for (size_t i = chunks_.size(); i > 0; i--) {
3686 const RTLIL::SigChunk &chunk = chunks_[i-1];
3687 if (chunk.wire != NULL)
3688 for (int j = 0; j < chunk.width; j++)
3689 str += "?";
3690 else
3691 str += RTLIL::Const(chunk.data).as_string();
3692 }
3693 return str;
3694 }
3695
3696 RTLIL::Const RTLIL::SigSpec::as_const() const
3697 {
3698 cover("kernel.rtlil.sigspec.as_const");
3699
3700 pack();
3701 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3702 if (width_)
3703 return chunks_[0].data;
3704 return RTLIL::Const();
3705 }
3706
3707 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3708 {
3709 cover("kernel.rtlil.sigspec.as_wire");
3710
3711 pack();
3712 log_assert(is_wire());
3713 return chunks_[0].wire;
3714 }
3715
3716 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3717 {
3718 cover("kernel.rtlil.sigspec.as_chunk");
3719
3720 pack();
3721 log_assert(is_chunk());
3722 return chunks_[0];
3723 }
3724
3725 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3726 {
3727 cover("kernel.rtlil.sigspec.as_bit");
3728
3729 log_assert(width_ == 1);
3730 if (packed())
3731 return RTLIL::SigBit(*chunks_.begin());
3732 else
3733 return bits_[0];
3734 }
3735
3736 bool RTLIL::SigSpec::match(std::string pattern) const
3737 {
3738 cover("kernel.rtlil.sigspec.match");
3739
3740 pack();
3741 std::string str = as_string();
3742 log_assert(pattern.size() == str.size());
3743
3744 for (size_t i = 0; i < pattern.size(); i++) {
3745 if (pattern[i] == ' ')
3746 continue;
3747 if (pattern[i] == '*') {
3748 if (str[i] != 'z' && str[i] != 'x')
3749 return false;
3750 continue;
3751 }
3752 if (pattern[i] != str[i])
3753 return false;
3754 }
3755
3756 return true;
3757 }
3758
3759 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3760 {
3761 cover("kernel.rtlil.sigspec.to_sigbit_set");
3762
3763 pack();
3764 std::set<RTLIL::SigBit> sigbits;
3765 for (auto &c : chunks_)
3766 for (int i = 0; i < c.width; i++)
3767 sigbits.insert(RTLIL::SigBit(c, i));
3768 return sigbits;
3769 }
3770
3771 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3772 {
3773 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3774
3775 pack();
3776 pool<RTLIL::SigBit> sigbits;
3777 for (auto &c : chunks_)
3778 for (int i = 0; i < c.width; i++)
3779 sigbits.insert(RTLIL::SigBit(c, i));
3780 return sigbits;
3781 }
3782
3783 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3784 {
3785 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3786
3787 unpack();
3788 return bits_;
3789 }
3790
3791 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3792 {
3793 cover("kernel.rtlil.sigspec.to_sigbit_map");
3794
3795 unpack();
3796 other.unpack();
3797
3798 log_assert(width_ == other.width_);
3799
3800 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3801 for (int i = 0; i < width_; i++)
3802 new_map[bits_[i]] = other.bits_[i];
3803
3804 return new_map;
3805 }
3806
3807 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3808 {
3809 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3810
3811 unpack();
3812 other.unpack();
3813
3814 log_assert(width_ == other.width_);
3815
3816 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3817 for (int i = 0; i < width_; i++)
3818 new_map[bits_[i]] = other.bits_[i];
3819
3820 return new_map;
3821 }
3822
3823 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3824 {
3825 size_t start = 0, end = 0;
3826 while ((end = text.find(sep, start)) != std::string::npos) {
3827 tokens.push_back(text.substr(start, end - start));
3828 start = end + 1;
3829 }
3830 tokens.push_back(text.substr(start));
3831 }
3832
3833 static int sigspec_parse_get_dummy_line_num()
3834 {
3835 return 0;
3836 }
3837
3838 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3839 {
3840 cover("kernel.rtlil.sigspec.parse");
3841
3842 AST::current_filename = "input";
3843 AST::use_internal_line_num();
3844 AST::set_line_num(0);
3845
3846 std::vector<std::string> tokens;
3847 sigspec_parse_split(tokens, str, ',');
3848
3849 sig = RTLIL::SigSpec();
3850 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3851 {
3852 std::string netname = tokens[tokidx];
3853 std::string indices;
3854
3855 if (netname.size() == 0)
3856 continue;
3857
3858 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3859 cover("kernel.rtlil.sigspec.parse.const");
3860 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3861 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3862 if (ast == NULL)
3863 return false;
3864 sig.append(RTLIL::Const(ast->bits));
3865 delete ast;
3866 continue;
3867 }
3868
3869 if (module == NULL)
3870 return false;
3871
3872 cover("kernel.rtlil.sigspec.parse.net");
3873
3874 if (netname[0] != '$' && netname[0] != '\\')
3875 netname = "\\" + netname;
3876
3877 if (module->wires_.count(netname) == 0) {
3878 size_t indices_pos = netname.size()-1;
3879 if (indices_pos > 2 && netname[indices_pos] == ']')
3880 {
3881 indices_pos--;
3882 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3883 if (indices_pos > 0 && netname[indices_pos] == ':') {
3884 indices_pos--;
3885 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3886 }
3887 if (indices_pos > 0 && netname[indices_pos] == '[') {
3888 indices = netname.substr(indices_pos);
3889 netname = netname.substr(0, indices_pos);
3890 }
3891 }
3892 }
3893
3894 if (module->wires_.count(netname) == 0)
3895 return false;
3896
3897 RTLIL::Wire *wire = module->wires_.at(netname);
3898 if (!indices.empty()) {
3899 std::vector<std::string> index_tokens;
3900 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3901 if (index_tokens.size() == 1) {
3902 cover("kernel.rtlil.sigspec.parse.bit_sel");
3903 int a = atoi(index_tokens.at(0).c_str());
3904 if (a < 0 || a >= wire->width)
3905 return false;
3906 sig.append(RTLIL::SigSpec(wire, a));
3907 } else {
3908 cover("kernel.rtlil.sigspec.parse.part_sel");
3909 int a = atoi(index_tokens.at(0).c_str());
3910 int b = atoi(index_tokens.at(1).c_str());
3911 if (a > b) {
3912 int tmp = a;
3913 a = b, b = tmp;
3914 }
3915 if (a < 0 || a >= wire->width)
3916 return false;
3917 if (b < 0 || b >= wire->width)
3918 return false;
3919 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3920 }
3921 } else
3922 sig.append(wire);
3923 }
3924
3925 return true;
3926 }
3927
3928 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3929 {
3930 if (str.empty() || str[0] != '@')
3931 return parse(sig, module, str);
3932
3933 cover("kernel.rtlil.sigspec.parse.sel");
3934
3935 str = RTLIL::escape_id(str.substr(1));
3936 if (design->selection_vars.count(str) == 0)
3937 return false;
3938
3939 sig = RTLIL::SigSpec();
3940 RTLIL::Selection &sel = design->selection_vars.at(str);
3941 for (auto &it : module->wires_)
3942 if (sel.selected_member(module->name, it.first))
3943 sig.append(it.second);
3944
3945 return true;
3946 }
3947
3948 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3949 {
3950 if (str == "0") {
3951 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3952 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3953 return true;
3954 }
3955
3956 if (str == "~0") {
3957 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3958 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3959 return true;
3960 }
3961
3962 if (lhs.chunks_.size() == 1) {
3963 char *p = (char*)str.c_str(), *endptr;
3964 long int val = strtol(p, &endptr, 10);
3965 if (endptr && endptr != p && *endptr == 0) {
3966 sig = RTLIL::SigSpec(val, lhs.width_);
3967 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3968 return true;
3969 }
3970 }
3971
3972 return parse(sig, module, str);
3973 }
3974
3975 RTLIL::CaseRule::~CaseRule()
3976 {
3977 for (auto it = switches.begin(); it != switches.end(); it++)
3978 delete *it;
3979 }
3980
3981 bool RTLIL::CaseRule::empty() const
3982 {
3983 return actions.empty() && switches.empty();
3984 }
3985
3986 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3987 {
3988 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3989 new_caserule->compare = compare;
3990 new_caserule->actions = actions;
3991 for (auto &it : switches)
3992 new_caserule->switches.push_back(it->clone());
3993 return new_caserule;
3994 }
3995
3996 RTLIL::SwitchRule::~SwitchRule()
3997 {
3998 for (auto it = cases.begin(); it != cases.end(); it++)
3999 delete *it;
4000 }
4001
4002 bool RTLIL::SwitchRule::empty() const
4003 {
4004 return cases.empty();
4005 }
4006
4007 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4008 {
4009 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4010 new_switchrule->signal = signal;
4011 new_switchrule->attributes = attributes;
4012 for (auto &it : cases)
4013 new_switchrule->cases.push_back(it->clone());
4014 return new_switchrule;
4015
4016 }
4017
4018 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4019 {
4020 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4021 new_syncrule->type = type;
4022 new_syncrule->signal = signal;
4023 new_syncrule->actions = actions;
4024 return new_syncrule;
4025 }
4026
4027 RTLIL::Process::~Process()
4028 {
4029 for (auto it = syncs.begin(); it != syncs.end(); it++)
4030 delete *it;
4031 }
4032
4033 RTLIL::Process *RTLIL::Process::clone() const
4034 {
4035 RTLIL::Process *new_proc = new RTLIL::Process;
4036
4037 new_proc->name = name;
4038 new_proc->attributes = attributes;
4039
4040 RTLIL::CaseRule *rc_ptr = root_case.clone();
4041 new_proc->root_case = *rc_ptr;
4042 rc_ptr->switches.clear();
4043 delete rc_ptr;
4044
4045 for (auto &it : syncs)
4046 new_proc->syncs.push_back(it->clone());
4047
4048 return new_proc;
4049 }
4050
4051 #ifdef WITH_PYTHON
4052 RTLIL::Memory::~Memory()
4053 {
4054 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4055 }
4056 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4057 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4058 {
4059 return &all_memorys;
4060 }
4061 #endif
4062 YOSYS_NAMESPACE_END