2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
32 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
37 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_
[8];
41 int RTLIL::IdString::last_created_idx_ptr_
;
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
48 dict
<std::string
, std::string
> RTLIL::constpad
;
50 const pool
<IdString
> &RTLIL::builtin_ff_cell_types() {
51 static const pool
<IdString
> res
= {
99 flags
= RTLIL::CONST_FLAG_NONE
;
102 RTLIL::Const::Const(std::string str
)
104 flags
= RTLIL::CONST_FLAG_STRING
;
105 for (int i
= str
.size()-1; i
>= 0; i
--) {
106 unsigned char ch
= str
[i
];
107 for (int j
= 0; j
< 8; j
++) {
108 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
114 RTLIL::Const::Const(int val
, int width
)
116 flags
= RTLIL::CONST_FLAG_NONE
;
117 for (int i
= 0; i
< width
; i
++) {
118 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
123 RTLIL::Const::Const(RTLIL::State bit
, int width
)
125 flags
= RTLIL::CONST_FLAG_NONE
;
126 for (int i
= 0; i
< width
; i
++)
130 RTLIL::Const::Const(const std::vector
<bool> &bits
)
132 flags
= RTLIL::CONST_FLAG_NONE
;
133 for (const auto &b
: bits
)
134 this->bits
.emplace_back(b
? State::S1
: State::S0
);
137 RTLIL::Const::Const(const RTLIL::Const
&c
)
140 for (const auto &b
: c
.bits
)
141 this->bits
.push_back(b
);
144 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
146 if (bits
.size() != other
.bits
.size())
147 return bits
.size() < other
.bits
.size();
148 for (size_t i
= 0; i
< bits
.size(); i
++)
149 if (bits
[i
] != other
.bits
[i
])
150 return bits
[i
] < other
.bits
[i
];
154 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
156 return bits
== other
.bits
;
159 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
161 return bits
!= other
.bits
;
164 bool RTLIL::Const::as_bool() const
166 for (size_t i
= 0; i
< bits
.size(); i
++)
167 if (bits
[i
] == State::S1
)
172 int RTLIL::Const::as_int(bool is_signed
) const
175 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
176 if (bits
[i
] == State::S1
)
178 if (is_signed
&& bits
.back() == State::S1
)
179 for (size_t i
= bits
.size(); i
< 32; i
++)
184 std::string
RTLIL::Const::as_string() const
187 ret
.reserve(bits
.size());
188 for (size_t i
= bits
.size(); i
> 0; i
--)
190 case S0
: ret
+= "0"; break;
191 case S1
: ret
+= "1"; break;
192 case Sx
: ret
+= "x"; break;
193 case Sz
: ret
+= "z"; break;
194 case Sa
: ret
+= "-"; break;
195 case Sm
: ret
+= "m"; break;
200 RTLIL::Const
RTLIL::Const::from_string(const std::string
&str
)
203 c
.bits
.reserve(str
.size());
204 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
206 case '0': c
.bits
.push_back(State::S0
); break;
207 case '1': c
.bits
.push_back(State::S1
); break;
208 case 'x': c
.bits
.push_back(State::Sx
); break;
209 case 'z': c
.bits
.push_back(State::Sz
); break;
210 case 'm': c
.bits
.push_back(State::Sm
); break;
211 default: c
.bits
.push_back(State::Sa
);
216 std::string
RTLIL::Const::decode_string() const
219 string
.reserve(GetSize(bits
)/8);
220 for (int i
= 0; i
< GetSize(bits
); i
+= 8) {
222 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
223 if (bits
[i
+ j
] == RTLIL::State::S1
)
228 std::reverse(string
.begin(), string
.end());
232 bool RTLIL::Const::is_fully_zero() const
234 cover("kernel.rtlil.const.is_fully_zero");
236 for (const auto &bit
: bits
)
237 if (bit
!= RTLIL::State::S0
)
243 bool RTLIL::Const::is_fully_ones() const
245 cover("kernel.rtlil.const.is_fully_ones");
247 for (const auto &bit
: bits
)
248 if (bit
!= RTLIL::State::S1
)
254 bool RTLIL::Const::is_fully_def() const
256 cover("kernel.rtlil.const.is_fully_def");
258 for (const auto &bit
: bits
)
259 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
265 bool RTLIL::Const::is_fully_undef() const
267 cover("kernel.rtlil.const.is_fully_undef");
269 for (const auto &bit
: bits
)
270 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
276 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id
) const
278 return attributes
.count(id
);
281 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
284 attributes
[id
] = RTLIL::Const(1);
286 attributes
.erase(id
);
289 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
291 const auto it
= attributes
.find(id
);
292 if (it
== attributes
.end())
294 return it
->second
.as_bool();
297 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id
, string value
)
300 attributes
.erase(id
);
302 attributes
[id
] = value
;
305 string
RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id
) const
308 const auto it
= attributes
.find(id
);
309 if (it
!= attributes
.end())
310 value
= it
->second
.decode_string();
314 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
317 for (const auto &s
: data
) {
318 if (!attrval
.empty())
322 attributes
[id
] = RTLIL::Const(attrval
);
325 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
327 pool
<string
> union_data
= get_strpool_attribute(id
);
328 union_data
.insert(data
.begin(), data
.end());
329 if (!union_data
.empty())
330 set_strpool_attribute(id
, union_data
);
333 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
336 if (attributes
.count(id
) != 0)
337 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
342 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
346 if (selected_modules
.count(mod_name
) > 0)
348 if (selected_members
.count(mod_name
) > 0)
353 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
357 if (selected_modules
.count(mod_name
) > 0)
362 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
366 if (selected_modules
.count(mod_name
) > 0)
368 if (selected_members
.count(mod_name
) > 0)
369 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
374 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
376 if (full_selection
) {
377 selected_modules
.clear();
378 selected_members
.clear();
382 std::vector
<RTLIL::IdString
> del_list
, add_list
;
385 for (auto mod_name
: selected_modules
) {
386 if (design
->modules_
.count(mod_name
) == 0)
387 del_list
.push_back(mod_name
);
388 selected_members
.erase(mod_name
);
390 for (auto mod_name
: del_list
)
391 selected_modules
.erase(mod_name
);
394 for (auto &it
: selected_members
)
395 if (design
->modules_
.count(it
.first
) == 0)
396 del_list
.push_back(it
.first
);
397 for (auto mod_name
: del_list
)
398 selected_members
.erase(mod_name
);
400 for (auto &it
: selected_members
) {
402 for (auto memb_name
: it
.second
)
403 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
404 del_list
.push_back(memb_name
);
405 for (auto memb_name
: del_list
)
406 it
.second
.erase(memb_name
);
411 for (auto &it
: selected_members
)
412 if (it
.second
.size() == 0)
413 del_list
.push_back(it
.first
);
414 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
415 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
416 add_list
.push_back(it
.first
);
417 for (auto mod_name
: del_list
)
418 selected_members
.erase(mod_name
);
419 for (auto mod_name
: add_list
) {
420 selected_members
.erase(mod_name
);
421 selected_modules
.insert(mod_name
);
424 if (selected_modules
.size() == design
->modules_
.size()) {
425 full_selection
= true;
426 selected_modules
.clear();
427 selected_members
.clear();
431 RTLIL::Design::Design()
432 : verilog_defines (new define_map_t
)
434 static unsigned int hashidx_count
= 123456789;
435 hashidx_count
= mkhash_xorshift(hashidx_count
);
436 hashidx_
= hashidx_count
;
438 refcount_modules_
= 0;
439 selection_stack
.push_back(RTLIL::Selection());
442 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
446 RTLIL::Design::~Design()
448 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
450 for (auto n
: verilog_packages
)
452 for (auto n
: verilog_globals
)
455 RTLIL::Design::get_all_designs()->erase(hashidx_
);
460 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
461 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
467 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
469 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
472 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
474 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
477 RTLIL::Module
*RTLIL::Design::top_module()
479 RTLIL::Module
*module
= nullptr;
480 int module_count
= 0;
482 for (auto mod
: selected_modules()) {
483 if (mod
->get_bool_attribute(ID::top
))
489 return module_count
== 1 ? module
: nullptr;
492 void RTLIL::Design::add(RTLIL::Module
*module
)
494 log_assert(modules_
.count(module
->name
) == 0);
495 log_assert(refcount_modules_
== 0);
496 modules_
[module
->name
] = module
;
497 module
->design
= this;
499 for (auto mon
: monitors
)
500 mon
->notify_module_add(module
);
503 log("#X# New Module: %s\n", log_id(module
));
504 log_backtrace("-X- ", yosys_xtrace
-1);
508 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
510 log_assert(modules_
.count(name
) == 0);
511 log_assert(refcount_modules_
== 0);
513 RTLIL::Module
*module
= new RTLIL::Module
;
514 modules_
[name
] = module
;
515 module
->design
= this;
518 for (auto mon
: monitors
)
519 mon
->notify_module_add(module
);
522 log("#X# New Module: %s\n", log_id(module
));
523 log_backtrace("-X- ", yosys_xtrace
-1);
529 void RTLIL::Design::scratchpad_unset(const std::string
&varname
)
531 scratchpad
.erase(varname
);
534 void RTLIL::Design::scratchpad_set_int(const std::string
&varname
, int value
)
536 scratchpad
[varname
] = stringf("%d", value
);
539 void RTLIL::Design::scratchpad_set_bool(const std::string
&varname
, bool value
)
541 scratchpad
[varname
] = value
? "true" : "false";
544 void RTLIL::Design::scratchpad_set_string(const std::string
&varname
, std::string value
)
546 scratchpad
[varname
] = std::move(value
);
549 int RTLIL::Design::scratchpad_get_int(const std::string
&varname
, int default_value
) const
551 auto it
= scratchpad
.find(varname
);
552 if (it
== scratchpad
.end())
553 return default_value
;
555 const std::string
&str
= it
->second
;
557 if (str
== "0" || str
== "false")
560 if (str
== "1" || str
== "true")
563 char *endptr
= nullptr;
564 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
565 return *endptr
? default_value
: parsed_value
;
568 bool RTLIL::Design::scratchpad_get_bool(const std::string
&varname
, bool default_value
) const
570 auto it
= scratchpad
.find(varname
);
571 if (it
== scratchpad
.end())
572 return default_value
;
574 const std::string
&str
= it
->second
;
576 if (str
== "0" || str
== "false")
579 if (str
== "1" || str
== "true")
582 return default_value
;
585 std::string
RTLIL::Design::scratchpad_get_string(const std::string
&varname
, const std::string
&default_value
) const
587 auto it
= scratchpad
.find(varname
);
588 if (it
== scratchpad
.end())
589 return default_value
;
594 void RTLIL::Design::remove(RTLIL::Module
*module
)
596 for (auto mon
: monitors
)
597 mon
->notify_module_del(module
);
600 log("#X# Remove Module: %s\n", log_id(module
));
601 log_backtrace("-X- ", yosys_xtrace
-1);
604 log_assert(modules_
.at(module
->name
) == module
);
605 log_assert(refcount_modules_
== 0);
606 modules_
.erase(module
->name
);
610 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
612 modules_
.erase(module
->name
);
613 module
->name
= new_name
;
617 void RTLIL::Design::sort()
620 modules_
.sort(sort_by_id_str());
621 for (auto &it
: modules_
)
625 void RTLIL::Design::check()
628 for (auto &it
: modules_
) {
629 log_assert(this == it
.second
->design
);
630 log_assert(it
.first
== it
.second
->name
);
631 log_assert(!it
.first
.empty());
637 void RTLIL::Design::optimize()
639 for (auto &it
: modules_
)
640 it
.second
->optimize();
641 for (auto &it
: selection_stack
)
643 for (auto &it
: selection_vars
)
644 it
.second
.optimize(this);
647 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
649 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
651 if (selection_stack
.size() == 0)
653 return selection_stack
.back().selected_module(mod_name
);
656 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
658 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
660 if (selection_stack
.size() == 0)
662 return selection_stack
.back().selected_whole_module(mod_name
);
665 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
667 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
669 if (selection_stack
.size() == 0)
671 return selection_stack
.back().selected_member(mod_name
, memb_name
);
674 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
676 return selected_module(mod
->name
);
679 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
681 return selected_whole_module(mod
->name
);
684 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
686 std::vector
<RTLIL::Module
*> result
;
687 result
.reserve(modules_
.size());
688 for (auto &it
: modules_
)
689 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
690 result
.push_back(it
.second
);
694 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
696 std::vector
<RTLIL::Module
*> result
;
697 result
.reserve(modules_
.size());
698 for (auto &it
: modules_
)
699 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
700 result
.push_back(it
.second
);
704 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
706 std::vector
<RTLIL::Module
*> result
;
707 result
.reserve(modules_
.size());
708 for (auto &it
: modules_
)
709 if (it
.second
->get_blackbox_attribute())
711 else if (selected_whole_module(it
.first
))
712 result
.push_back(it
.second
);
713 else if (selected_module(it
.first
))
714 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
718 RTLIL::Module::Module()
720 static unsigned int hashidx_count
= 123456789;
721 hashidx_count
= mkhash_xorshift(hashidx_count
);
722 hashidx_
= hashidx_count
;
729 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
733 RTLIL::Module::~Module()
735 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
737 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
739 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
741 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
744 RTLIL::Module::get_all_modules()->erase(hashidx_
);
749 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
750 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
756 void RTLIL::Module::makeblackbox()
758 pool
<RTLIL::Wire
*> delwires
;
760 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
761 if (!it
->second
->port_input
&& !it
->second
->port_output
)
762 delwires
.insert(it
->second
);
764 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
768 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
772 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
776 connections_
.clear();
779 set_bool_attribute(ID::blackbox
);
782 void RTLIL::Module::reprocess_module(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Module
*> &)
784 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
787 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, bool mayfail
)
790 return RTLIL::IdString();
791 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
795 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, const dict
<RTLIL::IdString
, RTLIL::Module
*> &, const dict
<RTLIL::IdString
, RTLIL::IdString
> &, bool mayfail
)
798 return RTLIL::IdString();
799 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
802 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
804 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
809 struct InternalCellChecker
811 RTLIL::Module
*module
;
813 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
815 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
817 void error(int linenr
)
819 std::stringstream buf
;
820 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
822 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
823 module
? module
->name
.c_str() : "", module
? "." : "",
824 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
827 int param(RTLIL::IdString name
)
829 auto it
= cell
->parameters
.find(name
);
830 if (it
== cell
->parameters
.end())
832 expected_params
.insert(name
);
833 return it
->second
.as_int();
836 int param_bool(RTLIL::IdString name
)
839 if (GetSize(cell
->parameters
.at(name
)) > 32)
841 if (v
!= 0 && v
!= 1)
846 int param_bool(RTLIL::IdString name
, bool expected
)
848 int v
= param_bool(name
);
854 void param_bits(RTLIL::IdString name
, int width
)
857 if (GetSize(cell
->parameters
.at(name
).bits
) != width
)
861 void port(RTLIL::IdString name
, int width
)
863 auto it
= cell
->connections_
.find(name
);
864 if (it
== cell
->connections_
.end())
866 if (GetSize(it
->second
) != width
)
868 expected_ports
.insert(name
);
871 void check_expected(bool check_matched_sign
= false)
873 for (auto ¶
: cell
->parameters
)
874 if (expected_params
.count(para
.first
) == 0)
876 for (auto &conn
: cell
->connections())
877 if (expected_ports
.count(conn
.first
) == 0)
880 if (check_matched_sign
) {
881 log_assert(expected_params
.count(ID::A_SIGNED
) != 0 && expected_params
.count(ID::B_SIGNED
) != 0);
882 bool a_is_signed
= cell
->parameters
.at(ID::A_SIGNED
).as_bool();
883 bool b_is_signed
= cell
->parameters
.at(ID::B_SIGNED
).as_bool();
884 if (a_is_signed
!= b_is_signed
)
891 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
892 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
895 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
896 param_bool(ID::A_SIGNED
);
897 port(ID::A
, param(ID::A_WIDTH
));
898 port(ID::Y
, param(ID::Y_WIDTH
));
903 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
904 param_bool(ID::A_SIGNED
);
905 param_bool(ID::B_SIGNED
);
906 port(ID::A
, param(ID::A_WIDTH
));
907 port(ID::B
, param(ID::B_WIDTH
));
908 port(ID::Y
, param(ID::Y_WIDTH
));
909 check_expected(true);
913 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
914 param_bool(ID::A_SIGNED
);
915 port(ID::A
, param(ID::A_WIDTH
));
916 port(ID::Y
, param(ID::Y_WIDTH
));
921 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
))) {
922 param_bool(ID::A_SIGNED
);
923 param_bool(ID::B_SIGNED
, /*expected=*/false);
924 port(ID::A
, param(ID::A_WIDTH
));
925 port(ID::B
, param(ID::B_WIDTH
));
926 port(ID::Y
, param(ID::Y_WIDTH
));
927 check_expected(/*check_matched_sign=*/false);
931 if (cell
->type
.in(ID($shift
), ID($shiftx
))) {
932 param_bool(ID::A_SIGNED
);
933 param_bool(ID::B_SIGNED
);
934 port(ID::A
, param(ID::A_WIDTH
));
935 port(ID::B
, param(ID::B_WIDTH
));
936 port(ID::Y
, param(ID::Y_WIDTH
));
937 check_expected(/*check_matched_sign=*/false);
941 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
942 param_bool(ID::A_SIGNED
);
943 param_bool(ID::B_SIGNED
);
944 port(ID::A
, param(ID::A_WIDTH
));
945 port(ID::B
, param(ID::B_WIDTH
));
946 port(ID::Y
, param(ID::Y_WIDTH
));
947 check_expected(true);
951 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($pow
))) {
952 param_bool(ID::A_SIGNED
);
953 param_bool(ID::B_SIGNED
);
954 port(ID::A
, param(ID::A_WIDTH
));
955 port(ID::B
, param(ID::B_WIDTH
));
956 port(ID::Y
, param(ID::Y_WIDTH
));
957 check_expected(cell
->type
!= ID($pow
));
961 if (cell
->type
== ID($fa
)) {
962 port(ID::A
, param(ID::WIDTH
));
963 port(ID::B
, param(ID::WIDTH
));
964 port(ID::C
, param(ID::WIDTH
));
965 port(ID::X
, param(ID::WIDTH
));
966 port(ID::Y
, param(ID::WIDTH
));
971 if (cell
->type
== ID($lcu
)) {
972 port(ID::P
, param(ID::WIDTH
));
973 port(ID::G
, param(ID::WIDTH
));
975 port(ID::CO
, param(ID::WIDTH
));
980 if (cell
->type
== ID($alu
)) {
981 param_bool(ID::A_SIGNED
);
982 param_bool(ID::B_SIGNED
);
983 port(ID::A
, param(ID::A_WIDTH
));
984 port(ID::B
, param(ID::B_WIDTH
));
987 port(ID::X
, param(ID::Y_WIDTH
));
988 port(ID::Y
, param(ID::Y_WIDTH
));
989 port(ID::CO
, param(ID::Y_WIDTH
));
990 check_expected(true);
994 if (cell
->type
== ID($macc
)) {
996 param(ID::CONFIG_WIDTH
);
997 port(ID::A
, param(ID::A_WIDTH
));
998 port(ID::B
, param(ID::B_WIDTH
));
999 port(ID::Y
, param(ID::Y_WIDTH
));
1001 Macc().from_cell(cell
);
1005 if (cell
->type
== ID($logic_not
)) {
1006 param_bool(ID::A_SIGNED
);
1007 port(ID::A
, param(ID::A_WIDTH
));
1008 port(ID::Y
, param(ID::Y_WIDTH
));
1013 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
1014 param_bool(ID::A_SIGNED
);
1015 param_bool(ID::B_SIGNED
);
1016 port(ID::A
, param(ID::A_WIDTH
));
1017 port(ID::B
, param(ID::B_WIDTH
));
1018 port(ID::Y
, param(ID::Y_WIDTH
));
1019 check_expected(/*check_matched_sign=*/false);
1023 if (cell
->type
== ID($slice
)) {
1025 port(ID::A
, param(ID::A_WIDTH
));
1026 port(ID::Y
, param(ID::Y_WIDTH
));
1027 if (param(ID::OFFSET
) + param(ID::Y_WIDTH
) > param(ID::A_WIDTH
))
1033 if (cell
->type
== ID($concat
)) {
1034 port(ID::A
, param(ID::A_WIDTH
));
1035 port(ID::B
, param(ID::B_WIDTH
));
1036 port(ID::Y
, param(ID::A_WIDTH
) + param(ID::B_WIDTH
));
1041 if (cell
->type
== ID($mux
)) {
1042 port(ID::A
, param(ID::WIDTH
));
1043 port(ID::B
, param(ID::WIDTH
));
1045 port(ID::Y
, param(ID::WIDTH
));
1050 if (cell
->type
== ID($pmux
)) {
1051 port(ID::A
, param(ID::WIDTH
));
1052 port(ID::B
, param(ID::WIDTH
) * param(ID::S_WIDTH
));
1053 port(ID::S
, param(ID::S_WIDTH
));
1054 port(ID::Y
, param(ID::WIDTH
));
1059 if (cell
->type
== ID($lut
)) {
1061 port(ID::A
, param(ID::WIDTH
));
1067 if (cell
->type
== ID($sop
)) {
1070 port(ID::A
, param(ID::WIDTH
));
1076 if (cell
->type
== ID($sr
)) {
1077 param_bool(ID::SET_POLARITY
);
1078 param_bool(ID::CLR_POLARITY
);
1079 port(ID::SET
, param(ID::WIDTH
));
1080 port(ID::CLR
, param(ID::WIDTH
));
1081 port(ID::Q
, param(ID::WIDTH
));
1086 if (cell
->type
== ID($ff
)) {
1087 port(ID::D
, param(ID::WIDTH
));
1088 port(ID::Q
, param(ID::WIDTH
));
1093 if (cell
->type
== ID($dff
)) {
1094 param_bool(ID::CLK_POLARITY
);
1096 port(ID::D
, param(ID::WIDTH
));
1097 port(ID::Q
, param(ID::WIDTH
));
1102 if (cell
->type
== ID($dffe
)) {
1103 param_bool(ID::CLK_POLARITY
);
1104 param_bool(ID::EN_POLARITY
);
1107 port(ID::D
, param(ID::WIDTH
));
1108 port(ID::Q
, param(ID::WIDTH
));
1113 if (cell
->type
== ID($dffsr
)) {
1114 param_bool(ID::CLK_POLARITY
);
1115 param_bool(ID::SET_POLARITY
);
1116 param_bool(ID::CLR_POLARITY
);
1118 port(ID::SET
, param(ID::WIDTH
));
1119 port(ID::CLR
, param(ID::WIDTH
));
1120 port(ID::D
, param(ID::WIDTH
));
1121 port(ID::Q
, param(ID::WIDTH
));
1126 if (cell
->type
== ID($adff
)) {
1127 param_bool(ID::CLK_POLARITY
);
1128 param_bool(ID::ARST_POLARITY
);
1129 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1132 port(ID::D
, param(ID::WIDTH
));
1133 port(ID::Q
, param(ID::WIDTH
));
1138 if (cell
->type
== ID($dlatch
)) {
1139 param_bool(ID::EN_POLARITY
);
1141 port(ID::D
, param(ID::WIDTH
));
1142 port(ID::Q
, param(ID::WIDTH
));
1147 if (cell
->type
== ID($dlatchsr
)) {
1148 param_bool(ID::EN_POLARITY
);
1149 param_bool(ID::SET_POLARITY
);
1150 param_bool(ID::CLR_POLARITY
);
1152 port(ID::SET
, param(ID::WIDTH
));
1153 port(ID::CLR
, param(ID::WIDTH
));
1154 port(ID::D
, param(ID::WIDTH
));
1155 port(ID::Q
, param(ID::WIDTH
));
1160 if (cell
->type
== ID($fsm
)) {
1162 param_bool(ID::CLK_POLARITY
);
1163 param_bool(ID::ARST_POLARITY
);
1164 param(ID::STATE_BITS
);
1165 param(ID::STATE_NUM
);
1166 param(ID::STATE_NUM_LOG2
);
1167 param(ID::STATE_RST
);
1168 param_bits(ID::STATE_TABLE
, param(ID::STATE_BITS
) * param(ID::STATE_NUM
));
1169 param(ID::TRANS_NUM
);
1170 param_bits(ID::TRANS_TABLE
, param(ID::TRANS_NUM
) * (2*param(ID::STATE_NUM_LOG2
) + param(ID::CTRL_IN_WIDTH
) + param(ID::CTRL_OUT_WIDTH
)));
1173 port(ID::CTRL_IN
, param(ID::CTRL_IN_WIDTH
));
1174 port(ID::CTRL_OUT
, param(ID::CTRL_OUT_WIDTH
));
1179 if (cell
->type
== ID($memrd
)) {
1181 param_bool(ID::CLK_ENABLE
);
1182 param_bool(ID::CLK_POLARITY
);
1183 param_bool(ID::TRANSPARENT
);
1186 port(ID::ADDR
, param(ID::ABITS
));
1187 port(ID::DATA
, param(ID::WIDTH
));
1192 if (cell
->type
== ID($memwr
)) {
1194 param_bool(ID::CLK_ENABLE
);
1195 param_bool(ID::CLK_POLARITY
);
1196 param(ID::PRIORITY
);
1198 port(ID::EN
, param(ID::WIDTH
));
1199 port(ID::ADDR
, param(ID::ABITS
));
1200 port(ID::DATA
, param(ID::WIDTH
));
1205 if (cell
->type
== ID($meminit
)) {
1207 param(ID::PRIORITY
);
1208 port(ID::ADDR
, param(ID::ABITS
));
1209 port(ID::DATA
, param(ID::WIDTH
) * param(ID::WORDS
));
1214 if (cell
->type
== ID($mem
)) {
1219 param_bits(ID::RD_CLK_ENABLE
, max(1, param(ID::RD_PORTS
)));
1220 param_bits(ID::RD_CLK_POLARITY
, max(1, param(ID::RD_PORTS
)));
1221 param_bits(ID::RD_TRANSPARENT
, max(1, param(ID::RD_PORTS
)));
1222 param_bits(ID::WR_CLK_ENABLE
, max(1, param(ID::WR_PORTS
)));
1223 param_bits(ID::WR_CLK_POLARITY
, max(1, param(ID::WR_PORTS
)));
1224 port(ID::RD_CLK
, param(ID::RD_PORTS
));
1225 port(ID::RD_EN
, param(ID::RD_PORTS
));
1226 port(ID::RD_ADDR
, param(ID::RD_PORTS
) * param(ID::ABITS
));
1227 port(ID::RD_DATA
, param(ID::RD_PORTS
) * param(ID::WIDTH
));
1228 port(ID::WR_CLK
, param(ID::WR_PORTS
));
1229 port(ID::WR_EN
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1230 port(ID::WR_ADDR
, param(ID::WR_PORTS
) * param(ID::ABITS
));
1231 port(ID::WR_DATA
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1236 if (cell
->type
== ID($tribuf
)) {
1237 port(ID::A
, param(ID::WIDTH
));
1238 port(ID::Y
, param(ID::WIDTH
));
1244 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1251 if (cell
->type
== ID($initstate
)) {
1257 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1258 port(ID::Y
, param(ID::WIDTH
));
1263 if (cell
->type
== ID($equiv
)) {
1271 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1272 param_bool(ID::FULL
);
1273 param_bool(ID::SRC_DST_PEN
);
1274 param_bool(ID::SRC_DST_POL
);
1275 param(ID::T_RISE_MIN
);
1276 param(ID::T_RISE_TYP
);
1277 param(ID::T_RISE_MAX
);
1278 param(ID::T_FALL_MIN
);
1279 param(ID::T_FALL_TYP
);
1280 param(ID::T_FALL_MAX
);
1282 port(ID::SRC
, param(ID::SRC_WIDTH
));
1283 port(ID::DST
, param(ID::DST_WIDTH
));
1284 if (cell
->type
== ID($specify3
)) {
1285 param_bool(ID::EDGE_EN
);
1286 param_bool(ID::EDGE_POL
);
1287 param_bool(ID::DAT_DST_PEN
);
1288 param_bool(ID::DAT_DST_POL
);
1289 port(ID::DAT
, param(ID::DST_WIDTH
));
1295 if (cell
->type
== ID($specrule
)) {
1297 param_bool(ID::SRC_PEN
);
1298 param_bool(ID::SRC_POL
);
1299 param_bool(ID::DST_PEN
);
1300 param_bool(ID::DST_POL
);
1301 param(ID::T_LIMIT_MIN
);
1302 param(ID::T_LIMIT_TYP
);
1303 param(ID::T_LIMIT_MAX
);
1304 param(ID::T_LIMIT2_MIN
);
1305 param(ID::T_LIMIT2_TYP
);
1306 param(ID::T_LIMIT2_MAX
);
1307 port(ID::SRC_EN
, 1);
1308 port(ID::DST_EN
, 1);
1309 port(ID::SRC
, param(ID::SRC_WIDTH
));
1310 port(ID::DST
, param(ID::DST_WIDTH
));
1315 if (cell
->type
== ID($_BUF_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1316 if (cell
->type
== ID($_NOT_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1317 if (cell
->type
== ID($_AND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1318 if (cell
->type
== ID($_NAND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1319 if (cell
->type
== ID($_OR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1320 if (cell
->type
== ID($_NOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1321 if (cell
->type
== ID($_XOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1322 if (cell
->type
== ID($_XNOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1323 if (cell
->type
== ID($_ANDNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1324 if (cell
->type
== ID($_ORNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1325 if (cell
->type
== ID($_MUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1326 if (cell
->type
== ID($_NMUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1327 if (cell
->type
== ID($_AOI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1328 if (cell
->type
== ID($_OAI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1329 if (cell
->type
== ID($_AOI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1330 if (cell
->type
== ID($_OAI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1332 if (cell
->type
== ID($_TBUF_
)) { port(ID::A
,1); port(ID::Y
,1); port(ID::E
,1); check_expected(); return; }
1334 if (cell
->type
== ID($_MUX4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::S
,1); port(ID::T
,1); port(ID::Y
,1); check_expected(); return; }
1335 if (cell
->type
== ID($_MUX8_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::Y
,1); check_expected(); return; }
1336 if (cell
->type
== ID($_MUX16_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::I
,1); port(ID::J
,1); port(ID::K
,1); port(ID::L
,1); port(ID::M
,1); port(ID::N
,1); port(ID::O
,1); port(ID::P
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::V
,1); port(ID::Y
,1); check_expected(); return; }
1338 if (cell
->type
== ID($_SR_NN_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1339 if (cell
->type
== ID($_SR_NP_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1340 if (cell
->type
== ID($_SR_PN_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1341 if (cell
->type
== ID($_SR_PP_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1343 if (cell
->type
== ID($_FF_
)) { port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1344 if (cell
->type
== ID($_DFF_N_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1345 if (cell
->type
== ID($_DFF_P_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1347 if (cell
->type
== ID($_DFFE_NN_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1348 if (cell
->type
== ID($_DFFE_NP_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1349 if (cell
->type
== ID($_DFFE_PN_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1350 if (cell
->type
== ID($_DFFE_PP_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1352 if (cell
->type
== ID($_DFF_NN0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1353 if (cell
->type
== ID($_DFF_NN1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1354 if (cell
->type
== ID($_DFF_NP0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1355 if (cell
->type
== ID($_DFF_NP1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1356 if (cell
->type
== ID($_DFF_PN0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1357 if (cell
->type
== ID($_DFF_PN1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1358 if (cell
->type
== ID($_DFF_PP0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1359 if (cell
->type
== ID($_DFF_PP1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1361 if (cell
->type
== ID($_DFFSR_NNN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1362 if (cell
->type
== ID($_DFFSR_NNP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1363 if (cell
->type
== ID($_DFFSR_NPN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1364 if (cell
->type
== ID($_DFFSR_NPP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1365 if (cell
->type
== ID($_DFFSR_PNN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1366 if (cell
->type
== ID($_DFFSR_PNP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1367 if (cell
->type
== ID($_DFFSR_PPN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1368 if (cell
->type
== ID($_DFFSR_PPP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1370 if (cell
->type
== ID($_DLATCH_N_
)) { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1371 if (cell
->type
== ID($_DLATCH_P_
)) { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1373 if (cell
->type
== ID($_DLATCHSR_NNN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1374 if (cell
->type
== ID($_DLATCHSR_NNP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1375 if (cell
->type
== ID($_DLATCHSR_NPN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1376 if (cell
->type
== ID($_DLATCHSR_NPP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1377 if (cell
->type
== ID($_DLATCHSR_PNN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1378 if (cell
->type
== ID($_DLATCHSR_PNP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1379 if (cell
->type
== ID($_DLATCHSR_PPN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1380 if (cell
->type
== ID($_DLATCHSR_PPP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1388 void RTLIL::Module::sort()
1390 wires_
.sort(sort_by_id_str());
1391 cells_
.sort(sort_by_id_str());
1392 avail_parameters
.sort(sort_by_id_str());
1393 memories
.sort(sort_by_id_str());
1394 processes
.sort(sort_by_id_str());
1395 for (auto &it
: cells_
)
1397 for (auto &it
: wires_
)
1398 it
.second
->attributes
.sort(sort_by_id_str());
1399 for (auto &it
: memories
)
1400 it
.second
->attributes
.sort(sort_by_id_str());
1403 void RTLIL::Module::check()
1406 std::vector
<bool> ports_declared
;
1407 for (auto &it
: wires_
) {
1408 log_assert(this == it
.second
->module
);
1409 log_assert(it
.first
== it
.second
->name
);
1410 log_assert(!it
.first
.empty());
1411 log_assert(it
.second
->width
>= 0);
1412 log_assert(it
.second
->port_id
>= 0);
1413 for (auto &it2
: it
.second
->attributes
)
1414 log_assert(!it2
.first
.empty());
1415 if (it
.second
->port_id
) {
1416 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1417 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1418 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1419 if (GetSize(ports_declared
) < it
.second
->port_id
)
1420 ports_declared
.resize(it
.second
->port_id
);
1421 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1422 ports_declared
[it
.second
->port_id
-1] = true;
1424 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1426 for (auto port_declared
: ports_declared
)
1427 log_assert(port_declared
== true);
1428 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1430 for (auto &it
: memories
) {
1431 log_assert(it
.first
== it
.second
->name
);
1432 log_assert(!it
.first
.empty());
1433 log_assert(it
.second
->width
>= 0);
1434 log_assert(it
.second
->size
>= 0);
1435 for (auto &it2
: it
.second
->attributes
)
1436 log_assert(!it2
.first
.empty());
1439 for (auto &it
: cells_
) {
1440 log_assert(this == it
.second
->module
);
1441 log_assert(it
.first
== it
.second
->name
);
1442 log_assert(!it
.first
.empty());
1443 log_assert(!it
.second
->type
.empty());
1444 for (auto &it2
: it
.second
->connections()) {
1445 log_assert(!it2
.first
.empty());
1448 for (auto &it2
: it
.second
->attributes
)
1449 log_assert(!it2
.first
.empty());
1450 for (auto &it2
: it
.second
->parameters
)
1451 log_assert(!it2
.first
.empty());
1452 InternalCellChecker
checker(this, it
.second
);
1456 for (auto &it
: processes
) {
1457 log_assert(it
.first
== it
.second
->name
);
1458 log_assert(!it
.first
.empty());
1459 log_assert(it
.second
->root_case
.compare
.empty());
1460 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1461 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1462 for (auto &switch_it
: all_cases
[i
]->switches
) {
1463 for (auto &case_it
: switch_it
->cases
) {
1464 for (auto &compare_it
: case_it
->compare
) {
1465 log_assert(switch_it
->signal
.size() == compare_it
.size());
1467 all_cases
.push_back(case_it
);
1471 for (auto &sync_it
: it
.second
->syncs
) {
1472 switch (sync_it
->type
) {
1478 log_assert(!sync_it
->signal
.empty());
1483 log_assert(sync_it
->signal
.empty());
1489 for (auto &it
: connections_
) {
1490 log_assert(it
.first
.size() == it
.second
.size());
1491 log_assert(!it
.first
.has_const());
1496 for (auto &it
: attributes
)
1497 log_assert(!it
.first
.empty());
1501 void RTLIL::Module::optimize()
1505 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1507 log_assert(new_mod
->refcount_wires_
== 0);
1508 log_assert(new_mod
->refcount_cells_
== 0);
1510 new_mod
->avail_parameters
= avail_parameters
;
1512 for (auto &conn
: connections_
)
1513 new_mod
->connect(conn
);
1515 for (auto &attr
: attributes
)
1516 new_mod
->attributes
[attr
.first
] = attr
.second
;
1518 for (auto &it
: wires_
)
1519 new_mod
->addWire(it
.first
, it
.second
);
1521 for (auto &it
: memories
)
1522 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1524 for (auto &it
: cells_
)
1525 new_mod
->addCell(it
.first
, it
.second
);
1527 for (auto &it
: processes
)
1528 new_mod
->processes
[it
.first
] = it
.second
->clone();
1530 struct RewriteSigSpecWorker
1533 void operator()(RTLIL::SigSpec
&sig
)
1536 for (auto &c
: sig
.chunks_
)
1538 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1542 RewriteSigSpecWorker rewriteSigSpecWorker
;
1543 rewriteSigSpecWorker
.mod
= new_mod
;
1544 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1545 new_mod
->fixup_ports();
1548 RTLIL::Module
*RTLIL::Module::clone() const
1550 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1551 new_mod
->name
= name
;
1556 bool RTLIL::Module::has_memories() const
1558 return !memories
.empty();
1561 bool RTLIL::Module::has_processes() const
1563 return !processes
.empty();
1566 bool RTLIL::Module::has_memories_warn() const
1568 if (!memories
.empty())
1569 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1570 return !memories
.empty();
1573 bool RTLIL::Module::has_processes_warn() const
1575 if (!processes
.empty())
1576 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1577 return !processes
.empty();
1580 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1582 std::vector
<RTLIL::Wire
*> result
;
1583 result
.reserve(wires_
.size());
1584 for (auto &it
: wires_
)
1585 if (design
->selected(this, it
.second
))
1586 result
.push_back(it
.second
);
1590 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1592 std::vector
<RTLIL::Cell
*> result
;
1593 result
.reserve(cells_
.size());
1594 for (auto &it
: cells_
)
1595 if (design
->selected(this, it
.second
))
1596 result
.push_back(it
.second
);
1600 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1602 log_assert(!wire
->name
.empty());
1603 log_assert(count_id(wire
->name
) == 0);
1604 log_assert(refcount_wires_
== 0);
1605 wires_
[wire
->name
] = wire
;
1606 wire
->module
= this;
1609 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1611 log_assert(!cell
->name
.empty());
1612 log_assert(count_id(cell
->name
) == 0);
1613 log_assert(refcount_cells_
== 0);
1614 cells_
[cell
->name
] = cell
;
1615 cell
->module
= this;
1618 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1620 log_assert(refcount_wires_
== 0);
1622 struct DeleteWireWorker
1624 RTLIL::Module
*module
;
1625 const pool
<RTLIL::Wire
*> *wires_p
;
1627 void operator()(RTLIL::SigSpec
&sig
) {
1629 for (auto &c
: sig
.chunks_
)
1630 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1631 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1636 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1637 log_assert(GetSize(lhs
) == GetSize(rhs
));
1640 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1641 RTLIL::SigBit
&lhs_bit
= lhs
.bits_
[i
];
1642 RTLIL::SigBit
&rhs_bit
= rhs
.bits_
[i
];
1643 if ((lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
)) || (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))) {
1644 lhs_bit
= State::Sx
;
1645 rhs_bit
= State::Sx
;
1651 DeleteWireWorker delete_wire_worker
;
1652 delete_wire_worker
.module
= this;
1653 delete_wire_worker
.wires_p
= &wires
;
1654 rewrite_sigspecs2(delete_wire_worker
);
1656 for (auto &it
: wires
) {
1657 log_assert(wires_
.count(it
->name
) != 0);
1658 wires_
.erase(it
->name
);
1663 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1665 while (!cell
->connections_
.empty())
1666 cell
->unsetPort(cell
->connections_
.begin()->first
);
1668 log_assert(cells_
.count(cell
->name
) != 0);
1669 log_assert(refcount_cells_
== 0);
1670 cells_
.erase(cell
->name
);
1674 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1676 log_assert(wires_
[wire
->name
] == wire
);
1677 log_assert(refcount_wires_
== 0);
1678 wires_
.erase(wire
->name
);
1679 wire
->name
= new_name
;
1683 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1685 log_assert(cells_
[cell
->name
] == cell
);
1686 log_assert(refcount_wires_
== 0);
1687 cells_
.erase(cell
->name
);
1688 cell
->name
= new_name
;
1692 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1694 log_assert(count_id(old_name
) != 0);
1695 if (wires_
.count(old_name
))
1696 rename(wires_
.at(old_name
), new_name
);
1697 else if (cells_
.count(old_name
))
1698 rename(cells_
.at(old_name
), new_name
);
1703 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1705 log_assert(wires_
[w1
->name
] == w1
);
1706 log_assert(wires_
[w2
->name
] == w2
);
1707 log_assert(refcount_wires_
== 0);
1709 wires_
.erase(w1
->name
);
1710 wires_
.erase(w2
->name
);
1712 std::swap(w1
->name
, w2
->name
);
1714 wires_
[w1
->name
] = w1
;
1715 wires_
[w2
->name
] = w2
;
1718 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1720 log_assert(cells_
[c1
->name
] == c1
);
1721 log_assert(cells_
[c2
->name
] == c2
);
1722 log_assert(refcount_cells_
== 0);
1724 cells_
.erase(c1
->name
);
1725 cells_
.erase(c2
->name
);
1727 std::swap(c1
->name
, c2
->name
);
1729 cells_
[c1
->name
] = c1
;
1730 cells_
[c2
->name
] = c2
;
1733 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1736 return uniquify(name
, index
);
1739 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1742 if (count_id(name
) == 0)
1748 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1749 if (count_id(new_name
) == 0)
1755 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1757 if (a
->port_id
&& !b
->port_id
)
1759 if (!a
->port_id
&& b
->port_id
)
1762 if (a
->port_id
== b
->port_id
)
1763 return a
->name
< b
->name
;
1764 return a
->port_id
< b
->port_id
;
1767 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1769 for (auto mon
: monitors
)
1770 mon
->notify_connect(this, conn
);
1773 for (auto mon
: design
->monitors
)
1774 mon
->notify_connect(this, conn
);
1776 // ignore all attempts to assign constants to other constants
1777 if (conn
.first
.has_const()) {
1778 RTLIL::SigSig new_conn
;
1779 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1780 if (conn
.first
[i
].wire
) {
1781 new_conn
.first
.append(conn
.first
[i
]);
1782 new_conn
.second
.append(conn
.second
[i
]);
1784 if (GetSize(new_conn
.first
))
1790 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1791 log_backtrace("-X- ", yosys_xtrace
-1);
1794 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1795 connections_
.push_back(conn
);
1798 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1800 connect(RTLIL::SigSig(lhs
, rhs
));
1803 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1805 for (auto mon
: monitors
)
1806 mon
->notify_connect(this, new_conn
);
1809 for (auto mon
: design
->monitors
)
1810 mon
->notify_connect(this, new_conn
);
1813 log("#X# New connections vector in %s:\n", log_id(this));
1814 for (auto &conn
: new_conn
)
1815 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1816 log_backtrace("-X- ", yosys_xtrace
-1);
1819 connections_
= new_conn
;
1822 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1824 return connections_
;
1827 void RTLIL::Module::fixup_ports()
1829 std::vector
<RTLIL::Wire
*> all_ports
;
1831 for (auto &w
: wires_
)
1832 if (w
.second
->port_input
|| w
.second
->port_output
)
1833 all_ports
.push_back(w
.second
);
1835 w
.second
->port_id
= 0;
1837 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1840 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1841 ports
.push_back(all_ports
[i
]->name
);
1842 all_ports
[i
]->port_id
= i
+1;
1846 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1848 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1850 wire
->width
= width
;
1855 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1857 RTLIL::Wire
*wire
= addWire(name
);
1858 wire
->width
= other
->width
;
1859 wire
->start_offset
= other
->start_offset
;
1860 wire
->port_id
= other
->port_id
;
1861 wire
->port_input
= other
->port_input
;
1862 wire
->port_output
= other
->port_output
;
1863 wire
->upto
= other
->upto
;
1864 wire
->attributes
= other
->attributes
;
1868 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1870 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1877 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1879 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1880 cell
->connections_
= other
->connections_
;
1881 cell
->parameters
= other
->parameters
;
1882 cell
->attributes
= other
->attributes
;
1886 #define DEF_METHOD(_func, _y_size, _type) \
1887 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1888 RTLIL::Cell *cell = addCell(name, _type); \
1889 cell->parameters[ID::A_SIGNED] = is_signed; \
1890 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1891 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1892 cell->setPort(ID::A, sig_a); \
1893 cell->setPort(ID::Y, sig_y); \
1894 cell->set_src_attribute(src); \
1897 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1898 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1899 add ## _func(name, sig_a, sig_y, is_signed, src); \
1902 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
1903 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
1904 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
1905 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
1906 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
1907 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
1908 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
1909 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
1910 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
1913 #define DEF_METHOD(_func, _y_size, _type) \
1914 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1915 RTLIL::Cell *cell = addCell(name, _type); \
1916 cell->parameters[ID::A_SIGNED] = is_signed; \
1917 cell->parameters[ID::B_SIGNED] = is_signed; \
1918 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1919 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1920 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1921 cell->setPort(ID::A, sig_a); \
1922 cell->setPort(ID::B, sig_b); \
1923 cell->setPort(ID::Y, sig_y); \
1924 cell->set_src_attribute(src); \
1927 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1928 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1929 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1932 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
1933 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
1934 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
1935 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
1936 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
1937 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
1938 DEF_METHOD(Lt
, 1, ID($lt
))
1939 DEF_METHOD(Le
, 1, ID($le
))
1940 DEF_METHOD(Eq
, 1, ID($eq
))
1941 DEF_METHOD(Ne
, 1, ID($ne
))
1942 DEF_METHOD(Eqx
, 1, ID($eqx
))
1943 DEF_METHOD(Nex
, 1, ID($nex
))
1944 DEF_METHOD(Ge
, 1, ID($ge
))
1945 DEF_METHOD(Gt
, 1, ID($gt
))
1946 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
1947 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
1948 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
1949 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
1950 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
1951 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
1952 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
1955 #define DEF_METHOD(_func, _y_size, _type) \
1956 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1957 RTLIL::Cell *cell = addCell(name, _type); \
1958 cell->parameters[ID::A_SIGNED] = is_signed; \
1959 cell->parameters[ID::B_SIGNED] = false; \
1960 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1961 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1962 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1963 cell->setPort(ID::A, sig_a); \
1964 cell->setPort(ID::B, sig_b); \
1965 cell->setPort(ID::Y, sig_y); \
1966 cell->set_src_attribute(src); \
1969 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1970 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1971 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1974 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
1975 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
1976 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
1977 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
1980 #define DEF_METHOD(_func, _type, _pmux) \
1981 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1982 RTLIL::Cell *cell = addCell(name, _type); \
1983 cell->parameters[ID::WIDTH] = sig_a.size(); \
1984 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1985 cell->setPort(ID::A, sig_a); \
1986 cell->setPort(ID::B, sig_b); \
1987 cell->setPort(ID::S, sig_s); \
1988 cell->setPort(ID::Y, sig_y); \
1989 cell->set_src_attribute(src); \
1992 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1993 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1994 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1997 DEF_METHOD(Mux
, ID($mux
), 0)
1998 DEF_METHOD(Pmux
, ID($pmux
), 1)
2001 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2002 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2003 RTLIL::Cell *cell = addCell(name, _type); \
2004 cell->setPort("\\" #_P1, sig1); \
2005 cell->setPort("\\" #_P2, sig2); \
2006 cell->set_src_attribute(src); \
2009 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2010 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2011 add ## _func(name, sig1, sig2, src); \
2014 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2015 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2016 RTLIL::Cell *cell = addCell(name, _type); \
2017 cell->setPort("\\" #_P1, sig1); \
2018 cell->setPort("\\" #_P2, sig2); \
2019 cell->setPort("\\" #_P3, sig3); \
2020 cell->set_src_attribute(src); \
2023 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2024 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2025 add ## _func(name, sig1, sig2, sig3, src); \
2028 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2029 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2030 RTLIL::Cell *cell = addCell(name, _type); \
2031 cell->setPort("\\" #_P1, sig1); \
2032 cell->setPort("\\" #_P2, sig2); \
2033 cell->setPort("\\" #_P3, sig3); \
2034 cell->setPort("\\" #_P4, sig4); \
2035 cell->set_src_attribute(src); \
2038 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2039 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2040 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2043 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2044 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2045 RTLIL::Cell *cell = addCell(name, _type); \
2046 cell->setPort("\\" #_P1, sig1); \
2047 cell->setPort("\\" #_P2, sig2); \
2048 cell->setPort("\\" #_P3, sig3); \
2049 cell->setPort("\\" #_P4, sig4); \
2050 cell->setPort("\\" #_P5, sig5); \
2051 cell->set_src_attribute(src); \
2054 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2055 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2056 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2059 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
2060 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
2061 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
2062 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
2063 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
2064 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
2065 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
2066 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
2067 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
2068 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
2069 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
2070 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
2071 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
2072 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
2073 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
2074 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2080 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2082 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2083 cell
->parameters
[ID::A_SIGNED
] = a_signed
;
2084 cell
->parameters
[ID::B_SIGNED
] = b_signed
;
2085 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2086 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2087 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2088 cell
->setPort(ID::A
, sig_a
);
2089 cell
->setPort(ID::B
, sig_b
);
2090 cell
->setPort(ID::Y
, sig_y
);
2091 cell
->set_src_attribute(src
);
2095 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const offset
, const std::string
&src
)
2097 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2098 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2099 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2100 cell
->parameters
[ID::OFFSET
] = offset
;
2101 cell
->setPort(ID::A
, sig_a
);
2102 cell
->setPort(ID::Y
, sig_y
);
2103 cell
->set_src_attribute(src
);
2107 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2109 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2110 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2111 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2112 cell
->setPort(ID::A
, sig_a
);
2113 cell
->setPort(ID::B
, sig_b
);
2114 cell
->setPort(ID::Y
, sig_y
);
2115 cell
->set_src_attribute(src
);
2119 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const lut
, const std::string
&src
)
2121 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2122 cell
->parameters
[ID::LUT
] = lut
;
2123 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2124 cell
->setPort(ID::A
, sig_a
);
2125 cell
->setPort(ID::Y
, sig_y
);
2126 cell
->set_src_attribute(src
);
2130 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2132 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2133 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2134 cell
->setPort(ID::A
, sig_a
);
2135 cell
->setPort(ID::EN
, sig_en
);
2136 cell
->setPort(ID::Y
, sig_y
);
2137 cell
->set_src_attribute(src
);
2141 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2143 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2144 cell
->setPort(ID::A
, sig_a
);
2145 cell
->setPort(ID::EN
, sig_en
);
2146 cell
->set_src_attribute(src
);
2150 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2152 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2153 cell
->setPort(ID::A
, sig_a
);
2154 cell
->setPort(ID::EN
, sig_en
);
2155 cell
->set_src_attribute(src
);
2159 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2161 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2162 cell
->setPort(ID::A
, sig_a
);
2163 cell
->setPort(ID::EN
, sig_en
);
2164 cell
->set_src_attribute(src
);
2168 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2170 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2171 cell
->setPort(ID::A
, sig_a
);
2172 cell
->setPort(ID::EN
, sig_en
);
2173 cell
->set_src_attribute(src
);
2177 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2179 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2180 cell
->setPort(ID::A
, sig_a
);
2181 cell
->setPort(ID::EN
, sig_en
);
2182 cell
->set_src_attribute(src
);
2186 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2188 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2189 cell
->setPort(ID::A
, sig_a
);
2190 cell
->setPort(ID::B
, sig_b
);
2191 cell
->setPort(ID::Y
, sig_y
);
2192 cell
->set_src_attribute(src
);
2196 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
, const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2198 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2199 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2200 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2201 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2202 cell
->setPort(ID::SET
, sig_set
);
2203 cell
->setPort(ID::CLR
, sig_clr
);
2204 cell
->setPort(ID::Q
, sig_q
);
2205 cell
->set_src_attribute(src
);
2209 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2211 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2212 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2213 cell
->setPort(ID::D
, sig_d
);
2214 cell
->setPort(ID::Q
, sig_q
);
2215 cell
->set_src_attribute(src
);
2219 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2221 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2222 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2223 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2224 cell
->setPort(ID::CLK
, sig_clk
);
2225 cell
->setPort(ID::D
, sig_d
);
2226 cell
->setPort(ID::Q
, sig_q
);
2227 cell
->set_src_attribute(src
);
2231 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2233 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2234 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2235 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2236 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2237 cell
->setPort(ID::CLK
, sig_clk
);
2238 cell
->setPort(ID::EN
, sig_en
);
2239 cell
->setPort(ID::D
, sig_d
);
2240 cell
->setPort(ID::Q
, sig_q
);
2241 cell
->set_src_attribute(src
);
2245 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2246 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2248 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2249 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2250 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2251 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2252 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2253 cell
->setPort(ID::CLK
, sig_clk
);
2254 cell
->setPort(ID::SET
, sig_set
);
2255 cell
->setPort(ID::CLR
, sig_clr
);
2256 cell
->setPort(ID::D
, sig_d
);
2257 cell
->setPort(ID::Q
, sig_q
);
2258 cell
->set_src_attribute(src
);
2262 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2263 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2265 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2266 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2267 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2268 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2269 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2270 cell
->setPort(ID::CLK
, sig_clk
);
2271 cell
->setPort(ID::ARST
, sig_arst
);
2272 cell
->setPort(ID::D
, sig_d
);
2273 cell
->setPort(ID::Q
, sig_q
);
2274 cell
->set_src_attribute(src
);
2278 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2280 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2281 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2282 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2283 cell
->setPort(ID::EN
, sig_en
);
2284 cell
->setPort(ID::D
, sig_d
);
2285 cell
->setPort(ID::Q
, sig_q
);
2286 cell
->set_src_attribute(src
);
2290 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2291 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2293 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2294 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2295 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2296 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2297 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2298 cell
->setPort(ID::EN
, sig_en
);
2299 cell
->setPort(ID::SET
, sig_set
);
2300 cell
->setPort(ID::CLR
, sig_clr
);
2301 cell
->setPort(ID::D
, sig_d
);
2302 cell
->setPort(ID::Q
, sig_q
);
2303 cell
->set_src_attribute(src
);
2307 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2309 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2310 cell
->setPort(ID::D
, sig_d
);
2311 cell
->setPort(ID::Q
, sig_q
);
2312 cell
->set_src_attribute(src
);
2316 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2318 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2319 cell
->setPort(ID::C
, sig_clk
);
2320 cell
->setPort(ID::D
, sig_d
);
2321 cell
->setPort(ID::Q
, sig_q
);
2322 cell
->set_src_attribute(src
);
2326 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2328 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2329 cell
->setPort(ID::C
, sig_clk
);
2330 cell
->setPort(ID::E
, sig_en
);
2331 cell
->setPort(ID::D
, sig_d
);
2332 cell
->setPort(ID::Q
, sig_q
);
2333 cell
->set_src_attribute(src
);
2337 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2338 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2340 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2341 cell
->setPort(ID::C
, sig_clk
);
2342 cell
->setPort(ID::S
, sig_set
);
2343 cell
->setPort(ID::R
, sig_clr
);
2344 cell
->setPort(ID::D
, sig_d
);
2345 cell
->setPort(ID::Q
, sig_q
);
2346 cell
->set_src_attribute(src
);
2350 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2351 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2353 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2354 cell
->setPort(ID::C
, sig_clk
);
2355 cell
->setPort(ID::R
, sig_arst
);
2356 cell
->setPort(ID::D
, sig_d
);
2357 cell
->setPort(ID::Q
, sig_q
);
2358 cell
->set_src_attribute(src
);
2362 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2364 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2365 cell
->setPort(ID::E
, sig_en
);
2366 cell
->setPort(ID::D
, sig_d
);
2367 cell
->setPort(ID::Q
, sig_q
);
2368 cell
->set_src_attribute(src
);
2372 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2373 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2375 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2376 cell
->setPort(ID::E
, sig_en
);
2377 cell
->setPort(ID::S
, sig_set
);
2378 cell
->setPort(ID::R
, sig_clr
);
2379 cell
->setPort(ID::D
, sig_d
);
2380 cell
->setPort(ID::Q
, sig_q
);
2381 cell
->set_src_attribute(src
);
2385 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2387 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2388 Cell
*cell
= addCell(name
, ID($anyconst
));
2389 cell
->setParam(ID::WIDTH
, width
);
2390 cell
->setPort(ID::Y
, sig
);
2391 cell
->set_src_attribute(src
);
2395 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2397 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2398 Cell
*cell
= addCell(name
, ID($anyseq
));
2399 cell
->setParam(ID::WIDTH
, width
);
2400 cell
->setPort(ID::Y
, sig
);
2401 cell
->set_src_attribute(src
);
2405 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2407 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2408 Cell
*cell
= addCell(name
, ID($allconst
));
2409 cell
->setParam(ID::WIDTH
, width
);
2410 cell
->setPort(ID::Y
, sig
);
2411 cell
->set_src_attribute(src
);
2415 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2417 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2418 Cell
*cell
= addCell(name
, ID($allseq
));
2419 cell
->setParam(ID::WIDTH
, width
);
2420 cell
->setPort(ID::Y
, sig
);
2421 cell
->set_src_attribute(src
);
2425 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2427 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2428 Cell
*cell
= addCell(name
, ID($initstate
));
2429 cell
->setPort(ID::Y
, sig
);
2430 cell
->set_src_attribute(src
);
2436 static unsigned int hashidx_count
= 123456789;
2437 hashidx_count
= mkhash_xorshift(hashidx_count
);
2438 hashidx_
= hashidx_count
;
2445 port_output
= false;
2449 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2453 RTLIL::Wire::~Wire()
2456 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2461 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2462 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2468 RTLIL::Memory::Memory()
2470 static unsigned int hashidx_count
= 123456789;
2471 hashidx_count
= mkhash_xorshift(hashidx_count
);
2472 hashidx_
= hashidx_count
;
2478 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2482 RTLIL::Cell::Cell() : module(nullptr)
2484 static unsigned int hashidx_count
= 123456789;
2485 hashidx_count
= mkhash_xorshift(hashidx_count
);
2486 hashidx_
= hashidx_count
;
2488 // log("#memtrace# %p\n", this);
2492 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2496 RTLIL::Cell::~Cell()
2499 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2504 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2505 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2511 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2513 return connections_
.count(portname
) != 0;
2516 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2518 RTLIL::SigSpec signal
;
2519 auto conn_it
= connections_
.find(portname
);
2521 if (conn_it
!= connections_
.end())
2523 for (auto mon
: module
->monitors
)
2524 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2527 for (auto mon
: module
->design
->monitors
)
2528 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2531 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2532 log_backtrace("-X- ", yosys_xtrace
-1);
2535 connections_
.erase(conn_it
);
2539 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2541 auto r
= connections_
.insert(portname
);
2542 auto conn_it
= r
.first
;
2543 if (!r
.second
&& conn_it
->second
== signal
)
2546 for (auto mon
: module
->monitors
)
2547 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2550 for (auto mon
: module
->design
->monitors
)
2551 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2554 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2555 log_backtrace("-X- ", yosys_xtrace
-1);
2558 conn_it
->second
= std::move(signal
);
2561 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2563 return connections_
.at(portname
);
2566 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2568 return connections_
;
2571 bool RTLIL::Cell::known() const
2573 if (yosys_celltypes
.cell_known(type
))
2575 if (module
&& module
->design
&& module
->design
->module(type
))
2580 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2582 if (yosys_celltypes
.cell_known(type
))
2583 return yosys_celltypes
.cell_input(type
, portname
);
2584 if (module
&& module
->design
) {
2585 RTLIL::Module
*m
= module
->design
->module(type
);
2586 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2587 return w
&& w
->port_input
;
2592 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2594 if (yosys_celltypes
.cell_known(type
))
2595 return yosys_celltypes
.cell_output(type
, portname
);
2596 if (module
&& module
->design
) {
2597 RTLIL::Module
*m
= module
->design
->module(type
);
2598 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2599 return w
&& w
->port_output
;
2604 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2606 return parameters
.count(paramname
) != 0;
2609 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2611 parameters
.erase(paramname
);
2614 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2616 parameters
[paramname
] = std::move(value
);
2619 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2621 return parameters
.at(paramname
);
2624 void RTLIL::Cell::sort()
2626 connections_
.sort(sort_by_id_str());
2627 parameters
.sort(sort_by_id_str());
2628 attributes
.sort(sort_by_id_str());
2631 void RTLIL::Cell::check()
2634 InternalCellChecker
checker(NULL
, this);
2639 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2641 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
2642 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
2645 if (type
== ID($mux
) || type
== ID($pmux
)) {
2646 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
2647 if (type
== ID($pmux
))
2648 parameters
[ID::S_WIDTH
] = GetSize(connections_
[ID::S
]);
2653 if (type
== ID($lut
) || type
== ID($sop
)) {
2654 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::A
]);
2658 if (type
== ID($fa
)) {
2659 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
2663 if (type
== ID($lcu
)) {
2664 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::CO
]);
2668 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
2670 if (connections_
.count(ID::A
)) {
2671 if (signedness_ab
) {
2673 parameters
[ID::A_SIGNED
] = true;
2674 else if (parameters
.count(ID::A_SIGNED
) == 0)
2675 parameters
[ID::A_SIGNED
] = false;
2677 parameters
[ID::A_WIDTH
] = GetSize(connections_
[ID::A
]);
2680 if (connections_
.count(ID::B
)) {
2681 if (signedness_ab
) {
2683 parameters
[ID::B_SIGNED
] = true;
2684 else if (parameters
.count(ID::B_SIGNED
) == 0)
2685 parameters
[ID::B_SIGNED
] = false;
2687 parameters
[ID::B_WIDTH
] = GetSize(connections_
[ID::B
]);
2690 if (connections_
.count(ID::Y
))
2691 parameters
[ID::Y_WIDTH
] = GetSize(connections_
[ID::Y
]);
2693 if (connections_
.count(ID::Q
))
2694 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Q
]);
2699 RTLIL::SigChunk::SigChunk()
2706 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2710 width
= GetSize(data
);
2714 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2716 log_assert(wire
!= nullptr);
2718 this->width
= wire
->width
;
2722 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2724 log_assert(wire
!= nullptr);
2726 this->width
= width
;
2727 this->offset
= offset
;
2730 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2733 data
= RTLIL::Const(str
).bits
;
2734 width
= GetSize(data
);
2738 RTLIL::SigChunk::SigChunk(int val
, int width
)
2741 data
= RTLIL::Const(val
, width
).bits
;
2742 this->width
= GetSize(data
);
2746 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2749 data
= RTLIL::Const(bit
, width
).bits
;
2750 this->width
= GetSize(data
);
2754 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit
&bit
)
2759 data
= RTLIL::Const(bit
.data
).bits
;
2761 offset
= bit
.offset
;
2765 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
)
2770 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2772 RTLIL::SigChunk ret
;
2775 ret
.offset
= this->offset
+ offset
;
2778 for (int i
= 0; i
< length
; i
++)
2779 ret
.data
.push_back(data
[offset
+i
]);
2785 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2787 if (wire
&& other
.wire
)
2788 if (wire
->name
!= other
.wire
->name
)
2789 return wire
->name
< other
.wire
->name
;
2791 if (wire
!= other
.wire
)
2792 return wire
< other
.wire
;
2794 if (offset
!= other
.offset
)
2795 return offset
< other
.offset
;
2797 if (width
!= other
.width
)
2798 return width
< other
.width
;
2800 return data
< other
.data
;
2803 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2805 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2808 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2815 RTLIL::SigSpec::SigSpec()
2821 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2826 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2828 cover("kernel.rtlil.sigspec.init.list");
2833 log_assert(parts
.size() > 0);
2834 auto ie
= parts
.begin();
2835 auto it
= ie
+ parts
.size() - 1;
2840 RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2842 cover("kernel.rtlil.sigspec.assign");
2844 width_
= other
.width_
;
2845 hash_
= other
.hash_
;
2846 chunks_
= other
.chunks_
;
2847 bits_
= other
.bits_
;
2851 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2853 cover("kernel.rtlil.sigspec.init.const");
2855 chunks_
.emplace_back(value
);
2856 width_
= chunks_
.back().width
;
2861 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2863 cover("kernel.rtlil.sigspec.init.chunk");
2865 chunks_
.emplace_back(chunk
);
2866 width_
= chunks_
.back().width
;
2871 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2873 cover("kernel.rtlil.sigspec.init.wire");
2875 chunks_
.emplace_back(wire
);
2876 width_
= chunks_
.back().width
;
2881 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2883 cover("kernel.rtlil.sigspec.init.wire_part");
2885 chunks_
.emplace_back(wire
, offset
, width
);
2886 width_
= chunks_
.back().width
;
2891 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2893 cover("kernel.rtlil.sigspec.init.str");
2895 chunks_
.emplace_back(str
);
2896 width_
= chunks_
.back().width
;
2901 RTLIL::SigSpec::SigSpec(int val
, int width
)
2903 cover("kernel.rtlil.sigspec.init.int");
2905 chunks_
.emplace_back(val
, width
);
2911 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2913 cover("kernel.rtlil.sigspec.init.state");
2915 chunks_
.emplace_back(bit
, width
);
2921 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit
&bit
, int width
)
2923 cover("kernel.rtlil.sigspec.init.bit");
2925 if (bit
.wire
== NULL
)
2926 chunks_
.emplace_back(bit
.data
, width
);
2928 for (int i
= 0; i
< width
; i
++)
2929 chunks_
.push_back(bit
);
2935 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigChunk
> &chunks
)
2937 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2941 for (const auto &c
: chunks
)
2946 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigBit
> &bits
)
2948 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2952 for (const auto &bit
: bits
)
2957 RTLIL::SigSpec::SigSpec(const pool
<RTLIL::SigBit
> &bits
)
2959 cover("kernel.rtlil.sigspec.init.pool_bits");
2963 for (const auto &bit
: bits
)
2968 RTLIL::SigSpec::SigSpec(const std::set
<RTLIL::SigBit
> &bits
)
2970 cover("kernel.rtlil.sigspec.init.stdset_bits");
2974 for (const auto &bit
: bits
)
2979 RTLIL::SigSpec::SigSpec(bool bit
)
2981 cover("kernel.rtlil.sigspec.init.bool");
2985 append(SigBit(bit
));
2989 void RTLIL::SigSpec::pack() const
2991 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2993 if (that
->bits_
.empty())
2996 cover("kernel.rtlil.sigspec.convert.pack");
2997 log_assert(that
->chunks_
.empty());
2999 std::vector
<RTLIL::SigBit
> old_bits
;
3000 old_bits
.swap(that
->bits_
);
3002 RTLIL::SigChunk
*last
= NULL
;
3003 int last_end_offset
= 0;
3005 for (auto &bit
: old_bits
) {
3006 if (last
&& bit
.wire
== last
->wire
) {
3007 if (bit
.wire
== NULL
) {
3008 last
->data
.push_back(bit
.data
);
3011 } else if (last_end_offset
== bit
.offset
) {
3017 that
->chunks_
.push_back(bit
);
3018 last
= &that
->chunks_
.back();
3019 last_end_offset
= bit
.offset
+ 1;
3025 void RTLIL::SigSpec::unpack() const
3027 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3029 if (that
->chunks_
.empty())
3032 cover("kernel.rtlil.sigspec.convert.unpack");
3033 log_assert(that
->bits_
.empty());
3035 that
->bits_
.reserve(that
->width_
);
3036 for (auto &c
: that
->chunks_
)
3037 for (int i
= 0; i
< c
.width
; i
++)
3038 that
->bits_
.emplace_back(c
, i
);
3040 that
->chunks_
.clear();
3044 void RTLIL::SigSpec::updhash() const
3046 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3048 if (that
->hash_
!= 0)
3051 cover("kernel.rtlil.sigspec.hash");
3054 that
->hash_
= mkhash_init
;
3055 for (auto &c
: that
->chunks_
)
3056 if (c
.wire
== NULL
) {
3057 for (auto &v
: c
.data
)
3058 that
->hash_
= mkhash(that
->hash_
, v
);
3060 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3061 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3062 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3065 if (that
->hash_
== 0)
3069 void RTLIL::SigSpec::sort()
3072 cover("kernel.rtlil.sigspec.sort");
3073 std::sort(bits_
.begin(), bits_
.end());
3076 void RTLIL::SigSpec::sort_and_unify()
3079 cover("kernel.rtlil.sigspec.sort_and_unify");
3081 // A copy of the bits vector is used to prevent duplicating the logic from
3082 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3083 // that isn't showing up as significant in profiles.
3084 std::vector
<SigBit
> unique_bits
= bits_
;
3085 std::sort(unique_bits
.begin(), unique_bits
.end());
3086 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3087 unique_bits
.erase(last
, unique_bits
.end());
3089 *this = unique_bits
;
3092 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3094 replace(pattern
, with
, this);
3097 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3099 log_assert(other
!= NULL
);
3100 log_assert(width_
== other
->width_
);
3101 log_assert(pattern
.width_
== with
.width_
);
3108 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3109 if (pattern
.bits_
[i
].wire
!= NULL
) {
3110 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3111 if (bits_
[j
] == pattern
.bits_
[i
]) {
3112 other
->bits_
[j
] = with
.bits_
[i
];
3121 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3123 replace(rules
, this);
3126 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3128 cover("kernel.rtlil.sigspec.replace_dict");
3130 log_assert(other
!= NULL
);
3131 log_assert(width_
== other
->width_
);
3133 if (rules
.empty()) return;
3137 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3138 auto it
= rules
.find(bits_
[i
]);
3139 if (it
!= rules
.end())
3140 other
->bits_
[i
] = it
->second
;
3146 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3148 replace(rules
, this);
3151 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3153 cover("kernel.rtlil.sigspec.replace_map");
3155 log_assert(other
!= NULL
);
3156 log_assert(width_
== other
->width_
);
3158 if (rules
.empty()) return;
3162 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3163 auto it
= rules
.find(bits_
[i
]);
3164 if (it
!= rules
.end())
3165 other
->bits_
[i
] = it
->second
;
3171 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3173 remove2(pattern
, NULL
);
3176 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3178 RTLIL::SigSpec tmp
= *this;
3179 tmp
.remove2(pattern
, other
);
3182 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3185 cover("kernel.rtlil.sigspec.remove_other");
3187 cover("kernel.rtlil.sigspec.remove");
3190 if (other
!= NULL
) {
3191 log_assert(width_
== other
->width_
);
3195 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3197 if (bits_
[i
].wire
== NULL
) continue;
3199 for (auto &pattern_chunk
: pattern
.chunks())
3200 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3201 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3202 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3203 bits_
.erase(bits_
.begin() + i
);
3205 if (other
!= NULL
) {
3206 other
->bits_
.erase(other
->bits_
.begin() + i
);
3216 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3218 remove2(pattern
, NULL
);
3221 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3223 RTLIL::SigSpec tmp
= *this;
3224 tmp
.remove2(pattern
, other
);
3227 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3230 cover("kernel.rtlil.sigspec.remove_other");
3232 cover("kernel.rtlil.sigspec.remove");
3236 if (other
!= NULL
) {
3237 log_assert(width_
== other
->width_
);
3241 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3242 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3243 bits_
.erase(bits_
.begin() + i
);
3245 if (other
!= NULL
) {
3246 other
->bits_
.erase(other
->bits_
.begin() + i
);
3255 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3258 cover("kernel.rtlil.sigspec.remove_other");
3260 cover("kernel.rtlil.sigspec.remove");
3264 if (other
!= NULL
) {
3265 log_assert(width_
== other
->width_
);
3269 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3270 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3271 bits_
.erase(bits_
.begin() + i
);
3273 if (other
!= NULL
) {
3274 other
->bits_
.erase(other
->bits_
.begin() + i
);
3283 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3286 cover("kernel.rtlil.sigspec.extract_other");
3288 cover("kernel.rtlil.sigspec.extract");
3290 log_assert(other
== NULL
|| width_
== other
->width_
);
3293 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3295 for (auto& pattern_chunk
: pattern
.chunks()) {
3297 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3298 for (int i
= 0; i
< width_
; i
++)
3299 if (bits_match
[i
].wire
&&
3300 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3301 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3302 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3303 ret
.append(bits_other
[i
]);
3305 for (int i
= 0; i
< width_
; i
++)
3306 if (bits_match
[i
].wire
&&
3307 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3308 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3309 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3310 ret
.append(bits_match
[i
]);
3318 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3321 cover("kernel.rtlil.sigspec.extract_other");
3323 cover("kernel.rtlil.sigspec.extract");
3325 log_assert(other
== NULL
|| width_
== other
->width_
);
3327 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3331 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3332 for (int i
= 0; i
< width_
; i
++)
3333 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3334 ret
.append(bits_other
[i
]);
3336 for (int i
= 0; i
< width_
; i
++)
3337 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3338 ret
.append(bits_match
[i
]);
3345 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3347 cover("kernel.rtlil.sigspec.replace_pos");
3352 log_assert(offset
>= 0);
3353 log_assert(with
.width_
>= 0);
3354 log_assert(offset
+with
.width_
<= width_
);
3356 for (int i
= 0; i
< with
.width_
; i
++)
3357 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3362 void RTLIL::SigSpec::remove_const()
3366 cover("kernel.rtlil.sigspec.remove_const.packed");
3368 std::vector
<RTLIL::SigChunk
> new_chunks
;
3369 new_chunks
.reserve(GetSize(chunks_
));
3372 for (auto &chunk
: chunks_
)
3373 if (chunk
.wire
!= NULL
) {
3374 new_chunks
.push_back(chunk
);
3375 width_
+= chunk
.width
;
3378 chunks_
.swap(new_chunks
);
3382 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3384 std::vector
<RTLIL::SigBit
> new_bits
;
3385 new_bits
.reserve(width_
);
3387 for (auto &bit
: bits_
)
3388 if (bit
.wire
!= NULL
)
3389 new_bits
.push_back(bit
);
3391 bits_
.swap(new_bits
);
3392 width_
= bits_
.size();
3398 void RTLIL::SigSpec::remove(int offset
, int length
)
3400 cover("kernel.rtlil.sigspec.remove_pos");
3404 log_assert(offset
>= 0);
3405 log_assert(length
>= 0);
3406 log_assert(offset
+ length
<= width_
);
3408 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3409 width_
= bits_
.size();
3414 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3417 cover("kernel.rtlil.sigspec.extract_pos");
3418 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3421 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3423 if (signal
.width_
== 0)
3431 cover("kernel.rtlil.sigspec.append");
3433 if (packed() != signal
.packed()) {
3439 for (auto &other_c
: signal
.chunks_
)
3441 auto &my_last_c
= chunks_
.back();
3442 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3443 auto &this_data
= my_last_c
.data
;
3444 auto &other_data
= other_c
.data
;
3445 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3446 my_last_c
.width
+= other_c
.width
;
3448 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3449 my_last_c
.width
+= other_c
.width
;
3451 chunks_
.push_back(other_c
);
3454 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3456 width_
+= signal
.width_
;
3460 void RTLIL::SigSpec::append(const RTLIL::SigBit
&bit
)
3464 cover("kernel.rtlil.sigspec.append_bit.packed");
3466 if (chunks_
.size() == 0)
3467 chunks_
.push_back(bit
);
3469 if (bit
.wire
== NULL
)
3470 if (chunks_
.back().wire
== NULL
) {
3471 chunks_
.back().data
.push_back(bit
.data
);
3472 chunks_
.back().width
++;
3474 chunks_
.push_back(bit
);
3476 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3477 chunks_
.back().width
++;
3479 chunks_
.push_back(bit
);
3483 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3484 bits_
.push_back(bit
);
3491 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3493 cover("kernel.rtlil.sigspec.extend_u0");
3498 remove(width
, width_
- width
);
3500 if (width_
< width
) {
3501 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3503 padding
= RTLIL::State::S0
;
3504 while (width_
< width
)
3510 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3512 cover("kernel.rtlil.sigspec.repeat");
3515 for (int i
= 0; i
< num
; i
++)
3521 void RTLIL::SigSpec::check() const
3525 cover("kernel.rtlil.sigspec.check.skip");
3529 cover("kernel.rtlil.sigspec.check.packed");
3532 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3533 const RTLIL::SigChunk
&chunk
= chunks_
[i
];
3534 if (chunk
.wire
== NULL
) {
3536 log_assert(chunks_
[i
-1].wire
!= NULL
);
3537 log_assert(chunk
.offset
== 0);
3538 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3540 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3541 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3542 log_assert(chunk
.offset
>= 0);
3543 log_assert(chunk
.width
>= 0);
3544 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3545 log_assert(chunk
.data
.size() == 0);
3549 log_assert(w
== width_
);
3550 log_assert(bits_
.empty());
3554 cover("kernel.rtlil.sigspec.check.unpacked");
3556 log_assert(width_
== GetSize(bits_
));
3557 log_assert(chunks_
.empty());
3562 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3564 cover("kernel.rtlil.sigspec.comp_lt");
3569 if (width_
!= other
.width_
)
3570 return width_
< other
.width_
;
3575 if (chunks_
.size() != other
.chunks_
.size())
3576 return chunks_
.size() < other
.chunks_
.size();
3581 if (hash_
!= other
.hash_
)
3582 return hash_
< other
.hash_
;
3584 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3585 if (chunks_
[i
] != other
.chunks_
[i
]) {
3586 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3587 return chunks_
[i
] < other
.chunks_
[i
];
3590 cover("kernel.rtlil.sigspec.comp_lt.equal");
3594 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3596 cover("kernel.rtlil.sigspec.comp_eq");
3601 if (width_
!= other
.width_
)
3604 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3605 // since the RHS will contain one SigChunk of width 0 causing
3606 // the size check below to fail
3613 if (chunks_
.size() != other
.chunks_
.size())
3619 if (hash_
!= other
.hash_
)
3622 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3623 if (chunks_
[i
] != other
.chunks_
[i
]) {
3624 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3628 cover("kernel.rtlil.sigspec.comp_eq.equal");
3632 bool RTLIL::SigSpec::is_wire() const
3634 cover("kernel.rtlil.sigspec.is_wire");
3637 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3640 bool RTLIL::SigSpec::is_chunk() const
3642 cover("kernel.rtlil.sigspec.is_chunk");
3645 return GetSize(chunks_
) == 1;
3648 bool RTLIL::SigSpec::is_fully_const() const
3650 cover("kernel.rtlil.sigspec.is_fully_const");
3653 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3654 if (it
->width
> 0 && it
->wire
!= NULL
)
3659 bool RTLIL::SigSpec::is_fully_zero() const
3661 cover("kernel.rtlil.sigspec.is_fully_zero");
3664 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3665 if (it
->width
> 0 && it
->wire
!= NULL
)
3667 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3668 if (it
->data
[i
] != RTLIL::State::S0
)
3674 bool RTLIL::SigSpec::is_fully_ones() const
3676 cover("kernel.rtlil.sigspec.is_fully_ones");
3679 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3680 if (it
->width
> 0 && it
->wire
!= NULL
)
3682 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3683 if (it
->data
[i
] != RTLIL::State::S1
)
3689 bool RTLIL::SigSpec::is_fully_def() const
3691 cover("kernel.rtlil.sigspec.is_fully_def");
3694 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3695 if (it
->width
> 0 && it
->wire
!= NULL
)
3697 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3698 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3704 bool RTLIL::SigSpec::is_fully_undef() const
3706 cover("kernel.rtlil.sigspec.is_fully_undef");
3709 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3710 if (it
->width
> 0 && it
->wire
!= NULL
)
3712 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3713 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3719 bool RTLIL::SigSpec::has_const() const
3721 cover("kernel.rtlil.sigspec.has_const");
3724 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3725 if (it
->width
> 0 && it
->wire
== NULL
)
3730 bool RTLIL::SigSpec::has_marked_bits() const
3732 cover("kernel.rtlil.sigspec.has_marked_bits");
3735 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3736 if (it
->width
> 0 && it
->wire
== NULL
) {
3737 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3738 if (it
->data
[i
] == RTLIL::State::Sm
)
3744 bool RTLIL::SigSpec::as_bool() const
3746 cover("kernel.rtlil.sigspec.as_bool");
3749 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3751 return RTLIL::Const(chunks_
[0].data
).as_bool();
3755 int RTLIL::SigSpec::as_int(bool is_signed
) const
3757 cover("kernel.rtlil.sigspec.as_int");
3760 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3762 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3766 std::string
RTLIL::SigSpec::as_string() const
3768 cover("kernel.rtlil.sigspec.as_string");
3772 str
.reserve(size());
3773 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3774 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3775 if (chunk
.wire
!= NULL
)
3776 str
.append(chunk
.width
, '?');
3778 str
+= RTLIL::Const(chunk
.data
).as_string();
3783 RTLIL::Const
RTLIL::SigSpec::as_const() const
3785 cover("kernel.rtlil.sigspec.as_const");
3788 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3790 return chunks_
[0].data
;
3791 return RTLIL::Const();
3794 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3796 cover("kernel.rtlil.sigspec.as_wire");
3799 log_assert(is_wire());
3800 return chunks_
[0].wire
;
3803 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3805 cover("kernel.rtlil.sigspec.as_chunk");
3808 log_assert(is_chunk());
3812 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3814 cover("kernel.rtlil.sigspec.as_bit");
3816 log_assert(width_
== 1);
3818 return RTLIL::SigBit(*chunks_
.begin());
3823 bool RTLIL::SigSpec::match(const char* pattern
) const
3825 cover("kernel.rtlil.sigspec.match");
3828 log_assert(int(strlen(pattern
)) == GetSize(bits_
));
3830 for (auto it
= bits_
.rbegin(); it
!= bits_
.rend(); it
++, pattern
++) {
3831 if (*pattern
== ' ')
3833 if (*pattern
== '*') {
3834 if (*it
!= State::Sz
&& *it
!= State::Sx
)
3838 if (*pattern
== '0') {
3839 if (*it
!= State::S0
)
3842 if (*pattern
== '1') {
3843 if (*it
!= State::S1
)
3852 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3854 cover("kernel.rtlil.sigspec.to_sigbit_set");
3857 std::set
<RTLIL::SigBit
> sigbits
;
3858 for (auto &c
: chunks_
)
3859 for (int i
= 0; i
< c
.width
; i
++)
3860 sigbits
.insert(RTLIL::SigBit(c
, i
));
3864 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3866 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3869 pool
<RTLIL::SigBit
> sigbits
;
3870 sigbits
.reserve(size());
3871 for (auto &c
: chunks_
)
3872 for (int i
= 0; i
< c
.width
; i
++)
3873 sigbits
.insert(RTLIL::SigBit(c
, i
));
3877 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3879 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3885 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3887 cover("kernel.rtlil.sigspec.to_sigbit_map");
3892 log_assert(width_
== other
.width_
);
3894 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3895 for (int i
= 0; i
< width_
; i
++)
3896 new_map
[bits_
[i
]] = other
.bits_
[i
];
3901 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3903 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3908 log_assert(width_
== other
.width_
);
3910 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3911 new_map
.reserve(size());
3912 for (int i
= 0; i
< width_
; i
++)
3913 new_map
[bits_
[i
]] = other
.bits_
[i
];
3918 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3920 size_t start
= 0, end
= 0;
3921 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3922 tokens
.push_back(text
.substr(start
, end
- start
));
3925 tokens
.push_back(text
.substr(start
));
3928 static int sigspec_parse_get_dummy_line_num()
3933 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3935 cover("kernel.rtlil.sigspec.parse");
3937 AST::current_filename
= "input";
3939 std::vector
<std::string
> tokens
;
3940 sigspec_parse_split(tokens
, str
, ',');
3942 sig
= RTLIL::SigSpec();
3943 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3945 std::string netname
= tokens
[tokidx
];
3946 std::string indices
;
3948 if (netname
.size() == 0)
3951 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3952 cover("kernel.rtlil.sigspec.parse.const");
3953 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3954 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3957 sig
.append(RTLIL::Const(ast
->bits
));
3965 cover("kernel.rtlil.sigspec.parse.net");
3967 if (netname
[0] != '$' && netname
[0] != '\\')
3968 netname
= "\\" + netname
;
3970 if (module
->wires_
.count(netname
) == 0) {
3971 size_t indices_pos
= netname
.size()-1;
3972 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3975 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3976 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3978 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3980 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3981 indices
= netname
.substr(indices_pos
);
3982 netname
= netname
.substr(0, indices_pos
);
3987 if (module
->wires_
.count(netname
) == 0)
3990 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3991 if (!indices
.empty()) {
3992 std::vector
<std::string
> index_tokens
;
3993 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3994 if (index_tokens
.size() == 1) {
3995 cover("kernel.rtlil.sigspec.parse.bit_sel");
3996 int a
= atoi(index_tokens
.at(0).c_str());
3997 if (a
< 0 || a
>= wire
->width
)
3999 sig
.append(RTLIL::SigSpec(wire
, a
));
4001 cover("kernel.rtlil.sigspec.parse.part_sel");
4002 int a
= atoi(index_tokens
.at(0).c_str());
4003 int b
= atoi(index_tokens
.at(1).c_str());
4008 if (a
< 0 || a
>= wire
->width
)
4010 if (b
< 0 || b
>= wire
->width
)
4012 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
4021 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
4023 if (str
.empty() || str
[0] != '@')
4024 return parse(sig
, module
, str
);
4026 cover("kernel.rtlil.sigspec.parse.sel");
4028 str
= RTLIL::escape_id(str
.substr(1));
4029 if (design
->selection_vars
.count(str
) == 0)
4032 sig
= RTLIL::SigSpec();
4033 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
4034 for (auto &it
: module
->wires_
)
4035 if (sel
.selected_member(module
->name
, it
.first
))
4036 sig
.append(it
.second
);
4041 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4044 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4045 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
4050 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4051 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4055 if (lhs
.chunks_
.size() == 1) {
4056 char *p
= (char*)str
.c_str(), *endptr
;
4057 long int val
= strtol(p
, &endptr
, 10);
4058 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4059 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4060 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4065 return parse(sig
, module
, str
);
4068 RTLIL::CaseRule::~CaseRule()
4070 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4074 bool RTLIL::CaseRule::empty() const
4076 return actions
.empty() && switches
.empty();
4079 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4081 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4082 new_caserule
->compare
= compare
;
4083 new_caserule
->actions
= actions
;
4084 for (auto &it
: switches
)
4085 new_caserule
->switches
.push_back(it
->clone());
4086 return new_caserule
;
4089 RTLIL::SwitchRule::~SwitchRule()
4091 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4095 bool RTLIL::SwitchRule::empty() const
4097 return cases
.empty();
4100 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4102 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4103 new_switchrule
->signal
= signal
;
4104 new_switchrule
->attributes
= attributes
;
4105 for (auto &it
: cases
)
4106 new_switchrule
->cases
.push_back(it
->clone());
4107 return new_switchrule
;
4111 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4113 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4114 new_syncrule
->type
= type
;
4115 new_syncrule
->signal
= signal
;
4116 new_syncrule
->actions
= actions
;
4117 return new_syncrule
;
4120 RTLIL::Process::~Process()
4122 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4126 RTLIL::Process
*RTLIL::Process::clone() const
4128 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4130 new_proc
->name
= name
;
4131 new_proc
->attributes
= attributes
;
4133 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4134 new_proc
->root_case
= *rc_ptr
;
4135 rc_ptr
->switches
.clear();
4138 for (auto &it
: syncs
)
4139 new_proc
->syncs
.push_back(it
->clone());
4145 RTLIL::Memory::~Memory()
4147 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4149 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4150 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4152 return &all_memorys
;