kernel/rtlil.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/macc.h"
  22 #include "kernel/celltypes.h"
  23 #include "frontends/verilog/verilog_frontend.h"
  24 #include "frontends/verilog/preproc.h"
  25 #include "backends/ilang/ilang_backend.h"
  26
  27 #include <string.h>
  28 #include <algorithm>
  29
  30 YOSYS_NAMESPACE_BEGIN
  31
  32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
  33 std::vector<char*> RTLIL::IdString::global_id_storage_;
  34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
  35 #ifndef YOSYS_NO_IDS_REFCNT
  36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
  37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
  38 #endif
  39 #ifdef YOSYS_USE_STICKY_IDS
  40 int RTLIL::IdString::last_created_idx_[8];
  41 int RTLIL::IdString::last_created_idx_ptr_;
  42 #endif
  43
  44 #define X(_id) IdString RTLIL::ID::_id;
  45 #include "kernel/constids.inc"
  46 #undef X
  47
  48 dict<std::string, std::string> RTLIL::constpad;
  49
  50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
  51         static const pool<IdString> res = {
  52                 ID($sr),
  53                 ID($ff),
  54                 ID($dff),
  55                 ID($dffe),
  56                 ID($dffsr),
  57                 ID($adff),
  58                 ID($dlatch),
  59                 ID($dlatchsr),
  60                 ID($_DFFE_NN_),
  61                 ID($_DFFE_NP_),
  62                 ID($_DFFE_PN_),
  63                 ID($_DFFE_PP_),
  64                 ID($_DFFSR_NNN_),
  65                 ID($_DFFSR_NNP_),
  66                 ID($_DFFSR_NPN_),
  67                 ID($_DFFSR_NPP_),
  68                 ID($_DFFSR_PNN_),
  69                 ID($_DFFSR_PNP_),
  70                 ID($_DFFSR_PPN_),
  71                 ID($_DFFSR_PPP_),
  72                 ID($_DFF_NN0_),
  73                 ID($_DFF_NN1_),
  74                 ID($_DFF_NP0_),
  75                 ID($_DFF_NP1_),
  76                 ID($_DFF_N_),
  77                 ID($_DFF_PN0_),
  78                 ID($_DFF_PN1_),
  79                 ID($_DFF_PP0_),
  80                 ID($_DFF_PP1_),
  81                 ID($_DFF_P_),
  82                 ID($_DLATCHSR_NNN_),
  83                 ID($_DLATCHSR_NNP_),
  84                 ID($_DLATCHSR_NPN_),
  85                 ID($_DLATCHSR_NPP_),
  86                 ID($_DLATCHSR_PNN_),
  87                 ID($_DLATCHSR_PNP_),
  88                 ID($_DLATCHSR_PPN_),
  89                 ID($_DLATCHSR_PPP_),
  90                 ID($_DLATCH_N_),
  91                 ID($_DLATCH_P_),
  92                 ID($_FF_),
  93         };
  94         return res;
  95 }
  96
  97 RTLIL::Const::Const()
  98 {
  99         flags = RTLIL::CONST_FLAG_NONE;
 100 }
 101
 102 RTLIL::Const::Const(std::string str)
 103 {
 104         flags = RTLIL::CONST_FLAG_STRING;
 105         for (int i = str.size()-1; i >= 0; i--) {
 106                 unsigned char ch = str[i];
 107                 for (int j = 0; j < 8; j++) {
 108                         bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
 109                         ch = ch >> 1;
 110                 }
 111         }
 112 }
 113
 114 RTLIL::Const::Const(int val, int width)
 115 {
 116         flags = RTLIL::CONST_FLAG_NONE;
 117         for (int i = 0; i < width; i++) {
 118                 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
 119                 val = val >> 1;
 120         }
 121 }
 122
 123 RTLIL::Const::Const(RTLIL::State bit, int width)
 124 {
 125         flags = RTLIL::CONST_FLAG_NONE;
 126         for (int i = 0; i < width; i++)
 127                 bits.push_back(bit);
 128 }
 129
 130 RTLIL::Const::Const(const std::vector<bool> &bits)
 131 {
 132         flags = RTLIL::CONST_FLAG_NONE;
 133         for (const auto &b : bits)
 134                 this->bits.emplace_back(b ? State::S1 : State::S0);
 135 }
 136
 137 RTLIL::Const::Const(const RTLIL::Const &c)
 138 {
 139         flags = c.flags;
 140         for (const auto &b : c.bits)
 141                 this->bits.push_back(b);
 142 }
 143
 144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
 145 {
 146         if (bits.size() != other.bits.size())
 147                 return bits.size() < other.bits.size();
 148         for (size_t i = 0; i < bits.size(); i++)
 149                 if (bits[i] != other.bits[i])
 150                         return bits[i] < other.bits[i];
 151         return false;
 152 }
 153
 154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
 155 {
 156         return bits == other.bits;
 157 }
 158
 159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
 160 {
 161         return bits != other.bits;
 162 }
 163
 164 bool RTLIL::Const::as_bool() const
 165 {
 166         for (size_t i = 0; i < bits.size(); i++)
 167                 if (bits[i] == State::S1)
 168                         return true;
 169         return false;
 170 }
 171
 172 int RTLIL::Const::as_int(bool is_signed) const
 173 {
 174         int32_t ret = 0;
 175         for (size_t i = 0; i < bits.size() && i < 32; i++)
 176                 if (bits[i] == State::S1)
 177                         ret |= 1 << i;
 178         if (is_signed && bits.back() == State::S1)
 179                 for (size_t i = bits.size(); i < 32; i++)
 180                         ret |= 1 << i;
 181         return ret;
 182 }
 183
 184 std::string RTLIL::Const::as_string() const
 185 {
 186         std::string ret;
 187         ret.reserve(bits.size());
 188         for (size_t i = bits.size(); i > 0; i--)
 189                 switch (bits[i-1]) {
 190                         case S0: ret += "0"; break;
 191                         case S1: ret += "1"; break;
 192                         case Sx: ret += "x"; break;
 193                         case Sz: ret += "z"; break;
 194                         case Sa: ret += "-"; break;
 195                         case Sm: ret += "m"; break;
 196                 }
 197         return ret;
 198 }
 199
 200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
 201 {
 202         Const c;
 203         c.bits.reserve(str.size());
 204         for (auto it = str.rbegin(); it != str.rend(); it++)
 205                 switch (*it) {
 206                         case '0': c.bits.push_back(State::S0); break;
 207                         case '1': c.bits.push_back(State::S1); break;
 208                         case 'x': c.bits.push_back(State::Sx); break;
 209                         case 'z': c.bits.push_back(State::Sz); break;
 210                         case 'm': c.bits.push_back(State::Sm); break;
 211                         default: c.bits.push_back(State::Sa);
 212                 }
 213         return c;
 214 }
 215
 216 std::string RTLIL::Const::decode_string() const
 217 {
 218         std::string string;
 219         string.reserve(GetSize(bits)/8);
 220         for (int i = 0; i < GetSize(bits); i += 8) {
 221                 char ch = 0;
 222                 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
 223                         if (bits[i + j] == RTLIL::State::S1)
 224                                 ch |= 1 << j;
 225                 if (ch != 0)
 226                         string.append({ch});
 227         }
 228         std::reverse(string.begin(), string.end());
 229         return string;
 230 }
 231
 232 bool RTLIL::Const::is_fully_zero() const
 233 {
 234         cover("kernel.rtlil.const.is_fully_zero");
 235
 236         for (const auto &bit : bits)
 237                 if (bit != RTLIL::State::S0)
 238                         return false;
 239
 240         return true;
 241 }
 242
 243 bool RTLIL::Const::is_fully_ones() const
 244 {
 245         cover("kernel.rtlil.const.is_fully_ones");
 246
 247         for (const auto &bit : bits)
 248                 if (bit != RTLIL::State::S1)
 249                         return false;
 250
 251         return true;
 252 }
 253
 254 bool RTLIL::Const::is_fully_def() const
 255 {
 256         cover("kernel.rtlil.const.is_fully_def");
 257
 258         for (const auto &bit : bits)
 259                 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
 260                         return false;
 261
 262         return true;
 263 }
 264
 265 bool RTLIL::Const::is_fully_undef() const
 266 {
 267         cover("kernel.rtlil.const.is_fully_undef");
 268
 269         for (const auto &bit : bits)
 270                 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
 271                         return false;
 272
 273         return true;
 274 }
 275
 276 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
 277 {
 278         return attributes.count(id);
 279 }
 280
 281 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
 282 {
 283         if (value)
 284                 attributes[id] = RTLIL::Const(1);
 285         else
 286                 attributes.erase(id);
 287 }
 288
 289 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
 290 {
 291         const auto it = attributes.find(id);
 292         if (it == attributes.end())
 293                 return false;
 294         return it->second.as_bool();
 295 }
 296
 297 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
 298 {
 299         if (value.empty())
 300                 attributes.erase(id);
 301         else
 302                 attributes[id] = value;
 303 }
 304
 305 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
 306 {
 307         std::string value;
 308         const auto it = attributes.find(id);
 309         if (it != attributes.end())
 310                 value = it->second.decode_string();
 311         return value;
 312 }
 313
 314 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
 315 {
 316         string attrval;
 317         for (const auto &s : data) {
 318                 if (!attrval.empty())
 319                         attrval += "|";
 320                 attrval += s;
 321         }
 322         attributes[id] = RTLIL::Const(attrval);
 323 }
 324
 325 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
 326 {
 327         pool<string> union_data = get_strpool_attribute(id);
 328         union_data.insert(data.begin(), data.end());
 329         if (!union_data.empty())
 330                 set_strpool_attribute(id, union_data);
 331 }
 332
 333 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
 334 {
 335         pool<string> data;
 336         if (attributes.count(id) != 0)
 337                 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
 338                         data.insert(s);
 339         return data;
 340 }
 341
 342 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
 343 {
 344         if (full_selection)
 345                 return true;
 346         if (selected_modules.count(mod_name) > 0)
 347                 return true;
 348         if (selected_members.count(mod_name) > 0)
 349                 return true;
 350         return false;
 351 }
 352
 353 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
 354 {
 355         if (full_selection)
 356                 return true;
 357         if (selected_modules.count(mod_name) > 0)
 358                 return true;
 359         return false;
 360 }
 361
 362 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 363 {
 364         if (full_selection)
 365                 return true;
 366         if (selected_modules.count(mod_name) > 0)
 367                 return true;
 368         if (selected_members.count(mod_name) > 0)
 369                 if (selected_members.at(mod_name).count(memb_name) > 0)
 370                         return true;
 371         return false;
 372 }
 373
 374 void RTLIL::Selection::optimize(RTLIL::Design *design)
 375 {
 376         if (full_selection) {
 377                 selected_modules.clear();
 378                 selected_members.clear();
 379                 return;
 380         }
 381
 382         std::vector<RTLIL::IdString> del_list, add_list;
 383
 384         del_list.clear();
 385         for (auto mod_name : selected_modules) {
 386                 if (design->modules_.count(mod_name) == 0)
 387                         del_list.push_back(mod_name);
 388                 selected_members.erase(mod_name);
 389         }
 390         for (auto mod_name : del_list)
 391                 selected_modules.erase(mod_name);
 392
 393         del_list.clear();
 394         for (auto &it : selected_members)
 395                 if (design->modules_.count(it.first) == 0)
 396                         del_list.push_back(it.first);
 397         for (auto mod_name : del_list)
 398                 selected_members.erase(mod_name);
 399
 400         for (auto &it : selected_members) {
 401                 del_list.clear();
 402                 for (auto memb_name : it.second)
 403                         if (design->modules_[it.first]->count_id(memb_name) == 0)
 404                                 del_list.push_back(memb_name);
 405                 for (auto memb_name : del_list)
 406                         it.second.erase(memb_name);
 407         }
 408
 409         del_list.clear();
 410         add_list.clear();
 411         for (auto &it : selected_members)
 412                 if (it.second.size() == 0)
 413                         del_list.push_back(it.first);
 414                 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
 415                                 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
 416                         add_list.push_back(it.first);
 417         for (auto mod_name : del_list)
 418                 selected_members.erase(mod_name);
 419         for (auto mod_name : add_list) {
 420                 selected_members.erase(mod_name);
 421                 selected_modules.insert(mod_name);
 422         }
 423
 424         if (selected_modules.size() == design->modules_.size()) {
 425                 full_selection = true;
 426                 selected_modules.clear();
 427                 selected_members.clear();
 428         }
 429 }
 430
 431 RTLIL::Design::Design()
 432   : verilog_defines (new define_map_t)
 433 {
 434         static unsigned int hashidx_count = 123456789;
 435         hashidx_count = mkhash_xorshift(hashidx_count);
 436         hashidx_ = hashidx_count;
 437
 438         refcount_modules_ = 0;
 439         selection_stack.push_back(RTLIL::Selection());
 440
 441 #ifdef WITH_PYTHON
 442         RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
 443 #endif
 444 }
 445
 446 RTLIL::Design::~Design()
 447 {
 448         for (auto it = modules_.begin(); it != modules_.end(); ++it)
 449                 delete it->second;
 450         for (auto n : verilog_packages)
 451                 delete n;
 452         for (auto n : verilog_globals)
 453                 delete n;
 454 #ifdef WITH_PYTHON
 455         RTLIL::Design::get_all_designs()->erase(hashidx_);
 456 #endif
 457 }
 458
 459 #ifdef WITH_PYTHON
 460 static std::map<unsigned int, RTLIL::Design*> all_designs;
 461 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
 462 {
 463         return &all_designs;
 464 }
 465 #endif
 466
 467 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
 468 {
 469         return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
 470 }
 471
 472 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
 473 {
 474         return modules_.count(name) ? modules_.at(name) : NULL;
 475 }
 476
 477 RTLIL::Module *RTLIL::Design::top_module()
 478 {
 479         RTLIL::Module *module = nullptr;
 480         int module_count = 0;
 481
 482         for (auto mod : selected_modules()) {
 483                 if (mod->get_bool_attribute(ID::top))
 484                         return mod;
 485                 module_count++;
 486                 module = mod;
 487         }
 488
 489         return module_count == 1 ? module : nullptr;
 490 }
 491
 492 void RTLIL::Design::add(RTLIL::Module *module)
 493 {
 494         log_assert(modules_.count(module->name) == 0);
 495         log_assert(refcount_modules_ == 0);
 496         modules_[module->name] = module;
 497         module->design = this;
 498
 499         for (auto mon : monitors)
 500                 mon->notify_module_add(module);
 501
 502         if (yosys_xtrace) {
 503                 log("#X# New Module: %s\n", log_id(module));
 504                 log_backtrace("-X- ", yosys_xtrace-1);
 505         }
 506 }
 507
 508 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
 509 {
 510         log_assert(modules_.count(name) == 0);
 511         log_assert(refcount_modules_ == 0);
 512
 513         RTLIL::Module *module = new RTLIL::Module;
 514         modules_[name] = module;
 515         module->design = this;
 516         module->name = name;
 517
 518         for (auto mon : monitors)
 519                 mon->notify_module_add(module);
 520
 521         if (yosys_xtrace) {
 522                 log("#X# New Module: %s\n", log_id(module));
 523                 log_backtrace("-X- ", yosys_xtrace-1);
 524         }
 525
 526         return module;
 527 }
 528
 529 void RTLIL::Design::scratchpad_unset(const std::string &varname)
 530 {
 531         scratchpad.erase(varname);
 532 }
 533
 534 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
 535 {
 536         scratchpad[varname] = stringf("%d", value);
 537 }
 538
 539 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
 540 {
 541         scratchpad[varname] = value ? "true" : "false";
 542 }
 543
 544 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
 545 {
 546         scratchpad[varname] = std::move(value);
 547 }
 548
 549 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
 550 {
 551         auto it = scratchpad.find(varname);
 552         if (it == scratchpad.end())
 553                 return default_value;
 554
 555         const std::string &str = it->second;
 556
 557         if (str == "0" || str == "false")
 558                 return 0;
 559
 560         if (str == "1" || str == "true")
 561                 return 1;
 562
 563         char *endptr = nullptr;
 564         long int parsed_value = strtol(str.c_str(), &endptr, 10);
 565         return *endptr ? default_value : parsed_value;
 566 }
 567
 568 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
 569 {
 570         auto it = scratchpad.find(varname);
 571         if (it == scratchpad.end())
 572                 return default_value;
 573
 574         const std::string &str = it->second;
 575
 576         if (str == "0" || str == "false")
 577                 return false;
 578
 579         if (str == "1" || str == "true")
 580                 return true;
 581
 582         return default_value;
 583 }
 584
 585 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
 586 {
 587         auto it = scratchpad.find(varname);
 588         if (it == scratchpad.end())
 589                 return default_value;
 590
 591         return it->second;
 592 }
 593
 594 void RTLIL::Design::remove(RTLIL::Module *module)
 595 {
 596         for (auto mon : monitors)
 597                 mon->notify_module_del(module);
 598
 599         if (yosys_xtrace) {
 600                 log("#X# Remove Module: %s\n", log_id(module));
 601                 log_backtrace("-X- ", yosys_xtrace-1);
 602         }
 603
 604         log_assert(modules_.at(module->name) == module);
 605         log_assert(refcount_modules_ == 0);
 606         modules_.erase(module->name);
 607         delete module;
 608 }
 609
 610 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
 611 {
 612         modules_.erase(module->name);
 613         module->name = new_name;
 614         add(module);
 615 }
 616
 617 void RTLIL::Design::sort()
 618 {
 619         scratchpad.sort();
 620         modules_.sort(sort_by_id_str());
 621         for (auto &it : modules_)
 622                 it.second->sort();
 623 }
 624
 625 void RTLIL::Design::check()
 626 {
 627 #ifndef NDEBUG
 628         for (auto &it : modules_) {
 629                 log_assert(this == it.second->design);
 630                 log_assert(it.first == it.second->name);
 631                 log_assert(!it.first.empty());
 632                 it.second->check();
 633         }
 634 #endif
 635 }
 636
 637 void RTLIL::Design::optimize()
 638 {
 639         for (auto &it : modules_)
 640                 it.second->optimize();
 641         for (auto &it : selection_stack)
 642                 it.optimize(this);
 643         for (auto &it : selection_vars)
 644                 it.second.optimize(this);
 645 }
 646
 647 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
 648 {
 649         if (!selected_active_module.empty() && mod_name != selected_active_module)
 650                 return false;
 651         if (selection_stack.size() == 0)
 652                 return true;
 653         return selection_stack.back().selected_module(mod_name);
 654 }
 655
 656 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
 657 {
 658         if (!selected_active_module.empty() && mod_name != selected_active_module)
 659                 return false;
 660         if (selection_stack.size() == 0)
 661                 return true;
 662         return selection_stack.back().selected_whole_module(mod_name);
 663 }
 664
 665 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 666 {
 667         if (!selected_active_module.empty() && mod_name != selected_active_module)
 668                 return false;
 669         if (selection_stack.size() == 0)
 670                 return true;
 671         return selection_stack.back().selected_member(mod_name, memb_name);
 672 }
 673
 674 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
 675 {
 676         return selected_module(mod->name);
 677 }
 678
 679 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
 680 {
 681         return selected_whole_module(mod->name);
 682 }
 683
 684 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
 685 {
 686         std::vector<RTLIL::Module*> result;
 687         result.reserve(modules_.size());
 688         for (auto &it : modules_)
 689                 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
 690                         result.push_back(it.second);
 691         return result;
 692 }
 693
 694 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
 695 {
 696         std::vector<RTLIL::Module*> result;
 697         result.reserve(modules_.size());
 698         for (auto &it : modules_)
 699                 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
 700                         result.push_back(it.second);
 701         return result;
 702 }
 703
 704 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
 705 {
 706         std::vector<RTLIL::Module*> result;
 707         result.reserve(modules_.size());
 708         for (auto &it : modules_)
 709                 if (it.second->get_blackbox_attribute())
 710                         continue;
 711                 else if (selected_whole_module(it.first))
 712                         result.push_back(it.second);
 713                 else if (selected_module(it.first))
 714                         log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
 715         return result;
 716 }
 717
 718 RTLIL::Module::Module()
 719 {
 720         static unsigned int hashidx_count = 123456789;
 721         hashidx_count = mkhash_xorshift(hashidx_count);
 722         hashidx_ = hashidx_count;
 723
 724         design = nullptr;
 725         refcount_wires_ = 0;
 726         refcount_cells_ = 0;
 727
 728 #ifdef WITH_PYTHON
 729         RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
 730 #endif
 731 }
 732
 733 RTLIL::Module::~Module()
 734 {
 735         for (auto it = wires_.begin(); it != wires_.end(); ++it)
 736                 delete it->second;
 737         for (auto it = memories.begin(); it != memories.end(); ++it)
 738                 delete it->second;
 739         for (auto it = cells_.begin(); it != cells_.end(); ++it)
 740                 delete it->second;
 741         for (auto it = processes.begin(); it != processes.end(); ++it)
 742                 delete it->second;
 743 #ifdef WITH_PYTHON
 744         RTLIL::Module::get_all_modules()->erase(hashidx_);
 745 #endif
 746 }
 747
 748 #ifdef WITH_PYTHON
 749 static std::map<unsigned int, RTLIL::Module*> all_modules;
 750 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
 751 {
 752         return &all_modules;
 753 }
 754 #endif
 755
 756 void RTLIL::Module::makeblackbox()
 757 {
 758         pool<RTLIL::Wire*> delwires;
 759
 760         for (auto it = wires_.begin(); it != wires_.end(); ++it)
 761                 if (!it->second->port_input && !it->second->port_output)
 762                         delwires.insert(it->second);
 763
 764         for (auto it = memories.begin(); it != memories.end(); ++it)
 765                 delete it->second;
 766         memories.clear();
 767
 768         for (auto it = cells_.begin(); it != cells_.end(); ++it)
 769                 delete it->second;
 770         cells_.clear();
 771
 772         for (auto it = processes.begin(); it != processes.end(); ++it)
 773                 delete it->second;
 774         processes.clear();
 775
 776         connections_.clear();
 777
 778         remove(delwires);
 779         set_bool_attribute(ID::blackbox);
 780 }
 781
 782 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
 783 {
 784         log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
 785 }
 786
 787 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
 788 {
 789         if (mayfail)
 790                 return RTLIL::IdString();
 791         log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 792 }
 793
 794
 795 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
 796 {
 797         if (mayfail)
 798                 return RTLIL::IdString();
 799         log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 800 }
 801
 802 size_t RTLIL::Module::count_id(RTLIL::IdString id)
 803 {
 804         return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
 805 }
 806
 807 #ifndef NDEBUG
 808 namespace {
 809         struct InternalCellChecker
 810         {
 811                 RTLIL::Module *module;
 812                 RTLIL::Cell *cell;
 813                 pool<RTLIL::IdString> expected_params, expected_ports;
 814
 815                 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
 816
 817                 void error(int linenr)
 818                 {
 819                         std::stringstream buf;
 820                         ILANG_BACKEND::dump_cell(buf, "  ", cell);
 821
 822                         log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
 823                                         module ? module->name.c_str() : "", module ? "." : "",
 824                                         cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
 825                 }
 826
 827                 int param(RTLIL::IdString name)
 828                 {
 829                         auto it = cell->parameters.find(name);
 830                         if (it == cell->parameters.end())
 831                                 error(__LINE__);
 832                         expected_params.insert(name);
 833                         return it->second.as_int();
 834                 }
 835
 836                 int param_bool(RTLIL::IdString name)
 837                 {
 838                         int v = param(name);
 839                         if (GetSize(cell->parameters.at(name)) > 32)
 840                                 error(__LINE__);
 841                         if (v != 0 && v != 1)
 842                                 error(__LINE__);
 843                         return v;
 844                 }
 845
 846                 int param_bool(RTLIL::IdString name, bool expected)
 847                 {
 848                         int v = param_bool(name);
 849                         if (v != expected)
 850                                 error(__LINE__);
 851                         return v;
 852                 }
 853
 854                 void param_bits(RTLIL::IdString name, int width)
 855                 {
 856                         param(name);
 857                         if (GetSize(cell->parameters.at(name).bits) != width)
 858                                 error(__LINE__);
 859                 }
 860
 861                 void port(RTLIL::IdString name, int width)
 862                 {
 863                         auto it = cell->connections_.find(name);
 864                         if (it == cell->connections_.end())
 865                                 error(__LINE__);
 866                         if (GetSize(it->second) != width)
 867                                 error(__LINE__);
 868                         expected_ports.insert(name);
 869                 }
 870
 871                 void check_expected(bool check_matched_sign = false)
 872                 {
 873                         for (auto &para : cell->parameters)
 874                                 if (expected_params.count(para.first) == 0)
 875                                         error(__LINE__);
 876                         for (auto &conn : cell->connections())
 877                                 if (expected_ports.count(conn.first) == 0)
 878                                         error(__LINE__);
 879
 880                         if (check_matched_sign) {
 881                                 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
 882                                 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
 883                                 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
 884                                 if (a_is_signed != b_is_signed)
 885                                         error(__LINE__);
 886                         }
 887                 }
 888
 889                 void check()
 890                 {
 891                         if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
 892                                         cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
 893                                 return;
 894
 895                         if (cell->type.in(ID($not), ID($pos), ID($neg))) {
 896                                 param_bool(ID::A_SIGNED);
 897                                 port(ID::A, param(ID::A_WIDTH));
 898                                 port(ID::Y, param(ID::Y_WIDTH));
 899                                 check_expected();
 900                                 return;
 901                         }
 902
 903                         if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
 904                                 param_bool(ID::A_SIGNED);
 905                                 param_bool(ID::B_SIGNED);
 906                                 port(ID::A, param(ID::A_WIDTH));
 907                                 port(ID::B, param(ID::B_WIDTH));
 908                                 port(ID::Y, param(ID::Y_WIDTH));
 909                                 check_expected(true);
 910                                 return;
 911                         }
 912
 913                         if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
 914                                 param_bool(ID::A_SIGNED);
 915                                 port(ID::A, param(ID::A_WIDTH));
 916                                 port(ID::Y, param(ID::Y_WIDTH));
 917                                 check_expected();
 918                                 return;
 919                         }
 920
 921                         if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
 922                                 param_bool(ID::A_SIGNED);
 923                                 param_bool(ID::B_SIGNED, /*expected=*/false);
 924                                 port(ID::A, param(ID::A_WIDTH));
 925                                 port(ID::B, param(ID::B_WIDTH));
 926                                 port(ID::Y, param(ID::Y_WIDTH));
 927                                 check_expected(/*check_matched_sign=*/false);
 928                                 return;
 929                         }
 930
 931                         if (cell->type.in(ID($shift), ID($shiftx))) {
 932                                 param_bool(ID::A_SIGNED);
 933                                 param_bool(ID::B_SIGNED);
 934                                 port(ID::A, param(ID::A_WIDTH));
 935                                 port(ID::B, param(ID::B_WIDTH));
 936                                 port(ID::Y, param(ID::Y_WIDTH));
 937                                 check_expected(/*check_matched_sign=*/false);
 938                                 return;
 939                         }
 940
 941                         if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
 942                                 param_bool(ID::A_SIGNED);
 943                                 param_bool(ID::B_SIGNED);
 944                                 port(ID::A, param(ID::A_WIDTH));
 945                                 port(ID::B, param(ID::B_WIDTH));
 946                                 port(ID::Y, param(ID::Y_WIDTH));
 947                                 check_expected(true);
 948                                 return;
 949                         }
 950
 951                         if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
 952                                 param_bool(ID::A_SIGNED);
 953                                 param_bool(ID::B_SIGNED);
 954                                 port(ID::A, param(ID::A_WIDTH));
 955                                 port(ID::B, param(ID::B_WIDTH));
 956                                 port(ID::Y, param(ID::Y_WIDTH));
 957                                 check_expected(cell->type != ID($pow));
 958                                 return;
 959                         }
 960
 961                         if (cell->type == ID($fa)) {
 962                                 port(ID::A, param(ID::WIDTH));
 963                                 port(ID::B, param(ID::WIDTH));
 964                                 port(ID::C, param(ID::WIDTH));
 965                                 port(ID::X, param(ID::WIDTH));
 966                                 port(ID::Y, param(ID::WIDTH));
 967                                 check_expected();
 968                                 return;
 969                         }
 970
 971                         if (cell->type == ID($lcu)) {
 972                                 port(ID::P, param(ID::WIDTH));
 973                                 port(ID::G, param(ID::WIDTH));
 974                                 port(ID::CI, 1);
 975                                 port(ID::CO, param(ID::WIDTH));
 976                                 check_expected();
 977                                 return;
 978                         }
 979
 980                         if (cell->type == ID($alu)) {
 981                                 param_bool(ID::A_SIGNED);
 982                                 param_bool(ID::B_SIGNED);
 983                                 port(ID::A, param(ID::A_WIDTH));
 984                                 port(ID::B, param(ID::B_WIDTH));
 985                                 port(ID::CI, 1);
 986                                 port(ID::BI, 1);
 987                                 port(ID::X, param(ID::Y_WIDTH));
 988                                 port(ID::Y, param(ID::Y_WIDTH));
 989                                 port(ID::CO, param(ID::Y_WIDTH));
 990                                 check_expected(true);
 991                                 return;
 992                         }
 993
 994                         if (cell->type == ID($macc)) {
 995                                 param(ID::CONFIG);
 996                                 param(ID::CONFIG_WIDTH);
 997                                 port(ID::A, param(ID::A_WIDTH));
 998                                 port(ID::B, param(ID::B_WIDTH));
 999                                 port(ID::Y, param(ID::Y_WIDTH));
1000                                 check_expected();
1001                                 Macc().from_cell(cell);
1002                                 return;
1003                         }
1004
1005                         if (cell->type == ID($logic_not)) {
1006                                 param_bool(ID::A_SIGNED);
1007                                 port(ID::A, param(ID::A_WIDTH));
1008                                 port(ID::Y, param(ID::Y_WIDTH));
1009                                 check_expected();
1010                                 return;
1011                         }
1012
1013                         if (cell->type.in(ID($logic_and), ID($logic_or))) {
1014                                 param_bool(ID::A_SIGNED);
1015                                 param_bool(ID::B_SIGNED);
1016                                 port(ID::A, param(ID::A_WIDTH));
1017                                 port(ID::B, param(ID::B_WIDTH));
1018                                 port(ID::Y, param(ID::Y_WIDTH));
1019                                 check_expected(/*check_matched_sign=*/false);
1020                                 return;
1021                         }
1022
1023                         if (cell->type == ID($slice)) {
1024                                 param(ID::OFFSET);
1025                                 port(ID::A, param(ID::A_WIDTH));
1026                                 port(ID::Y, param(ID::Y_WIDTH));
1027                                 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1028                                         error(__LINE__);
1029                                 check_expected();
1030                                 return;
1031                         }
1032
1033                         if (cell->type == ID($concat)) {
1034                                 port(ID::A, param(ID::A_WIDTH));
1035                                 port(ID::B, param(ID::B_WIDTH));
1036                                 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1037                                 check_expected();
1038                                 return;
1039                         }
1040
1041                         if (cell->type == ID($mux)) {
1042                                 port(ID::A, param(ID::WIDTH));
1043                                 port(ID::B, param(ID::WIDTH));
1044                                 port(ID::S, 1);
1045                                 port(ID::Y, param(ID::WIDTH));
1046                                 check_expected();
1047                                 return;
1048                         }
1049
1050                         if (cell->type == ID($pmux)) {
1051                                 port(ID::A, param(ID::WIDTH));
1052                                 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1053                                 port(ID::S, param(ID::S_WIDTH));
1054                                 port(ID::Y, param(ID::WIDTH));
1055                                 check_expected();
1056                                 return;
1057                         }
1058
1059                         if (cell->type == ID($lut)) {
1060                                 param(ID::LUT);
1061                                 port(ID::A, param(ID::WIDTH));
1062                                 port(ID::Y, 1);
1063                                 check_expected();
1064                                 return;
1065                         }
1066
1067                         if (cell->type == ID($sop)) {
1068                                 param(ID::DEPTH);
1069                                 param(ID::TABLE);
1070                                 port(ID::A, param(ID::WIDTH));
1071                                 port(ID::Y, 1);
1072                                 check_expected();
1073                                 return;
1074                         }
1075
1076                         if (cell->type == ID($sr)) {
1077                                 param_bool(ID::SET_POLARITY);
1078                                 param_bool(ID::CLR_POLARITY);
1079                                 port(ID::SET, param(ID::WIDTH));
1080                                 port(ID::CLR, param(ID::WIDTH));
1081                                 port(ID::Q,   param(ID::WIDTH));
1082                                 check_expected();
1083                                 return;
1084                         }
1085
1086                         if (cell->type == ID($ff)) {
1087                                 port(ID::D, param(ID::WIDTH));
1088                                 port(ID::Q, param(ID::WIDTH));
1089                                 check_expected();
1090                                 return;
1091                         }
1092
1093                         if (cell->type == ID($dff)) {
1094                                 param_bool(ID::CLK_POLARITY);
1095                                 port(ID::CLK, 1);
1096                                 port(ID::D, param(ID::WIDTH));
1097                                 port(ID::Q, param(ID::WIDTH));
1098                                 check_expected();
1099                                 return;
1100                         }
1101
1102                         if (cell->type == ID($dffe)) {
1103                                 param_bool(ID::CLK_POLARITY);
1104                                 param_bool(ID::EN_POLARITY);
1105                                 port(ID::CLK, 1);
1106                                 port(ID::EN, 1);
1107                                 port(ID::D, param(ID::WIDTH));
1108                                 port(ID::Q, param(ID::WIDTH));
1109                                 check_expected();
1110                                 return;
1111                         }
1112
1113                         if (cell->type == ID($dffsr)) {
1114                                 param_bool(ID::CLK_POLARITY);
1115                                 param_bool(ID::SET_POLARITY);
1116                                 param_bool(ID::CLR_POLARITY);
1117                                 port(ID::CLK, 1);
1118                                 port(ID::SET, param(ID::WIDTH));
1119                                 port(ID::CLR, param(ID::WIDTH));
1120                                 port(ID::D, param(ID::WIDTH));
1121                                 port(ID::Q, param(ID::WIDTH));
1122                                 check_expected();
1123                                 return;
1124                         }
1125
1126                         if (cell->type == ID($adff)) {
1127                                 param_bool(ID::CLK_POLARITY);
1128                                 param_bool(ID::ARST_POLARITY);
1129                                 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1130                                 port(ID::CLK, 1);
1131                                 port(ID::ARST, 1);
1132                                 port(ID::D, param(ID::WIDTH));
1133                                 port(ID::Q, param(ID::WIDTH));
1134                                 check_expected();
1135                                 return;
1136                         }
1137
1138                         if (cell->type == ID($dlatch)) {
1139                                 param_bool(ID::EN_POLARITY);
1140                                 port(ID::EN, 1);
1141                                 port(ID::D, param(ID::WIDTH));
1142                                 port(ID::Q, param(ID::WIDTH));
1143                                 check_expected();
1144                                 return;
1145                         }
1146
1147                         if (cell->type == ID($dlatchsr)) {
1148                                 param_bool(ID::EN_POLARITY);
1149                                 param_bool(ID::SET_POLARITY);
1150                                 param_bool(ID::CLR_POLARITY);
1151                                 port(ID::EN, 1);
1152                                 port(ID::SET, param(ID::WIDTH));
1153                                 port(ID::CLR, param(ID::WIDTH));
1154                                 port(ID::D, param(ID::WIDTH));
1155                                 port(ID::Q, param(ID::WIDTH));
1156                                 check_expected();
1157                                 return;
1158                         }
1159
1160                         if (cell->type == ID($fsm)) {
1161                                 param(ID::NAME);
1162                                 param_bool(ID::CLK_POLARITY);
1163                                 param_bool(ID::ARST_POLARITY);
1164                                 param(ID::STATE_BITS);
1165                                 param(ID::STATE_NUM);
1166                                 param(ID::STATE_NUM_LOG2);
1167                                 param(ID::STATE_RST);
1168                                 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1169                                 param(ID::TRANS_NUM);
1170                                 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1171                                 port(ID::CLK, 1);
1172                                 port(ID::ARST, 1);
1173                                 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1174                                 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1175                                 check_expected();
1176                                 return;
1177                         }
1178
1179                         if (cell->type == ID($memrd)) {
1180                                 param(ID::MEMID);
1181                                 param_bool(ID::CLK_ENABLE);
1182                                 param_bool(ID::CLK_POLARITY);
1183                                 param_bool(ID::TRANSPARENT);
1184                                 port(ID::CLK, 1);
1185                                 port(ID::EN, 1);
1186                                 port(ID::ADDR, param(ID::ABITS));
1187                                 port(ID::DATA, param(ID::WIDTH));
1188                                 check_expected();
1189                                 return;
1190                         }
1191
1192                         if (cell->type == ID($memwr)) {
1193                                 param(ID::MEMID);
1194                                 param_bool(ID::CLK_ENABLE);
1195                                 param_bool(ID::CLK_POLARITY);
1196                                 param(ID::PRIORITY);
1197                                 port(ID::CLK, 1);
1198                                 port(ID::EN, param(ID::WIDTH));
1199                                 port(ID::ADDR, param(ID::ABITS));
1200                                 port(ID::DATA, param(ID::WIDTH));
1201                                 check_expected();
1202                                 return;
1203                         }
1204
1205                         if (cell->type == ID($meminit)) {
1206                                 param(ID::MEMID);
1207                                 param(ID::PRIORITY);
1208                                 port(ID::ADDR, param(ID::ABITS));
1209                                 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1210                                 check_expected();
1211                                 return;
1212                         }
1213
1214                         if (cell->type == ID($mem)) {
1215                                 param(ID::MEMID);
1216                                 param(ID::SIZE);
1217                                 param(ID::OFFSET);
1218                                 param(ID::INIT);
1219                                 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1220                                 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1221                                 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1222                                 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1223                                 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1224                                 port(ID::RD_CLK, param(ID::RD_PORTS));
1225                                 port(ID::RD_EN, param(ID::RD_PORTS));
1226                                 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1227                                 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1228                                 port(ID::WR_CLK, param(ID::WR_PORTS));
1229                                 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1230                                 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1231                                 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1232                                 check_expected();
1233                                 return;
1234                         }
1235
1236                         if (cell->type == ID($tribuf)) {
1237                                 port(ID::A, param(ID::WIDTH));
1238                                 port(ID::Y, param(ID::WIDTH));
1239                                 port(ID::EN, 1);
1240                                 check_expected();
1241                                 return;
1242                         }
1243
1244                         if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1245                                 port(ID::A, 1);
1246                                 port(ID::EN, 1);
1247                                 check_expected();
1248                                 return;
1249                         }
1250
1251                         if (cell->type == ID($initstate)) {
1252                                 port(ID::Y, 1);
1253                                 check_expected();
1254                                 return;
1255                         }
1256
1257                         if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1258                                 port(ID::Y, param(ID::WIDTH));
1259                                 check_expected();
1260                                 return;
1261                         }
1262
1263                         if (cell->type == ID($equiv)) {
1264                                 port(ID::A, 1);
1265                                 port(ID::B, 1);
1266                                 port(ID::Y, 1);
1267                                 check_expected();
1268                                 return;
1269                         }
1270
1271                         if (cell->type.in(ID($specify2), ID($specify3))) {
1272                                 param_bool(ID::FULL);
1273                                 param_bool(ID::SRC_DST_PEN);
1274                                 param_bool(ID::SRC_DST_POL);
1275                                 param(ID::T_RISE_MIN);
1276                                 param(ID::T_RISE_TYP);
1277                                 param(ID::T_RISE_MAX);
1278                                 param(ID::T_FALL_MIN);
1279                                 param(ID::T_FALL_TYP);
1280                                 param(ID::T_FALL_MAX);
1281                                 port(ID::EN, 1);
1282                                 port(ID::SRC, param(ID::SRC_WIDTH));
1283                                 port(ID::DST, param(ID::DST_WIDTH));
1284                                 if (cell->type == ID($specify3)) {
1285                                         param_bool(ID::EDGE_EN);
1286                                         param_bool(ID::EDGE_POL);
1287                                         param_bool(ID::DAT_DST_PEN);
1288                                         param_bool(ID::DAT_DST_POL);
1289                                         port(ID::DAT, param(ID::DST_WIDTH));
1290                                 }
1291                                 check_expected();
1292                                 return;
1293                         }
1294
1295                         if (cell->type == ID($specrule)) {
1296                                 param(ID::TYPE);
1297                                 param_bool(ID::SRC_PEN);
1298                                 param_bool(ID::SRC_POL);
1299                                 param_bool(ID::DST_PEN);
1300                                 param_bool(ID::DST_POL);
1301                                 param(ID::T_LIMIT_MIN);
1302                                 param(ID::T_LIMIT_TYP);
1303                                 param(ID::T_LIMIT_MAX);
1304                                 param(ID::T_LIMIT2_MIN);
1305                                 param(ID::T_LIMIT2_TYP);
1306                                 param(ID::T_LIMIT2_MAX);
1307                                 port(ID::SRC_EN, 1);
1308                                 port(ID::DST_EN, 1);
1309                                 port(ID::SRC, param(ID::SRC_WIDTH));
1310                                 port(ID::DST, param(ID::DST_WIDTH));
1311                                 check_expected();
1312                                 return;
1313                         }
1314
1315                         if (cell->type == ID($_BUF_))    { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1316                         if (cell->type == ID($_NOT_))    { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1317                         if (cell->type == ID($_AND_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1318                         if (cell->type == ID($_NAND_))   { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1319                         if (cell->type == ID($_OR_))     { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1320                         if (cell->type == ID($_NOR_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1321                         if (cell->type == ID($_XOR_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1322                         if (cell->type == ID($_XNOR_))   { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1323                         if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1324                         if (cell->type == ID($_ORNOT_))  { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1325                         if (cell->type == ID($_MUX_))    { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1326                         if (cell->type == ID($_NMUX_))   { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1327                         if (cell->type == ID($_AOI3_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1328                         if (cell->type == ID($_OAI3_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1329                         if (cell->type == ID($_AOI4_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1330                         if (cell->type == ID($_OAI4_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1331
1332                         if (cell->type == ID($_TBUF_))  { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1333
1334                         if (cell->type == ID($_MUX4_))  { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1335                         if (cell->type == ID($_MUX8_))  { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1336                         if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1337
1338                         if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1339                         if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1340                         if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1341                         if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1342
1343                         if (cell->type == ID($_FF_))    { port(ID::D,1); port(ID::Q,1); check_expected();  return; }
1344                         if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1345                         if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1346
1347                         if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1348                         if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1349                         if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1350                         if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1351
1352                         if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1353                         if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1354                         if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1355                         if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1356                         if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1357                         if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1358                         if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1359                         if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1360
1361                         if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1362                         if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1363                         if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1364                         if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1365                         if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1366                         if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1367                         if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1368                         if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1369
1370                         if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1371                         if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1372
1373                         if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1374                         if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1375                         if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1376                         if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1377                         if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1378                         if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1379                         if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1380                         if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1381
1382                         error(__LINE__);
1383                 }
1384         };
1385 }
1386 #endif
1387
1388 void RTLIL::Module::sort()
1389 {
1390         wires_.sort(sort_by_id_str());
1391         cells_.sort(sort_by_id_str());
1392         parameter_default_values.sort(sort_by_id_str());
1393         memories.sort(sort_by_id_str());
1394         processes.sort(sort_by_id_str());
1395         for (auto &it : cells_)
1396                 it.second->sort();
1397         for (auto &it : wires_)
1398                 it.second->attributes.sort(sort_by_id_str());
1399         for (auto &it : memories)
1400                 it.second->attributes.sort(sort_by_id_str());
1401 }
1402
1403 void RTLIL::Module::check()
1404 {
1405 #ifndef NDEBUG
1406         std::vector<bool> ports_declared;
1407         for (auto &it : wires_) {
1408                 log_assert(this == it.second->module);
1409                 log_assert(it.first == it.second->name);
1410                 log_assert(!it.first.empty());
1411                 log_assert(it.second->width >= 0);
1412                 log_assert(it.second->port_id >= 0);
1413                 for (auto &it2 : it.second->attributes)
1414                         log_assert(!it2.first.empty());
1415                 if (it.second->port_id) {
1416                         log_assert(GetSize(ports) >= it.second->port_id);
1417                         log_assert(ports.at(it.second->port_id-1) == it.first);
1418                         log_assert(it.second->port_input || it.second->port_output);
1419                         if (GetSize(ports_declared) < it.second->port_id)
1420                                 ports_declared.resize(it.second->port_id);
1421                         log_assert(ports_declared[it.second->port_id-1] == false);
1422                         ports_declared[it.second->port_id-1] = true;
1423                 } else
1424                         log_assert(!it.second->port_input && !it.second->port_output);
1425         }
1426         for (auto port_declared : ports_declared)
1427                 log_assert(port_declared == true);
1428         log_assert(GetSize(ports) == GetSize(ports_declared));
1429
1430         for (auto &it : memories) {
1431                 log_assert(it.first == it.second->name);
1432                 log_assert(!it.first.empty());
1433                 log_assert(it.second->width >= 0);
1434                 log_assert(it.second->size >= 0);
1435                 for (auto &it2 : it.second->attributes)
1436                         log_assert(!it2.first.empty());
1437         }
1438
1439         for (auto &it : cells_) {
1440                 log_assert(this == it.second->module);
1441                 log_assert(it.first == it.second->name);
1442                 log_assert(!it.first.empty());
1443                 log_assert(!it.second->type.empty());
1444                 for (auto &it2 : it.second->connections()) {
1445                         log_assert(!it2.first.empty());
1446                         it2.second.check();
1447                 }
1448                 for (auto &it2 : it.second->attributes)
1449                         log_assert(!it2.first.empty());
1450                 for (auto &it2 : it.second->parameters)
1451                         log_assert(!it2.first.empty());
1452                 InternalCellChecker checker(this, it.second);
1453                 checker.check();
1454         }
1455
1456         for (auto &it : processes) {
1457                 log_assert(it.first == it.second->name);
1458                 log_assert(!it.first.empty());
1459                 log_assert(it.second->root_case.compare.empty());
1460                 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1461                 for (size_t i = 0; i < all_cases.size(); i++) {
1462                         for (auto &switch_it : all_cases[i]->switches) {
1463                                 for (auto &case_it : switch_it->cases) {
1464                                         for (auto &compare_it : case_it->compare) {
1465                                                 log_assert(switch_it->signal.size() == compare_it.size());
1466                                         }
1467                                         all_cases.push_back(case_it);
1468                                 }
1469                         }
1470                 }
1471                 for (auto &sync_it : it.second->syncs) {
1472                         switch (sync_it->type) {
1473                                 case SyncType::ST0:
1474                                 case SyncType::ST1:
1475                                 case SyncType::STp:
1476                                 case SyncType::STn:
1477                                 case SyncType::STe:
1478                                         log_assert(!sync_it->signal.empty());
1479                                         break;
1480                                 case SyncType::STa:
1481                                 case SyncType::STg:
1482                                 case SyncType::STi:
1483                                         log_assert(sync_it->signal.empty());
1484                                         break;
1485                         }
1486                 }
1487         }
1488
1489         for (auto &it : connections_) {
1490                 log_assert(it.first.size() == it.second.size());
1491                 log_assert(!it.first.has_const());
1492                 it.first.check();
1493                 it.second.check();
1494         }
1495
1496         for (auto &it : attributes)
1497                 log_assert(!it.first.empty());
1498 #endif
1499 }
1500
1501 void RTLIL::Module::optimize()
1502 {
1503 }
1504
1505 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1506 {
1507         log_assert(new_mod->refcount_wires_ == 0);
1508         log_assert(new_mod->refcount_cells_ == 0);
1509
1510         new_mod->avail_parameters = avail_parameters;
1511         new_mod->parameter_default_values = parameter_default_values;
1512
1513         for (auto &conn : connections_)
1514                 new_mod->connect(conn);
1515
1516         for (auto &attr : attributes)
1517                 new_mod->attributes[attr.first] = attr.second;
1518
1519         for (auto &it : wires_)
1520                 new_mod->addWire(it.first, it.second);
1521
1522         for (auto &it : memories)
1523                 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1524
1525         for (auto &it : cells_)
1526                 new_mod->addCell(it.first, it.second);
1527
1528         for (auto &it : processes)
1529                 new_mod->processes[it.first] = it.second->clone();
1530
1531         struct RewriteSigSpecWorker
1532         {
1533                 RTLIL::Module *mod;
1534                 void operator()(RTLIL::SigSpec &sig)
1535                 {
1536                         sig.pack();
1537                         for (auto &c : sig.chunks_)
1538                                 if (c.wire != NULL)
1539                                         c.wire = mod->wires_.at(c.wire->name);
1540                 }
1541         };
1542
1543         RewriteSigSpecWorker rewriteSigSpecWorker;
1544         rewriteSigSpecWorker.mod = new_mod;
1545         new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1546         new_mod->fixup_ports();
1547 }
1548
1549 RTLIL::Module *RTLIL::Module::clone() const
1550 {
1551         RTLIL::Module *new_mod = new RTLIL::Module;
1552         new_mod->name = name;
1553         cloneInto(new_mod);
1554         return new_mod;
1555 }
1556
1557 bool RTLIL::Module::has_memories() const
1558 {
1559         return !memories.empty();
1560 }
1561
1562 bool RTLIL::Module::has_processes() const
1563 {
1564         return !processes.empty();
1565 }
1566
1567 bool RTLIL::Module::has_memories_warn() const
1568 {
1569         if (!memories.empty())
1570                 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1571         return !memories.empty();
1572 }
1573
1574 bool RTLIL::Module::has_processes_warn() const
1575 {
1576         if (!processes.empty())
1577                 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1578         return !processes.empty();
1579 }
1580
1581 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1582 {
1583         std::vector<RTLIL::Wire*> result;
1584         result.reserve(wires_.size());
1585         for (auto &it : wires_)
1586                 if (design->selected(this, it.second))
1587                         result.push_back(it.second);
1588         return result;
1589 }
1590
1591 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1592 {
1593         std::vector<RTLIL::Cell*> result;
1594         result.reserve(cells_.size());
1595         for (auto &it : cells_)
1596                 if (design->selected(this, it.second))
1597                         result.push_back(it.second);
1598         return result;
1599 }
1600
1601 void RTLIL::Module::add(RTLIL::Wire *wire)
1602 {
1603         log_assert(!wire->name.empty());
1604         log_assert(count_id(wire->name) == 0);
1605         log_assert(refcount_wires_ == 0);
1606         wires_[wire->name] = wire;
1607         wire->module = this;
1608 }
1609
1610 void RTLIL::Module::add(RTLIL::Cell *cell)
1611 {
1612         log_assert(!cell->name.empty());
1613         log_assert(count_id(cell->name) == 0);
1614         log_assert(refcount_cells_ == 0);
1615         cells_[cell->name] = cell;
1616         cell->module = this;
1617 }
1618
1619 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1620 {
1621         log_assert(refcount_wires_ == 0);
1622
1623         struct DeleteWireWorker
1624         {
1625                 RTLIL::Module *module;
1626                 const pool<RTLIL::Wire*> *wires_p;
1627
1628                 void operator()(RTLIL::SigSpec &sig) {
1629                         sig.pack();
1630                         for (auto &c : sig.chunks_)
1631                                 if (c.wire != NULL && wires_p->count(c.wire)) {
1632                                         c.wire = module->addWire(NEW_ID, c.width);
1633                                         c.offset = 0;
1634                                 }
1635                 }
1636
1637                 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1638                         log_assert(GetSize(lhs) == GetSize(rhs));
1639                         lhs.unpack();
1640                         rhs.unpack();
1641                         for (int i = 0; i < GetSize(lhs); i++) {
1642                                 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1643                                 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1644                                 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1645                                         lhs_bit = State::Sx;
1646                                         rhs_bit = State::Sx;
1647                                 }
1648                         }
1649                 }
1650         };
1651
1652         DeleteWireWorker delete_wire_worker;
1653         delete_wire_worker.module = this;
1654         delete_wire_worker.wires_p = &wires;
1655         rewrite_sigspecs2(delete_wire_worker);
1656
1657         for (auto &it : wires) {
1658                 log_assert(wires_.count(it->name) != 0);
1659                 wires_.erase(it->name);
1660                 delete it;
1661         }
1662 }
1663
1664 void RTLIL::Module::remove(RTLIL::Cell *cell)
1665 {
1666         while (!cell->connections_.empty())
1667                 cell->unsetPort(cell->connections_.begin()->first);
1668
1669         log_assert(cells_.count(cell->name) != 0);
1670         log_assert(refcount_cells_ == 0);
1671         cells_.erase(cell->name);
1672         delete cell;
1673 }
1674
1675 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1676 {
1677         log_assert(wires_[wire->name] == wire);
1678         log_assert(refcount_wires_ == 0);
1679         wires_.erase(wire->name);
1680         wire->name = new_name;
1681         add(wire);
1682 }
1683
1684 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1685 {
1686         log_assert(cells_[cell->name] == cell);
1687         log_assert(refcount_wires_ == 0);
1688         cells_.erase(cell->name);
1689         cell->name = new_name;
1690         add(cell);
1691 }
1692
1693 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1694 {
1695         log_assert(count_id(old_name) != 0);
1696         if (wires_.count(old_name))
1697                 rename(wires_.at(old_name), new_name);
1698         else if (cells_.count(old_name))
1699                 rename(cells_.at(old_name), new_name);
1700         else
1701                 log_abort();
1702 }
1703
1704 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1705 {
1706         log_assert(wires_[w1->name] == w1);
1707         log_assert(wires_[w2->name] == w2);
1708         log_assert(refcount_wires_ == 0);
1709
1710         wires_.erase(w1->name);
1711         wires_.erase(w2->name);
1712
1713         std::swap(w1->name, w2->name);
1714
1715         wires_[w1->name] = w1;
1716         wires_[w2->name] = w2;
1717 }
1718
1719 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1720 {
1721         log_assert(cells_[c1->name] == c1);
1722         log_assert(cells_[c2->name] == c2);
1723         log_assert(refcount_cells_ == 0);
1724
1725         cells_.erase(c1->name);
1726         cells_.erase(c2->name);
1727
1728         std::swap(c1->name, c2->name);
1729
1730         cells_[c1->name] = c1;
1731         cells_[c2->name] = c2;
1732 }
1733
1734 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1735 {
1736         int index = 0;
1737         return uniquify(name, index);
1738 }
1739
1740 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1741 {
1742         if (index == 0) {
1743                 if (count_id(name) == 0)
1744                         return name;
1745                 index++;
1746         }
1747
1748         while (1) {
1749                 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1750                 if (count_id(new_name) == 0)
1751                         return new_name;
1752                 index++;
1753         }
1754 }
1755
1756 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1757 {
1758         if (a->port_id && !b->port_id)
1759                 return true;
1760         if (!a->port_id && b->port_id)
1761                 return false;
1762
1763         if (a->port_id == b->port_id)
1764                 return a->name < b->name;
1765         return a->port_id < b->port_id;
1766 }
1767
1768 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1769 {
1770         for (auto mon : monitors)
1771                 mon->notify_connect(this, conn);
1772
1773         if (design)
1774                 for (auto mon : design->monitors)
1775                         mon->notify_connect(this, conn);
1776
1777         // ignore all attempts to assign constants to other constants
1778         if (conn.first.has_const()) {
1779                 RTLIL::SigSig new_conn;
1780                 for (int i = 0; i < GetSize(conn.first); i++)
1781                         if (conn.first[i].wire) {
1782                                 new_conn.first.append(conn.first[i]);
1783                                 new_conn.second.append(conn.second[i]);
1784                         }
1785                 if (GetSize(new_conn.first))
1786                         connect(new_conn);
1787                 return;
1788         }
1789
1790         if (yosys_xtrace) {
1791                 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1792                 log_backtrace("-X- ", yosys_xtrace-1);
1793         }
1794
1795         log_assert(GetSize(conn.first) == GetSize(conn.second));
1796         connections_.push_back(conn);
1797 }
1798
1799 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1800 {
1801         connect(RTLIL::SigSig(lhs, rhs));
1802 }
1803
1804 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1805 {
1806         for (auto mon : monitors)
1807                 mon->notify_connect(this, new_conn);
1808
1809         if (design)
1810                 for (auto mon : design->monitors)
1811                         mon->notify_connect(this, new_conn);
1812
1813         if (yosys_xtrace) {
1814                 log("#X# New connections vector in %s:\n", log_id(this));
1815                 for (auto &conn: new_conn)
1816                         log("#X#    %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1817                 log_backtrace("-X- ", yosys_xtrace-1);
1818         }
1819
1820         connections_ = new_conn;
1821 }
1822
1823 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1824 {
1825         return connections_;
1826 }
1827
1828 void RTLIL::Module::fixup_ports()
1829 {
1830         std::vector<RTLIL::Wire*> all_ports;
1831
1832         for (auto &w : wires_)
1833                 if (w.second->port_input || w.second->port_output)
1834                         all_ports.push_back(w.second);
1835                 else
1836                         w.second->port_id = 0;
1837
1838         std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1839
1840         ports.clear();
1841         for (size_t i = 0; i < all_ports.size(); i++) {
1842                 ports.push_back(all_ports[i]->name);
1843                 all_ports[i]->port_id = i+1;
1844         }
1845 }
1846
1847 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1848 {
1849         RTLIL::Wire *wire = new RTLIL::Wire;
1850         wire->name = name;
1851         wire->width = width;
1852         add(wire);
1853         return wire;
1854 }
1855
1856 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1857 {
1858         RTLIL::Wire *wire = addWire(name);
1859         wire->width = other->width;
1860         wire->start_offset = other->start_offset;
1861         wire->port_id = other->port_id;
1862         wire->port_input = other->port_input;
1863         wire->port_output = other->port_output;
1864         wire->upto = other->upto;
1865         wire->is_signed = other->is_signed;
1866         wire->attributes = other->attributes;
1867         return wire;
1868 }
1869
1870 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1871 {
1872         RTLIL::Cell *cell = new RTLIL::Cell;
1873         cell->name = name;
1874         cell->type = type;
1875         add(cell);
1876         return cell;
1877 }
1878
1879 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1880 {
1881         RTLIL::Cell *cell = addCell(name, other->type);
1882         cell->connections_ = other->connections_;
1883         cell->parameters = other->parameters;
1884         cell->attributes = other->attributes;
1885         return cell;
1886 }
1887
1888 #define DEF_METHOD(_func, _y_size, _type) \
1889         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1890                 RTLIL::Cell *cell = addCell(name, _type);           \
1891                 cell->parameters[ID::A_SIGNED] = is_signed;         \
1892                 cell->parameters[ID::A_WIDTH] = sig_a.size();       \
1893                 cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
1894                 cell->setPort(ID::A, sig_a);                        \
1895                 cell->setPort(ID::Y, sig_y);                        \
1896                 cell->set_src_attribute(src);                       \
1897                 return cell;                                        \
1898         } \
1899         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1900                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);    \
1901                 add ## _func(name, sig_a, sig_y, is_signed, src);   \
1902                 return sig_y;                                       \
1903         }
1904 DEF_METHOD(Not,        sig_a.size(), ID($not))
1905 DEF_METHOD(Pos,        sig_a.size(), ID($pos))
1906 DEF_METHOD(Neg,        sig_a.size(), ID($neg))
1907 DEF_METHOD(ReduceAnd,  1, ID($reduce_and))
1908 DEF_METHOD(ReduceOr,   1, ID($reduce_or))
1909 DEF_METHOD(ReduceXor,  1, ID($reduce_xor))
1910 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1911 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1912 DEF_METHOD(LogicNot,   1, ID($logic_not))
1913 #undef DEF_METHOD
1914
1915 #define DEF_METHOD(_func, _y_size, _type) \
1916         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1917                 RTLIL::Cell *cell = addCell(name, _type);           \
1918                 cell->parameters[ID::A_SIGNED] = is_signed;         \
1919                 cell->parameters[ID::B_SIGNED] = is_signed;         \
1920                 cell->parameters[ID::A_WIDTH] = sig_a.size();       \
1921                 cell->parameters[ID::B_WIDTH] = sig_b.size();       \
1922                 cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
1923                 cell->setPort(ID::A, sig_a);                        \
1924                 cell->setPort(ID::B, sig_b);                        \
1925                 cell->setPort(ID::Y, sig_y);                        \
1926                 cell->set_src_attribute(src);                       \
1927                 return cell;                                        \
1928         } \
1929         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1930                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
1931                 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1932                 return sig_y;                                            \
1933         }
1934 DEF_METHOD(And,      max(sig_a.size(), sig_b.size()), ID($and))
1935 DEF_METHOD(Or,       max(sig_a.size(), sig_b.size()), ID($or))
1936 DEF_METHOD(Xor,      max(sig_a.size(), sig_b.size()), ID($xor))
1937 DEF_METHOD(Xnor,     max(sig_a.size(), sig_b.size()), ID($xnor))
1938 DEF_METHOD(Shift,    sig_a.size(), ID($shift))
1939 DEF_METHOD(Shiftx,   sig_a.size(), ID($shiftx))
1940 DEF_METHOD(Lt,       1, ID($lt))
1941 DEF_METHOD(Le,       1, ID($le))
1942 DEF_METHOD(Eq,       1, ID($eq))
1943 DEF_METHOD(Ne,       1, ID($ne))
1944 DEF_METHOD(Eqx,      1, ID($eqx))
1945 DEF_METHOD(Nex,      1, ID($nex))
1946 DEF_METHOD(Ge,       1, ID($ge))
1947 DEF_METHOD(Gt,       1, ID($gt))
1948 DEF_METHOD(Add,      max(sig_a.size(), sig_b.size()), ID($add))
1949 DEF_METHOD(Sub,      max(sig_a.size(), sig_b.size()), ID($sub))
1950 DEF_METHOD(Mul,      max(sig_a.size(), sig_b.size()), ID($mul))
1951 DEF_METHOD(Div,      max(sig_a.size(), sig_b.size()), ID($div))
1952 DEF_METHOD(Mod,      max(sig_a.size(), sig_b.size()), ID($mod))
1953 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
1954 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
1955 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1956 DEF_METHOD(LogicOr,  1, ID($logic_or))
1957 #undef DEF_METHOD
1958
1959 #define DEF_METHOD(_func, _y_size, _type) \
1960         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1961                 RTLIL::Cell *cell = addCell(name, _type);           \
1962                 cell->parameters[ID::A_SIGNED] = is_signed;         \
1963                 cell->parameters[ID::B_SIGNED] = false;             \
1964                 cell->parameters[ID::A_WIDTH] = sig_a.size();       \
1965                 cell->parameters[ID::B_WIDTH] = sig_b.size();       \
1966                 cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
1967                 cell->setPort(ID::A, sig_a);                        \
1968                 cell->setPort(ID::B, sig_b);                        \
1969                 cell->setPort(ID::Y, sig_y);                        \
1970                 cell->set_src_attribute(src);                       \
1971                 return cell;                                        \
1972         } \
1973         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1974                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
1975                 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1976                 return sig_y;                                            \
1977         }
1978 DEF_METHOD(Shl,      sig_a.size(), ID($shl))
1979 DEF_METHOD(Shr,      sig_a.size(), ID($shr))
1980 DEF_METHOD(Sshl,     sig_a.size(), ID($sshl))
1981 DEF_METHOD(Sshr,     sig_a.size(), ID($sshr))
1982 #undef DEF_METHOD
1983
1984 #define DEF_METHOD(_func, _type, _pmux) \
1985         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1986                 RTLIL::Cell *cell = addCell(name, _type);                 \
1987                 cell->parameters[ID::WIDTH] = sig_a.size();               \
1988                 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size();  \
1989                 cell->setPort(ID::A, sig_a);                              \
1990                 cell->setPort(ID::B, sig_b);                              \
1991                 cell->setPort(ID::S, sig_s);                              \
1992                 cell->setPort(ID::Y, sig_y);                              \
1993                 cell->set_src_attribute(src);                             \
1994                 return cell;                                              \
1995         } \
1996         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1997                 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size());     \
1998                 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src);      \
1999                 return sig_y;                                             \
2000         }
2001 DEF_METHOD(Mux,      ID($mux),        0)
2002 DEF_METHOD(Pmux,     ID($pmux),       1)
2003 #undef DEF_METHOD
2004
2005 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2006         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2007                 RTLIL::Cell *cell = addCell(name, _type);         \
2008                 cell->setPort("\\" #_P1, sig1);                   \
2009                 cell->setPort("\\" #_P2, sig2);                   \
2010                 cell->set_src_attribute(src);                     \
2011                 return cell;                                      \
2012         } \
2013         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2014                 RTLIL::SigBit sig2 = addWire(NEW_ID);             \
2015                 add ## _func(name, sig1, sig2, src);              \
2016                 return sig2;                                      \
2017         }
2018 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2019         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2020                 RTLIL::Cell *cell = addCell(name, _type);         \
2021                 cell->setPort("\\" #_P1, sig1);                   \
2022                 cell->setPort("\\" #_P2, sig2);                   \
2023                 cell->setPort("\\" #_P3, sig3);                   \
2024                 cell->set_src_attribute(src);                     \
2025                 return cell;                                      \
2026         } \
2027         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2028                 RTLIL::SigBit sig3 = addWire(NEW_ID);             \
2029                 add ## _func(name, sig1, sig2, sig3, src);        \
2030                 return sig3;                                      \
2031         }
2032 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2033         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2034                 RTLIL::Cell *cell = addCell(name, _type);         \
2035                 cell->setPort("\\" #_P1, sig1);                   \
2036                 cell->setPort("\\" #_P2, sig2);                   \
2037                 cell->setPort("\\" #_P3, sig3);                   \
2038                 cell->setPort("\\" #_P4, sig4);                   \
2039                 cell->set_src_attribute(src);                     \
2040                 return cell;                                      \
2041         } \
2042         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2043                 RTLIL::SigBit sig4 = addWire(NEW_ID);             \
2044                 add ## _func(name, sig1, sig2, sig3, sig4, src);  \
2045                 return sig4;                                      \
2046         }
2047 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2048         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2049                 RTLIL::Cell *cell = addCell(name, _type);         \
2050                 cell->setPort("\\" #_P1, sig1);                   \
2051                 cell->setPort("\\" #_P2, sig2);                   \
2052                 cell->setPort("\\" #_P3, sig3);                   \
2053                 cell->setPort("\\" #_P4, sig4);                   \
2054                 cell->setPort("\\" #_P5, sig5);                   \
2055                 cell->set_src_attribute(src);                     \
2056                 return cell;                                      \
2057         } \
2058         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2059                 RTLIL::SigBit sig5 = addWire(NEW_ID);                  \
2060                 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2061                 return sig5;                                           \
2062         }
2063 DEF_METHOD_2(BufGate,    ID($_BUF_),    A, Y)
2064 DEF_METHOD_2(NotGate,    ID($_NOT_),    A, Y)
2065 DEF_METHOD_3(AndGate,    ID($_AND_),    A, B, Y)
2066 DEF_METHOD_3(NandGate,   ID($_NAND_),   A, B, Y)
2067 DEF_METHOD_3(OrGate,     ID($_OR_),     A, B, Y)
2068 DEF_METHOD_3(NorGate,    ID($_NOR_),    A, B, Y)
2069 DEF_METHOD_3(XorGate,    ID($_XOR_),    A, B, Y)
2070 DEF_METHOD_3(XnorGate,   ID($_XNOR_),   A, B, Y)
2071 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2072 DEF_METHOD_3(OrnotGate,  ID($_ORNOT_),  A, B, Y)
2073 DEF_METHOD_4(MuxGate,    ID($_MUX_),    A, B, S, Y)
2074 DEF_METHOD_4(NmuxGate,   ID($_NMUX_),   A, B, S, Y)
2075 DEF_METHOD_4(Aoi3Gate,   ID($_AOI3_),   A, B, C, Y)
2076 DEF_METHOD_4(Oai3Gate,   ID($_OAI3_),   A, B, C, Y)
2077 DEF_METHOD_5(Aoi4Gate,   ID($_AOI4_),   A, B, C, D, Y)
2078 DEF_METHOD_5(Oai4Gate,   ID($_OAI4_),   A, B, C, D, Y)
2079 #undef DEF_METHOD_2
2080 #undef DEF_METHOD_3
2081 #undef DEF_METHOD_4
2082 #undef DEF_METHOD_5
2083
2084 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2085 {
2086         RTLIL::Cell *cell = addCell(name, ID($pow));
2087         cell->parameters[ID::A_SIGNED] = a_signed;
2088         cell->parameters[ID::B_SIGNED] = b_signed;
2089         cell->parameters[ID::A_WIDTH] = sig_a.size();
2090         cell->parameters[ID::B_WIDTH] = sig_b.size();
2091         cell->parameters[ID::Y_WIDTH] = sig_y.size();
2092         cell->setPort(ID::A, sig_a);
2093         cell->setPort(ID::B, sig_b);
2094         cell->setPort(ID::Y, sig_y);
2095         cell->set_src_attribute(src);
2096         return cell;
2097 }
2098
2099 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2100 {
2101         RTLIL::Cell *cell = addCell(name, ID($slice));
2102         cell->parameters[ID::A_WIDTH] = sig_a.size();
2103         cell->parameters[ID::Y_WIDTH] = sig_y.size();
2104         cell->parameters[ID::OFFSET] = offset;
2105         cell->setPort(ID::A, sig_a);
2106         cell->setPort(ID::Y, sig_y);
2107         cell->set_src_attribute(src);
2108         return cell;
2109 }
2110
2111 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2112 {
2113         RTLIL::Cell *cell = addCell(name, ID($concat));
2114         cell->parameters[ID::A_WIDTH] = sig_a.size();
2115         cell->parameters[ID::B_WIDTH] = sig_b.size();
2116         cell->setPort(ID::A, sig_a);
2117         cell->setPort(ID::B, sig_b);
2118         cell->setPort(ID::Y, sig_y);
2119         cell->set_src_attribute(src);
2120         return cell;
2121 }
2122
2123 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2124 {
2125         RTLIL::Cell *cell = addCell(name, ID($lut));
2126         cell->parameters[ID::LUT] = lut;
2127         cell->parameters[ID::WIDTH] = sig_a.size();
2128         cell->setPort(ID::A, sig_a);
2129         cell->setPort(ID::Y, sig_y);
2130         cell->set_src_attribute(src);
2131         return cell;
2132 }
2133
2134 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2135 {
2136         RTLIL::Cell *cell = addCell(name, ID($tribuf));
2137         cell->parameters[ID::WIDTH] = sig_a.size();
2138         cell->setPort(ID::A, sig_a);
2139         cell->setPort(ID::EN, sig_en);
2140         cell->setPort(ID::Y, sig_y);
2141         cell->set_src_attribute(src);
2142         return cell;
2143 }
2144
2145 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2146 {
2147         RTLIL::Cell *cell = addCell(name, ID($assert));
2148         cell->setPort(ID::A, sig_a);
2149         cell->setPort(ID::EN, sig_en);
2150         cell->set_src_attribute(src);
2151         return cell;
2152 }
2153
2154 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2155 {
2156         RTLIL::Cell *cell = addCell(name, ID($assume));
2157         cell->setPort(ID::A, sig_a);
2158         cell->setPort(ID::EN, sig_en);
2159         cell->set_src_attribute(src);
2160         return cell;
2161 }
2162
2163 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2164 {
2165         RTLIL::Cell *cell = addCell(name, ID($live));
2166         cell->setPort(ID::A, sig_a);
2167         cell->setPort(ID::EN, sig_en);
2168         cell->set_src_attribute(src);
2169         return cell;
2170 }
2171
2172 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2173 {
2174         RTLIL::Cell *cell = addCell(name, ID($fair));
2175         cell->setPort(ID::A, sig_a);
2176         cell->setPort(ID::EN, sig_en);
2177         cell->set_src_attribute(src);
2178         return cell;
2179 }
2180
2181 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2182 {
2183         RTLIL::Cell *cell = addCell(name, ID($cover));
2184         cell->setPort(ID::A, sig_a);
2185         cell->setPort(ID::EN, sig_en);
2186         cell->set_src_attribute(src);
2187         return cell;
2188 }
2189
2190 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2191 {
2192         RTLIL::Cell *cell = addCell(name, ID($equiv));
2193         cell->setPort(ID::A, sig_a);
2194         cell->setPort(ID::B, sig_b);
2195         cell->setPort(ID::Y, sig_y);
2196         cell->set_src_attribute(src);
2197         return cell;
2198 }
2199
2200 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2201 {
2202         RTLIL::Cell *cell = addCell(name, ID($sr));
2203         cell->parameters[ID::SET_POLARITY] = set_polarity;
2204         cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2205         cell->parameters[ID::WIDTH] = sig_q.size();
2206         cell->setPort(ID::SET, sig_set);
2207         cell->setPort(ID::CLR, sig_clr);
2208         cell->setPort(ID::Q, sig_q);
2209         cell->set_src_attribute(src);
2210         return cell;
2211 }
2212
2213 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2214 {
2215         RTLIL::Cell *cell = addCell(name, ID($ff));
2216         cell->parameters[ID::WIDTH] = sig_q.size();
2217         cell->setPort(ID::D, sig_d);
2218         cell->setPort(ID::Q, sig_q);
2219         cell->set_src_attribute(src);
2220         return cell;
2221 }
2222
2223 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2224 {
2225         RTLIL::Cell *cell = addCell(name, ID($dff));
2226         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2227         cell->parameters[ID::WIDTH] = sig_q.size();
2228         cell->setPort(ID::CLK, sig_clk);
2229         cell->setPort(ID::D, sig_d);
2230         cell->setPort(ID::Q, sig_q);
2231         cell->set_src_attribute(src);
2232         return cell;
2233 }
2234
2235 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2236 {
2237         RTLIL::Cell *cell = addCell(name, ID($dffe));
2238         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2239         cell->parameters[ID::EN_POLARITY] = en_polarity;
2240         cell->parameters[ID::WIDTH] = sig_q.size();
2241         cell->setPort(ID::CLK, sig_clk);
2242         cell->setPort(ID::EN, sig_en);
2243         cell->setPort(ID::D, sig_d);
2244         cell->setPort(ID::Q, sig_q);
2245         cell->set_src_attribute(src);
2246         return cell;
2247 }
2248
2249 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2250                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2251 {
2252         RTLIL::Cell *cell = addCell(name, ID($dffsr));
2253         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2254         cell->parameters[ID::SET_POLARITY] = set_polarity;
2255         cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2256         cell->parameters[ID::WIDTH] = sig_q.size();
2257         cell->setPort(ID::CLK, sig_clk);
2258         cell->setPort(ID::SET, sig_set);
2259         cell->setPort(ID::CLR, sig_clr);
2260         cell->setPort(ID::D, sig_d);
2261         cell->setPort(ID::Q, sig_q);
2262         cell->set_src_attribute(src);
2263         return cell;
2264 }
2265
2266 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2267                 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2268 {
2269         RTLIL::Cell *cell = addCell(name, ID($adff));
2270         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2271         cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2272         cell->parameters[ID::ARST_VALUE] = arst_value;
2273         cell->parameters[ID::WIDTH] = sig_q.size();
2274         cell->setPort(ID::CLK, sig_clk);
2275         cell->setPort(ID::ARST, sig_arst);
2276         cell->setPort(ID::D, sig_d);
2277         cell->setPort(ID::Q, sig_q);
2278         cell->set_src_attribute(src);
2279         return cell;
2280 }
2281
2282 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2283 {
2284         RTLIL::Cell *cell = addCell(name, ID($dlatch));
2285         cell->parameters[ID::EN_POLARITY] = en_polarity;
2286         cell->parameters[ID::WIDTH] = sig_q.size();
2287         cell->setPort(ID::EN, sig_en);
2288         cell->setPort(ID::D, sig_d);
2289         cell->setPort(ID::Q, sig_q);
2290         cell->set_src_attribute(src);
2291         return cell;
2292 }
2293
2294 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2295                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2296 {
2297         RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2298         cell->parameters[ID::EN_POLARITY] = en_polarity;
2299         cell->parameters[ID::SET_POLARITY] = set_polarity;
2300         cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2301         cell->parameters[ID::WIDTH] = sig_q.size();
2302         cell->setPort(ID::EN, sig_en);
2303         cell->setPort(ID::SET, sig_set);
2304         cell->setPort(ID::CLR, sig_clr);
2305         cell->setPort(ID::D, sig_d);
2306         cell->setPort(ID::Q, sig_q);
2307         cell->set_src_attribute(src);
2308         return cell;
2309 }
2310
2311 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2312 {
2313         RTLIL::Cell *cell = addCell(name, ID($_FF_));
2314         cell->setPort(ID::D, sig_d);
2315         cell->setPort(ID::Q, sig_q);
2316         cell->set_src_attribute(src);
2317         return cell;
2318 }
2319
2320 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2321 {
2322         RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2323         cell->setPort(ID::C, sig_clk);
2324         cell->setPort(ID::D, sig_d);
2325         cell->setPort(ID::Q, sig_q);
2326         cell->set_src_attribute(src);
2327         return cell;
2328 }
2329
2330 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2331 {
2332         RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2333         cell->setPort(ID::C, sig_clk);
2334         cell->setPort(ID::E, sig_en);
2335         cell->setPort(ID::D, sig_d);
2336         cell->setPort(ID::Q, sig_q);
2337         cell->set_src_attribute(src);
2338         return cell;
2339 }
2340
2341 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2342                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2343 {
2344         RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2345         cell->setPort(ID::C, sig_clk);
2346         cell->setPort(ID::S, sig_set);
2347         cell->setPort(ID::R, sig_clr);
2348         cell->setPort(ID::D, sig_d);
2349         cell->setPort(ID::Q, sig_q);
2350         cell->set_src_attribute(src);
2351         return cell;
2352 }
2353
2354 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2355                 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2356 {
2357         RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2358         cell->setPort(ID::C, sig_clk);
2359         cell->setPort(ID::R, sig_arst);
2360         cell->setPort(ID::D, sig_d);
2361         cell->setPort(ID::Q, sig_q);
2362         cell->set_src_attribute(src);
2363         return cell;
2364 }
2365
2366 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2367 {
2368         RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2369         cell->setPort(ID::E, sig_en);
2370         cell->setPort(ID::D, sig_d);
2371         cell->setPort(ID::Q, sig_q);
2372         cell->set_src_attribute(src);
2373         return cell;
2374 }
2375
2376 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2377                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2378 {
2379         RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2380         cell->setPort(ID::E, sig_en);
2381         cell->setPort(ID::S, sig_set);
2382         cell->setPort(ID::R, sig_clr);
2383         cell->setPort(ID::D, sig_d);
2384         cell->setPort(ID::Q, sig_q);
2385         cell->set_src_attribute(src);
2386         return cell;
2387 }
2388
2389 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2390 {
2391         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2392         Cell *cell = addCell(name, ID($anyconst));
2393         cell->setParam(ID::WIDTH, width);
2394         cell->setPort(ID::Y, sig);
2395         cell->set_src_attribute(src);
2396         return sig;
2397 }
2398
2399 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2400 {
2401         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2402         Cell *cell = addCell(name, ID($anyseq));
2403         cell->setParam(ID::WIDTH, width);
2404         cell->setPort(ID::Y, sig);
2405         cell->set_src_attribute(src);
2406         return sig;
2407 }
2408
2409 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2410 {
2411         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2412         Cell *cell = addCell(name, ID($allconst));
2413         cell->setParam(ID::WIDTH, width);
2414         cell->setPort(ID::Y, sig);
2415         cell->set_src_attribute(src);
2416         return sig;
2417 }
2418
2419 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2420 {
2421         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2422         Cell *cell = addCell(name, ID($allseq));
2423         cell->setParam(ID::WIDTH, width);
2424         cell->setPort(ID::Y, sig);
2425         cell->set_src_attribute(src);
2426         return sig;
2427 }
2428
2429 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2430 {
2431         RTLIL::SigSpec sig = addWire(NEW_ID);
2432         Cell *cell = addCell(name, ID($initstate));
2433         cell->setPort(ID::Y, sig);
2434         cell->set_src_attribute(src);
2435         return sig;
2436 }
2437
2438 RTLIL::Wire::Wire()
2439 {
2440         static unsigned int hashidx_count = 123456789;
2441         hashidx_count = mkhash_xorshift(hashidx_count);
2442         hashidx_ = hashidx_count;
2443
2444         module = nullptr;
2445         width = 1;
2446         start_offset = 0;
2447         port_id = 0;
2448         port_input = false;
2449         port_output = false;
2450         upto = false;
2451         is_signed = false;
2452
2453 #ifdef WITH_PYTHON
2454         RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2455 #endif
2456 }
2457
2458 RTLIL::Wire::~Wire()
2459 {
2460 #ifdef WITH_PYTHON
2461         RTLIL::Wire::get_all_wires()->erase(hashidx_);
2462 #endif
2463 }
2464
2465 #ifdef WITH_PYTHON
2466 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2467 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2468 {
2469         return &all_wires;
2470 }
2471 #endif
2472
2473 RTLIL::Memory::Memory()
2474 {
2475         static unsigned int hashidx_count = 123456789;
2476         hashidx_count = mkhash_xorshift(hashidx_count);
2477         hashidx_ = hashidx_count;
2478
2479         width = 1;
2480         start_offset = 0;
2481         size = 0;
2482 #ifdef WITH_PYTHON
2483         RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2484 #endif
2485 }
2486
2487 RTLIL::Cell::Cell() : module(nullptr)
2488 {
2489         static unsigned int hashidx_count = 123456789;
2490         hashidx_count = mkhash_xorshift(hashidx_count);
2491         hashidx_ = hashidx_count;
2492
2493         // log("#memtrace# %p\n", this);
2494         memhasher();
2495
2496 #ifdef WITH_PYTHON
2497         RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2498 #endif
2499 }
2500
2501 RTLIL::Cell::~Cell()
2502 {
2503 #ifdef WITH_PYTHON
2504         RTLIL::Cell::get_all_cells()->erase(hashidx_);
2505 #endif
2506 }
2507
2508 #ifdef WITH_PYTHON
2509 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2510 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2511 {
2512         return &all_cells;
2513 }
2514 #endif
2515
2516 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2517 {
2518         return connections_.count(portname) != 0;
2519 }
2520
2521 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2522 {
2523         RTLIL::SigSpec signal;
2524         auto conn_it = connections_.find(portname);
2525
2526         if (conn_it != connections_.end())
2527         {
2528                 for (auto mon : module->monitors)
2529                         mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2530
2531                 if (module->design)
2532                         for (auto mon : module->design->monitors)
2533                                 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2534
2535                 if (yosys_xtrace) {
2536                         log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2537                         log_backtrace("-X- ", yosys_xtrace-1);
2538                 }
2539
2540                 connections_.erase(conn_it);
2541         }
2542 }
2543
2544 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2545 {
2546         auto r = connections_.insert(portname);
2547         auto conn_it = r.first;
2548         if (!r.second && conn_it->second == signal)
2549                 return;
2550
2551         for (auto mon : module->monitors)
2552                 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2553
2554         if (module->design)
2555                 for (auto mon : module->design->monitors)
2556                         mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2557
2558         if (yosys_xtrace) {
2559                 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2560                 log_backtrace("-X- ", yosys_xtrace-1);
2561         }
2562
2563         conn_it->second = std::move(signal);
2564 }
2565
2566 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2567 {
2568         return connections_.at(portname);
2569 }
2570
2571 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2572 {
2573         return connections_;
2574 }
2575
2576 bool RTLIL::Cell::known() const
2577 {
2578         if (yosys_celltypes.cell_known(type))
2579                 return true;
2580         if (module && module->design && module->design->module(type))
2581                 return true;
2582         return false;
2583 }
2584
2585 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2586 {
2587         if (yosys_celltypes.cell_known(type))
2588                 return yosys_celltypes.cell_input(type, portname);
2589         if (module && module->design) {
2590                 RTLIL::Module *m = module->design->module(type);
2591                 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2592                 return w && w->port_input;
2593         }
2594         return false;
2595 }
2596
2597 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2598 {
2599         if (yosys_celltypes.cell_known(type))
2600                 return yosys_celltypes.cell_output(type, portname);
2601         if (module && module->design) {
2602                 RTLIL::Module *m = module->design->module(type);
2603                 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2604                 return w && w->port_output;
2605         }
2606         return false;
2607 }
2608
2609 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2610 {
2611         return parameters.count(paramname) != 0;
2612 }
2613
2614 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2615 {
2616         parameters.erase(paramname);
2617 }
2618
2619 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2620 {
2621         parameters[paramname] = std::move(value);
2622 }
2623
2624 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2625 {
2626         const auto &it = parameters.find(paramname);
2627         if (it != parameters.end())
2628                 return it->second;
2629         if (module && module->design) {
2630                 RTLIL::Module *m = module->design->module(type);
2631                 if (m)
2632                         return m->parameter_default_values.at(paramname);
2633         }
2634         throw std::out_of_range("Cell::getParam()");
2635 }
2636
2637 void RTLIL::Cell::sort()
2638 {
2639         connections_.sort(sort_by_id_str());
2640         parameters.sort(sort_by_id_str());
2641         attributes.sort(sort_by_id_str());
2642 }
2643
2644 void RTLIL::Cell::check()
2645 {
2646 #ifndef NDEBUG
2647         InternalCellChecker checker(NULL, this);
2648         checker.check();
2649 #endif
2650 }
2651
2652 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2653 {
2654         if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2655                         type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2656                 return;
2657
2658         if (type == ID($mux) || type == ID($pmux)) {
2659                 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2660                 if (type == ID($pmux))
2661                         parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2662                 check();
2663                 return;
2664         }
2665
2666         if (type == ID($lut) || type == ID($sop)) {
2667                 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2668                 return;
2669         }
2670
2671         if (type == ID($fa)) {
2672                 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2673                 return;
2674         }
2675
2676         if (type == ID($lcu)) {
2677                 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2678                 return;
2679         }
2680
2681         bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2682
2683         if (connections_.count(ID::A)) {
2684                 if (signedness_ab) {
2685                         if (set_a_signed)
2686                                 parameters[ID::A_SIGNED] = true;
2687                         else if (parameters.count(ID::A_SIGNED) == 0)
2688                                 parameters[ID::A_SIGNED] = false;
2689                 }
2690                 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2691         }
2692
2693         if (connections_.count(ID::B)) {
2694                 if (signedness_ab) {
2695                         if (set_b_signed)
2696                                 parameters[ID::B_SIGNED] = true;
2697                         else if (parameters.count(ID::B_SIGNED) == 0)
2698                                 parameters[ID::B_SIGNED] = false;
2699                 }
2700                 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2701         }
2702
2703         if (connections_.count(ID::Y))
2704                 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2705
2706         if (connections_.count(ID::Q))
2707                 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2708
2709         check();
2710 }
2711
2712 RTLIL::SigChunk::SigChunk()
2713 {
2714         wire = NULL;
2715         width = 0;
2716         offset = 0;
2717 }
2718
2719 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2720 {
2721         wire = NULL;
2722         data = value.bits;
2723         width = GetSize(data);
2724         offset = 0;
2725 }
2726
2727 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2728 {
2729         log_assert(wire != nullptr);
2730         this->wire = wire;
2731         this->width = wire->width;
2732         this->offset = 0;
2733 }
2734
2735 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2736 {
2737         log_assert(wire != nullptr);
2738         this->wire = wire;
2739         this->width = width;
2740         this->offset = offset;
2741 }
2742
2743 RTLIL::SigChunk::SigChunk(const std::string &str)
2744 {
2745         wire = NULL;
2746         data = RTLIL::Const(str).bits;
2747         width = GetSize(data);
2748         offset = 0;
2749 }
2750
2751 RTLIL::SigChunk::SigChunk(int val, int width)
2752 {
2753         wire = NULL;
2754         data = RTLIL::Const(val, width).bits;
2755         this->width = GetSize(data);
2756         offset = 0;
2757 }
2758
2759 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2760 {
2761         wire = NULL;
2762         data = RTLIL::Const(bit, width).bits;
2763         this->width = GetSize(data);
2764         offset = 0;
2765 }
2766
2767 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2768 {
2769         wire = bit.wire;
2770         offset = 0;
2771         if (wire == NULL)
2772                 data = RTLIL::Const(bit.data).bits;
2773         else
2774                 offset = bit.offset;
2775         width = 1;
2776 }
2777
2778 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2779 {
2780         *this = sigchunk;
2781 }
2782
2783 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2784 {
2785         RTLIL::SigChunk ret;
2786         if (wire) {
2787                 ret.wire = wire;
2788                 ret.offset = this->offset + offset;
2789                 ret.width = length;
2790         } else {
2791                 for (int i = 0; i < length; i++)
2792                         ret.data.push_back(data[offset+i]);
2793                 ret.width = length;
2794         }
2795         return ret;
2796 }
2797
2798 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2799 {
2800         if (wire && other.wire)
2801                 if (wire->name != other.wire->name)
2802                         return wire->name < other.wire->name;
2803
2804         if (wire != other.wire)
2805                 return wire < other.wire;
2806
2807         if (offset != other.offset)
2808                 return offset < other.offset;
2809
2810         if (width != other.width)
2811                 return width < other.width;
2812
2813         return data < other.data;
2814 }
2815
2816 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2817 {
2818         return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2819 }
2820
2821 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2822 {
2823         if (*this == other)
2824                 return false;
2825         return true;
2826 }
2827
2828 RTLIL::SigSpec::SigSpec()
2829 {
2830         width_ = 0;
2831         hash_ = 0;
2832 }
2833
2834 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2835 {
2836         *this = other;
2837 }
2838
2839 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2840 {
2841         cover("kernel.rtlil.sigspec.init.list");
2842
2843         width_ = 0;
2844         hash_ = 0;
2845
2846         log_assert(parts.size() > 0);
2847         auto ie = parts.begin();
2848         auto it = ie + parts.size() - 1;
2849         while (it >= ie)
2850                 append(*it--);
2851 }
2852
2853 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2854 {
2855         cover("kernel.rtlil.sigspec.assign");
2856
2857         width_ = other.width_;
2858         hash_ = other.hash_;
2859         chunks_ = other.chunks_;
2860         bits_ = other.bits_;
2861         return *this;
2862 }
2863
2864 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2865 {
2866         cover("kernel.rtlil.sigspec.init.const");
2867
2868         chunks_.emplace_back(value);
2869         width_ = chunks_.back().width;
2870         hash_ = 0;
2871         check();
2872 }
2873
2874 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2875 {
2876         cover("kernel.rtlil.sigspec.init.chunk");
2877
2878         chunks_.emplace_back(chunk);
2879         width_ = chunks_.back().width;
2880         hash_ = 0;
2881         check();
2882 }
2883
2884 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2885 {
2886         cover("kernel.rtlil.sigspec.init.wire");
2887
2888         chunks_.emplace_back(wire);
2889         width_ = chunks_.back().width;
2890         hash_ = 0;
2891         check();
2892 }
2893
2894 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2895 {
2896         cover("kernel.rtlil.sigspec.init.wire_part");
2897
2898         chunks_.emplace_back(wire, offset, width);
2899         width_ = chunks_.back().width;
2900         hash_ = 0;
2901         check();
2902 }
2903
2904 RTLIL::SigSpec::SigSpec(const std::string &str)
2905 {
2906         cover("kernel.rtlil.sigspec.init.str");
2907
2908         chunks_.emplace_back(str);
2909         width_ = chunks_.back().width;
2910         hash_ = 0;
2911         check();
2912 }
2913
2914 RTLIL::SigSpec::SigSpec(int val, int width)
2915 {
2916         cover("kernel.rtlil.sigspec.init.int");
2917
2918         chunks_.emplace_back(val, width);
2919         width_ = width;
2920         hash_ = 0;
2921         check();
2922 }
2923
2924 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2925 {
2926         cover("kernel.rtlil.sigspec.init.state");
2927
2928         chunks_.emplace_back(bit, width);
2929         width_ = width;
2930         hash_ = 0;
2931         check();
2932 }
2933
2934 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2935 {
2936         cover("kernel.rtlil.sigspec.init.bit");
2937
2938         if (bit.wire == NULL)
2939                 chunks_.emplace_back(bit.data, width);
2940         else
2941                 for (int i = 0; i < width; i++)
2942                         chunks_.push_back(bit);
2943         width_ = width;
2944         hash_ = 0;
2945         check();
2946 }
2947
2948 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2949 {
2950         cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2951
2952         width_ = 0;
2953         hash_ = 0;
2954         for (const auto &c : chunks)
2955                 append(c);
2956         check();
2957 }
2958
2959 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2960 {
2961         cover("kernel.rtlil.sigspec.init.stdvec_bits");
2962
2963         width_ = 0;
2964         hash_ = 0;
2965         for (const auto &bit : bits)
2966                 append(bit);
2967         check();
2968 }
2969
2970 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2971 {
2972         cover("kernel.rtlil.sigspec.init.pool_bits");
2973
2974         width_ = 0;
2975         hash_ = 0;
2976         for (const auto &bit : bits)
2977                 append(bit);
2978         check();
2979 }
2980
2981 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2982 {
2983         cover("kernel.rtlil.sigspec.init.stdset_bits");
2984
2985         width_ = 0;
2986         hash_ = 0;
2987         for (const auto &bit : bits)
2988                 append(bit);
2989         check();
2990 }
2991
2992 RTLIL::SigSpec::SigSpec(bool bit)
2993 {
2994         cover("kernel.rtlil.sigspec.init.bool");
2995
2996         width_ = 0;
2997         hash_ = 0;
2998         append(SigBit(bit));
2999         check();
3000 }
3001
3002 void RTLIL::SigSpec::pack() const
3003 {
3004         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3005
3006         if (that->bits_.empty())
3007                 return;
3008
3009         cover("kernel.rtlil.sigspec.convert.pack");
3010         log_assert(that->chunks_.empty());
3011
3012         std::vector<RTLIL::SigBit> old_bits;
3013         old_bits.swap(that->bits_);
3014
3015         RTLIL::SigChunk *last = NULL;
3016         int last_end_offset = 0;
3017
3018         for (auto &bit : old_bits) {
3019                 if (last && bit.wire == last->wire) {
3020                         if (bit.wire == NULL) {
3021                                 last->data.push_back(bit.data);
3022                                 last->width++;
3023                                 continue;
3024                         } else if (last_end_offset == bit.offset) {
3025                                 last_end_offset++;
3026                                 last->width++;
3027                                 continue;
3028                         }
3029                 }
3030                 that->chunks_.push_back(bit);
3031                 last = &that->chunks_.back();
3032                 last_end_offset = bit.offset + 1;
3033         }
3034
3035         check();
3036 }
3037
3038 void RTLIL::SigSpec::unpack() const
3039 {
3040         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3041
3042         if (that->chunks_.empty())
3043                 return;
3044
3045         cover("kernel.rtlil.sigspec.convert.unpack");
3046         log_assert(that->bits_.empty());
3047
3048         that->bits_.reserve(that->width_);
3049         for (auto &c : that->chunks_)
3050                 for (int i = 0; i < c.width; i++)
3051                         that->bits_.emplace_back(c, i);
3052
3053         that->chunks_.clear();
3054         that->hash_ = 0;
3055 }
3056
3057 void RTLIL::SigSpec::updhash() const
3058 {
3059         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3060
3061         if (that->hash_ != 0)
3062                 return;
3063
3064         cover("kernel.rtlil.sigspec.hash");
3065         that->pack();
3066
3067         that->hash_ = mkhash_init;
3068         for (auto &c : that->chunks_)
3069                 if (c.wire == NULL) {
3070                         for (auto &v : c.data)
3071                                 that->hash_ = mkhash(that->hash_, v);
3072                 } else {
3073                         that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3074                         that->hash_ = mkhash(that->hash_, c.offset);
3075                         that->hash_ = mkhash(that->hash_, c.width);
3076                 }
3077
3078         if (that->hash_ == 0)
3079                 that->hash_ = 1;
3080 }
3081
3082 void RTLIL::SigSpec::sort()
3083 {
3084         unpack();
3085         cover("kernel.rtlil.sigspec.sort");
3086         std::sort(bits_.begin(), bits_.end());
3087 }
3088
3089 void RTLIL::SigSpec::sort_and_unify()
3090 {
3091         unpack();
3092         cover("kernel.rtlil.sigspec.sort_and_unify");
3093
3094         // A copy of the bits vector is used to prevent duplicating the logic from
3095         // SigSpec::SigSpec(std::vector<SigBit>).  This incurrs an extra copy but
3096         // that isn't showing up as significant in profiles.
3097         std::vector<SigBit> unique_bits = bits_;
3098         std::sort(unique_bits.begin(), unique_bits.end());
3099         auto last = std::unique(unique_bits.begin(), unique_bits.end());
3100         unique_bits.erase(last, unique_bits.end());
3101
3102         *this = unique_bits;
3103 }
3104
3105 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3106 {
3107         replace(pattern, with, this);
3108 }
3109
3110 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3111 {
3112         log_assert(other != NULL);
3113         log_assert(width_ == other->width_);
3114         log_assert(pattern.width_ == with.width_);
3115
3116         pattern.unpack();
3117         with.unpack();
3118         unpack();
3119         other->unpack();
3120
3121         for (int i = 0; i < GetSize(pattern.bits_); i++) {
3122                 if (pattern.bits_[i].wire != NULL) {
3123                         for (int j = 0; j < GetSize(bits_); j++) {
3124                                 if (bits_[j] == pattern.bits_[i]) {
3125                                         other->bits_[j] = with.bits_[i];
3126                                 }
3127                         }
3128                 }
3129         }
3130
3131         other->check();
3132 }
3133
3134 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3135 {
3136         replace(rules, this);
3137 }
3138
3139 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3140 {
3141         cover("kernel.rtlil.sigspec.replace_dict");
3142
3143         log_assert(other != NULL);
3144         log_assert(width_ == other->width_);
3145
3146         if (rules.empty()) return;
3147         unpack();
3148         other->unpack();
3149
3150         for (int i = 0; i < GetSize(bits_); i++) {
3151                 auto it = rules.find(bits_[i]);
3152                 if (it != rules.end())
3153                         other->bits_[i] = it->second;
3154         }
3155
3156         other->check();
3157 }
3158
3159 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3160 {
3161         replace(rules, this);
3162 }
3163
3164 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3165 {
3166         cover("kernel.rtlil.sigspec.replace_map");
3167
3168         log_assert(other != NULL);
3169         log_assert(width_ == other->width_);
3170
3171         if (rules.empty()) return;
3172         unpack();
3173         other->unpack();
3174
3175         for (int i = 0; i < GetSize(bits_); i++) {
3176                 auto it = rules.find(bits_[i]);
3177                 if (it != rules.end())
3178                         other->bits_[i] = it->second;
3179         }
3180
3181         other->check();
3182 }
3183
3184 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3185 {
3186         remove2(pattern, NULL);
3187 }
3188
3189 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3190 {
3191         RTLIL::SigSpec tmp = *this;
3192         tmp.remove2(pattern, other);
3193 }
3194
3195 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3196 {
3197         if (other)
3198                 cover("kernel.rtlil.sigspec.remove_other");
3199         else
3200                 cover("kernel.rtlil.sigspec.remove");
3201
3202         unpack();
3203         if (other != NULL) {
3204                 log_assert(width_ == other->width_);
3205                 other->unpack();
3206         }
3207
3208         for (int i = GetSize(bits_) - 1; i >= 0; i--)
3209         {
3210                 if (bits_[i].wire == NULL) continue;
3211
3212                 for (auto &pattern_chunk : pattern.chunks())
3213                         if (bits_[i].wire == pattern_chunk.wire &&
3214                                 bits_[i].offset >= pattern_chunk.offset &&
3215                                 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3216                                 bits_.erase(bits_.begin() + i);
3217                                 width_--;
3218                                 if (other != NULL) {
3219                                         other->bits_.erase(other->bits_.begin() + i);
3220                                         other->width_--;
3221                                 }
3222                                 break;
3223                         }
3224         }
3225
3226         check();
3227 }
3228
3229 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3230 {
3231         remove2(pattern, NULL);
3232 }
3233
3234 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3235 {
3236         RTLIL::SigSpec tmp = *this;
3237         tmp.remove2(pattern, other);
3238 }
3239
3240 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3241 {
3242         if (other)
3243                 cover("kernel.rtlil.sigspec.remove_other");
3244         else
3245                 cover("kernel.rtlil.sigspec.remove");
3246
3247         unpack();
3248
3249         if (other != NULL) {
3250                 log_assert(width_ == other->width_);
3251                 other->unpack();
3252         }
3253
3254         for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3255                 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3256                         bits_.erase(bits_.begin() + i);
3257                         width_--;
3258                         if (other != NULL) {
3259                                 other->bits_.erase(other->bits_.begin() + i);
3260                                 other->width_--;
3261                         }
3262                 }
3263         }
3264
3265         check();
3266 }
3267
3268 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3269 {
3270         if (other)
3271                 cover("kernel.rtlil.sigspec.remove_other");
3272         else
3273                 cover("kernel.rtlil.sigspec.remove");
3274
3275         unpack();
3276
3277         if (other != NULL) {
3278                 log_assert(width_ == other->width_);
3279                 other->unpack();
3280         }
3281
3282         for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3283                 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3284                         bits_.erase(bits_.begin() + i);
3285                         width_--;
3286                         if (other != NULL) {
3287                                 other->bits_.erase(other->bits_.begin() + i);
3288                                 other->width_--;
3289                         }
3290                 }
3291         }
3292
3293         check();
3294 }
3295
3296 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3297 {
3298         if (other)
3299                 cover("kernel.rtlil.sigspec.extract_other");
3300         else
3301                 cover("kernel.rtlil.sigspec.extract");
3302
3303         log_assert(other == NULL || width_ == other->width_);
3304
3305         RTLIL::SigSpec ret;
3306         std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3307
3308         for (auto& pattern_chunk : pattern.chunks()) {
3309                 if (other) {
3310                         std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3311                         for (int i = 0; i < width_; i++)
3312                                 if (bits_match[i].wire &&
3313                                         bits_match[i].wire == pattern_chunk.wire &&
3314                                         bits_match[i].offset >= pattern_chunk.offset &&
3315                                         bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3316                                         ret.append(bits_other[i]);
3317                 } else {
3318                         for (int i = 0; i < width_; i++)
3319                                 if (bits_match[i].wire &&
3320                                         bits_match[i].wire == pattern_chunk.wire &&
3321                                         bits_match[i].offset >= pattern_chunk.offset &&
3322                                         bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3323                                         ret.append(bits_match[i]);
3324                 }
3325         }
3326
3327         ret.check();
3328         return ret;
3329 }
3330
3331 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3332 {
3333         if (other)
3334                 cover("kernel.rtlil.sigspec.extract_other");
3335         else
3336                 cover("kernel.rtlil.sigspec.extract");
3337
3338         log_assert(other == NULL || width_ == other->width_);
3339
3340         std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3341         RTLIL::SigSpec ret;
3342
3343         if (other) {
3344                 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3345                 for (int i = 0; i < width_; i++)
3346                         if (bits_match[i].wire && pattern.count(bits_match[i]))
3347                                 ret.append(bits_other[i]);
3348         } else {
3349                 for (int i = 0; i < width_; i++)
3350                         if (bits_match[i].wire && pattern.count(bits_match[i]))
3351                                 ret.append(bits_match[i]);
3352         }
3353
3354         ret.check();
3355         return ret;
3356 }
3357
3358 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3359 {
3360         cover("kernel.rtlil.sigspec.replace_pos");
3361
3362         unpack();
3363         with.unpack();
3364
3365         log_assert(offset >= 0);
3366         log_assert(with.width_ >= 0);
3367         log_assert(offset+with.width_ <= width_);
3368
3369         for (int i = 0; i < with.width_; i++)
3370                 bits_.at(offset + i) = with.bits_.at(i);
3371
3372         check();
3373 }
3374
3375 void RTLIL::SigSpec::remove_const()
3376 {
3377         if (packed())
3378         {
3379                 cover("kernel.rtlil.sigspec.remove_const.packed");
3380
3381                 std::vector<RTLIL::SigChunk> new_chunks;
3382                 new_chunks.reserve(GetSize(chunks_));
3383
3384                 width_ = 0;
3385                 for (auto &chunk : chunks_)
3386                         if (chunk.wire != NULL) {
3387                                 new_chunks.push_back(chunk);
3388                                 width_ += chunk.width;
3389                         }
3390
3391                 chunks_.swap(new_chunks);
3392         }
3393         else
3394         {
3395                 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3396
3397                 std::vector<RTLIL::SigBit> new_bits;
3398                 new_bits.reserve(width_);
3399
3400                 for (auto &bit : bits_)
3401                         if (bit.wire != NULL)
3402                                 new_bits.push_back(bit);
3403
3404                 bits_.swap(new_bits);
3405                 width_ = bits_.size();
3406         }
3407
3408         check();
3409 }
3410
3411 void RTLIL::SigSpec::remove(int offset, int length)
3412 {
3413         cover("kernel.rtlil.sigspec.remove_pos");
3414
3415         unpack();
3416
3417         log_assert(offset >= 0);
3418         log_assert(length >= 0);
3419         log_assert(offset + length <= width_);
3420
3421         bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3422         width_ = bits_.size();
3423
3424         check();
3425 }
3426
3427 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3428 {
3429         unpack();
3430         cover("kernel.rtlil.sigspec.extract_pos");
3431         return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3432 }
3433
3434 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3435 {
3436         if (signal.width_ == 0)
3437                 return;
3438
3439         if (width_ == 0) {
3440                 *this = signal;
3441                 return;
3442         }
3443
3444         cover("kernel.rtlil.sigspec.append");
3445
3446         if (packed() != signal.packed()) {
3447                 pack();
3448                 signal.pack();
3449         }
3450
3451         if (packed())
3452                 for (auto &other_c : signal.chunks_)
3453                 {
3454                         auto &my_last_c = chunks_.back();
3455                         if (my_last_c.wire == NULL && other_c.wire == NULL) {
3456                                 auto &this_data = my_last_c.data;
3457                                 auto &other_data = other_c.data;
3458                                 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3459                                 my_last_c.width += other_c.width;
3460                         } else
3461                         if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3462                                 my_last_c.width += other_c.width;
3463                         } else
3464                                 chunks_.push_back(other_c);
3465                 }
3466         else
3467                 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3468
3469         width_ += signal.width_;
3470         check();
3471 }
3472
3473 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3474 {
3475         if (packed())
3476         {
3477                 cover("kernel.rtlil.sigspec.append_bit.packed");
3478
3479                 if (chunks_.size() == 0)
3480                         chunks_.push_back(bit);
3481                 else
3482                         if (bit.wire == NULL)
3483                                 if (chunks_.back().wire == NULL) {
3484                                         chunks_.back().data.push_back(bit.data);
3485                                         chunks_.back().width++;
3486                                 } else
3487                                         chunks_.push_back(bit);
3488                         else
3489                                 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3490                                         chunks_.back().width++;
3491                                 else
3492                                         chunks_.push_back(bit);
3493         }
3494         else
3495         {
3496                 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3497                 bits_.push_back(bit);
3498         }
3499
3500         width_++;
3501         check();
3502 }
3503
3504 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3505 {
3506         cover("kernel.rtlil.sigspec.extend_u0");
3507
3508         pack();
3509
3510         if (width_ > width)
3511                 remove(width, width_ - width);
3512
3513         if (width_ < width) {
3514                 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3515                 if (!is_signed)
3516                         padding = RTLIL::State::S0;
3517                 while (width_ < width)
3518                         append(padding);
3519         }
3520
3521 }
3522
3523 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3524 {
3525         cover("kernel.rtlil.sigspec.repeat");
3526
3527         RTLIL::SigSpec sig;
3528         for (int i = 0; i < num; i++)
3529                 sig.append(*this);
3530         return sig;
3531 }
3532
3533 #ifndef NDEBUG
3534 void RTLIL::SigSpec::check() const
3535 {
3536         if (width_ > 64)
3537         {
3538                 cover("kernel.rtlil.sigspec.check.skip");
3539         }
3540         else if (packed())
3541         {
3542                 cover("kernel.rtlil.sigspec.check.packed");
3543
3544                 int w = 0;
3545                 for (size_t i = 0; i < chunks_.size(); i++) {
3546                         const RTLIL::SigChunk &chunk = chunks_[i];
3547                         if (chunk.wire == NULL) {
3548                                 if (i > 0)
3549                                         log_assert(chunks_[i-1].wire != NULL);
3550                                 log_assert(chunk.offset == 0);
3551                                 log_assert(chunk.data.size() == (size_t)chunk.width);
3552                         } else {
3553                                 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3554                                         log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3555                                 log_assert(chunk.offset >= 0);
3556                                 log_assert(chunk.width >= 0);
3557                                 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3558                                 log_assert(chunk.data.size() == 0);
3559                         }
3560                         w += chunk.width;
3561                 }
3562                 log_assert(w == width_);
3563                 log_assert(bits_.empty());
3564         }
3565         else
3566         {
3567                 cover("kernel.rtlil.sigspec.check.unpacked");
3568
3569                 log_assert(width_ == GetSize(bits_));
3570                 log_assert(chunks_.empty());
3571         }
3572 }
3573 #endif
3574
3575 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3576 {
3577         cover("kernel.rtlil.sigspec.comp_lt");
3578
3579         if (this == &other)
3580                 return false;
3581
3582         if (width_ != other.width_)
3583                 return width_ < other.width_;
3584
3585         pack();
3586         other.pack();
3587
3588         if (chunks_.size() != other.chunks_.size())
3589                 return chunks_.size() < other.chunks_.size();
3590
3591         updhash();
3592         other.updhash();
3593
3594         if (hash_ != other.hash_)
3595                 return hash_ < other.hash_;
3596
3597         for (size_t i = 0; i < chunks_.size(); i++)
3598                 if (chunks_[i] != other.chunks_[i]) {
3599                         cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3600                         return chunks_[i] < other.chunks_[i];
3601                 }
3602
3603         cover("kernel.rtlil.sigspec.comp_lt.equal");
3604         return false;
3605 }
3606
3607 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3608 {
3609         cover("kernel.rtlil.sigspec.comp_eq");
3610
3611         if (this == &other)
3612                 return true;
3613
3614         if (width_ != other.width_)
3615                 return false;
3616
3617         // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3618         //   since the RHS will contain one SigChunk of width 0 causing
3619         //   the size check below to fail
3620         if (width_ == 0)
3621                 return true;
3622
3623         pack();
3624         other.pack();
3625
3626         if (chunks_.size() != other.chunks_.size())
3627                 return false;
3628
3629         updhash();
3630         other.updhash();
3631
3632         if (hash_ != other.hash_)
3633                 return false;
3634
3635         for (size_t i = 0; i < chunks_.size(); i++)
3636                 if (chunks_[i] != other.chunks_[i]) {
3637                         cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3638                         return false;
3639                 }
3640
3641         cover("kernel.rtlil.sigspec.comp_eq.equal");
3642         return true;
3643 }
3644
3645 bool RTLIL::SigSpec::is_wire() const
3646 {
3647         cover("kernel.rtlil.sigspec.is_wire");
3648
3649         pack();
3650         return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3651 }
3652
3653 bool RTLIL::SigSpec::is_chunk() const
3654 {
3655         cover("kernel.rtlil.sigspec.is_chunk");
3656
3657         pack();
3658         return GetSize(chunks_) == 1;
3659 }
3660
3661 bool RTLIL::SigSpec::is_fully_const() const
3662 {
3663         cover("kernel.rtlil.sigspec.is_fully_const");
3664
3665         pack();
3666         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3667                 if (it->width > 0 && it->wire != NULL)
3668                         return false;
3669         return true;
3670 }
3671
3672 bool RTLIL::SigSpec::is_fully_zero() const
3673 {
3674         cover("kernel.rtlil.sigspec.is_fully_zero");
3675
3676         pack();
3677         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3678                 if (it->width > 0 && it->wire != NULL)
3679                         return false;
3680                 for (size_t i = 0; i < it->data.size(); i++)
3681                         if (it->data[i] != RTLIL::State::S0)
3682                                 return false;
3683         }
3684         return true;
3685 }
3686
3687 bool RTLIL::SigSpec::is_fully_ones() const
3688 {
3689         cover("kernel.rtlil.sigspec.is_fully_ones");
3690
3691         pack();
3692         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3693                 if (it->width > 0 && it->wire != NULL)
3694                         return false;
3695                 for (size_t i = 0; i < it->data.size(); i++)
3696                         if (it->data[i] != RTLIL::State::S1)
3697                                 return false;
3698         }
3699         return true;
3700 }
3701
3702 bool RTLIL::SigSpec::is_fully_def() const
3703 {
3704         cover("kernel.rtlil.sigspec.is_fully_def");
3705
3706         pack();
3707         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3708                 if (it->width > 0 && it->wire != NULL)
3709                         return false;
3710                 for (size_t i = 0; i < it->data.size(); i++)
3711                         if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3712                                 return false;
3713         }
3714         return true;
3715 }
3716
3717 bool RTLIL::SigSpec::is_fully_undef() const
3718 {
3719         cover("kernel.rtlil.sigspec.is_fully_undef");
3720
3721         pack();
3722         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3723                 if (it->width > 0 && it->wire != NULL)
3724                         return false;
3725                 for (size_t i = 0; i < it->data.size(); i++)
3726                         if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3727                                 return false;
3728         }
3729         return true;
3730 }
3731
3732 bool RTLIL::SigSpec::has_const() const
3733 {
3734         cover("kernel.rtlil.sigspec.has_const");
3735
3736         pack();
3737         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3738                 if (it->width > 0 && it->wire == NULL)
3739                         return true;
3740         return false;
3741 }
3742
3743 bool RTLIL::SigSpec::has_marked_bits() const
3744 {
3745         cover("kernel.rtlil.sigspec.has_marked_bits");
3746
3747         pack();
3748         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3749                 if (it->width > 0 && it->wire == NULL) {
3750                         for (size_t i = 0; i < it->data.size(); i++)
3751                                 if (it->data[i] == RTLIL::State::Sm)
3752                                         return true;
3753                 }
3754         return false;
3755 }
3756
3757 bool RTLIL::SigSpec::as_bool() const
3758 {
3759         cover("kernel.rtlil.sigspec.as_bool");
3760
3761         pack();
3762         log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3763         if (width_)
3764                 return RTLIL::Const(chunks_[0].data).as_bool();
3765         return false;
3766 }
3767
3768 int RTLIL::SigSpec::as_int(bool is_signed) const
3769 {
3770         cover("kernel.rtlil.sigspec.as_int");
3771
3772         pack();
3773         log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3774         if (width_)
3775                 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3776         return 0;
3777 }
3778
3779 std::string RTLIL::SigSpec::as_string() const
3780 {
3781         cover("kernel.rtlil.sigspec.as_string");
3782
3783         pack();
3784         std::string str;
3785         str.reserve(size());
3786         for (size_t i = chunks_.size(); i > 0; i--) {
3787                 const RTLIL::SigChunk &chunk = chunks_[i-1];
3788                 if (chunk.wire != NULL)
3789                         str.append(chunk.width, '?');
3790                 else
3791                         str += RTLIL::Const(chunk.data).as_string();
3792         }
3793         return str;
3794 }
3795
3796 RTLIL::Const RTLIL::SigSpec::as_const() const
3797 {
3798         cover("kernel.rtlil.sigspec.as_const");
3799
3800         pack();
3801         log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3802         if (width_)
3803                 return chunks_[0].data;
3804         return RTLIL::Const();
3805 }
3806
3807 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3808 {
3809         cover("kernel.rtlil.sigspec.as_wire");
3810
3811         pack();
3812         log_assert(is_wire());
3813         return chunks_[0].wire;
3814 }
3815
3816 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3817 {
3818         cover("kernel.rtlil.sigspec.as_chunk");
3819
3820         pack();
3821         log_assert(is_chunk());
3822         return chunks_[0];
3823 }
3824
3825 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3826 {
3827         cover("kernel.rtlil.sigspec.as_bit");
3828
3829         log_assert(width_ == 1);
3830         if (packed())
3831                 return RTLIL::SigBit(*chunks_.begin());
3832         else
3833                 return bits_[0];
3834 }
3835
3836 bool RTLIL::SigSpec::match(const char* pattern) const
3837 {
3838         cover("kernel.rtlil.sigspec.match");
3839
3840         unpack();
3841         log_assert(int(strlen(pattern)) == GetSize(bits_));
3842
3843         for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3844                 if (*pattern == ' ')
3845                         continue;
3846                 if (*pattern == '*') {
3847                         if (*it != State::Sz && *it != State::Sx)
3848                                 return false;
3849                         continue;
3850                 }
3851                 if (*pattern == '0') {
3852                         if (*it != State::S0)
3853                                 return false;
3854                 } else
3855                 if (*pattern == '1') {
3856                         if (*it != State::S1)
3857                                 return false;
3858                 } else
3859                         log_abort();
3860         }
3861
3862         return true;
3863 }
3864
3865 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3866 {
3867         cover("kernel.rtlil.sigspec.to_sigbit_set");
3868
3869         pack();
3870         std::set<RTLIL::SigBit> sigbits;
3871         for (auto &c : chunks_)
3872                 for (int i = 0; i < c.width; i++)
3873                         sigbits.insert(RTLIL::SigBit(c, i));
3874         return sigbits;
3875 }
3876
3877 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3878 {
3879         cover("kernel.rtlil.sigspec.to_sigbit_pool");
3880
3881         pack();
3882         pool<RTLIL::SigBit> sigbits;
3883         sigbits.reserve(size());
3884         for (auto &c : chunks_)
3885                 for (int i = 0; i < c.width; i++)
3886                         sigbits.insert(RTLIL::SigBit(c, i));
3887         return sigbits;
3888 }
3889
3890 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3891 {
3892         cover("kernel.rtlil.sigspec.to_sigbit_vector");
3893
3894         unpack();
3895         return bits_;
3896 }
3897
3898 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3899 {
3900         cover("kernel.rtlil.sigspec.to_sigbit_map");
3901
3902         unpack();
3903         other.unpack();
3904
3905         log_assert(width_ == other.width_);
3906
3907         std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3908         for (int i = 0; i < width_; i++)
3909                 new_map[bits_[i]] = other.bits_[i];
3910
3911         return new_map;
3912 }
3913
3914 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3915 {
3916         cover("kernel.rtlil.sigspec.to_sigbit_dict");
3917
3918         unpack();
3919         other.unpack();
3920
3921         log_assert(width_ == other.width_);
3922
3923         dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3924         new_map.reserve(size());
3925         for (int i = 0; i < width_; i++)
3926                 new_map[bits_[i]] = other.bits_[i];
3927
3928         return new_map;
3929 }
3930
3931 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3932 {
3933         size_t start = 0, end = 0;
3934         while ((end = text.find(sep, start)) != std::string::npos) {
3935                 tokens.push_back(text.substr(start, end - start));
3936                 start = end + 1;
3937         }
3938         tokens.push_back(text.substr(start));
3939 }
3940
3941 static int sigspec_parse_get_dummy_line_num()
3942 {
3943         return 0;
3944 }
3945
3946 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3947 {
3948         cover("kernel.rtlil.sigspec.parse");
3949
3950         AST::current_filename = "input";
3951
3952         std::vector<std::string> tokens;
3953         sigspec_parse_split(tokens, str, ',');
3954
3955         sig = RTLIL::SigSpec();
3956         for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3957         {
3958                 std::string netname = tokens[tokidx];
3959                 std::string indices;
3960
3961                 if (netname.size() == 0)
3962                         continue;
3963
3964                 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3965                         cover("kernel.rtlil.sigspec.parse.const");
3966                         AST::get_line_num = sigspec_parse_get_dummy_line_num;
3967                         AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3968                         if (ast == NULL)
3969                                 return false;
3970                         sig.append(RTLIL::Const(ast->bits));
3971                         delete ast;
3972                         continue;
3973                 }
3974
3975                 if (module == NULL)
3976                         return false;
3977
3978                 cover("kernel.rtlil.sigspec.parse.net");
3979
3980                 if (netname[0] != '$' && netname[0] != '\\')
3981                         netname = "\\" + netname;
3982
3983                 if (module->wires_.count(netname) == 0) {
3984                         size_t indices_pos = netname.size()-1;
3985                         if (indices_pos > 2 && netname[indices_pos] == ']')
3986                         {
3987                                 indices_pos--;
3988                                 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3989                                 if (indices_pos > 0 && netname[indices_pos] == ':') {
3990                                         indices_pos--;
3991                                         while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3992                                 }
3993                                 if (indices_pos > 0 && netname[indices_pos] == '[') {
3994                                         indices = netname.substr(indices_pos);
3995                                         netname = netname.substr(0, indices_pos);
3996                                 }
3997                         }
3998                 }
3999
4000                 if (module->wires_.count(netname) == 0)
4001                         return false;
4002
4003                 RTLIL::Wire *wire = module->wires_.at(netname);
4004                 if (!indices.empty()) {
4005                         std::vector<std::string> index_tokens;
4006                         sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4007                         if (index_tokens.size() == 1) {
4008                                 cover("kernel.rtlil.sigspec.parse.bit_sel");
4009                                 int a = atoi(index_tokens.at(0).c_str());
4010                                 if (a < 0 || a >= wire->width)
4011                                         return false;
4012                                 sig.append(RTLIL::SigSpec(wire, a));
4013                         } else {
4014                                 cover("kernel.rtlil.sigspec.parse.part_sel");
4015                                 int a = atoi(index_tokens.at(0).c_str());
4016                                 int b = atoi(index_tokens.at(1).c_str());
4017                                 if (a > b) {
4018                                         int tmp = a;
4019                                         a = b, b = tmp;
4020                                 }
4021                                 if (a < 0 || a >= wire->width)
4022                                         return false;
4023                                 if (b < 0 || b >= wire->width)
4024                                         return false;
4025                                 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4026                         }
4027                 } else
4028                         sig.append(wire);
4029         }
4030
4031         return true;
4032 }
4033
4034 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4035 {
4036         if (str.empty() || str[0] != '@')
4037                 return parse(sig, module, str);
4038
4039         cover("kernel.rtlil.sigspec.parse.sel");
4040
4041         str = RTLIL::escape_id(str.substr(1));
4042         if (design->selection_vars.count(str) == 0)
4043                 return false;
4044
4045         sig = RTLIL::SigSpec();
4046         RTLIL::Selection &sel = design->selection_vars.at(str);
4047         for (auto &it : module->wires_)
4048                 if (sel.selected_member(module->name, it.first))
4049                         sig.append(it.second);
4050
4051         return true;
4052 }
4053
4054 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4055 {
4056         if (str == "0") {
4057                 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4058                 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4059                 return true;
4060         }
4061
4062         if (str == "~0") {
4063                 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4064                 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4065                 return true;
4066         }
4067
4068         if (lhs.chunks_.size() == 1) {
4069                 char *p = (char*)str.c_str(), *endptr;
4070                 long int val = strtol(p, &endptr, 10);
4071                 if (endptr && endptr != p && *endptr == 0) {
4072                         sig = RTLIL::SigSpec(val, lhs.width_);
4073                         cover("kernel.rtlil.sigspec.parse.rhs_dec");
4074                         return true;
4075                 }
4076         }
4077
4078         return parse(sig, module, str);
4079 }
4080
4081 RTLIL::CaseRule::~CaseRule()
4082 {
4083         for (auto it = switches.begin(); it != switches.end(); it++)
4084                 delete *it;
4085 }
4086
4087 bool RTLIL::CaseRule::empty() const
4088 {
4089         return actions.empty() && switches.empty();
4090 }
4091
4092 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4093 {
4094         RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4095         new_caserule->compare = compare;
4096         new_caserule->actions = actions;
4097         for (auto &it : switches)
4098                 new_caserule->switches.push_back(it->clone());
4099         return new_caserule;
4100 }
4101
4102 RTLIL::SwitchRule::~SwitchRule()
4103 {
4104         for (auto it = cases.begin(); it != cases.end(); it++)
4105                 delete *it;
4106 }
4107
4108 bool RTLIL::SwitchRule::empty() const
4109 {
4110         return cases.empty();
4111 }
4112
4113 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4114 {
4115         RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4116         new_switchrule->signal = signal;
4117         new_switchrule->attributes = attributes;
4118         for (auto &it : cases)
4119                 new_switchrule->cases.push_back(it->clone());
4120         return new_switchrule;
4121
4122 }
4123
4124 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4125 {
4126         RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4127         new_syncrule->type = type;
4128         new_syncrule->signal = signal;
4129         new_syncrule->actions = actions;
4130         return new_syncrule;
4131 }
4132
4133 RTLIL::Process::~Process()
4134 {
4135         for (auto it = syncs.begin(); it != syncs.end(); it++)
4136                 delete *it;
4137 }
4138
4139 RTLIL::Process *RTLIL::Process::clone() const
4140 {
4141         RTLIL::Process *new_proc = new RTLIL::Process;
4142
4143         new_proc->name = name;
4144         new_proc->attributes = attributes;
4145
4146         RTLIL::CaseRule *rc_ptr = root_case.clone();
4147         new_proc->root_case = *rc_ptr;
4148         rc_ptr->switches.clear();
4149         delete rc_ptr;
4150
4151         for (auto &it : syncs)
4152                 new_proc->syncs.push_back(it->clone());
4153
4154         return new_proc;
4155 }
4156
4157 #ifdef WITH_PYTHON
4158 RTLIL::Memory::~Memory()
4159 {
4160         RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4161 }
4162 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4163 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4164 {
4165         return &all_memorys;
4166 }
4167 #endif
4168 YOSYS_NAMESPACE_END