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kernel: fix DeleteWireWorker
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<char*> RTLIL::IdString::global_id_storage_;
33 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
34 #ifndef YOSYS_NO_IDS_REFCNT
35 std::vector<int> RTLIL::IdString::global_refcount_storage_;
36 std::vector<int> RTLIL::IdString::global_free_idx_list_;
37 #endif
38 #ifdef YOSYS_USE_STICKY_IDS
39 int RTLIL::IdString::last_created_idx_[8];
40 int RTLIL::IdString::last_created_idx_ptr_;
41 #endif
42
43 IdString RTLIL::ID::A;
44 IdString RTLIL::ID::B;
45 IdString RTLIL::ID::Y;
46 IdString RTLIL::ID::keep;
47 IdString RTLIL::ID::whitebox;
48 IdString RTLIL::ID::blackbox;
49 dict<std::string, std::string> RTLIL::constpad;
50
51 RTLIL::Const::Const()
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 }
55
56 RTLIL::Const::Const(std::string str)
57 {
58 flags = RTLIL::CONST_FLAG_STRING;
59 for (int i = str.size()-1; i >= 0; i--) {
60 unsigned char ch = str[i];
61 for (int j = 0; j < 8; j++) {
62 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
63 ch = ch >> 1;
64 }
65 }
66 }
67
68 RTLIL::Const::Const(int val, int width)
69 {
70 flags = RTLIL::CONST_FLAG_NONE;
71 for (int i = 0; i < width; i++) {
72 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
73 val = val >> 1;
74 }
75 }
76
77 RTLIL::Const::Const(RTLIL::State bit, int width)
78 {
79 flags = RTLIL::CONST_FLAG_NONE;
80 for (int i = 0; i < width; i++)
81 bits.push_back(bit);
82 }
83
84 RTLIL::Const::Const(const std::vector<bool> &bits)
85 {
86 flags = RTLIL::CONST_FLAG_NONE;
87 for (auto b : bits)
88 this->bits.push_back(b ? State::S1 : State::S0);
89 }
90
91 RTLIL::Const::Const(const RTLIL::Const &c)
92 {
93 flags = c.flags;
94 for (auto b : c.bits)
95 this->bits.push_back(b);
96 }
97
98 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
99 {
100 if (bits.size() != other.bits.size())
101 return bits.size() < other.bits.size();
102 for (size_t i = 0; i < bits.size(); i++)
103 if (bits[i] != other.bits[i])
104 return bits[i] < other.bits[i];
105 return false;
106 }
107
108 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
109 {
110 return bits == other.bits;
111 }
112
113 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
114 {
115 return bits != other.bits;
116 }
117
118 bool RTLIL::Const::as_bool() const
119 {
120 for (size_t i = 0; i < bits.size(); i++)
121 if (bits[i] == State::S1)
122 return true;
123 return false;
124 }
125
126 int RTLIL::Const::as_int(bool is_signed) const
127 {
128 int32_t ret = 0;
129 for (size_t i = 0; i < bits.size() && i < 32; i++)
130 if (bits[i] == State::S1)
131 ret |= 1 << i;
132 if (is_signed && bits.back() == State::S1)
133 for (size_t i = bits.size(); i < 32; i++)
134 ret |= 1 << i;
135 return ret;
136 }
137
138 std::string RTLIL::Const::as_string() const
139 {
140 std::string ret;
141 for (size_t i = bits.size(); i > 0; i--)
142 switch (bits[i-1]) {
143 case S0: ret += "0"; break;
144 case S1: ret += "1"; break;
145 case Sx: ret += "x"; break;
146 case Sz: ret += "z"; break;
147 case Sa: ret += "-"; break;
148 case Sm: ret += "m"; break;
149 }
150 return ret;
151 }
152
153 RTLIL::Const RTLIL::Const::from_string(std::string str)
154 {
155 Const c;
156 for (auto it = str.rbegin(); it != str.rend(); it++)
157 switch (*it) {
158 case '0': c.bits.push_back(State::S0); break;
159 case '1': c.bits.push_back(State::S1); break;
160 case 'x': c.bits.push_back(State::Sx); break;
161 case 'z': c.bits.push_back(State::Sz); break;
162 case 'm': c.bits.push_back(State::Sm); break;
163 default: c.bits.push_back(State::Sa);
164 }
165 return c;
166 }
167
168 std::string RTLIL::Const::decode_string() const
169 {
170 std::string string;
171 std::vector<char> string_chars;
172 for (int i = 0; i < int (bits.size()); i += 8) {
173 char ch = 0;
174 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
175 if (bits[i + j] == RTLIL::State::S1)
176 ch |= 1 << j;
177 if (ch != 0)
178 string_chars.push_back(ch);
179 }
180 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
181 string += string_chars[i];
182 return string;
183 }
184
185 bool RTLIL::Const::is_fully_zero() const
186 {
187 cover("kernel.rtlil.const.is_fully_zero");
188
189 for (auto bit : bits)
190 if (bit != RTLIL::State::S0)
191 return false;
192
193 return true;
194 }
195
196 bool RTLIL::Const::is_fully_ones() const
197 {
198 cover("kernel.rtlil.const.is_fully_ones");
199
200 for (auto bit : bits)
201 if (bit != RTLIL::State::S1)
202 return false;
203
204 return true;
205 }
206
207 bool RTLIL::Const::is_fully_def() const
208 {
209 cover("kernel.rtlil.const.is_fully_def");
210
211 for (auto bit : bits)
212 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
213 return false;
214
215 return true;
216 }
217
218 bool RTLIL::Const::is_fully_undef() const
219 {
220 cover("kernel.rtlil.const.is_fully_undef");
221
222 for (auto bit : bits)
223 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
224 return false;
225
226 return true;
227 }
228
229 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
230 {
231 if (value)
232 attributes[id] = RTLIL::Const(1);
233 else {
234 const auto it = attributes.find(id);
235 if (it != attributes.end())
236 attributes.erase(it);
237 }
238 }
239
240 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
241 {
242 const auto it = attributes.find(id);
243 if (it == attributes.end())
244 return false;
245 return it->second.as_bool();
246 }
247
248 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
249 {
250 string attrval;
251 for (auto &s : data) {
252 if (!attrval.empty())
253 attrval += "|";
254 attrval += s;
255 }
256 attributes[id] = RTLIL::Const(attrval);
257 }
258
259 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
260 {
261 pool<string> union_data = get_strpool_attribute(id);
262 union_data.insert(data.begin(), data.end());
263 if (!union_data.empty())
264 set_strpool_attribute(id, union_data);
265 }
266
267 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
268 {
269 pool<string> data;
270 if (attributes.count(id) != 0)
271 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
272 data.insert(s);
273 return data;
274 }
275
276 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
277 {
278 if (src.empty())
279 attributes.erase(ID(src));
280 else
281 attributes[ID(src)] = src;
282 }
283
284 std::string RTLIL::AttrObject::get_src_attribute() const
285 {
286 std::string src;
287 if (attributes.count(ID(src)))
288 src = attributes.at(ID(src)).decode_string();
289 return src;
290 }
291
292 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
293 {
294 if (full_selection)
295 return true;
296 if (selected_modules.count(mod_name) > 0)
297 return true;
298 if (selected_members.count(mod_name) > 0)
299 return true;
300 return false;
301 }
302
303 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
304 {
305 if (full_selection)
306 return true;
307 if (selected_modules.count(mod_name) > 0)
308 return true;
309 return false;
310 }
311
312 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
313 {
314 if (full_selection)
315 return true;
316 if (selected_modules.count(mod_name) > 0)
317 return true;
318 if (selected_members.count(mod_name) > 0)
319 if (selected_members.at(mod_name).count(memb_name) > 0)
320 return true;
321 return false;
322 }
323
324 void RTLIL::Selection::optimize(RTLIL::Design *design)
325 {
326 if (full_selection) {
327 selected_modules.clear();
328 selected_members.clear();
329 return;
330 }
331
332 std::vector<RTLIL::IdString> del_list, add_list;
333
334 del_list.clear();
335 for (auto mod_name : selected_modules) {
336 if (design->modules_.count(mod_name) == 0)
337 del_list.push_back(mod_name);
338 selected_members.erase(mod_name);
339 }
340 for (auto mod_name : del_list)
341 selected_modules.erase(mod_name);
342
343 del_list.clear();
344 for (auto &it : selected_members)
345 if (design->modules_.count(it.first) == 0)
346 del_list.push_back(it.first);
347 for (auto mod_name : del_list)
348 selected_members.erase(mod_name);
349
350 for (auto &it : selected_members) {
351 del_list.clear();
352 for (auto memb_name : it.second)
353 if (design->modules_[it.first]->count_id(memb_name) == 0)
354 del_list.push_back(memb_name);
355 for (auto memb_name : del_list)
356 it.second.erase(memb_name);
357 }
358
359 del_list.clear();
360 add_list.clear();
361 for (auto &it : selected_members)
362 if (it.second.size() == 0)
363 del_list.push_back(it.first);
364 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
365 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
366 add_list.push_back(it.first);
367 for (auto mod_name : del_list)
368 selected_members.erase(mod_name);
369 for (auto mod_name : add_list) {
370 selected_members.erase(mod_name);
371 selected_modules.insert(mod_name);
372 }
373
374 if (selected_modules.size() == design->modules_.size()) {
375 full_selection = true;
376 selected_modules.clear();
377 selected_members.clear();
378 }
379 }
380
381 RTLIL::Design::Design()
382 {
383 static unsigned int hashidx_count = 123456789;
384 hashidx_count = mkhash_xorshift(hashidx_count);
385 hashidx_ = hashidx_count;
386
387 refcount_modules_ = 0;
388 selection_stack.push_back(RTLIL::Selection());
389
390 #ifdef WITH_PYTHON
391 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
392 #endif
393 }
394
395 RTLIL::Design::~Design()
396 {
397 for (auto it = modules_.begin(); it != modules_.end(); ++it)
398 delete it->second;
399 for (auto n : verilog_packages)
400 delete n;
401 for (auto n : verilog_globals)
402 delete n;
403 #ifdef WITH_PYTHON
404 RTLIL::Design::get_all_designs()->erase(hashidx_);
405 #endif
406 }
407
408 #ifdef WITH_PYTHON
409 static std::map<unsigned int, RTLIL::Design*> all_designs;
410 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
411 {
412 return &all_designs;
413 }
414 #endif
415
416 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
417 {
418 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
419 }
420
421 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
422 {
423 return modules_.count(name) ? modules_.at(name) : NULL;
424 }
425
426 RTLIL::Module *RTLIL::Design::top_module()
427 {
428 RTLIL::Module *module = nullptr;
429 int module_count = 0;
430
431 for (auto mod : selected_modules()) {
432 if (mod->get_bool_attribute(ID(top)))
433 return mod;
434 module_count++;
435 module = mod;
436 }
437
438 return module_count == 1 ? module : nullptr;
439 }
440
441 void RTLIL::Design::add(RTLIL::Module *module)
442 {
443 log_assert(modules_.count(module->name) == 0);
444 log_assert(refcount_modules_ == 0);
445 modules_[module->name] = module;
446 module->design = this;
447
448 for (auto mon : monitors)
449 mon->notify_module_add(module);
450
451 if (yosys_xtrace) {
452 log("#X# New Module: %s\n", log_id(module));
453 log_backtrace("-X- ", yosys_xtrace-1);
454 }
455 }
456
457 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
458 {
459 log_assert(modules_.count(name) == 0);
460 log_assert(refcount_modules_ == 0);
461
462 RTLIL::Module *module = new RTLIL::Module;
463 modules_[name] = module;
464 module->design = this;
465 module->name = name;
466
467 for (auto mon : monitors)
468 mon->notify_module_add(module);
469
470 if (yosys_xtrace) {
471 log("#X# New Module: %s\n", log_id(module));
472 log_backtrace("-X- ", yosys_xtrace-1);
473 }
474
475 return module;
476 }
477
478 void RTLIL::Design::scratchpad_unset(std::string varname)
479 {
480 scratchpad.erase(varname);
481 }
482
483 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
484 {
485 scratchpad[varname] = stringf("%d", value);
486 }
487
488 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
489 {
490 scratchpad[varname] = value ? "true" : "false";
491 }
492
493 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
494 {
495 scratchpad[varname] = value;
496 }
497
498 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
499 {
500 if (scratchpad.count(varname) == 0)
501 return default_value;
502
503 std::string str = scratchpad.at(varname);
504
505 if (str == "0" || str == "false")
506 return 0;
507
508 if (str == "1" || str == "true")
509 return 1;
510
511 char *endptr = nullptr;
512 long int parsed_value = strtol(str.c_str(), &endptr, 10);
513 return *endptr ? default_value : parsed_value;
514 }
515
516 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
517 {
518 if (scratchpad.count(varname) == 0)
519 return default_value;
520
521 std::string str = scratchpad.at(varname);
522
523 if (str == "0" || str == "false")
524 return false;
525
526 if (str == "1" || str == "true")
527 return true;
528
529 return default_value;
530 }
531
532 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
533 {
534 if (scratchpad.count(varname) == 0)
535 return default_value;
536 return scratchpad.at(varname);
537 }
538
539 void RTLIL::Design::remove(RTLIL::Module *module)
540 {
541 for (auto mon : monitors)
542 mon->notify_module_del(module);
543
544 if (yosys_xtrace) {
545 log("#X# Remove Module: %s\n", log_id(module));
546 log_backtrace("-X- ", yosys_xtrace-1);
547 }
548
549 log_assert(modules_.at(module->name) == module);
550 modules_.erase(module->name);
551 delete module;
552 }
553
554 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
555 {
556 modules_.erase(module->name);
557 module->name = new_name;
558 add(module);
559 }
560
561 void RTLIL::Design::sort()
562 {
563 scratchpad.sort();
564 modules_.sort(sort_by_id_str());
565 for (auto &it : modules_)
566 it.second->sort();
567 }
568
569 void RTLIL::Design::check()
570 {
571 #ifndef NDEBUG
572 for (auto &it : modules_) {
573 log_assert(this == it.second->design);
574 log_assert(it.first == it.second->name);
575 log_assert(!it.first.empty());
576 it.second->check();
577 }
578 #endif
579 }
580
581 void RTLIL::Design::optimize()
582 {
583 for (auto &it : modules_)
584 it.second->optimize();
585 for (auto &it : selection_stack)
586 it.optimize(this);
587 for (auto &it : selection_vars)
588 it.second.optimize(this);
589 }
590
591 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
592 {
593 if (!selected_active_module.empty() && mod_name != selected_active_module)
594 return false;
595 if (selection_stack.size() == 0)
596 return true;
597 return selection_stack.back().selected_module(mod_name);
598 }
599
600 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
601 {
602 if (!selected_active_module.empty() && mod_name != selected_active_module)
603 return false;
604 if (selection_stack.size() == 0)
605 return true;
606 return selection_stack.back().selected_whole_module(mod_name);
607 }
608
609 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
610 {
611 if (!selected_active_module.empty() && mod_name != selected_active_module)
612 return false;
613 if (selection_stack.size() == 0)
614 return true;
615 return selection_stack.back().selected_member(mod_name, memb_name);
616 }
617
618 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
619 {
620 return selected_module(mod->name);
621 }
622
623 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
624 {
625 return selected_whole_module(mod->name);
626 }
627
628 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
629 {
630 std::vector<RTLIL::Module*> result;
631 result.reserve(modules_.size());
632 for (auto &it : modules_)
633 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
634 result.push_back(it.second);
635 return result;
636 }
637
638 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
639 {
640 std::vector<RTLIL::Module*> result;
641 result.reserve(modules_.size());
642 for (auto &it : modules_)
643 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
644 result.push_back(it.second);
645 return result;
646 }
647
648 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
649 {
650 std::vector<RTLIL::Module*> result;
651 result.reserve(modules_.size());
652 for (auto &it : modules_)
653 if (it.second->get_blackbox_attribute())
654 continue;
655 else if (selected_whole_module(it.first))
656 result.push_back(it.second);
657 else if (selected_module(it.first))
658 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
659 return result;
660 }
661
662 RTLIL::Module::Module()
663 {
664 static unsigned int hashidx_count = 123456789;
665 hashidx_count = mkhash_xorshift(hashidx_count);
666 hashidx_ = hashidx_count;
667
668 design = nullptr;
669 refcount_wires_ = 0;
670 refcount_cells_ = 0;
671
672 #ifdef WITH_PYTHON
673 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
674 #endif
675 }
676
677 RTLIL::Module::~Module()
678 {
679 for (auto it = wires_.begin(); it != wires_.end(); ++it)
680 delete it->second;
681 for (auto it = memories.begin(); it != memories.end(); ++it)
682 delete it->second;
683 for (auto it = cells_.begin(); it != cells_.end(); ++it)
684 delete it->second;
685 for (auto it = processes.begin(); it != processes.end(); ++it)
686 delete it->second;
687 #ifdef WITH_PYTHON
688 RTLIL::Module::get_all_modules()->erase(hashidx_);
689 #endif
690 }
691
692 #ifdef WITH_PYTHON
693 static std::map<unsigned int, RTLIL::Module*> all_modules;
694 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
695 {
696 return &all_modules;
697 }
698 #endif
699
700 void RTLIL::Module::makeblackbox()
701 {
702 pool<RTLIL::Wire*> delwires;
703
704 for (auto it = wires_.begin(); it != wires_.end(); ++it)
705 if (!it->second->port_input && !it->second->port_output)
706 delwires.insert(it->second);
707
708 for (auto it = memories.begin(); it != memories.end(); ++it)
709 delete it->second;
710 memories.clear();
711
712 for (auto it = cells_.begin(); it != cells_.end(); ++it)
713 delete it->second;
714 cells_.clear();
715
716 for (auto it = processes.begin(); it != processes.end(); ++it)
717 delete it->second;
718 processes.clear();
719
720 remove(delwires);
721 set_bool_attribute(ID::blackbox);
722 }
723
724 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
725 {
726 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
727 }
728
729 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
730 {
731 if (mayfail)
732 return RTLIL::IdString();
733 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
734 }
735
736
737 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
738 {
739 if (mayfail)
740 return RTLIL::IdString();
741 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
742 }
743
744 size_t RTLIL::Module::count_id(RTLIL::IdString id)
745 {
746 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
747 }
748
749 #ifndef NDEBUG
750 namespace {
751 struct InternalCellChecker
752 {
753 RTLIL::Module *module;
754 RTLIL::Cell *cell;
755 pool<RTLIL::IdString> expected_params, expected_ports;
756
757 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
758
759 void error(int linenr)
760 {
761 std::stringstream buf;
762 ILANG_BACKEND::dump_cell(buf, " ", cell);
763
764 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
765 module ? module->name.c_str() : "", module ? "." : "",
766 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
767 }
768
769 int param(RTLIL::IdString name)
770 {
771 if (cell->parameters.count(name) == 0)
772 error(__LINE__);
773 expected_params.insert(name);
774 return cell->parameters.at(name).as_int();
775 }
776
777 int param_bool(RTLIL::IdString name)
778 {
779 int v = param(name);
780 if (cell->parameters.at(name).bits.size() > 32)
781 error(__LINE__);
782 if (v != 0 && v != 1)
783 error(__LINE__);
784 return v;
785 }
786
787 int param_bool(RTLIL::IdString name, bool expected)
788 {
789 int v = param_bool(name);
790 if (v != expected)
791 error(__LINE__);
792 return v;
793 }
794
795 void param_bits(RTLIL::IdString name, int width)
796 {
797 param(name);
798 if (int(cell->parameters.at(name).bits.size()) != width)
799 error(__LINE__);
800 }
801
802 void port(RTLIL::IdString name, int width)
803 {
804 if (!cell->hasPort(name))
805 error(__LINE__);
806 if (cell->getPort(name).size() != width)
807 error(__LINE__);
808 expected_ports.insert(name);
809 }
810
811 void check_expected(bool check_matched_sign = true)
812 {
813 for (auto &para : cell->parameters)
814 if (expected_params.count(para.first) == 0)
815 error(__LINE__);
816 for (auto &conn : cell->connections())
817 if (expected_ports.count(conn.first) == 0)
818 error(__LINE__);
819
820 if (expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) && check_matched_sign) {
821 bool a_is_signed = param(ID(A_SIGNED)) != 0;
822 bool b_is_signed = param(ID(B_SIGNED)) != 0;
823 if (a_is_signed != b_is_signed)
824 error(__LINE__);
825 }
826 }
827
828 void check_gate(const char *ports)
829 {
830 if (cell->parameters.size() != 0)
831 error(__LINE__);
832
833 for (const char *p = ports; *p; p++) {
834 char portname[3] = { '\\', *p, 0 };
835 if (!cell->hasPort(portname))
836 error(__LINE__);
837 if (cell->getPort(portname).size() != 1)
838 error(__LINE__);
839 }
840
841 for (auto &conn : cell->connections()) {
842 if (conn.first.size() != 2 || conn.first[0] != '\\')
843 error(__LINE__);
844 if (strchr(ports, conn.first[1]) == NULL)
845 error(__LINE__);
846 }
847 }
848
849 void check()
850 {
851 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
852 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
853 return;
854
855 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
856 param_bool(ID(A_SIGNED));
857 port(ID::A, param(ID(A_WIDTH)));
858 port(ID::Y, param(ID(Y_WIDTH)));
859 check_expected();
860 return;
861 }
862
863 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
864 param_bool(ID(A_SIGNED));
865 param_bool(ID(B_SIGNED));
866 port(ID::A, param(ID(A_WIDTH)));
867 port(ID::B, param(ID(B_WIDTH)));
868 port(ID::Y, param(ID(Y_WIDTH)));
869 check_expected();
870 return;
871 }
872
873 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
874 param_bool(ID(A_SIGNED));
875 port(ID::A, param(ID(A_WIDTH)));
876 port(ID::Y, param(ID(Y_WIDTH)));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
882 param_bool(ID(A_SIGNED));
883 param_bool(ID(B_SIGNED), /*expected=*/false);
884 port(ID::A, param(ID(A_WIDTH)));
885 port(ID::B, param(ID(B_WIDTH)));
886 port(ID::Y, param(ID(Y_WIDTH)));
887 check_expected(/*check_matched_sign=*/false);
888 return;
889 }
890
891 if (cell->type.in(ID($shift), ID($shiftx))) {
892 param_bool(ID(A_SIGNED));
893 param_bool(ID(B_SIGNED));
894 port(ID::A, param(ID(A_WIDTH)));
895 port(ID::B, param(ID(B_WIDTH)));
896 port(ID::Y, param(ID(Y_WIDTH)));
897 check_expected(/*check_matched_sign=*/false);
898 return;
899 }
900
901 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
902 param_bool(ID(A_SIGNED));
903 param_bool(ID(B_SIGNED));
904 port(ID::A, param(ID(A_WIDTH)));
905 port(ID::B, param(ID(B_WIDTH)));
906 port(ID::Y, param(ID(Y_WIDTH)));
907 check_expected();
908 return;
909 }
910
911 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
912 param_bool(ID(A_SIGNED));
913 param_bool(ID(B_SIGNED));
914 port(ID::A, param(ID(A_WIDTH)));
915 port(ID::B, param(ID(B_WIDTH)));
916 port(ID::Y, param(ID(Y_WIDTH)));
917 check_expected(cell->type != ID($pow));
918 return;
919 }
920
921 if (cell->type == ID($fa)) {
922 port(ID::A, param(ID(WIDTH)));
923 port(ID::B, param(ID(WIDTH)));
924 port(ID(C), param(ID(WIDTH)));
925 port(ID(X), param(ID(WIDTH)));
926 port(ID::Y, param(ID(WIDTH)));
927 check_expected();
928 return;
929 }
930
931 if (cell->type == ID($lcu)) {
932 port(ID(P), param(ID(WIDTH)));
933 port(ID(G), param(ID(WIDTH)));
934 port(ID(CI), 1);
935 port(ID(CO), param(ID(WIDTH)));
936 check_expected();
937 return;
938 }
939
940 if (cell->type == ID($alu)) {
941 param_bool(ID(A_SIGNED));
942 param_bool(ID(B_SIGNED));
943 port(ID::A, param(ID(A_WIDTH)));
944 port(ID::B, param(ID(B_WIDTH)));
945 port(ID(CI), 1);
946 port(ID(BI), 1);
947 port(ID(X), param(ID(Y_WIDTH)));
948 port(ID::Y, param(ID(Y_WIDTH)));
949 port(ID(CO), param(ID(Y_WIDTH)));
950 check_expected();
951 return;
952 }
953
954 if (cell->type == ID($macc)) {
955 param(ID(CONFIG));
956 param(ID(CONFIG_WIDTH));
957 port(ID::A, param(ID(A_WIDTH)));
958 port(ID::B, param(ID(B_WIDTH)));
959 port(ID::Y, param(ID(Y_WIDTH)));
960 check_expected();
961 Macc().from_cell(cell);
962 return;
963 }
964
965 if (cell->type == ID($logic_not)) {
966 param_bool(ID(A_SIGNED));
967 port(ID::A, param(ID(A_WIDTH)));
968 port(ID::Y, param(ID(Y_WIDTH)));
969 check_expected();
970 return;
971 }
972
973 if (cell->type.in(ID($logic_and), ID($logic_or))) {
974 param_bool(ID(A_SIGNED));
975 param_bool(ID(B_SIGNED));
976 port(ID::A, param(ID(A_WIDTH)));
977 port(ID::B, param(ID(B_WIDTH)));
978 port(ID::Y, param(ID(Y_WIDTH)));
979 check_expected(/*check_matched_sign=*/false);
980 return;
981 }
982
983 if (cell->type == ID($slice)) {
984 param(ID(OFFSET));
985 port(ID::A, param(ID(A_WIDTH)));
986 port(ID::Y, param(ID(Y_WIDTH)));
987 if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
988 error(__LINE__);
989 check_expected();
990 return;
991 }
992
993 if (cell->type == ID($concat)) {
994 port(ID::A, param(ID(A_WIDTH)));
995 port(ID::B, param(ID(B_WIDTH)));
996 port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
997 check_expected();
998 return;
999 }
1000
1001 if (cell->type == ID($mux)) {
1002 port(ID::A, param(ID(WIDTH)));
1003 port(ID::B, param(ID(WIDTH)));
1004 port(ID(S), 1);
1005 port(ID::Y, param(ID(WIDTH)));
1006 check_expected();
1007 return;
1008 }
1009
1010 if (cell->type == ID($pmux)) {
1011 port(ID::A, param(ID(WIDTH)));
1012 port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
1013 port(ID(S), param(ID(S_WIDTH)));
1014 port(ID::Y, param(ID(WIDTH)));
1015 check_expected();
1016 return;
1017 }
1018
1019 if (cell->type == ID($lut)) {
1020 param(ID(LUT));
1021 port(ID::A, param(ID(WIDTH)));
1022 port(ID::Y, 1);
1023 check_expected();
1024 return;
1025 }
1026
1027 if (cell->type == ID($sop)) {
1028 param(ID(DEPTH));
1029 param(ID(TABLE));
1030 port(ID::A, param(ID(WIDTH)));
1031 port(ID::Y, 1);
1032 check_expected();
1033 return;
1034 }
1035
1036 if (cell->type == ID($sr)) {
1037 param_bool(ID(SET_POLARITY));
1038 param_bool(ID(CLR_POLARITY));
1039 port(ID(SET), param(ID(WIDTH)));
1040 port(ID(CLR), param(ID(WIDTH)));
1041 port(ID(Q), param(ID(WIDTH)));
1042 check_expected();
1043 return;
1044 }
1045
1046 if (cell->type == ID($ff)) {
1047 port(ID(D), param(ID(WIDTH)));
1048 port(ID(Q), param(ID(WIDTH)));
1049 check_expected();
1050 return;
1051 }
1052
1053 if (cell->type == ID($dff)) {
1054 param_bool(ID(CLK_POLARITY));
1055 port(ID(CLK), 1);
1056 port(ID(D), param(ID(WIDTH)));
1057 port(ID(Q), param(ID(WIDTH)));
1058 check_expected();
1059 return;
1060 }
1061
1062 if (cell->type == ID($dffe)) {
1063 param_bool(ID(CLK_POLARITY));
1064 param_bool(ID(EN_POLARITY));
1065 port(ID(CLK), 1);
1066 port(ID(EN), 1);
1067 port(ID(D), param(ID(WIDTH)));
1068 port(ID(Q), param(ID(WIDTH)));
1069 check_expected();
1070 return;
1071 }
1072
1073 if (cell->type == ID($dffsr)) {
1074 param_bool(ID(CLK_POLARITY));
1075 param_bool(ID(SET_POLARITY));
1076 param_bool(ID(CLR_POLARITY));
1077 port(ID(CLK), 1);
1078 port(ID(SET), param(ID(WIDTH)));
1079 port(ID(CLR), param(ID(WIDTH)));
1080 port(ID(D), param(ID(WIDTH)));
1081 port(ID(Q), param(ID(WIDTH)));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == ID($adff)) {
1087 param_bool(ID(CLK_POLARITY));
1088 param_bool(ID(ARST_POLARITY));
1089 param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
1090 port(ID(CLK), 1);
1091 port(ID(ARST), 1);
1092 port(ID(D), param(ID(WIDTH)));
1093 port(ID(Q), param(ID(WIDTH)));
1094 check_expected();
1095 return;
1096 }
1097
1098 if (cell->type == ID($dlatch)) {
1099 param_bool(ID(EN_POLARITY));
1100 port(ID(EN), 1);
1101 port(ID(D), param(ID(WIDTH)));
1102 port(ID(Q), param(ID(WIDTH)));
1103 check_expected();
1104 return;
1105 }
1106
1107 if (cell->type == ID($dlatchsr)) {
1108 param_bool(ID(EN_POLARITY));
1109 param_bool(ID(SET_POLARITY));
1110 param_bool(ID(CLR_POLARITY));
1111 port(ID(EN), 1);
1112 port(ID(SET), param(ID(WIDTH)));
1113 port(ID(CLR), param(ID(WIDTH)));
1114 port(ID(D), param(ID(WIDTH)));
1115 port(ID(Q), param(ID(WIDTH)));
1116 check_expected();
1117 return;
1118 }
1119
1120 if (cell->type == ID($fsm)) {
1121 param(ID(NAME));
1122 param_bool(ID(CLK_POLARITY));
1123 param_bool(ID(ARST_POLARITY));
1124 param(ID(STATE_BITS));
1125 param(ID(STATE_NUM));
1126 param(ID(STATE_NUM_LOG2));
1127 param(ID(STATE_RST));
1128 param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
1129 param(ID(TRANS_NUM));
1130 param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
1131 port(ID(CLK), 1);
1132 port(ID(ARST), 1);
1133 port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
1134 port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
1135 check_expected();
1136 return;
1137 }
1138
1139 if (cell->type == ID($memrd)) {
1140 param(ID(MEMID));
1141 param_bool(ID(CLK_ENABLE));
1142 param_bool(ID(CLK_POLARITY));
1143 param_bool(ID(TRANSPARENT));
1144 port(ID(CLK), 1);
1145 port(ID(EN), 1);
1146 port(ID(ADDR), param(ID(ABITS)));
1147 port(ID(DATA), param(ID(WIDTH)));
1148 check_expected();
1149 return;
1150 }
1151
1152 if (cell->type == ID($memwr)) {
1153 param(ID(MEMID));
1154 param_bool(ID(CLK_ENABLE));
1155 param_bool(ID(CLK_POLARITY));
1156 param(ID(PRIORITY));
1157 port(ID(CLK), 1);
1158 port(ID(EN), param(ID(WIDTH)));
1159 port(ID(ADDR), param(ID(ABITS)));
1160 port(ID(DATA), param(ID(WIDTH)));
1161 check_expected();
1162 return;
1163 }
1164
1165 if (cell->type == ID($meminit)) {
1166 param(ID(MEMID));
1167 param(ID(PRIORITY));
1168 port(ID(ADDR), param(ID(ABITS)));
1169 port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type == ID($mem)) {
1175 param(ID(MEMID));
1176 param(ID(SIZE));
1177 param(ID(OFFSET));
1178 param(ID(INIT));
1179 param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
1180 param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
1181 param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
1182 param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
1183 param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
1184 port(ID(RD_CLK), param(ID(RD_PORTS)));
1185 port(ID(RD_EN), param(ID(RD_PORTS)));
1186 port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
1187 port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
1188 port(ID(WR_CLK), param(ID(WR_PORTS)));
1189 port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1190 port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
1191 port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1192 check_expected();
1193 return;
1194 }
1195
1196 if (cell->type == ID($tribuf)) {
1197 port(ID::A, param(ID(WIDTH)));
1198 port(ID::Y, param(ID(WIDTH)));
1199 port(ID(EN), 1);
1200 check_expected();
1201 return;
1202 }
1203
1204 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1205 port(ID::A, 1);
1206 port(ID(EN), 1);
1207 check_expected();
1208 return;
1209 }
1210
1211 if (cell->type == ID($initstate)) {
1212 port(ID::Y, 1);
1213 check_expected();
1214 return;
1215 }
1216
1217 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1218 port(ID::Y, param(ID(WIDTH)));
1219 check_expected();
1220 return;
1221 }
1222
1223 if (cell->type == ID($equiv)) {
1224 port(ID::A, 1);
1225 port(ID::B, 1);
1226 port(ID::Y, 1);
1227 check_expected();
1228 return;
1229 }
1230
1231 if (cell->type.in(ID($specify2), ID($specify3))) {
1232 param_bool(ID(FULL));
1233 param_bool(ID(SRC_DST_PEN));
1234 param_bool(ID(SRC_DST_POL));
1235 param(ID(T_RISE_MIN));
1236 param(ID(T_RISE_TYP));
1237 param(ID(T_RISE_MAX));
1238 param(ID(T_FALL_MIN));
1239 param(ID(T_FALL_TYP));
1240 param(ID(T_FALL_MAX));
1241 port(ID(EN), 1);
1242 port(ID(SRC), param(ID(SRC_WIDTH)));
1243 port(ID(DST), param(ID(DST_WIDTH)));
1244 if (cell->type == ID($specify3)) {
1245 param_bool(ID(EDGE_EN));
1246 param_bool(ID(EDGE_POL));
1247 param_bool(ID(DAT_DST_PEN));
1248 param_bool(ID(DAT_DST_POL));
1249 port(ID(DAT), param(ID(DST_WIDTH)));
1250 }
1251 check_expected();
1252 return;
1253 }
1254
1255 if (cell->type == ID($specrule)) {
1256 param(ID(TYPE));
1257 param_bool(ID(SRC_PEN));
1258 param_bool(ID(SRC_POL));
1259 param_bool(ID(DST_PEN));
1260 param_bool(ID(DST_POL));
1261 param(ID(T_LIMIT_MIN));
1262 param(ID(T_LIMIT_TYP));
1263 param(ID(T_LIMIT_MAX));
1264 param(ID(T_LIMIT2_MIN));
1265 param(ID(T_LIMIT2_TYP));
1266 param(ID(T_LIMIT2_MAX));
1267 port(ID(SRC_EN), 1);
1268 port(ID(DST_EN), 1);
1269 port(ID(SRC), param(ID(SRC_WIDTH)));
1270 port(ID(DST), param(ID(DST_WIDTH)));
1271 check_expected();
1272 return;
1273 }
1274
1275 if (cell->type == ID($_BUF_)) { check_gate("AY"); return; }
1276 if (cell->type == ID($_NOT_)) { check_gate("AY"); return; }
1277 if (cell->type == ID($_AND_)) { check_gate("ABY"); return; }
1278 if (cell->type == ID($_NAND_)) { check_gate("ABY"); return; }
1279 if (cell->type == ID($_OR_)) { check_gate("ABY"); return; }
1280 if (cell->type == ID($_NOR_)) { check_gate("ABY"); return; }
1281 if (cell->type == ID($_XOR_)) { check_gate("ABY"); return; }
1282 if (cell->type == ID($_XNOR_)) { check_gate("ABY"); return; }
1283 if (cell->type == ID($_ANDNOT_)) { check_gate("ABY"); return; }
1284 if (cell->type == ID($_ORNOT_)) { check_gate("ABY"); return; }
1285 if (cell->type == ID($_MUX_)) { check_gate("ABSY"); return; }
1286 if (cell->type == ID($_NMUX_)) { check_gate("ABSY"); return; }
1287 if (cell->type == ID($_AOI3_)) { check_gate("ABCY"); return; }
1288 if (cell->type == ID($_OAI3_)) { check_gate("ABCY"); return; }
1289 if (cell->type == ID($_AOI4_)) { check_gate("ABCDY"); return; }
1290 if (cell->type == ID($_OAI4_)) { check_gate("ABCDY"); return; }
1291
1292 if (cell->type == ID($_TBUF_)) { check_gate("AYE"); return; }
1293
1294 if (cell->type == ID($_MUX4_)) { check_gate("ABCDSTY"); return; }
1295 if (cell->type == ID($_MUX8_)) { check_gate("ABCDEFGHSTUY"); return; }
1296 if (cell->type == ID($_MUX16_)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1297
1298 if (cell->type == ID($_SR_NN_)) { check_gate("SRQ"); return; }
1299 if (cell->type == ID($_SR_NP_)) { check_gate("SRQ"); return; }
1300 if (cell->type == ID($_SR_PN_)) { check_gate("SRQ"); return; }
1301 if (cell->type == ID($_SR_PP_)) { check_gate("SRQ"); return; }
1302
1303 if (cell->type == ID($_FF_)) { check_gate("DQ"); return; }
1304 if (cell->type == ID($_DFF_N_)) { check_gate("DQC"); return; }
1305 if (cell->type == ID($_DFF_P_)) { check_gate("DQC"); return; }
1306
1307 if (cell->type == ID($_DFFE_NN_)) { check_gate("DQCE"); return; }
1308 if (cell->type == ID($_DFFE_NP_)) { check_gate("DQCE"); return; }
1309 if (cell->type == ID($_DFFE_PN_)) { check_gate("DQCE"); return; }
1310 if (cell->type == ID($_DFFE_PP_)) { check_gate("DQCE"); return; }
1311
1312 if (cell->type == ID($_DFF_NN0_)) { check_gate("DQCR"); return; }
1313 if (cell->type == ID($_DFF_NN1_)) { check_gate("DQCR"); return; }
1314 if (cell->type == ID($_DFF_NP0_)) { check_gate("DQCR"); return; }
1315 if (cell->type == ID($_DFF_NP1_)) { check_gate("DQCR"); return; }
1316 if (cell->type == ID($_DFF_PN0_)) { check_gate("DQCR"); return; }
1317 if (cell->type == ID($_DFF_PN1_)) { check_gate("DQCR"); return; }
1318 if (cell->type == ID($_DFF_PP0_)) { check_gate("DQCR"); return; }
1319 if (cell->type == ID($_DFF_PP1_)) { check_gate("DQCR"); return; }
1320
1321 if (cell->type == ID($_DFFSR_NNN_)) { check_gate("CSRDQ"); return; }
1322 if (cell->type == ID($_DFFSR_NNP_)) { check_gate("CSRDQ"); return; }
1323 if (cell->type == ID($_DFFSR_NPN_)) { check_gate("CSRDQ"); return; }
1324 if (cell->type == ID($_DFFSR_NPP_)) { check_gate("CSRDQ"); return; }
1325 if (cell->type == ID($_DFFSR_PNN_)) { check_gate("CSRDQ"); return; }
1326 if (cell->type == ID($_DFFSR_PNP_)) { check_gate("CSRDQ"); return; }
1327 if (cell->type == ID($_DFFSR_PPN_)) { check_gate("CSRDQ"); return; }
1328 if (cell->type == ID($_DFFSR_PPP_)) { check_gate("CSRDQ"); return; }
1329
1330 if (cell->type == ID($_DLATCH_N_)) { check_gate("EDQ"); return; }
1331 if (cell->type == ID($_DLATCH_P_)) { check_gate("EDQ"); return; }
1332
1333 if (cell->type == ID($_DLATCHSR_NNN_)) { check_gate("ESRDQ"); return; }
1334 if (cell->type == ID($_DLATCHSR_NNP_)) { check_gate("ESRDQ"); return; }
1335 if (cell->type == ID($_DLATCHSR_NPN_)) { check_gate("ESRDQ"); return; }
1336 if (cell->type == ID($_DLATCHSR_NPP_)) { check_gate("ESRDQ"); return; }
1337 if (cell->type == ID($_DLATCHSR_PNN_)) { check_gate("ESRDQ"); return; }
1338 if (cell->type == ID($_DLATCHSR_PNP_)) { check_gate("ESRDQ"); return; }
1339 if (cell->type == ID($_DLATCHSR_PPN_)) { check_gate("ESRDQ"); return; }
1340 if (cell->type == ID($_DLATCHSR_PPP_)) { check_gate("ESRDQ"); return; }
1341
1342 error(__LINE__);
1343 }
1344 };
1345 }
1346 #endif
1347
1348 void RTLIL::Module::sort()
1349 {
1350 wires_.sort(sort_by_id_str());
1351 cells_.sort(sort_by_id_str());
1352 avail_parameters.sort(sort_by_id_str());
1353 memories.sort(sort_by_id_str());
1354 processes.sort(sort_by_id_str());
1355 for (auto &it : cells_)
1356 it.second->sort();
1357 for (auto &it : wires_)
1358 it.second->attributes.sort(sort_by_id_str());
1359 for (auto &it : memories)
1360 it.second->attributes.sort(sort_by_id_str());
1361 }
1362
1363 void RTLIL::Module::check()
1364 {
1365 #ifndef NDEBUG
1366 std::vector<bool> ports_declared;
1367 for (auto &it : wires_) {
1368 log_assert(this == it.second->module);
1369 log_assert(it.first == it.second->name);
1370 log_assert(!it.first.empty());
1371 log_assert(it.second->width >= 0);
1372 log_assert(it.second->port_id >= 0);
1373 for (auto &it2 : it.second->attributes)
1374 log_assert(!it2.first.empty());
1375 if (it.second->port_id) {
1376 log_assert(GetSize(ports) >= it.second->port_id);
1377 log_assert(ports.at(it.second->port_id-1) == it.first);
1378 log_assert(it.second->port_input || it.second->port_output);
1379 if (GetSize(ports_declared) < it.second->port_id)
1380 ports_declared.resize(it.second->port_id);
1381 log_assert(ports_declared[it.second->port_id-1] == false);
1382 ports_declared[it.second->port_id-1] = true;
1383 } else
1384 log_assert(!it.second->port_input && !it.second->port_output);
1385 }
1386 for (auto port_declared : ports_declared)
1387 log_assert(port_declared == true);
1388 log_assert(GetSize(ports) == GetSize(ports_declared));
1389
1390 for (auto &it : memories) {
1391 log_assert(it.first == it.second->name);
1392 log_assert(!it.first.empty());
1393 log_assert(it.second->width >= 0);
1394 log_assert(it.second->size >= 0);
1395 for (auto &it2 : it.second->attributes)
1396 log_assert(!it2.first.empty());
1397 }
1398
1399 for (auto &it : cells_) {
1400 log_assert(this == it.second->module);
1401 log_assert(it.first == it.second->name);
1402 log_assert(!it.first.empty());
1403 log_assert(!it.second->type.empty());
1404 for (auto &it2 : it.second->connections()) {
1405 log_assert(!it2.first.empty());
1406 it2.second.check();
1407 }
1408 for (auto &it2 : it.second->attributes)
1409 log_assert(!it2.first.empty());
1410 for (auto &it2 : it.second->parameters)
1411 log_assert(!it2.first.empty());
1412 InternalCellChecker checker(this, it.second);
1413 checker.check();
1414 }
1415
1416 for (auto &it : processes) {
1417 log_assert(it.first == it.second->name);
1418 log_assert(!it.first.empty());
1419 log_assert(it.second->root_case.compare.empty());
1420 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1421 for (size_t i = 0; i < all_cases.size(); i++) {
1422 for (auto &switch_it : all_cases[i]->switches) {
1423 for (auto &case_it : switch_it->cases) {
1424 for (auto &compare_it : case_it->compare) {
1425 log_assert(switch_it->signal.size() == compare_it.size());
1426 }
1427 all_cases.push_back(case_it);
1428 }
1429 }
1430 }
1431 for (auto &sync_it : it.second->syncs) {
1432 switch (sync_it->type) {
1433 case SyncType::ST0:
1434 case SyncType::ST1:
1435 case SyncType::STp:
1436 case SyncType::STn:
1437 case SyncType::STe:
1438 log_assert(!sync_it->signal.empty());
1439 break;
1440 case SyncType::STa:
1441 case SyncType::STg:
1442 case SyncType::STi:
1443 log_assert(sync_it->signal.empty());
1444 break;
1445 }
1446 }
1447 }
1448
1449 for (auto &it : connections_) {
1450 log_assert(it.first.size() == it.second.size());
1451 log_assert(!it.first.has_const());
1452 it.first.check();
1453 it.second.check();
1454 }
1455
1456 for (auto &it : attributes)
1457 log_assert(!it.first.empty());
1458 #endif
1459 }
1460
1461 void RTLIL::Module::optimize()
1462 {
1463 }
1464
1465 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1466 {
1467 log_assert(new_mod->refcount_wires_ == 0);
1468 log_assert(new_mod->refcount_cells_ == 0);
1469
1470 new_mod->avail_parameters = avail_parameters;
1471
1472 for (auto &conn : connections_)
1473 new_mod->connect(conn);
1474
1475 for (auto &attr : attributes)
1476 new_mod->attributes[attr.first] = attr.second;
1477
1478 for (auto &it : wires_)
1479 new_mod->addWire(it.first, it.second);
1480
1481 for (auto &it : memories)
1482 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1483
1484 for (auto &it : cells_)
1485 new_mod->addCell(it.first, it.second);
1486
1487 for (auto &it : processes)
1488 new_mod->processes[it.first] = it.second->clone();
1489
1490 struct RewriteSigSpecWorker
1491 {
1492 RTLIL::Module *mod;
1493 void operator()(RTLIL::SigSpec &sig)
1494 {
1495 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1496 for (auto &c : chunks)
1497 if (c.wire != NULL)
1498 c.wire = mod->wires_.at(c.wire->name);
1499 sig = chunks;
1500 }
1501 };
1502
1503 RewriteSigSpecWorker rewriteSigSpecWorker;
1504 rewriteSigSpecWorker.mod = new_mod;
1505 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1506 new_mod->fixup_ports();
1507 }
1508
1509 RTLIL::Module *RTLIL::Module::clone() const
1510 {
1511 RTLIL::Module *new_mod = new RTLIL::Module;
1512 new_mod->name = name;
1513 cloneInto(new_mod);
1514 return new_mod;
1515 }
1516
1517 bool RTLIL::Module::has_memories() const
1518 {
1519 return !memories.empty();
1520 }
1521
1522 bool RTLIL::Module::has_processes() const
1523 {
1524 return !processes.empty();
1525 }
1526
1527 bool RTLIL::Module::has_memories_warn() const
1528 {
1529 if (!memories.empty())
1530 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1531 return !memories.empty();
1532 }
1533
1534 bool RTLIL::Module::has_processes_warn() const
1535 {
1536 if (!processes.empty())
1537 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1538 return !processes.empty();
1539 }
1540
1541 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1542 {
1543 std::vector<RTLIL::Wire*> result;
1544 result.reserve(wires_.size());
1545 for (auto &it : wires_)
1546 if (design->selected(this, it.second))
1547 result.push_back(it.second);
1548 return result;
1549 }
1550
1551 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1552 {
1553 std::vector<RTLIL::Cell*> result;
1554 result.reserve(cells_.size());
1555 for (auto &it : cells_)
1556 if (design->selected(this, it.second))
1557 result.push_back(it.second);
1558 return result;
1559 }
1560
1561 void RTLIL::Module::add(RTLIL::Wire *wire)
1562 {
1563 log_assert(!wire->name.empty());
1564 log_assert(count_id(wire->name) == 0);
1565 log_assert(refcount_wires_ == 0);
1566 wires_[wire->name] = wire;
1567 wire->module = this;
1568 }
1569
1570 void RTLIL::Module::add(RTLIL::Cell *cell)
1571 {
1572 log_assert(!cell->name.empty());
1573 log_assert(count_id(cell->name) == 0);
1574 log_assert(refcount_cells_ == 0);
1575 cells_[cell->name] = cell;
1576 cell->module = this;
1577 }
1578
1579 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1580 {
1581 log_assert(refcount_wires_ == 0);
1582
1583 struct DeleteWireWorker
1584 {
1585 RTLIL::Module *module;
1586 const pool<RTLIL::Wire*> *wires_p;
1587
1588 void operator()(RTLIL::SigSpec &sig) {
1589 sig.pack();
1590 for (auto &c : sig.chunks_)
1591 if (c.wire != NULL && wires_p->count(c.wire)) {
1592 c.wire = module->addWire(NEW_ID, c.width);
1593 c.offset = 0;
1594 }
1595 }
1596
1597 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1598 log_assert(GetSize(lhs) == GetSize(rhs));
1599 lhs.unpack();
1600 rhs.unpack();
1601 for (int i = 0; i < GetSize(lhs); i++) {
1602 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1603 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1604 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1605 lhs_bit = State::Sx;
1606 rhs_bit = State::Sx;
1607 }
1608 }
1609 }
1610 };
1611
1612 DeleteWireWorker delete_wire_worker;
1613 delete_wire_worker.module = this;
1614 delete_wire_worker.wires_p = &wires;
1615 rewrite_sigspecs2(delete_wire_worker);
1616
1617 for (auto &it : wires) {
1618 log_assert(wires_.count(it->name) != 0);
1619 wires_.erase(it->name);
1620 delete it;
1621 }
1622 }
1623
1624 void RTLIL::Module::remove(RTLIL::Cell *cell)
1625 {
1626 while (!cell->connections_.empty())
1627 cell->unsetPort(cell->connections_.begin()->first);
1628
1629 log_assert(cells_.count(cell->name) != 0);
1630 log_assert(refcount_cells_ == 0);
1631 cells_.erase(cell->name);
1632 delete cell;
1633 }
1634
1635 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1636 {
1637 log_assert(wires_[wire->name] == wire);
1638 log_assert(refcount_wires_ == 0);
1639 wires_.erase(wire->name);
1640 wire->name = new_name;
1641 add(wire);
1642 }
1643
1644 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1645 {
1646 log_assert(cells_[cell->name] == cell);
1647 log_assert(refcount_wires_ == 0);
1648 cells_.erase(cell->name);
1649 cell->name = new_name;
1650 add(cell);
1651 }
1652
1653 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1654 {
1655 log_assert(count_id(old_name) != 0);
1656 if (wires_.count(old_name))
1657 rename(wires_.at(old_name), new_name);
1658 else if (cells_.count(old_name))
1659 rename(cells_.at(old_name), new_name);
1660 else
1661 log_abort();
1662 }
1663
1664 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1665 {
1666 log_assert(wires_[w1->name] == w1);
1667 log_assert(wires_[w2->name] == w2);
1668 log_assert(refcount_wires_ == 0);
1669
1670 wires_.erase(w1->name);
1671 wires_.erase(w2->name);
1672
1673 std::swap(w1->name, w2->name);
1674
1675 wires_[w1->name] = w1;
1676 wires_[w2->name] = w2;
1677 }
1678
1679 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1680 {
1681 log_assert(cells_[c1->name] == c1);
1682 log_assert(cells_[c2->name] == c2);
1683 log_assert(refcount_cells_ == 0);
1684
1685 cells_.erase(c1->name);
1686 cells_.erase(c2->name);
1687
1688 std::swap(c1->name, c2->name);
1689
1690 cells_[c1->name] = c1;
1691 cells_[c2->name] = c2;
1692 }
1693
1694 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1695 {
1696 int index = 0;
1697 return uniquify(name, index);
1698 }
1699
1700 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1701 {
1702 if (index == 0) {
1703 if (count_id(name) == 0)
1704 return name;
1705 index++;
1706 }
1707
1708 while (1) {
1709 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1710 if (count_id(new_name) == 0)
1711 return new_name;
1712 index++;
1713 }
1714 }
1715
1716 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1717 {
1718 if (a->port_id && !b->port_id)
1719 return true;
1720 if (!a->port_id && b->port_id)
1721 return false;
1722
1723 if (a->port_id == b->port_id)
1724 return a->name < b->name;
1725 return a->port_id < b->port_id;
1726 }
1727
1728 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1729 {
1730 for (auto mon : monitors)
1731 mon->notify_connect(this, conn);
1732
1733 if (design)
1734 for (auto mon : design->monitors)
1735 mon->notify_connect(this, conn);
1736
1737 // ignore all attempts to assign constants to other constants
1738 if (conn.first.has_const()) {
1739 RTLIL::SigSig new_conn;
1740 for (int i = 0; i < GetSize(conn.first); i++)
1741 if (conn.first[i].wire) {
1742 new_conn.first.append(conn.first[i]);
1743 new_conn.second.append(conn.second[i]);
1744 }
1745 if (GetSize(new_conn.first))
1746 connect(new_conn);
1747 return;
1748 }
1749
1750 if (yosys_xtrace) {
1751 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1752 log_backtrace("-X- ", yosys_xtrace-1);
1753 }
1754
1755 log_assert(GetSize(conn.first) == GetSize(conn.second));
1756 connections_.push_back(conn);
1757 }
1758
1759 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1760 {
1761 connect(RTLIL::SigSig(lhs, rhs));
1762 }
1763
1764 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1765 {
1766 for (auto mon : monitors)
1767 mon->notify_connect(this, new_conn);
1768
1769 if (design)
1770 for (auto mon : design->monitors)
1771 mon->notify_connect(this, new_conn);
1772
1773 if (yosys_xtrace) {
1774 log("#X# New connections vector in %s:\n", log_id(this));
1775 for (auto &conn: new_conn)
1776 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1777 log_backtrace("-X- ", yosys_xtrace-1);
1778 }
1779
1780 connections_ = new_conn;
1781 }
1782
1783 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1784 {
1785 return connections_;
1786 }
1787
1788 void RTLIL::Module::fixup_ports()
1789 {
1790 std::vector<RTLIL::Wire*> all_ports;
1791
1792 for (auto &w : wires_)
1793 if (w.second->port_input || w.second->port_output)
1794 all_ports.push_back(w.second);
1795 else
1796 w.second->port_id = 0;
1797
1798 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1799
1800 ports.clear();
1801 for (size_t i = 0; i < all_ports.size(); i++) {
1802 ports.push_back(all_ports[i]->name);
1803 all_ports[i]->port_id = i+1;
1804 }
1805 }
1806
1807 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1808 {
1809 RTLIL::Wire *wire = new RTLIL::Wire;
1810 wire->name = name;
1811 wire->width = width;
1812 add(wire);
1813 return wire;
1814 }
1815
1816 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1817 {
1818 RTLIL::Wire *wire = addWire(name);
1819 wire->width = other->width;
1820 wire->start_offset = other->start_offset;
1821 wire->port_id = other->port_id;
1822 wire->port_input = other->port_input;
1823 wire->port_output = other->port_output;
1824 wire->upto = other->upto;
1825 wire->attributes = other->attributes;
1826 return wire;
1827 }
1828
1829 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1830 {
1831 RTLIL::Cell *cell = new RTLIL::Cell;
1832 cell->name = name;
1833 cell->type = type;
1834 add(cell);
1835 return cell;
1836 }
1837
1838 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1839 {
1840 RTLIL::Cell *cell = addCell(name, other->type);
1841 cell->connections_ = other->connections_;
1842 cell->parameters = other->parameters;
1843 cell->attributes = other->attributes;
1844 return cell;
1845 }
1846
1847 #define DEF_METHOD(_func, _y_size, _type) \
1848 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1849 RTLIL::Cell *cell = addCell(name, _type); \
1850 cell->parameters[ID(A_SIGNED)] = is_signed; \
1851 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1852 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1853 cell->setPort(ID::A, sig_a); \
1854 cell->setPort(ID::Y, sig_y); \
1855 cell->set_src_attribute(src); \
1856 return cell; \
1857 } \
1858 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1859 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1860 add ## _func(name, sig_a, sig_y, is_signed, src); \
1861 return sig_y; \
1862 }
1863 DEF_METHOD(Not, sig_a.size(), ID($not))
1864 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1865 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1866 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1867 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1868 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1869 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1870 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1871 DEF_METHOD(LogicNot, 1, ID($logic_not))
1872 #undef DEF_METHOD
1873
1874 #define DEF_METHOD(_func, _y_size, _type) \
1875 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1876 RTLIL::Cell *cell = addCell(name, _type); \
1877 cell->parameters[ID(A_SIGNED)] = is_signed; \
1878 cell->parameters[ID(B_SIGNED)] = is_signed; \
1879 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1880 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1881 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1882 cell->setPort(ID::A, sig_a); \
1883 cell->setPort(ID::B, sig_b); \
1884 cell->setPort(ID::Y, sig_y); \
1885 cell->set_src_attribute(src); \
1886 return cell; \
1887 } \
1888 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1889 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1890 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1891 return sig_y; \
1892 }
1893 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1894 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1895 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1896 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1897 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1898 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1899 DEF_METHOD(Lt, 1, ID($lt))
1900 DEF_METHOD(Le, 1, ID($le))
1901 DEF_METHOD(Eq, 1, ID($eq))
1902 DEF_METHOD(Ne, 1, ID($ne))
1903 DEF_METHOD(Eqx, 1, ID($eqx))
1904 DEF_METHOD(Nex, 1, ID($nex))
1905 DEF_METHOD(Ge, 1, ID($ge))
1906 DEF_METHOD(Gt, 1, ID($gt))
1907 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1908 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1909 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1910 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1911 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1912 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1913 DEF_METHOD(LogicOr, 1, ID($logic_or))
1914 #undef DEF_METHOD
1915
1916 #define DEF_METHOD(_func, _y_size, _type) \
1917 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1918 RTLIL::Cell *cell = addCell(name, _type); \
1919 cell->parameters[ID(A_SIGNED)] = is_signed; \
1920 cell->parameters[ID(B_SIGNED)] = false; \
1921 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1922 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1923 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1924 cell->setPort(ID::A, sig_a); \
1925 cell->setPort(ID::B, sig_b); \
1926 cell->setPort(ID::Y, sig_y); \
1927 cell->set_src_attribute(src); \
1928 return cell; \
1929 } \
1930 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1931 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1932 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1933 return sig_y; \
1934 }
1935 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1936 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1937 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1938 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1939 #undef DEF_METHOD
1940
1941 #define DEF_METHOD(_func, _type, _pmux) \
1942 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1943 RTLIL::Cell *cell = addCell(name, _type); \
1944 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1945 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1946 cell->setPort(ID::A, sig_a); \
1947 cell->setPort(ID::B, sig_b); \
1948 cell->setPort(ID(S), sig_s); \
1949 cell->setPort(ID::Y, sig_y); \
1950 cell->set_src_attribute(src); \
1951 return cell; \
1952 } \
1953 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1954 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1955 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1956 return sig_y; \
1957 }
1958 DEF_METHOD(Mux, ID($mux), 0)
1959 DEF_METHOD(Pmux, ID($pmux), 1)
1960 #undef DEF_METHOD
1961
1962 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1963 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1964 RTLIL::Cell *cell = addCell(name, _type); \
1965 cell->setPort("\\" #_P1, sig1); \
1966 cell->setPort("\\" #_P2, sig2); \
1967 cell->set_src_attribute(src); \
1968 return cell; \
1969 } \
1970 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1971 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1972 add ## _func(name, sig1, sig2, src); \
1973 return sig2; \
1974 }
1975 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1976 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1977 RTLIL::Cell *cell = addCell(name, _type); \
1978 cell->setPort("\\" #_P1, sig1); \
1979 cell->setPort("\\" #_P2, sig2); \
1980 cell->setPort("\\" #_P3, sig3); \
1981 cell->set_src_attribute(src); \
1982 return cell; \
1983 } \
1984 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1985 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1986 add ## _func(name, sig1, sig2, sig3, src); \
1987 return sig3; \
1988 }
1989 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1990 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1991 RTLIL::Cell *cell = addCell(name, _type); \
1992 cell->setPort("\\" #_P1, sig1); \
1993 cell->setPort("\\" #_P2, sig2); \
1994 cell->setPort("\\" #_P3, sig3); \
1995 cell->setPort("\\" #_P4, sig4); \
1996 cell->set_src_attribute(src); \
1997 return cell; \
1998 } \
1999 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
2000 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2001 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2002 return sig4; \
2003 }
2004 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2005 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
2006 RTLIL::Cell *cell = addCell(name, _type); \
2007 cell->setPort("\\" #_P1, sig1); \
2008 cell->setPort("\\" #_P2, sig2); \
2009 cell->setPort("\\" #_P3, sig3); \
2010 cell->setPort("\\" #_P4, sig4); \
2011 cell->setPort("\\" #_P5, sig5); \
2012 cell->set_src_attribute(src); \
2013 return cell; \
2014 } \
2015 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
2016 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2017 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2018 return sig5; \
2019 }
2020 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2021 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2022 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2023 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2024 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2025 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2026 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2027 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2028 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2029 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2030 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2031 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2032 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2033 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2034 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2035 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2036 #undef DEF_METHOD_2
2037 #undef DEF_METHOD_3
2038 #undef DEF_METHOD_4
2039 #undef DEF_METHOD_5
2040
2041 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
2042 {
2043 RTLIL::Cell *cell = addCell(name, ID($pow));
2044 cell->parameters[ID(A_SIGNED)] = a_signed;
2045 cell->parameters[ID(B_SIGNED)] = b_signed;
2046 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2047 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2048 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2049 cell->setPort(ID::A, sig_a);
2050 cell->setPort(ID::B, sig_b);
2051 cell->setPort(ID::Y, sig_y);
2052 cell->set_src_attribute(src);
2053 return cell;
2054 }
2055
2056 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2057 {
2058 RTLIL::Cell *cell = addCell(name, ID($slice));
2059 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2060 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2061 cell->parameters[ID(OFFSET)] = offset;
2062 cell->setPort(ID::A, sig_a);
2063 cell->setPort(ID::Y, sig_y);
2064 cell->set_src_attribute(src);
2065 return cell;
2066 }
2067
2068 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2069 {
2070 RTLIL::Cell *cell = addCell(name, ID($concat));
2071 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2072 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2073 cell->setPort(ID::A, sig_a);
2074 cell->setPort(ID::B, sig_b);
2075 cell->setPort(ID::Y, sig_y);
2076 cell->set_src_attribute(src);
2077 return cell;
2078 }
2079
2080 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2081 {
2082 RTLIL::Cell *cell = addCell(name, ID($lut));
2083 cell->parameters[ID(LUT)] = lut;
2084 cell->parameters[ID(WIDTH)] = sig_a.size();
2085 cell->setPort(ID::A, sig_a);
2086 cell->setPort(ID::Y, sig_y);
2087 cell->set_src_attribute(src);
2088 return cell;
2089 }
2090
2091 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2092 {
2093 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2094 cell->parameters[ID(WIDTH)] = sig_a.size();
2095 cell->setPort(ID::A, sig_a);
2096 cell->setPort(ID(EN), sig_en);
2097 cell->setPort(ID::Y, sig_y);
2098 cell->set_src_attribute(src);
2099 return cell;
2100 }
2101
2102 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2103 {
2104 RTLIL::Cell *cell = addCell(name, ID($assert));
2105 cell->setPort(ID::A, sig_a);
2106 cell->setPort(ID(EN), sig_en);
2107 cell->set_src_attribute(src);
2108 return cell;
2109 }
2110
2111 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2112 {
2113 RTLIL::Cell *cell = addCell(name, ID($assume));
2114 cell->setPort(ID::A, sig_a);
2115 cell->setPort(ID(EN), sig_en);
2116 cell->set_src_attribute(src);
2117 return cell;
2118 }
2119
2120 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2121 {
2122 RTLIL::Cell *cell = addCell(name, ID($live));
2123 cell->setPort(ID::A, sig_a);
2124 cell->setPort(ID(EN), sig_en);
2125 cell->set_src_attribute(src);
2126 return cell;
2127 }
2128
2129 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2130 {
2131 RTLIL::Cell *cell = addCell(name, ID($fair));
2132 cell->setPort(ID::A, sig_a);
2133 cell->setPort(ID(EN), sig_en);
2134 cell->set_src_attribute(src);
2135 return cell;
2136 }
2137
2138 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2139 {
2140 RTLIL::Cell *cell = addCell(name, ID($cover));
2141 cell->setPort(ID::A, sig_a);
2142 cell->setPort(ID(EN), sig_en);
2143 cell->set_src_attribute(src);
2144 return cell;
2145 }
2146
2147 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2148 {
2149 RTLIL::Cell *cell = addCell(name, ID($equiv));
2150 cell->setPort(ID::A, sig_a);
2151 cell->setPort(ID::B, sig_b);
2152 cell->setPort(ID::Y, sig_y);
2153 cell->set_src_attribute(src);
2154 return cell;
2155 }
2156
2157 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2158 {
2159 RTLIL::Cell *cell = addCell(name, ID($sr));
2160 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2161 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2162 cell->parameters[ID(WIDTH)] = sig_q.size();
2163 cell->setPort(ID(SET), sig_set);
2164 cell->setPort(ID(CLR), sig_clr);
2165 cell->setPort(ID(Q), sig_q);
2166 cell->set_src_attribute(src);
2167 return cell;
2168 }
2169
2170 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2171 {
2172 RTLIL::Cell *cell = addCell(name, ID($ff));
2173 cell->parameters[ID(WIDTH)] = sig_q.size();
2174 cell->setPort(ID(D), sig_d);
2175 cell->setPort(ID(Q), sig_q);
2176 cell->set_src_attribute(src);
2177 return cell;
2178 }
2179
2180 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2181 {
2182 RTLIL::Cell *cell = addCell(name, ID($dff));
2183 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2184 cell->parameters[ID(WIDTH)] = sig_q.size();
2185 cell->setPort(ID(CLK), sig_clk);
2186 cell->setPort(ID(D), sig_d);
2187 cell->setPort(ID(Q), sig_q);
2188 cell->set_src_attribute(src);
2189 return cell;
2190 }
2191
2192 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2193 {
2194 RTLIL::Cell *cell = addCell(name, ID($dffe));
2195 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2196 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2197 cell->parameters[ID(WIDTH)] = sig_q.size();
2198 cell->setPort(ID(CLK), sig_clk);
2199 cell->setPort(ID(EN), sig_en);
2200 cell->setPort(ID(D), sig_d);
2201 cell->setPort(ID(Q), sig_q);
2202 cell->set_src_attribute(src);
2203 return cell;
2204 }
2205
2206 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2207 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2208 {
2209 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2210 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2211 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2212 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2213 cell->parameters[ID(WIDTH)] = sig_q.size();
2214 cell->setPort(ID(CLK), sig_clk);
2215 cell->setPort(ID(SET), sig_set);
2216 cell->setPort(ID(CLR), sig_clr);
2217 cell->setPort(ID(D), sig_d);
2218 cell->setPort(ID(Q), sig_q);
2219 cell->set_src_attribute(src);
2220 return cell;
2221 }
2222
2223 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2224 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2225 {
2226 RTLIL::Cell *cell = addCell(name, ID($adff));
2227 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2228 cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
2229 cell->parameters[ID(ARST_VALUE)] = arst_value;
2230 cell->parameters[ID(WIDTH)] = sig_q.size();
2231 cell->setPort(ID(CLK), sig_clk);
2232 cell->setPort(ID(ARST), sig_arst);
2233 cell->setPort(ID(D), sig_d);
2234 cell->setPort(ID(Q), sig_q);
2235 cell->set_src_attribute(src);
2236 return cell;
2237 }
2238
2239 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2240 {
2241 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2242 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2243 cell->parameters[ID(WIDTH)] = sig_q.size();
2244 cell->setPort(ID(EN), sig_en);
2245 cell->setPort(ID(D), sig_d);
2246 cell->setPort(ID(Q), sig_q);
2247 cell->set_src_attribute(src);
2248 return cell;
2249 }
2250
2251 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2252 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2253 {
2254 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2255 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2256 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2257 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2258 cell->parameters[ID(WIDTH)] = sig_q.size();
2259 cell->setPort(ID(EN), sig_en);
2260 cell->setPort(ID(SET), sig_set);
2261 cell->setPort(ID(CLR), sig_clr);
2262 cell->setPort(ID(D), sig_d);
2263 cell->setPort(ID(Q), sig_q);
2264 cell->set_src_attribute(src);
2265 return cell;
2266 }
2267
2268 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2269 {
2270 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2271 cell->setPort(ID(D), sig_d);
2272 cell->setPort(ID(Q), sig_q);
2273 cell->set_src_attribute(src);
2274 return cell;
2275 }
2276
2277 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2278 {
2279 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2280 cell->setPort(ID(C), sig_clk);
2281 cell->setPort(ID(D), sig_d);
2282 cell->setPort(ID(Q), sig_q);
2283 cell->set_src_attribute(src);
2284 return cell;
2285 }
2286
2287 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2288 {
2289 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2290 cell->setPort(ID(C), sig_clk);
2291 cell->setPort(ID(E), sig_en);
2292 cell->setPort(ID(D), sig_d);
2293 cell->setPort(ID(Q), sig_q);
2294 cell->set_src_attribute(src);
2295 return cell;
2296 }
2297
2298 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2299 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2300 {
2301 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2302 cell->setPort(ID(C), sig_clk);
2303 cell->setPort(ID(S), sig_set);
2304 cell->setPort(ID(R), sig_clr);
2305 cell->setPort(ID(D), sig_d);
2306 cell->setPort(ID(Q), sig_q);
2307 cell->set_src_attribute(src);
2308 return cell;
2309 }
2310
2311 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2312 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2313 {
2314 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2315 cell->setPort(ID(C), sig_clk);
2316 cell->setPort(ID(R), sig_arst);
2317 cell->setPort(ID(D), sig_d);
2318 cell->setPort(ID(Q), sig_q);
2319 cell->set_src_attribute(src);
2320 return cell;
2321 }
2322
2323 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2324 {
2325 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2326 cell->setPort(ID(E), sig_en);
2327 cell->setPort(ID(D), sig_d);
2328 cell->setPort(ID(Q), sig_q);
2329 cell->set_src_attribute(src);
2330 return cell;
2331 }
2332
2333 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2334 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2335 {
2336 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2337 cell->setPort(ID(E), sig_en);
2338 cell->setPort(ID(S), sig_set);
2339 cell->setPort(ID(R), sig_clr);
2340 cell->setPort(ID(D), sig_d);
2341 cell->setPort(ID(Q), sig_q);
2342 cell->set_src_attribute(src);
2343 return cell;
2344 }
2345
2346 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2347 {
2348 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2349 Cell *cell = addCell(name, ID($anyconst));
2350 cell->setParam(ID(WIDTH), width);
2351 cell->setPort(ID::Y, sig);
2352 cell->set_src_attribute(src);
2353 return sig;
2354 }
2355
2356 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2357 {
2358 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2359 Cell *cell = addCell(name, ID($anyseq));
2360 cell->setParam(ID(WIDTH), width);
2361 cell->setPort(ID::Y, sig);
2362 cell->set_src_attribute(src);
2363 return sig;
2364 }
2365
2366 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2367 {
2368 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2369 Cell *cell = addCell(name, ID($allconst));
2370 cell->setParam(ID(WIDTH), width);
2371 cell->setPort(ID::Y, sig);
2372 cell->set_src_attribute(src);
2373 return sig;
2374 }
2375
2376 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2377 {
2378 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2379 Cell *cell = addCell(name, ID($allseq));
2380 cell->setParam(ID(WIDTH), width);
2381 cell->setPort(ID::Y, sig);
2382 cell->set_src_attribute(src);
2383 return sig;
2384 }
2385
2386 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2387 {
2388 RTLIL::SigSpec sig = addWire(NEW_ID);
2389 Cell *cell = addCell(name, ID($initstate));
2390 cell->setPort(ID::Y, sig);
2391 cell->set_src_attribute(src);
2392 return sig;
2393 }
2394
2395 RTLIL::Wire::Wire()
2396 {
2397 static unsigned int hashidx_count = 123456789;
2398 hashidx_count = mkhash_xorshift(hashidx_count);
2399 hashidx_ = hashidx_count;
2400
2401 module = nullptr;
2402 width = 1;
2403 start_offset = 0;
2404 port_id = 0;
2405 port_input = false;
2406 port_output = false;
2407 upto = false;
2408
2409 #ifdef WITH_PYTHON
2410 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2411 #endif
2412 }
2413
2414 RTLIL::Wire::~Wire()
2415 {
2416 #ifdef WITH_PYTHON
2417 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2418 #endif
2419 }
2420
2421 #ifdef WITH_PYTHON
2422 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2423 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2424 {
2425 return &all_wires;
2426 }
2427 #endif
2428
2429 RTLIL::Memory::Memory()
2430 {
2431 static unsigned int hashidx_count = 123456789;
2432 hashidx_count = mkhash_xorshift(hashidx_count);
2433 hashidx_ = hashidx_count;
2434
2435 width = 1;
2436 start_offset = 0;
2437 size = 0;
2438 #ifdef WITH_PYTHON
2439 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2440 #endif
2441 }
2442
2443 RTLIL::Cell::Cell() : module(nullptr)
2444 {
2445 static unsigned int hashidx_count = 123456789;
2446 hashidx_count = mkhash_xorshift(hashidx_count);
2447 hashidx_ = hashidx_count;
2448
2449 // log("#memtrace# %p\n", this);
2450 memhasher();
2451
2452 #ifdef WITH_PYTHON
2453 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2454 #endif
2455 }
2456
2457 RTLIL::Cell::~Cell()
2458 {
2459 #ifdef WITH_PYTHON
2460 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2461 #endif
2462 }
2463
2464 #ifdef WITH_PYTHON
2465 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2466 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2467 {
2468 return &all_cells;
2469 }
2470 #endif
2471
2472 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2473 {
2474 return connections_.count(portname) != 0;
2475 }
2476
2477 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2478 {
2479 RTLIL::SigSpec signal;
2480 auto conn_it = connections_.find(portname);
2481
2482 if (conn_it != connections_.end())
2483 {
2484 for (auto mon : module->monitors)
2485 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2486
2487 if (module->design)
2488 for (auto mon : module->design->monitors)
2489 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2490
2491 if (yosys_xtrace) {
2492 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2493 log_backtrace("-X- ", yosys_xtrace-1);
2494 }
2495
2496 connections_.erase(conn_it);
2497 }
2498 }
2499
2500 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2501 {
2502 auto conn_it = connections_.find(portname);
2503
2504 if (conn_it == connections_.end()) {
2505 connections_[portname] = RTLIL::SigSpec();
2506 conn_it = connections_.find(portname);
2507 log_assert(conn_it != connections_.end());
2508 } else
2509 if (conn_it->second == signal)
2510 return;
2511
2512 for (auto mon : module->monitors)
2513 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2514
2515 if (module->design)
2516 for (auto mon : module->design->monitors)
2517 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2518
2519 if (yosys_xtrace) {
2520 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2521 log_backtrace("-X- ", yosys_xtrace-1);
2522 }
2523
2524 conn_it->second = signal;
2525 }
2526
2527 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2528 {
2529 return connections_.at(portname);
2530 }
2531
2532 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2533 {
2534 return connections_;
2535 }
2536
2537 bool RTLIL::Cell::known() const
2538 {
2539 if (yosys_celltypes.cell_known(type))
2540 return true;
2541 if (module && module->design && module->design->module(type))
2542 return true;
2543 return false;
2544 }
2545
2546 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2547 {
2548 if (yosys_celltypes.cell_known(type))
2549 return yosys_celltypes.cell_input(type, portname);
2550 if (module && module->design) {
2551 RTLIL::Module *m = module->design->module(type);
2552 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2553 return w && w->port_input;
2554 }
2555 return false;
2556 }
2557
2558 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2559 {
2560 if (yosys_celltypes.cell_known(type))
2561 return yosys_celltypes.cell_output(type, portname);
2562 if (module && module->design) {
2563 RTLIL::Module *m = module->design->module(type);
2564 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2565 return w && w->port_output;
2566 }
2567 return false;
2568 }
2569
2570 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2571 {
2572 return parameters.count(paramname) != 0;
2573 }
2574
2575 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2576 {
2577 parameters.erase(paramname);
2578 }
2579
2580 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2581 {
2582 parameters[paramname] = value;
2583 }
2584
2585 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2586 {
2587 return parameters.at(paramname);
2588 }
2589
2590 void RTLIL::Cell::sort()
2591 {
2592 connections_.sort(sort_by_id_str());
2593 parameters.sort(sort_by_id_str());
2594 attributes.sort(sort_by_id_str());
2595 }
2596
2597 void RTLIL::Cell::check()
2598 {
2599 #ifndef NDEBUG
2600 InternalCellChecker checker(NULL, this);
2601 checker.check();
2602 #endif
2603 }
2604
2605 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2606 {
2607 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2608 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2609 return;
2610
2611 if (type == ID($mux) || type == ID($pmux)) {
2612 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2613 if (type == ID($pmux))
2614 parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
2615 check();
2616 return;
2617 }
2618
2619 if (type == ID($lut) || type == ID($sop)) {
2620 parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
2621 return;
2622 }
2623
2624 if (type == ID($fa)) {
2625 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2626 return;
2627 }
2628
2629 if (type == ID($lcu)) {
2630 parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
2631 return;
2632 }
2633
2634 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2635
2636 if (connections_.count(ID::A)) {
2637 if (signedness_ab) {
2638 if (set_a_signed)
2639 parameters[ID(A_SIGNED)] = true;
2640 else if (parameters.count(ID(A_SIGNED)) == 0)
2641 parameters[ID(A_SIGNED)] = false;
2642 }
2643 parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
2644 }
2645
2646 if (connections_.count(ID::B)) {
2647 if (signedness_ab) {
2648 if (set_b_signed)
2649 parameters[ID(B_SIGNED)] = true;
2650 else if (parameters.count(ID(B_SIGNED)) == 0)
2651 parameters[ID(B_SIGNED)] = false;
2652 }
2653 parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
2654 }
2655
2656 if (connections_.count(ID::Y))
2657 parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
2658
2659 if (connections_.count(ID(Q)))
2660 parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
2661
2662 check();
2663 }
2664
2665 RTLIL::SigChunk::SigChunk()
2666 {
2667 wire = NULL;
2668 width = 0;
2669 offset = 0;
2670 }
2671
2672 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2673 {
2674 wire = NULL;
2675 data = value.bits;
2676 width = GetSize(data);
2677 offset = 0;
2678 }
2679
2680 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2681 {
2682 log_assert(wire != nullptr);
2683 this->wire = wire;
2684 this->width = wire->width;
2685 this->offset = 0;
2686 }
2687
2688 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2689 {
2690 log_assert(wire != nullptr);
2691 this->wire = wire;
2692 this->width = width;
2693 this->offset = offset;
2694 }
2695
2696 RTLIL::SigChunk::SigChunk(const std::string &str)
2697 {
2698 wire = NULL;
2699 data = RTLIL::Const(str).bits;
2700 width = GetSize(data);
2701 offset = 0;
2702 }
2703
2704 RTLIL::SigChunk::SigChunk(int val, int width)
2705 {
2706 wire = NULL;
2707 data = RTLIL::Const(val, width).bits;
2708 this->width = GetSize(data);
2709 offset = 0;
2710 }
2711
2712 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2713 {
2714 wire = NULL;
2715 data = RTLIL::Const(bit, width).bits;
2716 this->width = GetSize(data);
2717 offset = 0;
2718 }
2719
2720 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2721 {
2722 wire = bit.wire;
2723 offset = 0;
2724 if (wire == NULL)
2725 data = RTLIL::Const(bit.data).bits;
2726 else
2727 offset = bit.offset;
2728 width = 1;
2729 }
2730
2731 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2732 {
2733 wire = sigchunk.wire;
2734 data = sigchunk.data;
2735 width = sigchunk.width;
2736 offset = sigchunk.offset;
2737 }
2738
2739 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2740 {
2741 RTLIL::SigChunk ret;
2742 if (wire) {
2743 ret.wire = wire;
2744 ret.offset = this->offset + offset;
2745 ret.width = length;
2746 } else {
2747 for (int i = 0; i < length; i++)
2748 ret.data.push_back(data[offset+i]);
2749 ret.width = length;
2750 }
2751 return ret;
2752 }
2753
2754 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2755 {
2756 if (wire && other.wire)
2757 if (wire->name != other.wire->name)
2758 return wire->name < other.wire->name;
2759
2760 if (wire != other.wire)
2761 return wire < other.wire;
2762
2763 if (offset != other.offset)
2764 return offset < other.offset;
2765
2766 if (width != other.width)
2767 return width < other.width;
2768
2769 return data < other.data;
2770 }
2771
2772 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2773 {
2774 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2775 }
2776
2777 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2778 {
2779 if (*this == other)
2780 return false;
2781 return true;
2782 }
2783
2784 RTLIL::SigSpec::SigSpec()
2785 {
2786 width_ = 0;
2787 hash_ = 0;
2788 }
2789
2790 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2791 {
2792 *this = other;
2793 }
2794
2795 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2796 {
2797 cover("kernel.rtlil.sigspec.init.list");
2798
2799 width_ = 0;
2800 hash_ = 0;
2801
2802 log_assert(parts.size() > 0);
2803 auto ie = parts.begin();
2804 auto it = ie + parts.size() - 1;
2805 while (it >= ie)
2806 append(*it--);
2807 }
2808
2809 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2810 {
2811 cover("kernel.rtlil.sigspec.assign");
2812
2813 width_ = other.width_;
2814 hash_ = other.hash_;
2815 chunks_ = other.chunks_;
2816 bits_.clear();
2817
2818 if (!other.bits_.empty())
2819 {
2820 RTLIL::SigChunk *last = NULL;
2821 int last_end_offset = 0;
2822
2823 for (auto &bit : other.bits_) {
2824 if (last && bit.wire == last->wire) {
2825 if (bit.wire == NULL) {
2826 last->data.push_back(bit.data);
2827 last->width++;
2828 continue;
2829 } else if (last_end_offset == bit.offset) {
2830 last_end_offset++;
2831 last->width++;
2832 continue;
2833 }
2834 }
2835 chunks_.push_back(bit);
2836 last = &chunks_.back();
2837 last_end_offset = bit.offset + 1;
2838 }
2839
2840 check();
2841 }
2842
2843 return *this;
2844 }
2845
2846 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2847 {
2848 cover("kernel.rtlil.sigspec.init.const");
2849
2850 chunks_.emplace_back(value);
2851 width_ = chunks_.back().width;
2852 hash_ = 0;
2853 check();
2854 }
2855
2856 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2857 {
2858 cover("kernel.rtlil.sigspec.init.chunk");
2859
2860 chunks_.emplace_back(chunk);
2861 width_ = chunks_.back().width;
2862 hash_ = 0;
2863 check();
2864 }
2865
2866 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2867 {
2868 cover("kernel.rtlil.sigspec.init.wire");
2869
2870 chunks_.emplace_back(wire);
2871 width_ = chunks_.back().width;
2872 hash_ = 0;
2873 check();
2874 }
2875
2876 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2877 {
2878 cover("kernel.rtlil.sigspec.init.wire_part");
2879
2880 chunks_.emplace_back(wire, offset, width);
2881 width_ = chunks_.back().width;
2882 hash_ = 0;
2883 check();
2884 }
2885
2886 RTLIL::SigSpec::SigSpec(const std::string &str)
2887 {
2888 cover("kernel.rtlil.sigspec.init.str");
2889
2890 chunks_.emplace_back(str);
2891 width_ = chunks_.back().width;
2892 hash_ = 0;
2893 check();
2894 }
2895
2896 RTLIL::SigSpec::SigSpec(int val, int width)
2897 {
2898 cover("kernel.rtlil.sigspec.init.int");
2899
2900 chunks_.emplace_back(val, width);
2901 width_ = width;
2902 hash_ = 0;
2903 check();
2904 }
2905
2906 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2907 {
2908 cover("kernel.rtlil.sigspec.init.state");
2909
2910 chunks_.emplace_back(bit, width);
2911 width_ = width;
2912 hash_ = 0;
2913 check();
2914 }
2915
2916 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2917 {
2918 cover("kernel.rtlil.sigspec.init.bit");
2919
2920 if (bit.wire == NULL)
2921 chunks_.emplace_back(bit.data, width);
2922 else
2923 for (int i = 0; i < width; i++)
2924 chunks_.push_back(bit);
2925 width_ = width;
2926 hash_ = 0;
2927 check();
2928 }
2929
2930 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2931 {
2932 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2933
2934 width_ = 0;
2935 hash_ = 0;
2936 for (const auto &c : chunks)
2937 append(c);
2938 check();
2939 }
2940
2941 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2942 {
2943 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2944
2945 width_ = 0;
2946 hash_ = 0;
2947 for (const auto &bit : bits)
2948 append(bit);
2949 check();
2950 }
2951
2952 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2953 {
2954 cover("kernel.rtlil.sigspec.init.pool_bits");
2955
2956 width_ = 0;
2957 hash_ = 0;
2958 for (const auto &bit : bits)
2959 append(bit);
2960 check();
2961 }
2962
2963 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2964 {
2965 cover("kernel.rtlil.sigspec.init.stdset_bits");
2966
2967 width_ = 0;
2968 hash_ = 0;
2969 for (const auto &bit : bits)
2970 append(bit);
2971 check();
2972 }
2973
2974 RTLIL::SigSpec::SigSpec(bool bit)
2975 {
2976 cover("kernel.rtlil.sigspec.init.bool");
2977
2978 width_ = 0;
2979 hash_ = 0;
2980 append(SigBit(bit));
2981 check();
2982 }
2983
2984 void RTLIL::SigSpec::pack() const
2985 {
2986 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2987
2988 if (that->bits_.empty())
2989 return;
2990
2991 cover("kernel.rtlil.sigspec.convert.pack");
2992 log_assert(that->chunks_.empty());
2993
2994 std::vector<RTLIL::SigBit> old_bits;
2995 old_bits.swap(that->bits_);
2996
2997 RTLIL::SigChunk *last = NULL;
2998 int last_end_offset = 0;
2999
3000 for (auto &bit : old_bits) {
3001 if (last && bit.wire == last->wire) {
3002 if (bit.wire == NULL) {
3003 last->data.push_back(bit.data);
3004 last->width++;
3005 continue;
3006 } else if (last_end_offset == bit.offset) {
3007 last_end_offset++;
3008 last->width++;
3009 continue;
3010 }
3011 }
3012 that->chunks_.push_back(bit);
3013 last = &that->chunks_.back();
3014 last_end_offset = bit.offset + 1;
3015 }
3016
3017 check();
3018 }
3019
3020 void RTLIL::SigSpec::unpack() const
3021 {
3022 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3023
3024 if (that->chunks_.empty())
3025 return;
3026
3027 cover("kernel.rtlil.sigspec.convert.unpack");
3028 log_assert(that->bits_.empty());
3029
3030 that->bits_.reserve(that->width_);
3031 for (auto &c : that->chunks_)
3032 for (int i = 0; i < c.width; i++)
3033 that->bits_.push_back(RTLIL::SigBit(c, i));
3034
3035 that->chunks_.clear();
3036 that->hash_ = 0;
3037 }
3038
3039 void RTLIL::SigSpec::updhash() const
3040 {
3041 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3042
3043 if (that->hash_ != 0)
3044 return;
3045
3046 cover("kernel.rtlil.sigspec.hash");
3047 that->pack();
3048
3049 that->hash_ = mkhash_init;
3050 for (auto &c : that->chunks_)
3051 if (c.wire == NULL) {
3052 for (auto &v : c.data)
3053 that->hash_ = mkhash(that->hash_, v);
3054 } else {
3055 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3056 that->hash_ = mkhash(that->hash_, c.offset);
3057 that->hash_ = mkhash(that->hash_, c.width);
3058 }
3059
3060 if (that->hash_ == 0)
3061 that->hash_ = 1;
3062 }
3063
3064 void RTLIL::SigSpec::sort()
3065 {
3066 unpack();
3067 cover("kernel.rtlil.sigspec.sort");
3068 std::sort(bits_.begin(), bits_.end());
3069 }
3070
3071 void RTLIL::SigSpec::sort_and_unify()
3072 {
3073 unpack();
3074 cover("kernel.rtlil.sigspec.sort_and_unify");
3075
3076 // A copy of the bits vector is used to prevent duplicating the logic from
3077 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3078 // that isn't showing up as significant in profiles.
3079 std::vector<SigBit> unique_bits = bits_;
3080 std::sort(unique_bits.begin(), unique_bits.end());
3081 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3082 unique_bits.erase(last, unique_bits.end());
3083
3084 *this = unique_bits;
3085 }
3086
3087 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3088 {
3089 replace(pattern, with, this);
3090 }
3091
3092 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3093 {
3094 log_assert(other != NULL);
3095 log_assert(width_ == other->width_);
3096 log_assert(pattern.width_ == with.width_);
3097
3098 pattern.unpack();
3099 with.unpack();
3100 unpack();
3101 other->unpack();
3102
3103 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3104 if (pattern.bits_[i].wire != NULL) {
3105 for (int j = 0; j < GetSize(bits_); j++) {
3106 if (bits_[j] == pattern.bits_[i]) {
3107 other->bits_[j] = with.bits_[i];
3108 }
3109 }
3110 }
3111 }
3112
3113 other->check();
3114 }
3115
3116 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3117 {
3118 replace(rules, this);
3119 }
3120
3121 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3122 {
3123 cover("kernel.rtlil.sigspec.replace_dict");
3124
3125 log_assert(other != NULL);
3126 log_assert(width_ == other->width_);
3127
3128 if (rules.empty()) return;
3129 unpack();
3130 other->unpack();
3131
3132 for (int i = 0; i < GetSize(bits_); i++) {
3133 auto it = rules.find(bits_[i]);
3134 if (it != rules.end())
3135 other->bits_[i] = it->second;
3136 }
3137
3138 other->check();
3139 }
3140
3141 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3142 {
3143 replace(rules, this);
3144 }
3145
3146 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3147 {
3148 cover("kernel.rtlil.sigspec.replace_map");
3149
3150 log_assert(other != NULL);
3151 log_assert(width_ == other->width_);
3152
3153 if (rules.empty()) return;
3154 unpack();
3155 other->unpack();
3156
3157 for (int i = 0; i < GetSize(bits_); i++) {
3158 auto it = rules.find(bits_[i]);
3159 if (it != rules.end())
3160 other->bits_[i] = it->second;
3161 }
3162
3163 other->check();
3164 }
3165
3166 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3167 {
3168 remove2(pattern, NULL);
3169 }
3170
3171 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3172 {
3173 RTLIL::SigSpec tmp = *this;
3174 tmp.remove2(pattern, other);
3175 }
3176
3177 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3178 {
3179 if (other)
3180 cover("kernel.rtlil.sigspec.remove_other");
3181 else
3182 cover("kernel.rtlil.sigspec.remove");
3183
3184 unpack();
3185 if (other != NULL) {
3186 log_assert(width_ == other->width_);
3187 other->unpack();
3188 }
3189
3190 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3191 {
3192 if (bits_[i].wire == NULL) continue;
3193
3194 for (auto &pattern_chunk : pattern.chunks())
3195 if (bits_[i].wire == pattern_chunk.wire &&
3196 bits_[i].offset >= pattern_chunk.offset &&
3197 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3198 bits_.erase(bits_.begin() + i);
3199 width_--;
3200 if (other != NULL) {
3201 other->bits_.erase(other->bits_.begin() + i);
3202 other->width_--;
3203 }
3204 break;
3205 }
3206 }
3207
3208 check();
3209 }
3210
3211 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3212 {
3213 remove2(pattern, NULL);
3214 }
3215
3216 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3217 {
3218 RTLIL::SigSpec tmp = *this;
3219 tmp.remove2(pattern, other);
3220 }
3221
3222 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3223 {
3224 if (other)
3225 cover("kernel.rtlil.sigspec.remove_other");
3226 else
3227 cover("kernel.rtlil.sigspec.remove");
3228
3229 unpack();
3230
3231 if (other != NULL) {
3232 log_assert(width_ == other->width_);
3233 other->unpack();
3234 }
3235
3236 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3237 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3238 bits_.erase(bits_.begin() + i);
3239 width_--;
3240 if (other != NULL) {
3241 other->bits_.erase(other->bits_.begin() + i);
3242 other->width_--;
3243 }
3244 }
3245 }
3246
3247 check();
3248 }
3249
3250 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3251 {
3252 if (other)
3253 cover("kernel.rtlil.sigspec.remove_other");
3254 else
3255 cover("kernel.rtlil.sigspec.remove");
3256
3257 unpack();
3258
3259 if (other != NULL) {
3260 log_assert(width_ == other->width_);
3261 other->unpack();
3262 }
3263
3264 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3265 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3266 bits_.erase(bits_.begin() + i);
3267 width_--;
3268 if (other != NULL) {
3269 other->bits_.erase(other->bits_.begin() + i);
3270 other->width_--;
3271 }
3272 }
3273 }
3274
3275 check();
3276 }
3277
3278 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3279 {
3280 if (other)
3281 cover("kernel.rtlil.sigspec.extract_other");
3282 else
3283 cover("kernel.rtlil.sigspec.extract");
3284
3285 log_assert(other == NULL || width_ == other->width_);
3286
3287 RTLIL::SigSpec ret;
3288 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3289
3290 for (auto& pattern_chunk : pattern.chunks()) {
3291 if (other) {
3292 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3293 for (int i = 0; i < width_; i++)
3294 if (bits_match[i].wire &&
3295 bits_match[i].wire == pattern_chunk.wire &&
3296 bits_match[i].offset >= pattern_chunk.offset &&
3297 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3298 ret.append(bits_other[i]);
3299 } else {
3300 for (int i = 0; i < width_; i++)
3301 if (bits_match[i].wire &&
3302 bits_match[i].wire == pattern_chunk.wire &&
3303 bits_match[i].offset >= pattern_chunk.offset &&
3304 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3305 ret.append(bits_match[i]);
3306 }
3307 }
3308
3309 ret.check();
3310 return ret;
3311 }
3312
3313 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3314 {
3315 if (other)
3316 cover("kernel.rtlil.sigspec.extract_other");
3317 else
3318 cover("kernel.rtlil.sigspec.extract");
3319
3320 log_assert(other == NULL || width_ == other->width_);
3321
3322 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3323 RTLIL::SigSpec ret;
3324
3325 if (other) {
3326 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3327 for (int i = 0; i < width_; i++)
3328 if (bits_match[i].wire && pattern.count(bits_match[i]))
3329 ret.append(bits_other[i]);
3330 } else {
3331 for (int i = 0; i < width_; i++)
3332 if (bits_match[i].wire && pattern.count(bits_match[i]))
3333 ret.append(bits_match[i]);
3334 }
3335
3336 ret.check();
3337 return ret;
3338 }
3339
3340 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3341 {
3342 cover("kernel.rtlil.sigspec.replace_pos");
3343
3344 unpack();
3345 with.unpack();
3346
3347 log_assert(offset >= 0);
3348 log_assert(with.width_ >= 0);
3349 log_assert(offset+with.width_ <= width_);
3350
3351 for (int i = 0; i < with.width_; i++)
3352 bits_.at(offset + i) = with.bits_.at(i);
3353
3354 check();
3355 }
3356
3357 void RTLIL::SigSpec::remove_const()
3358 {
3359 if (packed())
3360 {
3361 cover("kernel.rtlil.sigspec.remove_const.packed");
3362
3363 std::vector<RTLIL::SigChunk> new_chunks;
3364 new_chunks.reserve(GetSize(chunks_));
3365
3366 width_ = 0;
3367 for (auto &chunk : chunks_)
3368 if (chunk.wire != NULL) {
3369 new_chunks.push_back(chunk);
3370 width_ += chunk.width;
3371 }
3372
3373 chunks_.swap(new_chunks);
3374 }
3375 else
3376 {
3377 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3378
3379 std::vector<RTLIL::SigBit> new_bits;
3380 new_bits.reserve(width_);
3381
3382 for (auto &bit : bits_)
3383 if (bit.wire != NULL)
3384 new_bits.push_back(bit);
3385
3386 bits_.swap(new_bits);
3387 width_ = bits_.size();
3388 }
3389
3390 check();
3391 }
3392
3393 void RTLIL::SigSpec::remove(int offset, int length)
3394 {
3395 cover("kernel.rtlil.sigspec.remove_pos");
3396
3397 unpack();
3398
3399 log_assert(offset >= 0);
3400 log_assert(length >= 0);
3401 log_assert(offset + length <= width_);
3402
3403 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3404 width_ = bits_.size();
3405
3406 check();
3407 }
3408
3409 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3410 {
3411 unpack();
3412 cover("kernel.rtlil.sigspec.extract_pos");
3413 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3414 }
3415
3416 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3417 {
3418 if (signal.width_ == 0)
3419 return;
3420
3421 if (width_ == 0) {
3422 *this = signal;
3423 return;
3424 }
3425
3426 cover("kernel.rtlil.sigspec.append");
3427
3428 if (packed() != signal.packed()) {
3429 pack();
3430 signal.pack();
3431 }
3432
3433 if (packed())
3434 for (auto &other_c : signal.chunks_)
3435 {
3436 auto &my_last_c = chunks_.back();
3437 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3438 auto &this_data = my_last_c.data;
3439 auto &other_data = other_c.data;
3440 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3441 my_last_c.width += other_c.width;
3442 } else
3443 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3444 my_last_c.width += other_c.width;
3445 } else
3446 chunks_.push_back(other_c);
3447 }
3448 else
3449 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3450
3451 width_ += signal.width_;
3452 check();
3453 }
3454
3455 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3456 {
3457 if (packed())
3458 {
3459 cover("kernel.rtlil.sigspec.append_bit.packed");
3460
3461 if (chunks_.size() == 0)
3462 chunks_.push_back(bit);
3463 else
3464 if (bit.wire == NULL)
3465 if (chunks_.back().wire == NULL) {
3466 chunks_.back().data.push_back(bit.data);
3467 chunks_.back().width++;
3468 } else
3469 chunks_.push_back(bit);
3470 else
3471 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3472 chunks_.back().width++;
3473 else
3474 chunks_.push_back(bit);
3475 }
3476 else
3477 {
3478 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3479 bits_.push_back(bit);
3480 }
3481
3482 width_++;
3483 check();
3484 }
3485
3486 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3487 {
3488 cover("kernel.rtlil.sigspec.extend_u0");
3489
3490 pack();
3491
3492 if (width_ > width)
3493 remove(width, width_ - width);
3494
3495 if (width_ < width) {
3496 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3497 if (!is_signed)
3498 padding = RTLIL::State::S0;
3499 while (width_ < width)
3500 append(padding);
3501 }
3502
3503 }
3504
3505 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3506 {
3507 cover("kernel.rtlil.sigspec.repeat");
3508
3509 RTLIL::SigSpec sig;
3510 for (int i = 0; i < num; i++)
3511 sig.append(*this);
3512 return sig;
3513 }
3514
3515 #ifndef NDEBUG
3516 void RTLIL::SigSpec::check() const
3517 {
3518 if (width_ > 64)
3519 {
3520 cover("kernel.rtlil.sigspec.check.skip");
3521 }
3522 else if (packed())
3523 {
3524 cover("kernel.rtlil.sigspec.check.packed");
3525
3526 int w = 0;
3527 for (size_t i = 0; i < chunks_.size(); i++) {
3528 const RTLIL::SigChunk chunk = chunks_[i];
3529 if (chunk.wire == NULL) {
3530 if (i > 0)
3531 log_assert(chunks_[i-1].wire != NULL);
3532 log_assert(chunk.offset == 0);
3533 log_assert(chunk.data.size() == (size_t)chunk.width);
3534 } else {
3535 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3536 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3537 log_assert(chunk.offset >= 0);
3538 log_assert(chunk.width >= 0);
3539 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3540 log_assert(chunk.data.size() == 0);
3541 }
3542 w += chunk.width;
3543 }
3544 log_assert(w == width_);
3545 log_assert(bits_.empty());
3546 }
3547 else
3548 {
3549 cover("kernel.rtlil.sigspec.check.unpacked");
3550
3551 log_assert(width_ == GetSize(bits_));
3552 log_assert(chunks_.empty());
3553 }
3554 }
3555 #endif
3556
3557 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3558 {
3559 cover("kernel.rtlil.sigspec.comp_lt");
3560
3561 if (this == &other)
3562 return false;
3563
3564 if (width_ != other.width_)
3565 return width_ < other.width_;
3566
3567 pack();
3568 other.pack();
3569
3570 if (chunks_.size() != other.chunks_.size())
3571 return chunks_.size() < other.chunks_.size();
3572
3573 updhash();
3574 other.updhash();
3575
3576 if (hash_ != other.hash_)
3577 return hash_ < other.hash_;
3578
3579 for (size_t i = 0; i < chunks_.size(); i++)
3580 if (chunks_[i] != other.chunks_[i]) {
3581 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3582 return chunks_[i] < other.chunks_[i];
3583 }
3584
3585 cover("kernel.rtlil.sigspec.comp_lt.equal");
3586 return false;
3587 }
3588
3589 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3590 {
3591 cover("kernel.rtlil.sigspec.comp_eq");
3592
3593 if (this == &other)
3594 return true;
3595
3596 if (width_ != other.width_)
3597 return false;
3598
3599 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3600 // since the RHS will contain one SigChunk of width 0 causing
3601 // the size check below to fail
3602 if (width_ == 0)
3603 return true;
3604
3605 pack();
3606 other.pack();
3607
3608 if (chunks_.size() != other.chunks_.size())
3609 return false;
3610
3611 updhash();
3612 other.updhash();
3613
3614 if (hash_ != other.hash_)
3615 return false;
3616
3617 for (size_t i = 0; i < chunks_.size(); i++)
3618 if (chunks_[i] != other.chunks_[i]) {
3619 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3620 return false;
3621 }
3622
3623 cover("kernel.rtlil.sigspec.comp_eq.equal");
3624 return true;
3625 }
3626
3627 bool RTLIL::SigSpec::is_wire() const
3628 {
3629 cover("kernel.rtlil.sigspec.is_wire");
3630
3631 pack();
3632 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3633 }
3634
3635 bool RTLIL::SigSpec::is_chunk() const
3636 {
3637 cover("kernel.rtlil.sigspec.is_chunk");
3638
3639 pack();
3640 return GetSize(chunks_) == 1;
3641 }
3642
3643 bool RTLIL::SigSpec::is_fully_const() const
3644 {
3645 cover("kernel.rtlil.sigspec.is_fully_const");
3646
3647 pack();
3648 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3649 if (it->width > 0 && it->wire != NULL)
3650 return false;
3651 return true;
3652 }
3653
3654 bool RTLIL::SigSpec::is_fully_zero() const
3655 {
3656 cover("kernel.rtlil.sigspec.is_fully_zero");
3657
3658 pack();
3659 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3660 if (it->width > 0 && it->wire != NULL)
3661 return false;
3662 for (size_t i = 0; i < it->data.size(); i++)
3663 if (it->data[i] != RTLIL::State::S0)
3664 return false;
3665 }
3666 return true;
3667 }
3668
3669 bool RTLIL::SigSpec::is_fully_ones() const
3670 {
3671 cover("kernel.rtlil.sigspec.is_fully_ones");
3672
3673 pack();
3674 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3675 if (it->width > 0 && it->wire != NULL)
3676 return false;
3677 for (size_t i = 0; i < it->data.size(); i++)
3678 if (it->data[i] != RTLIL::State::S1)
3679 return false;
3680 }
3681 return true;
3682 }
3683
3684 bool RTLIL::SigSpec::is_fully_def() const
3685 {
3686 cover("kernel.rtlil.sigspec.is_fully_def");
3687
3688 pack();
3689 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3690 if (it->width > 0 && it->wire != NULL)
3691 return false;
3692 for (size_t i = 0; i < it->data.size(); i++)
3693 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3694 return false;
3695 }
3696 return true;
3697 }
3698
3699 bool RTLIL::SigSpec::is_fully_undef() const
3700 {
3701 cover("kernel.rtlil.sigspec.is_fully_undef");
3702
3703 pack();
3704 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3705 if (it->width > 0 && it->wire != NULL)
3706 return false;
3707 for (size_t i = 0; i < it->data.size(); i++)
3708 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3709 return false;
3710 }
3711 return true;
3712 }
3713
3714 bool RTLIL::SigSpec::has_const() const
3715 {
3716 cover("kernel.rtlil.sigspec.has_const");
3717
3718 pack();
3719 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3720 if (it->width > 0 && it->wire == NULL)
3721 return true;
3722 return false;
3723 }
3724
3725 bool RTLIL::SigSpec::has_marked_bits() const
3726 {
3727 cover("kernel.rtlil.sigspec.has_marked_bits");
3728
3729 pack();
3730 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3731 if (it->width > 0 && it->wire == NULL) {
3732 for (size_t i = 0; i < it->data.size(); i++)
3733 if (it->data[i] == RTLIL::State::Sm)
3734 return true;
3735 }
3736 return false;
3737 }
3738
3739 bool RTLIL::SigSpec::as_bool() const
3740 {
3741 cover("kernel.rtlil.sigspec.as_bool");
3742
3743 pack();
3744 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3745 if (width_)
3746 return RTLIL::Const(chunks_[0].data).as_bool();
3747 return false;
3748 }
3749
3750 int RTLIL::SigSpec::as_int(bool is_signed) const
3751 {
3752 cover("kernel.rtlil.sigspec.as_int");
3753
3754 pack();
3755 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3756 if (width_)
3757 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3758 return 0;
3759 }
3760
3761 std::string RTLIL::SigSpec::as_string() const
3762 {
3763 cover("kernel.rtlil.sigspec.as_string");
3764
3765 pack();
3766 std::string str;
3767 for (size_t i = chunks_.size(); i > 0; i--) {
3768 const RTLIL::SigChunk &chunk = chunks_[i-1];
3769 if (chunk.wire != NULL)
3770 for (int j = 0; j < chunk.width; j++)
3771 str += "?";
3772 else
3773 str += RTLIL::Const(chunk.data).as_string();
3774 }
3775 return str;
3776 }
3777
3778 RTLIL::Const RTLIL::SigSpec::as_const() const
3779 {
3780 cover("kernel.rtlil.sigspec.as_const");
3781
3782 pack();
3783 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3784 if (width_)
3785 return chunks_[0].data;
3786 return RTLIL::Const();
3787 }
3788
3789 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3790 {
3791 cover("kernel.rtlil.sigspec.as_wire");
3792
3793 pack();
3794 log_assert(is_wire());
3795 return chunks_[0].wire;
3796 }
3797
3798 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3799 {
3800 cover("kernel.rtlil.sigspec.as_chunk");
3801
3802 pack();
3803 log_assert(is_chunk());
3804 return chunks_[0];
3805 }
3806
3807 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3808 {
3809 cover("kernel.rtlil.sigspec.as_bit");
3810
3811 log_assert(width_ == 1);
3812 if (packed())
3813 return RTLIL::SigBit(*chunks_.begin());
3814 else
3815 return bits_[0];
3816 }
3817
3818 bool RTLIL::SigSpec::match(std::string pattern) const
3819 {
3820 cover("kernel.rtlil.sigspec.match");
3821
3822 pack();
3823 std::string str = as_string();
3824 log_assert(pattern.size() == str.size());
3825
3826 for (size_t i = 0; i < pattern.size(); i++) {
3827 if (pattern[i] == ' ')
3828 continue;
3829 if (pattern[i] == '*') {
3830 if (str[i] != 'z' && str[i] != 'x')
3831 return false;
3832 continue;
3833 }
3834 if (pattern[i] != str[i])
3835 return false;
3836 }
3837
3838 return true;
3839 }
3840
3841 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3842 {
3843 cover("kernel.rtlil.sigspec.to_sigbit_set");
3844
3845 pack();
3846 std::set<RTLIL::SigBit> sigbits;
3847 for (auto &c : chunks_)
3848 for (int i = 0; i < c.width; i++)
3849 sigbits.insert(RTLIL::SigBit(c, i));
3850 return sigbits;
3851 }
3852
3853 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3854 {
3855 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3856
3857 pack();
3858 pool<RTLIL::SigBit> sigbits;
3859 for (auto &c : chunks_)
3860 for (int i = 0; i < c.width; i++)
3861 sigbits.insert(RTLIL::SigBit(c, i));
3862 return sigbits;
3863 }
3864
3865 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3866 {
3867 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3868
3869 unpack();
3870 return bits_;
3871 }
3872
3873 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3874 {
3875 cover("kernel.rtlil.sigspec.to_sigbit_map");
3876
3877 unpack();
3878 other.unpack();
3879
3880 log_assert(width_ == other.width_);
3881
3882 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3883 for (int i = 0; i < width_; i++)
3884 new_map[bits_[i]] = other.bits_[i];
3885
3886 return new_map;
3887 }
3888
3889 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3890 {
3891 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3892
3893 unpack();
3894 other.unpack();
3895
3896 log_assert(width_ == other.width_);
3897
3898 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3899 for (int i = 0; i < width_; i++)
3900 new_map[bits_[i]] = other.bits_[i];
3901
3902 return new_map;
3903 }
3904
3905 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3906 {
3907 size_t start = 0, end = 0;
3908 while ((end = text.find(sep, start)) != std::string::npos) {
3909 tokens.push_back(text.substr(start, end - start));
3910 start = end + 1;
3911 }
3912 tokens.push_back(text.substr(start));
3913 }
3914
3915 static int sigspec_parse_get_dummy_line_num()
3916 {
3917 return 0;
3918 }
3919
3920 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3921 {
3922 cover("kernel.rtlil.sigspec.parse");
3923
3924 AST::current_filename = "input";
3925
3926 std::vector<std::string> tokens;
3927 sigspec_parse_split(tokens, str, ',');
3928
3929 sig = RTLIL::SigSpec();
3930 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3931 {
3932 std::string netname = tokens[tokidx];
3933 std::string indices;
3934
3935 if (netname.size() == 0)
3936 continue;
3937
3938 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3939 cover("kernel.rtlil.sigspec.parse.const");
3940 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3941 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3942 if (ast == NULL)
3943 return false;
3944 sig.append(RTLIL::Const(ast->bits));
3945 delete ast;
3946 continue;
3947 }
3948
3949 if (module == NULL)
3950 return false;
3951
3952 cover("kernel.rtlil.sigspec.parse.net");
3953
3954 if (netname[0] != '$' && netname[0] != '\\')
3955 netname = "\\" + netname;
3956
3957 if (module->wires_.count(netname) == 0) {
3958 size_t indices_pos = netname.size()-1;
3959 if (indices_pos > 2 && netname[indices_pos] == ']')
3960 {
3961 indices_pos--;
3962 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3963 if (indices_pos > 0 && netname[indices_pos] == ':') {
3964 indices_pos--;
3965 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3966 }
3967 if (indices_pos > 0 && netname[indices_pos] == '[') {
3968 indices = netname.substr(indices_pos);
3969 netname = netname.substr(0, indices_pos);
3970 }
3971 }
3972 }
3973
3974 if (module->wires_.count(netname) == 0)
3975 return false;
3976
3977 RTLIL::Wire *wire = module->wires_.at(netname);
3978 if (!indices.empty()) {
3979 std::vector<std::string> index_tokens;
3980 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3981 if (index_tokens.size() == 1) {
3982 cover("kernel.rtlil.sigspec.parse.bit_sel");
3983 int a = atoi(index_tokens.at(0).c_str());
3984 if (a < 0 || a >= wire->width)
3985 return false;
3986 sig.append(RTLIL::SigSpec(wire, a));
3987 } else {
3988 cover("kernel.rtlil.sigspec.parse.part_sel");
3989 int a = atoi(index_tokens.at(0).c_str());
3990 int b = atoi(index_tokens.at(1).c_str());
3991 if (a > b) {
3992 int tmp = a;
3993 a = b, b = tmp;
3994 }
3995 if (a < 0 || a >= wire->width)
3996 return false;
3997 if (b < 0 || b >= wire->width)
3998 return false;
3999 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4000 }
4001 } else
4002 sig.append(wire);
4003 }
4004
4005 return true;
4006 }
4007
4008 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4009 {
4010 if (str.empty() || str[0] != '@')
4011 return parse(sig, module, str);
4012
4013 cover("kernel.rtlil.sigspec.parse.sel");
4014
4015 str = RTLIL::escape_id(str.substr(1));
4016 if (design->selection_vars.count(str) == 0)
4017 return false;
4018
4019 sig = RTLIL::SigSpec();
4020 RTLIL::Selection &sel = design->selection_vars.at(str);
4021 for (auto &it : module->wires_)
4022 if (sel.selected_member(module->name, it.first))
4023 sig.append(it.second);
4024
4025 return true;
4026 }
4027
4028 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4029 {
4030 if (str == "0") {
4031 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4032 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4033 return true;
4034 }
4035
4036 if (str == "~0") {
4037 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4038 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4039 return true;
4040 }
4041
4042 if (lhs.chunks_.size() == 1) {
4043 char *p = (char*)str.c_str(), *endptr;
4044 long int val = strtol(p, &endptr, 10);
4045 if (endptr && endptr != p && *endptr == 0) {
4046 sig = RTLIL::SigSpec(val, lhs.width_);
4047 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4048 return true;
4049 }
4050 }
4051
4052 return parse(sig, module, str);
4053 }
4054
4055 RTLIL::CaseRule::~CaseRule()
4056 {
4057 for (auto it = switches.begin(); it != switches.end(); it++)
4058 delete *it;
4059 }
4060
4061 bool RTLIL::CaseRule::empty() const
4062 {
4063 return actions.empty() && switches.empty();
4064 }
4065
4066 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4067 {
4068 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4069 new_caserule->compare = compare;
4070 new_caserule->actions = actions;
4071 for (auto &it : switches)
4072 new_caserule->switches.push_back(it->clone());
4073 return new_caserule;
4074 }
4075
4076 RTLIL::SwitchRule::~SwitchRule()
4077 {
4078 for (auto it = cases.begin(); it != cases.end(); it++)
4079 delete *it;
4080 }
4081
4082 bool RTLIL::SwitchRule::empty() const
4083 {
4084 return cases.empty();
4085 }
4086
4087 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4088 {
4089 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4090 new_switchrule->signal = signal;
4091 new_switchrule->attributes = attributes;
4092 for (auto &it : cases)
4093 new_switchrule->cases.push_back(it->clone());
4094 return new_switchrule;
4095
4096 }
4097
4098 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4099 {
4100 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4101 new_syncrule->type = type;
4102 new_syncrule->signal = signal;
4103 new_syncrule->actions = actions;
4104 return new_syncrule;
4105 }
4106
4107 RTLIL::Process::~Process()
4108 {
4109 for (auto it = syncs.begin(); it != syncs.end(); it++)
4110 delete *it;
4111 }
4112
4113 RTLIL::Process *RTLIL::Process::clone() const
4114 {
4115 RTLIL::Process *new_proc = new RTLIL::Process;
4116
4117 new_proc->name = name;
4118 new_proc->attributes = attributes;
4119
4120 RTLIL::CaseRule *rc_ptr = root_case.clone();
4121 new_proc->root_case = *rc_ptr;
4122 rc_ptr->switches.clear();
4123 delete rc_ptr;
4124
4125 for (auto &it : syncs)
4126 new_proc->syncs.push_back(it->clone());
4127
4128 return new_proc;
4129 }
4130
4131 #ifdef WITH_PYTHON
4132 RTLIL::Memory::~Memory()
4133 {
4134 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4135 }
4136 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4137 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4138 {
4139 return &all_memorys;
4140 }
4141 #endif
4142 YOSYS_NAMESPACE_END