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Added module->addDffe() and module->addDffeGate()
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "frontends/verilog/verilog_frontend.h"
23 #include "backends/ilang/ilang_backend.h"
24
25 #include <string.h>
26 #include <algorithm>
27
28 YOSYS_NAMESPACE_BEGIN
29
30 std::vector<int> RTLIL::IdString::global_refcount_storage_;
31 std::vector<char*> RTLIL::IdString::global_id_storage_;
32 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
33 std::vector<int> RTLIL::IdString::global_free_idx_list_;
34
35 RTLIL::Const::Const()
36 {
37 flags = RTLIL::CONST_FLAG_NONE;
38 }
39
40 RTLIL::Const::Const(std::string str)
41 {
42 flags = RTLIL::CONST_FLAG_STRING;
43 for (int i = str.size()-1; i >= 0; i--) {
44 unsigned char ch = str[i];
45 for (int j = 0; j < 8; j++) {
46 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
47 ch = ch >> 1;
48 }
49 }
50 }
51
52 RTLIL::Const::Const(int val, int width)
53 {
54 flags = RTLIL::CONST_FLAG_NONE;
55 for (int i = 0; i < width; i++) {
56 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
57 val = val >> 1;
58 }
59 }
60
61 RTLIL::Const::Const(RTLIL::State bit, int width)
62 {
63 flags = RTLIL::CONST_FLAG_NONE;
64 for (int i = 0; i < width; i++)
65 bits.push_back(bit);
66 }
67
68 RTLIL::Const::Const(const std::vector<bool> &bits)
69 {
70 flags = RTLIL::CONST_FLAG_NONE;
71 for (auto b : bits)
72 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
73 }
74
75 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
76 {
77 if (bits.size() != other.bits.size())
78 return bits.size() < other.bits.size();
79 for (size_t i = 0; i < bits.size(); i++)
80 if (bits[i] != other.bits[i])
81 return bits[i] < other.bits[i];
82 return false;
83 }
84
85 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
86 {
87 return bits == other.bits;
88 }
89
90 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
91 {
92 return bits != other.bits;
93 }
94
95 bool RTLIL::Const::as_bool() const
96 {
97 for (size_t i = 0; i < bits.size(); i++)
98 if (bits[i] == RTLIL::S1)
99 return true;
100 return false;
101 }
102
103 int RTLIL::Const::as_int(bool is_signed) const
104 {
105 int32_t ret = 0;
106 for (size_t i = 0; i < bits.size() && i < 32; i++)
107 if (bits[i] == RTLIL::S1)
108 ret |= 1 << i;
109 if (is_signed && bits.back() == RTLIL::S1)
110 for (size_t i = bits.size(); i < 32; i++)
111 ret |= 1 << i;
112 return ret;
113 }
114
115 std::string RTLIL::Const::as_string() const
116 {
117 std::string ret;
118 for (size_t i = bits.size(); i > 0; i--)
119 switch (bits[i-1]) {
120 case S0: ret += "0"; break;
121 case S1: ret += "1"; break;
122 case Sx: ret += "x"; break;
123 case Sz: ret += "z"; break;
124 case Sa: ret += "-"; break;
125 case Sm: ret += "m"; break;
126 }
127 return ret;
128 }
129
130 std::string RTLIL::Const::decode_string() const
131 {
132 std::string string;
133 std::vector <char> string_chars;
134 for (int i = 0; i < int (bits.size()); i += 8) {
135 char ch = 0;
136 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
137 if (bits[i + j] == RTLIL::State::S1)
138 ch |= 1 << j;
139 if (ch != 0)
140 string_chars.push_back(ch);
141 }
142 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
143 string += string_chars[i];
144 return string;
145 }
146
147 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
148 {
149 if (full_selection)
150 return true;
151 if (selected_modules.count(mod_name) > 0)
152 return true;
153 if (selected_members.count(mod_name) > 0)
154 return true;
155 return false;
156 }
157
158 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
159 {
160 if (full_selection)
161 return true;
162 if (selected_modules.count(mod_name) > 0)
163 return true;
164 return false;
165 }
166
167 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
168 {
169 if (full_selection)
170 return true;
171 if (selected_modules.count(mod_name) > 0)
172 return true;
173 if (selected_members.count(mod_name) > 0)
174 if (selected_members.at(mod_name).count(memb_name) > 0)
175 return true;
176 return false;
177 }
178
179 void RTLIL::Selection::optimize(RTLIL::Design *design)
180 {
181 if (full_selection) {
182 selected_modules.clear();
183 selected_members.clear();
184 return;
185 }
186
187 std::vector<RTLIL::IdString> del_list, add_list;
188
189 del_list.clear();
190 for (auto mod_name : selected_modules) {
191 if (design->modules_.count(mod_name) == 0)
192 del_list.push_back(mod_name);
193 selected_members.erase(mod_name);
194 }
195 for (auto mod_name : del_list)
196 selected_modules.erase(mod_name);
197
198 del_list.clear();
199 for (auto &it : selected_members)
200 if (design->modules_.count(it.first) == 0)
201 del_list.push_back(it.first);
202 for (auto mod_name : del_list)
203 selected_members.erase(mod_name);
204
205 for (auto &it : selected_members) {
206 del_list.clear();
207 for (auto memb_name : it.second)
208 if (design->modules_[it.first]->count_id(memb_name) == 0)
209 del_list.push_back(memb_name);
210 for (auto memb_name : del_list)
211 it.second.erase(memb_name);
212 }
213
214 del_list.clear();
215 add_list.clear();
216 for (auto &it : selected_members)
217 if (it.second.size() == 0)
218 del_list.push_back(it.first);
219 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
220 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
221 add_list.push_back(it.first);
222 for (auto mod_name : del_list)
223 selected_members.erase(mod_name);
224 for (auto mod_name : add_list) {
225 selected_members.erase(mod_name);
226 selected_modules.insert(mod_name);
227 }
228
229 if (selected_modules.size() == design->modules_.size()) {
230 full_selection = true;
231 selected_modules.clear();
232 selected_members.clear();
233 }
234 }
235
236 RTLIL::Design::Design()
237 {
238 refcount_modules_ = 0;
239 selection_stack.push_back(RTLIL::Selection());
240 }
241
242 RTLIL::Design::~Design()
243 {
244 for (auto it = modules_.begin(); it != modules_.end(); it++)
245 delete it->second;
246 }
247
248 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
249 {
250 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
251 }
252
253 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
254 {
255 return modules_.count(name) ? modules_.at(name) : NULL;
256 }
257
258 void RTLIL::Design::add(RTLIL::Module *module)
259 {
260 log_assert(modules_.count(module->name) == 0);
261 log_assert(refcount_modules_ == 0);
262 modules_[module->name] = module;
263 module->design = this;
264
265 for (auto mon : monitors)
266 mon->notify_module_add(module);
267 }
268
269 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
270 {
271 log_assert(modules_.count(name) == 0);
272 log_assert(refcount_modules_ == 0);
273
274 RTLIL::Module *module = new RTLIL::Module;
275 modules_[name] = module;
276 module->design = this;
277 module->name = name;
278
279 for (auto mon : monitors)
280 mon->notify_module_add(module);
281
282 return module;
283 }
284
285 void RTLIL::Design::scratchpad_unset(std::string varname)
286 {
287 scratchpad.erase(varname);
288 }
289
290 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
291 {
292 scratchpad[varname] = stringf("%d", value);
293 }
294
295 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
296 {
297 scratchpad[varname] = value ? "true" : "false";
298 }
299
300 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
301 {
302 scratchpad[varname] = value;
303 }
304
305 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
306 {
307 if (scratchpad.count(varname) == 0)
308 return default_value;
309
310 std::string str = scratchpad.at(varname);
311
312 if (str == "0" || str == "false")
313 return 0;
314
315 if (str == "1" || str == "true")
316 return 1;
317
318 char *endptr = nullptr;
319 long int parsed_value = strtol(str.c_str(), &endptr, 10);
320 return *endptr ? default_value : parsed_value;
321 }
322
323 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
324 {
325 if (scratchpad.count(varname) == 0)
326 return default_value;
327
328 std::string str = scratchpad.at(varname);
329
330 if (str == "0" || str == "false")
331 return false;
332
333 if (str == "1" || str == "true")
334 return true;
335
336 return default_value;
337 }
338
339 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
340 {
341 if (scratchpad.count(varname) == 0)
342 return default_value;
343 return scratchpad.at(varname);
344 }
345
346 void RTLIL::Design::remove(RTLIL::Module *module)
347 {
348 for (auto mon : monitors)
349 mon->notify_module_del(module);
350
351 log_assert(modules_.at(module->name) == module);
352 modules_.erase(module->name);
353 delete module;
354 }
355
356 void RTLIL::Design::check()
357 {
358 #ifndef NDEBUG
359 for (auto &it : modules_) {
360 log_assert(this == it.second->design);
361 log_assert(it.first == it.second->name);
362 log_assert(!it.first.empty());
363 it.second->check();
364 }
365 #endif
366 }
367
368 void RTLIL::Design::optimize()
369 {
370 for (auto &it : modules_)
371 it.second->optimize();
372 for (auto &it : selection_stack)
373 it.optimize(this);
374 for (auto &it : selection_vars)
375 it.second.optimize(this);
376 }
377
378 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
379 {
380 if (!selected_active_module.empty() && mod_name != selected_active_module)
381 return false;
382 if (selection_stack.size() == 0)
383 return true;
384 return selection_stack.back().selected_module(mod_name);
385 }
386
387 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
388 {
389 if (!selected_active_module.empty() && mod_name != selected_active_module)
390 return false;
391 if (selection_stack.size() == 0)
392 return true;
393 return selection_stack.back().selected_whole_module(mod_name);
394 }
395
396 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
397 {
398 if (!selected_active_module.empty() && mod_name != selected_active_module)
399 return false;
400 if (selection_stack.size() == 0)
401 return true;
402 return selection_stack.back().selected_member(mod_name, memb_name);
403 }
404
405 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
406 {
407 return selected_module(mod->name);
408 }
409
410 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
411 {
412 return selected_whole_module(mod->name);
413 }
414
415 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
416 {
417 std::vector<RTLIL::Module*> result;
418 result.reserve(modules_.size());
419 for (auto &it : modules_)
420 if (selected_module(it.first))
421 result.push_back(it.second);
422 return result;
423 }
424
425 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
426 {
427 std::vector<RTLIL::Module*> result;
428 result.reserve(modules_.size());
429 for (auto &it : modules_)
430 if (selected_whole_module(it.first))
431 result.push_back(it.second);
432 return result;
433 }
434
435 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
436 {
437 std::vector<RTLIL::Module*> result;
438 result.reserve(modules_.size());
439 for (auto &it : modules_)
440 if (selected_whole_module(it.first))
441 result.push_back(it.second);
442 else if (selected_module(it.first))
443 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
444 return result;
445 }
446
447 RTLIL::Module::Module()
448 {
449 design = nullptr;
450 refcount_wires_ = 0;
451 refcount_cells_ = 0;
452 }
453
454 RTLIL::Module::~Module()
455 {
456 for (auto it = wires_.begin(); it != wires_.end(); it++)
457 delete it->second;
458 for (auto it = memories.begin(); it != memories.end(); it++)
459 delete it->second;
460 for (auto it = cells_.begin(); it != cells_.end(); it++)
461 delete it->second;
462 for (auto it = processes.begin(); it != processes.end(); it++)
463 delete it->second;
464 }
465
466 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
467 {
468 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
469 }
470
471 size_t RTLIL::Module::count_id(RTLIL::IdString id)
472 {
473 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
474 }
475
476 #ifndef NDEBUG
477 namespace {
478 struct InternalCellChecker
479 {
480 RTLIL::Module *module;
481 RTLIL::Cell *cell;
482 std::set<RTLIL::IdString> expected_params, expected_ports;
483
484 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
485
486 void error(int linenr)
487 {
488 std::stringstream buf;
489 ILANG_BACKEND::dump_cell(buf, " ", cell);
490
491 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
492 module ? module->name.c_str() : "", module ? "." : "",
493 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
494 }
495
496 int param(const char *name)
497 {
498 if (cell->parameters.count(name) == 0)
499 error(__LINE__);
500 expected_params.insert(name);
501 return cell->parameters.at(name).as_int();
502 }
503
504 int param_bool(const char *name)
505 {
506 int v = param(name);
507 if (cell->parameters.at(name).bits.size() > 32)
508 error(__LINE__);
509 if (v != 0 && v != 1)
510 error(__LINE__);
511 return v;
512 }
513
514 void param_bits(const char *name, int width)
515 {
516 param(name);
517 if (int(cell->parameters.at(name).bits.size()) != width)
518 error(__LINE__);
519 }
520
521 void port(const char *name, int width)
522 {
523 if (!cell->hasPort(name))
524 error(__LINE__);
525 if (cell->getPort(name).size() != width)
526 error(__LINE__);
527 expected_ports.insert(name);
528 }
529
530 void check_expected(bool check_matched_sign = true)
531 {
532 for (auto &para : cell->parameters)
533 if (expected_params.count(para.first) == 0)
534 error(__LINE__);
535 for (auto &conn : cell->connections())
536 if (expected_ports.count(conn.first) == 0)
537 error(__LINE__);
538
539 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
540 bool a_is_signed = param("\\A_SIGNED") != 0;
541 bool b_is_signed = param("\\B_SIGNED") != 0;
542 if (a_is_signed != b_is_signed)
543 error(__LINE__);
544 }
545 }
546
547 void check_gate(const char *ports)
548 {
549 if (cell->parameters.size() != 0)
550 error(__LINE__);
551
552 for (const char *p = ports; *p; p++) {
553 char portname[3] = { '\\', *p, 0 };
554 if (!cell->hasPort(portname))
555 error(__LINE__);
556 if (cell->getPort(portname).size() != 1)
557 error(__LINE__);
558 }
559
560 for (auto &conn : cell->connections()) {
561 if (conn.first.size() != 2 || conn.first[0] != '\\')
562 error(__LINE__);
563 if (strchr(ports, conn.first[1]) == NULL)
564 error(__LINE__);
565 }
566 }
567
568 void check()
569 {
570 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
571 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
572 return;
573
574 if (cell->type.in("$not", "$pos", "$neg")) {
575 param_bool("\\A_SIGNED");
576 port("\\A", param("\\A_WIDTH"));
577 port("\\Y", param("\\Y_WIDTH"));
578 check_expected();
579 return;
580 }
581
582 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
583 param_bool("\\A_SIGNED");
584 param_bool("\\B_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\B", param("\\B_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 check_expected();
589 return;
590 }
591
592 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
593 param_bool("\\A_SIGNED");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\Y", param("\\Y_WIDTH"));
596 check_expected();
597 return;
598 }
599
600 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
601 param_bool("\\A_SIGNED");
602 param_bool("\\B_SIGNED");
603 port("\\A", param("\\A_WIDTH"));
604 port("\\B", param("\\B_WIDTH"));
605 port("\\Y", param("\\Y_WIDTH"));
606 check_expected(false);
607 return;
608 }
609
610 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
611 param_bool("\\A_SIGNED");
612 param_bool("\\B_SIGNED");
613 port("\\A", param("\\A_WIDTH"));
614 port("\\B", param("\\B_WIDTH"));
615 port("\\Y", param("\\Y_WIDTH"));
616 check_expected();
617 return;
618 }
619
620 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
621 param_bool("\\A_SIGNED");
622 param_bool("\\B_SIGNED");
623 port("\\A", param("\\A_WIDTH"));
624 port("\\B", param("\\B_WIDTH"));
625 port("\\Y", param("\\Y_WIDTH"));
626 check_expected(cell->type != "$pow");
627 return;
628 }
629
630 if (cell->type == "$fa") {
631 port("\\A", param("\\WIDTH"));
632 port("\\B", param("\\WIDTH"));
633 port("\\C", param("\\WIDTH"));
634 port("\\X", param("\\WIDTH"));
635 port("\\Y", param("\\WIDTH"));
636 check_expected();
637 return;
638 }
639
640 if (cell->type == "$lcu") {
641 port("\\P", param("\\WIDTH"));
642 port("\\G", param("\\WIDTH"));
643 port("\\CI", 1);
644 port("\\CO", param("\\WIDTH"));
645 check_expected();
646 return;
647 }
648
649 if (cell->type == "$alu") {
650 param_bool("\\A_SIGNED");
651 param_bool("\\B_SIGNED");
652 port("\\A", param("\\A_WIDTH"));
653 port("\\B", param("\\B_WIDTH"));
654 port("\\CI", 1);
655 port("\\BI", 1);
656 port("\\X", param("\\Y_WIDTH"));
657 port("\\Y", param("\\Y_WIDTH"));
658 port("\\CO", param("\\Y_WIDTH"));
659 check_expected();
660 return;
661 }
662
663 if (cell->type == "$macc") {
664 param("\\CONFIG");
665 param("\\CONFIG_WIDTH");
666 port("\\A", param("\\A_WIDTH"));
667 port("\\B", param("\\B_WIDTH"));
668 port("\\Y", param("\\Y_WIDTH"));
669 check_expected();
670 Macc().from_cell(cell);
671 return;
672 }
673
674 if (cell->type == "$logic_not") {
675 param_bool("\\A_SIGNED");
676 port("\\A", param("\\A_WIDTH"));
677 port("\\Y", param("\\Y_WIDTH"));
678 check_expected();
679 return;
680 }
681
682 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
683 param_bool("\\A_SIGNED");
684 param_bool("\\B_SIGNED");
685 port("\\A", param("\\A_WIDTH"));
686 port("\\B", param("\\B_WIDTH"));
687 port("\\Y", param("\\Y_WIDTH"));
688 check_expected(false);
689 return;
690 }
691
692 if (cell->type == "$slice") {
693 param("\\OFFSET");
694 port("\\A", param("\\A_WIDTH"));
695 port("\\Y", param("\\Y_WIDTH"));
696 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
697 error(__LINE__);
698 check_expected();
699 return;
700 }
701
702 if (cell->type == "$concat") {
703 port("\\A", param("\\A_WIDTH"));
704 port("\\B", param("\\B_WIDTH"));
705 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
706 check_expected();
707 return;
708 }
709
710 if (cell->type == "$mux") {
711 port("\\A", param("\\WIDTH"));
712 port("\\B", param("\\WIDTH"));
713 port("\\S", 1);
714 port("\\Y", param("\\WIDTH"));
715 check_expected();
716 return;
717 }
718
719 if (cell->type == "$pmux") {
720 port("\\A", param("\\WIDTH"));
721 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
722 port("\\S", param("\\S_WIDTH"));
723 port("\\Y", param("\\WIDTH"));
724 check_expected();
725 return;
726 }
727
728 if (cell->type == "$lut") {
729 param("\\LUT");
730 port("\\A", param("\\WIDTH"));
731 port("\\Y", 1);
732 check_expected();
733 return;
734 }
735
736 if (cell->type == "$sr") {
737 param_bool("\\SET_POLARITY");
738 param_bool("\\CLR_POLARITY");
739 port("\\SET", param("\\WIDTH"));
740 port("\\CLR", param("\\WIDTH"));
741 port("\\Q", param("\\WIDTH"));
742 check_expected();
743 return;
744 }
745
746 if (cell->type == "$dff") {
747 param_bool("\\CLK_POLARITY");
748 port("\\CLK", 1);
749 port("\\D", param("\\WIDTH"));
750 port("\\Q", param("\\WIDTH"));
751 check_expected();
752 return;
753 }
754
755 if (cell->type == "$dffe") {
756 param_bool("\\CLK_POLARITY");
757 param_bool("\\EN_POLARITY");
758 port("\\CLK", 1);
759 port("\\EN", 1);
760 port("\\D", param("\\WIDTH"));
761 port("\\Q", param("\\WIDTH"));
762 check_expected();
763 return;
764 }
765
766 if (cell->type == "$dffsr") {
767 param_bool("\\CLK_POLARITY");
768 param_bool("\\SET_POLARITY");
769 param_bool("\\CLR_POLARITY");
770 port("\\CLK", 1);
771 port("\\SET", param("\\WIDTH"));
772 port("\\CLR", param("\\WIDTH"));
773 port("\\D", param("\\WIDTH"));
774 port("\\Q", param("\\WIDTH"));
775 check_expected();
776 return;
777 }
778
779 if (cell->type == "$adff") {
780 param_bool("\\CLK_POLARITY");
781 param_bool("\\ARST_POLARITY");
782 param_bits("\\ARST_VALUE", param("\\WIDTH"));
783 port("\\CLK", 1);
784 port("\\ARST", 1);
785 port("\\D", param("\\WIDTH"));
786 port("\\Q", param("\\WIDTH"));
787 check_expected();
788 return;
789 }
790
791 if (cell->type == "$dlatch") {
792 param_bool("\\EN_POLARITY");
793 port("\\EN", 1);
794 port("\\D", param("\\WIDTH"));
795 port("\\Q", param("\\WIDTH"));
796 check_expected();
797 return;
798 }
799
800 if (cell->type == "$dlatchsr") {
801 param_bool("\\EN_POLARITY");
802 param_bool("\\SET_POLARITY");
803 param_bool("\\CLR_POLARITY");
804 port("\\EN", 1);
805 port("\\SET", param("\\WIDTH"));
806 port("\\CLR", param("\\WIDTH"));
807 port("\\D", param("\\WIDTH"));
808 port("\\Q", param("\\WIDTH"));
809 check_expected();
810 return;
811 }
812
813 if (cell->type == "$fsm") {
814 param("\\NAME");
815 param_bool("\\CLK_POLARITY");
816 param_bool("\\ARST_POLARITY");
817 param("\\STATE_BITS");
818 param("\\STATE_NUM");
819 param("\\STATE_NUM_LOG2");
820 param("\\STATE_RST");
821 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
822 param("\\TRANS_NUM");
823 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
824 port("\\CLK", 1);
825 port("\\ARST", 1);
826 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
827 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
828 check_expected();
829 return;
830 }
831
832 if (cell->type == "$memrd") {
833 param("\\MEMID");
834 param_bool("\\CLK_ENABLE");
835 param_bool("\\CLK_POLARITY");
836 param_bool("\\TRANSPARENT");
837 port("\\CLK", 1);
838 port("\\ADDR", param("\\ABITS"));
839 port("\\DATA", param("\\WIDTH"));
840 check_expected();
841 return;
842 }
843
844 if (cell->type == "$memwr") {
845 param("\\MEMID");
846 param_bool("\\CLK_ENABLE");
847 param_bool("\\CLK_POLARITY");
848 param("\\PRIORITY");
849 port("\\CLK", 1);
850 port("\\EN", param("\\WIDTH"));
851 port("\\ADDR", param("\\ABITS"));
852 port("\\DATA", param("\\WIDTH"));
853 check_expected();
854 return;
855 }
856
857 if (cell->type == "$mem") {
858 param("\\MEMID");
859 param("\\SIZE");
860 param("\\OFFSET");
861 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
862 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
863 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
864 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
865 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
866 port("\\RD_CLK", param("\\RD_PORTS"));
867 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
868 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
869 port("\\WR_CLK", param("\\WR_PORTS"));
870 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
871 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
872 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
873 check_expected();
874 return;
875 }
876
877 if (cell->type == "$assert") {
878 port("\\A", 1);
879 port("\\EN", 1);
880 check_expected();
881 return;
882 }
883
884 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
885 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
886 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
887 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
888 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
889 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
890 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
891 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
892 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
893 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
894 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
895 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
896 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
897
898 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
899 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
900 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
901 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
902
903 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
904 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
905
906 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
907 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
908 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
909 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
910
911 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
912 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
913 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
914 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
915 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
916 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
917 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
918 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
919
920 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
921 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
922 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
923 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
924 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
925 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
926 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
927 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
928
929 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
930 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
931
932 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
933 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
934 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
935 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
936 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
937 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
938 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
939 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
940
941 error(__LINE__);
942 }
943 };
944 }
945 #endif
946
947 void RTLIL::Module::check()
948 {
949 #ifndef NDEBUG
950 std::vector<bool> ports_declared;
951 for (auto &it : wires_) {
952 log_assert(this == it.second->module);
953 log_assert(it.first == it.second->name);
954 log_assert(!it.first.empty());
955 log_assert(it.second->width >= 0);
956 log_assert(it.second->port_id >= 0);
957 for (auto &it2 : it.second->attributes)
958 log_assert(!it2.first.empty());
959 if (it.second->port_id) {
960 log_assert(GetSize(ports) >= it.second->port_id);
961 log_assert(ports.at(it.second->port_id-1) == it.first);
962 log_assert(it.second->port_input || it.second->port_output);
963 if (GetSize(ports_declared) < it.second->port_id)
964 ports_declared.resize(it.second->port_id);
965 log_assert(ports_declared[it.second->port_id-1] == false);
966 ports_declared[it.second->port_id-1] = true;
967 } else
968 log_assert(!it.second->port_input && !it.second->port_output);
969 }
970 for (auto port_declared : ports_declared)
971 log_assert(port_declared == true);
972 log_assert(GetSize(ports) == GetSize(ports_declared));
973
974 for (auto &it : memories) {
975 log_assert(it.first == it.second->name);
976 log_assert(!it.first.empty());
977 log_assert(it.second->width >= 0);
978 log_assert(it.second->size >= 0);
979 for (auto &it2 : it.second->attributes)
980 log_assert(!it2.first.empty());
981 }
982
983 for (auto &it : cells_) {
984 log_assert(this == it.second->module);
985 log_assert(it.first == it.second->name);
986 log_assert(!it.first.empty());
987 log_assert(!it.second->type.empty());
988 for (auto &it2 : it.second->connections()) {
989 log_assert(!it2.first.empty());
990 it2.second.check();
991 }
992 for (auto &it2 : it.second->attributes)
993 log_assert(!it2.first.empty());
994 for (auto &it2 : it.second->parameters)
995 log_assert(!it2.first.empty());
996 InternalCellChecker checker(this, it.second);
997 checker.check();
998 }
999
1000 for (auto &it : processes) {
1001 log_assert(it.first == it.second->name);
1002 log_assert(!it.first.empty());
1003 // FIXME: More checks here..
1004 }
1005
1006 for (auto &it : connections_) {
1007 log_assert(it.first.size() == it.second.size());
1008 it.first.check();
1009 it.second.check();
1010 }
1011
1012 for (auto &it : attributes)
1013 log_assert(!it.first.empty());
1014 #endif
1015 }
1016
1017 void RTLIL::Module::optimize()
1018 {
1019 }
1020
1021 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1022 {
1023 log_assert(new_mod->refcount_wires_ == 0);
1024 log_assert(new_mod->refcount_cells_ == 0);
1025
1026 new_mod->connections_ = connections_;
1027 new_mod->attributes = attributes;
1028
1029 for (auto &it : wires_)
1030 new_mod->addWire(it.first, it.second);
1031
1032 for (auto &it : memories)
1033 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1034
1035 for (auto &it : cells_)
1036 new_mod->addCell(it.first, it.second);
1037
1038 for (auto &it : processes)
1039 new_mod->processes[it.first] = it.second->clone();
1040
1041 struct RewriteSigSpecWorker
1042 {
1043 RTLIL::Module *mod;
1044 void operator()(RTLIL::SigSpec &sig)
1045 {
1046 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1047 for (auto &c : chunks)
1048 if (c.wire != NULL)
1049 c.wire = mod->wires_.at(c.wire->name);
1050 sig = chunks;
1051 }
1052 };
1053
1054 RewriteSigSpecWorker rewriteSigSpecWorker;
1055 rewriteSigSpecWorker.mod = new_mod;
1056 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1057 new_mod->fixup_ports();
1058 }
1059
1060 RTLIL::Module *RTLIL::Module::clone() const
1061 {
1062 RTLIL::Module *new_mod = new RTLIL::Module;
1063 new_mod->name = name;
1064 cloneInto(new_mod);
1065 return new_mod;
1066 }
1067
1068 bool RTLIL::Module::has_memories() const
1069 {
1070 return !memories.empty();
1071 }
1072
1073 bool RTLIL::Module::has_processes() const
1074 {
1075 return !processes.empty();
1076 }
1077
1078 bool RTLIL::Module::has_memories_warn() const
1079 {
1080 if (!memories.empty())
1081 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1082 return !memories.empty();
1083 }
1084
1085 bool RTLIL::Module::has_processes_warn() const
1086 {
1087 if (!processes.empty())
1088 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1089 return !processes.empty();
1090 }
1091
1092 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1093 {
1094 std::vector<RTLIL::Wire*> result;
1095 result.reserve(wires_.size());
1096 for (auto &it : wires_)
1097 if (design->selected(this, it.second))
1098 result.push_back(it.second);
1099 return result;
1100 }
1101
1102 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1103 {
1104 std::vector<RTLIL::Cell*> result;
1105 result.reserve(wires_.size());
1106 for (auto &it : cells_)
1107 if (design->selected(this, it.second))
1108 result.push_back(it.second);
1109 return result;
1110 }
1111
1112 void RTLIL::Module::add(RTLIL::Wire *wire)
1113 {
1114 log_assert(!wire->name.empty());
1115 log_assert(count_id(wire->name) == 0);
1116 log_assert(refcount_wires_ == 0);
1117 wires_[wire->name] = wire;
1118 wire->module = this;
1119 }
1120
1121 void RTLIL::Module::add(RTLIL::Cell *cell)
1122 {
1123 log_assert(!cell->name.empty());
1124 log_assert(count_id(cell->name) == 0);
1125 log_assert(refcount_cells_ == 0);
1126 cells_[cell->name] = cell;
1127 cell->module = this;
1128 }
1129
1130 namespace {
1131 struct DeleteWireWorker
1132 {
1133 RTLIL::Module *module;
1134 const std::set<RTLIL::Wire*> *wires_p;
1135
1136 void operator()(RTLIL::SigSpec &sig) {
1137 std::vector<RTLIL::SigChunk> chunks = sig;
1138 for (auto &c : chunks)
1139 if (c.wire != NULL && wires_p->count(c.wire)) {
1140 c.wire = module->addWire(NEW_ID, c.width);
1141 c.offset = 0;
1142 }
1143 sig = chunks;
1144 }
1145 };
1146 }
1147
1148 #if 0
1149 void RTLIL::Module::remove(RTLIL::Wire *wire)
1150 {
1151 std::setPort<RTLIL::Wire*> wires_;
1152 wires_.insert(wire);
1153 remove(wires_);
1154 }
1155 #endif
1156
1157 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1158 {
1159 log_assert(refcount_wires_ == 0);
1160
1161 DeleteWireWorker delete_wire_worker;
1162 delete_wire_worker.module = this;
1163 delete_wire_worker.wires_p = &wires;
1164 rewrite_sigspecs(delete_wire_worker);
1165
1166 for (auto &it : wires) {
1167 log_assert(wires_.count(it->name) != 0);
1168 wires_.erase(it->name);
1169 delete it;
1170 }
1171 }
1172
1173 void RTLIL::Module::remove(RTLIL::Cell *cell)
1174 {
1175 while (!cell->connections_.empty())
1176 cell->unsetPort(cell->connections_.begin()->first);
1177
1178 log_assert(cells_.count(cell->name) != 0);
1179 log_assert(refcount_cells_ == 0);
1180 cells_.erase(cell->name);
1181 delete cell;
1182 }
1183
1184 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1185 {
1186 log_assert(wires_[wire->name] == wire);
1187 log_assert(refcount_wires_ == 0);
1188 wires_.erase(wire->name);
1189 wire->name = new_name;
1190 add(wire);
1191 }
1192
1193 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1194 {
1195 log_assert(cells_[cell->name] == cell);
1196 log_assert(refcount_wires_ == 0);
1197 cells_.erase(cell->name);
1198 cell->name = new_name;
1199 add(cell);
1200 }
1201
1202 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1203 {
1204 log_assert(count_id(old_name) != 0);
1205 if (wires_.count(old_name))
1206 rename(wires_.at(old_name), new_name);
1207 else if (cells_.count(old_name))
1208 rename(cells_.at(old_name), new_name);
1209 else
1210 log_abort();
1211 }
1212
1213 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1214 {
1215 log_assert(wires_[w1->name] == w1);
1216 log_assert(wires_[w2->name] == w2);
1217 log_assert(refcount_wires_ == 0);
1218
1219 wires_.erase(w1->name);
1220 wires_.erase(w2->name);
1221
1222 std::swap(w1->name, w2->name);
1223
1224 wires_[w1->name] = w1;
1225 wires_[w2->name] = w2;
1226 }
1227
1228 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1229 {
1230 log_assert(cells_[c1->name] == c1);
1231 log_assert(cells_[c2->name] == c2);
1232 log_assert(refcount_cells_ == 0);
1233
1234 cells_.erase(c1->name);
1235 cells_.erase(c2->name);
1236
1237 std::swap(c1->name, c2->name);
1238
1239 cells_[c1->name] = c1;
1240 cells_[c2->name] = c2;
1241 }
1242
1243 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1244 {
1245 int index = 0;
1246 return uniquify(name, index);
1247 }
1248
1249 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1250 {
1251 if (index == 0) {
1252 if (count_id(name) == 0)
1253 return name;
1254 index++;
1255 }
1256
1257 while (1) {
1258 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1259 if (count_id(new_name) == 0)
1260 return new_name;
1261 index++;
1262 }
1263 }
1264
1265 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1266 {
1267 if (a->port_id && !b->port_id)
1268 return true;
1269 if (!a->port_id && b->port_id)
1270 return false;
1271
1272 if (a->port_id == b->port_id)
1273 return a->name < b->name;
1274 return a->port_id < b->port_id;
1275 }
1276
1277 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1278 {
1279 for (auto mon : monitors)
1280 mon->notify_connect(this, conn);
1281
1282 if (design)
1283 for (auto mon : design->monitors)
1284 mon->notify_connect(this, conn);
1285
1286 connections_.push_back(conn);
1287 }
1288
1289 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1290 {
1291 connect(RTLIL::SigSig(lhs, rhs));
1292 }
1293
1294 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1295 {
1296 for (auto mon : monitors)
1297 mon->notify_connect(this, new_conn);
1298
1299 if (design)
1300 for (auto mon : design->monitors)
1301 mon->notify_connect(this, new_conn);
1302
1303 connections_ = new_conn;
1304 }
1305
1306 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1307 {
1308 return connections_;
1309 }
1310
1311 void RTLIL::Module::fixup_ports()
1312 {
1313 std::vector<RTLIL::Wire*> all_ports;
1314
1315 for (auto &w : wires_)
1316 if (w.second->port_input || w.second->port_output)
1317 all_ports.push_back(w.second);
1318 else
1319 w.second->port_id = 0;
1320
1321 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1322
1323 ports.clear();
1324 for (size_t i = 0; i < all_ports.size(); i++) {
1325 ports.push_back(all_ports[i]->name);
1326 all_ports[i]->port_id = i+1;
1327 }
1328 }
1329
1330 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1331 {
1332 RTLIL::Wire *wire = new RTLIL::Wire;
1333 wire->name = name;
1334 wire->width = width;
1335 add(wire);
1336 return wire;
1337 }
1338
1339 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1340 {
1341 RTLIL::Wire *wire = addWire(name);
1342 wire->width = other->width;
1343 wire->start_offset = other->start_offset;
1344 wire->port_id = other->port_id;
1345 wire->port_input = other->port_input;
1346 wire->port_output = other->port_output;
1347 wire->upto = other->upto;
1348 wire->attributes = other->attributes;
1349 return wire;
1350 }
1351
1352 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1353 {
1354 RTLIL::Cell *cell = new RTLIL::Cell;
1355 cell->name = name;
1356 cell->type = type;
1357 add(cell);
1358 return cell;
1359 }
1360
1361 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1362 {
1363 RTLIL::Cell *cell = addCell(name, other->type);
1364 cell->connections_ = other->connections_;
1365 cell->parameters = other->parameters;
1366 cell->attributes = other->attributes;
1367 return cell;
1368 }
1369
1370 #define DEF_METHOD(_func, _y_size, _type) \
1371 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1372 RTLIL::Cell *cell = addCell(name, _type); \
1373 cell->parameters["\\A_SIGNED"] = is_signed; \
1374 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1375 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1376 cell->setPort("\\A", sig_a); \
1377 cell->setPort("\\Y", sig_y); \
1378 return cell; \
1379 } \
1380 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1381 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1382 add ## _func(name, sig_a, sig_y, is_signed); \
1383 return sig_y; \
1384 }
1385 DEF_METHOD(Not, sig_a.size(), "$not")
1386 DEF_METHOD(Pos, sig_a.size(), "$pos")
1387 DEF_METHOD(Neg, sig_a.size(), "$neg")
1388 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1389 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1390 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1391 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1392 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1393 DEF_METHOD(LogicNot, 1, "$logic_not")
1394 #undef DEF_METHOD
1395
1396 #define DEF_METHOD(_func, _y_size, _type) \
1397 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1398 RTLIL::Cell *cell = addCell(name, _type); \
1399 cell->parameters["\\A_SIGNED"] = is_signed; \
1400 cell->parameters["\\B_SIGNED"] = is_signed; \
1401 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1402 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1403 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1404 cell->setPort("\\A", sig_a); \
1405 cell->setPort("\\B", sig_b); \
1406 cell->setPort("\\Y", sig_y); \
1407 return cell; \
1408 } \
1409 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1410 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1411 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1412 return sig_y; \
1413 }
1414 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1415 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1416 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1417 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1418 DEF_METHOD(Shl, sig_a.size(), "$shl")
1419 DEF_METHOD(Shr, sig_a.size(), "$shr")
1420 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1421 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1422 DEF_METHOD(Shift, sig_a.size(), "$shift")
1423 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1424 DEF_METHOD(Lt, 1, "$lt")
1425 DEF_METHOD(Le, 1, "$le")
1426 DEF_METHOD(Eq, 1, "$eq")
1427 DEF_METHOD(Ne, 1, "$ne")
1428 DEF_METHOD(Eqx, 1, "$eqx")
1429 DEF_METHOD(Nex, 1, "$nex")
1430 DEF_METHOD(Ge, 1, "$ge")
1431 DEF_METHOD(Gt, 1, "$gt")
1432 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1433 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1434 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1435 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1436 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1437 DEF_METHOD(LogicAnd, 1, "$logic_and")
1438 DEF_METHOD(LogicOr, 1, "$logic_or")
1439 #undef DEF_METHOD
1440
1441 #define DEF_METHOD(_func, _type, _pmux) \
1442 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1443 RTLIL::Cell *cell = addCell(name, _type); \
1444 cell->parameters["\\WIDTH"] = sig_a.size(); \
1445 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1446 cell->setPort("\\A", sig_a); \
1447 cell->setPort("\\B", sig_b); \
1448 cell->setPort("\\S", sig_s); \
1449 cell->setPort("\\Y", sig_y); \
1450 return cell; \
1451 } \
1452 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1453 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1454 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1455 return sig_y; \
1456 }
1457 DEF_METHOD(Mux, "$mux", 0)
1458 DEF_METHOD(Pmux, "$pmux", 1)
1459 #undef DEF_METHOD
1460
1461 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1462 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1463 RTLIL::Cell *cell = addCell(name, _type); \
1464 cell->setPort("\\" #_P1, sig1); \
1465 cell->setPort("\\" #_P2, sig2); \
1466 return cell; \
1467 } \
1468 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1469 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1470 add ## _func(name, sig1, sig2); \
1471 return sig2; \
1472 }
1473 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1474 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1475 RTLIL::Cell *cell = addCell(name, _type); \
1476 cell->setPort("\\" #_P1, sig1); \
1477 cell->setPort("\\" #_P2, sig2); \
1478 cell->setPort("\\" #_P3, sig3); \
1479 return cell; \
1480 } \
1481 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1482 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1483 add ## _func(name, sig1, sig2, sig3); \
1484 return sig3; \
1485 }
1486 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1487 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1488 RTLIL::Cell *cell = addCell(name, _type); \
1489 cell->setPort("\\" #_P1, sig1); \
1490 cell->setPort("\\" #_P2, sig2); \
1491 cell->setPort("\\" #_P3, sig3); \
1492 cell->setPort("\\" #_P4, sig4); \
1493 return cell; \
1494 } \
1495 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1496 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1497 add ## _func(name, sig1, sig2, sig3, sig4); \
1498 return sig4; \
1499 }
1500 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1501 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1502 RTLIL::Cell *cell = addCell(name, _type); \
1503 cell->setPort("\\" #_P1, sig1); \
1504 cell->setPort("\\" #_P2, sig2); \
1505 cell->setPort("\\" #_P3, sig3); \
1506 cell->setPort("\\" #_P4, sig4); \
1507 cell->setPort("\\" #_P5, sig5); \
1508 return cell; \
1509 } \
1510 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1511 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1512 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1513 return sig5; \
1514 }
1515 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1516 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1517 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1518 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1519 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1520 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1521 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1522 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1523 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1524 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1525 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1526 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1527 #undef DEF_METHOD_2
1528 #undef DEF_METHOD_3
1529 #undef DEF_METHOD_4
1530 #undef DEF_METHOD_5
1531
1532 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1533 {
1534 RTLIL::Cell *cell = addCell(name, "$pow");
1535 cell->parameters["\\A_SIGNED"] = a_signed;
1536 cell->parameters["\\B_SIGNED"] = b_signed;
1537 cell->parameters["\\A_WIDTH"] = sig_a.size();
1538 cell->parameters["\\B_WIDTH"] = sig_b.size();
1539 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1540 cell->setPort("\\A", sig_a);
1541 cell->setPort("\\B", sig_b);
1542 cell->setPort("\\Y", sig_y);
1543 return cell;
1544 }
1545
1546 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1547 {
1548 RTLIL::Cell *cell = addCell(name, "$slice");
1549 cell->parameters["\\A_WIDTH"] = sig_a.size();
1550 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1551 cell->parameters["\\OFFSET"] = offset;
1552 cell->setPort("\\A", sig_a);
1553 cell->setPort("\\Y", sig_y);
1554 return cell;
1555 }
1556
1557 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1558 {
1559 RTLIL::Cell *cell = addCell(name, "$concat");
1560 cell->parameters["\\A_WIDTH"] = sig_a.size();
1561 cell->parameters["\\B_WIDTH"] = sig_b.size();
1562 cell->setPort("\\A", sig_a);
1563 cell->setPort("\\B", sig_b);
1564 cell->setPort("\\Y", sig_y);
1565 return cell;
1566 }
1567
1568 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1569 {
1570 RTLIL::Cell *cell = addCell(name, "$lut");
1571 cell->parameters["\\LUT"] = lut;
1572 cell->parameters["\\WIDTH"] = sig_i.size();
1573 cell->setPort("\\A", sig_i);
1574 cell->setPort("\\Y", sig_o);
1575 return cell;
1576 }
1577
1578 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1579 {
1580 RTLIL::Cell *cell = addCell(name, "$assert");
1581 cell->setPort("\\A", sig_a);
1582 cell->setPort("\\EN", sig_en);
1583 return cell;
1584 }
1585
1586 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1587 {
1588 RTLIL::Cell *cell = addCell(name, "$sr");
1589 cell->parameters["\\SET_POLARITY"] = set_polarity;
1590 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1591 cell->parameters["\\WIDTH"] = sig_q.size();
1592 cell->setPort("\\SET", sig_set);
1593 cell->setPort("\\CLR", sig_clr);
1594 cell->setPort("\\Q", sig_q);
1595 return cell;
1596 }
1597
1598 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1599 {
1600 RTLIL::Cell *cell = addCell(name, "$dff");
1601 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1602 cell->parameters["\\WIDTH"] = sig_q.size();
1603 cell->setPort("\\CLK", sig_clk);
1604 cell->setPort("\\D", sig_d);
1605 cell->setPort("\\Q", sig_q);
1606 return cell;
1607 }
1608
1609 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1610 {
1611 RTLIL::Cell *cell = addCell(name, "$dffe");
1612 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1613 cell->parameters["\\EN_POLARITY"] = en_polarity;
1614 cell->parameters["\\WIDTH"] = sig_q.size();
1615 cell->setPort("\\CLK", sig_clk);
1616 cell->setPort("\\EN", sig_en);
1617 cell->setPort("\\D", sig_d);
1618 cell->setPort("\\Q", sig_q);
1619 return cell;
1620 }
1621
1622 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1623 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1624 {
1625 RTLIL::Cell *cell = addCell(name, "$dffsr");
1626 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1627 cell->parameters["\\SET_POLARITY"] = set_polarity;
1628 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1629 cell->parameters["\\WIDTH"] = sig_q.size();
1630 cell->setPort("\\CLK", sig_clk);
1631 cell->setPort("\\SET", sig_set);
1632 cell->setPort("\\CLR", sig_clr);
1633 cell->setPort("\\D", sig_d);
1634 cell->setPort("\\Q", sig_q);
1635 return cell;
1636 }
1637
1638 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1639 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1640 {
1641 RTLIL::Cell *cell = addCell(name, "$adff");
1642 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1643 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1644 cell->parameters["\\ARST_VALUE"] = arst_value;
1645 cell->parameters["\\WIDTH"] = sig_q.size();
1646 cell->setPort("\\CLK", sig_clk);
1647 cell->setPort("\\ARST", sig_arst);
1648 cell->setPort("\\D", sig_d);
1649 cell->setPort("\\Q", sig_q);
1650 return cell;
1651 }
1652
1653 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1654 {
1655 RTLIL::Cell *cell = addCell(name, "$dlatch");
1656 cell->parameters["\\EN_POLARITY"] = en_polarity;
1657 cell->parameters["\\WIDTH"] = sig_q.size();
1658 cell->setPort("\\EN", sig_en);
1659 cell->setPort("\\D", sig_d);
1660 cell->setPort("\\Q", sig_q);
1661 return cell;
1662 }
1663
1664 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1665 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1666 {
1667 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1668 cell->parameters["\\EN_POLARITY"] = en_polarity;
1669 cell->parameters["\\SET_POLARITY"] = set_polarity;
1670 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1671 cell->parameters["\\WIDTH"] = sig_q.size();
1672 cell->setPort("\\EN", sig_en);
1673 cell->setPort("\\SET", sig_set);
1674 cell->setPort("\\CLR", sig_clr);
1675 cell->setPort("\\D", sig_d);
1676 cell->setPort("\\Q", sig_q);
1677 return cell;
1678 }
1679
1680 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1681 {
1682 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1683 cell->setPort("\\C", sig_clk);
1684 cell->setPort("\\D", sig_d);
1685 cell->setPort("\\Q", sig_q);
1686 return cell;
1687 }
1688
1689 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1690 {
1691 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
1692 cell->setPort("\\C", sig_clk);
1693 cell->setPort("\\E", sig_en);
1694 cell->setPort("\\D", sig_d);
1695 cell->setPort("\\Q", sig_q);
1696 return cell;
1697 }
1698
1699 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1700 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1701 {
1702 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1703 cell->setPort("\\C", sig_clk);
1704 cell->setPort("\\S", sig_set);
1705 cell->setPort("\\R", sig_clr);
1706 cell->setPort("\\D", sig_d);
1707 cell->setPort("\\Q", sig_q);
1708 return cell;
1709 }
1710
1711 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1712 bool arst_value, bool clk_polarity, bool arst_polarity)
1713 {
1714 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1715 cell->setPort("\\C", sig_clk);
1716 cell->setPort("\\R", sig_arst);
1717 cell->setPort("\\D", sig_d);
1718 cell->setPort("\\Q", sig_q);
1719 return cell;
1720 }
1721
1722 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1723 {
1724 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1725 cell->setPort("\\E", sig_en);
1726 cell->setPort("\\D", sig_d);
1727 cell->setPort("\\Q", sig_q);
1728 return cell;
1729 }
1730
1731 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1732 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1733 {
1734 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1735 cell->setPort("\\E", sig_en);
1736 cell->setPort("\\S", sig_set);
1737 cell->setPort("\\R", sig_clr);
1738 cell->setPort("\\D", sig_d);
1739 cell->setPort("\\Q", sig_q);
1740 return cell;
1741 }
1742
1743
1744 RTLIL::Wire::Wire()
1745 {
1746 module = nullptr;
1747 width = 1;
1748 start_offset = 0;
1749 port_id = 0;
1750 port_input = false;
1751 port_output = false;
1752 upto = false;
1753 }
1754
1755 RTLIL::Memory::Memory()
1756 {
1757 width = 1;
1758 size = 0;
1759 }
1760
1761 RTLIL::Cell::Cell() : module(nullptr)
1762 {
1763 }
1764
1765 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1766 {
1767 return connections_.count(portname) != 0;
1768 }
1769
1770 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1771 {
1772 RTLIL::SigSpec signal;
1773 auto conn_it = connections_.find(portname);
1774
1775 if (conn_it != connections_.end())
1776 {
1777 for (auto mon : module->monitors)
1778 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1779
1780 if (module->design)
1781 for (auto mon : module->design->monitors)
1782 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1783
1784 connections_.erase(conn_it);
1785 }
1786 }
1787
1788 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1789 {
1790 auto conn_it = connections_.find(portname);
1791
1792 if (conn_it == connections_.end()) {
1793 connections_[portname] = RTLIL::SigSpec();
1794 conn_it = connections_.find(portname);
1795 log_assert(conn_it != connections_.end());
1796 }
1797
1798 for (auto mon : module->monitors)
1799 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1800
1801 if (module->design)
1802 for (auto mon : module->design->monitors)
1803 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1804
1805 conn_it->second = signal;
1806 }
1807
1808 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1809 {
1810 return connections_.at(portname);
1811 }
1812
1813 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1814 {
1815 return connections_;
1816 }
1817
1818 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1819 {
1820 return parameters.count(paramname) != 0;
1821 }
1822
1823 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1824 {
1825 parameters.erase(paramname);
1826 }
1827
1828 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1829 {
1830 parameters[paramname] = value;
1831 }
1832
1833 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1834 {
1835 return parameters.at(paramname);
1836 }
1837
1838 void RTLIL::Cell::check()
1839 {
1840 #ifndef NDEBUG
1841 InternalCellChecker checker(NULL, this);
1842 checker.check();
1843 #endif
1844 }
1845
1846 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1847 {
1848 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1849 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1850 return;
1851
1852 if (type == "$mux" || type == "$pmux") {
1853 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
1854 if (type == "$pmux")
1855 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
1856 check();
1857 return;
1858 }
1859
1860 if (type == "$lut") {
1861 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
1862 return;
1863 }
1864
1865 if (type == "$fa") {
1866 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
1867 return;
1868 }
1869
1870 if (type == "$lcu") {
1871 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
1872 return;
1873 }
1874
1875 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
1876
1877 if (connections_.count("\\A")) {
1878 if (signedness_ab) {
1879 if (set_a_signed)
1880 parameters["\\A_SIGNED"] = true;
1881 else if (parameters.count("\\A_SIGNED") == 0)
1882 parameters["\\A_SIGNED"] = false;
1883 }
1884 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
1885 }
1886
1887 if (connections_.count("\\B")) {
1888 if (signedness_ab) {
1889 if (set_b_signed)
1890 parameters["\\B_SIGNED"] = true;
1891 else if (parameters.count("\\B_SIGNED") == 0)
1892 parameters["\\B_SIGNED"] = false;
1893 }
1894 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
1895 }
1896
1897 if (connections_.count("\\Y"))
1898 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
1899
1900 check();
1901 }
1902
1903 RTLIL::SigChunk::SigChunk()
1904 {
1905 wire = NULL;
1906 width = 0;
1907 offset = 0;
1908 }
1909
1910 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1911 {
1912 wire = NULL;
1913 data = value.bits;
1914 width = GetSize(data);
1915 offset = 0;
1916 }
1917
1918 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1919 {
1920 log_assert(wire != nullptr);
1921 this->wire = wire;
1922 this->width = wire->width;
1923 this->offset = 0;
1924 }
1925
1926 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1927 {
1928 log_assert(wire != nullptr);
1929 this->wire = wire;
1930 this->width = width;
1931 this->offset = offset;
1932 }
1933
1934 RTLIL::SigChunk::SigChunk(const std::string &str)
1935 {
1936 wire = NULL;
1937 data = RTLIL::Const(str).bits;
1938 width = GetSize(data);
1939 offset = 0;
1940 }
1941
1942 RTLIL::SigChunk::SigChunk(int val, int width)
1943 {
1944 wire = NULL;
1945 data = RTLIL::Const(val, width).bits;
1946 this->width = GetSize(data);
1947 offset = 0;
1948 }
1949
1950 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1951 {
1952 wire = NULL;
1953 data = RTLIL::Const(bit, width).bits;
1954 this->width = GetSize(data);
1955 offset = 0;
1956 }
1957
1958 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1959 {
1960 wire = bit.wire;
1961 offset = 0;
1962 if (wire == NULL)
1963 data = RTLIL::Const(bit.data).bits;
1964 else
1965 offset = bit.offset;
1966 width = 1;
1967 }
1968
1969 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1970 {
1971 RTLIL::SigChunk ret;
1972 if (wire) {
1973 ret.wire = wire;
1974 ret.offset = this->offset + offset;
1975 ret.width = length;
1976 } else {
1977 for (int i = 0; i < length; i++)
1978 ret.data.push_back(data[offset+i]);
1979 ret.width = length;
1980 }
1981 return ret;
1982 }
1983
1984 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1985 {
1986 if (wire && other.wire)
1987 if (wire->name != other.wire->name)
1988 return wire->name < other.wire->name;
1989
1990 if (wire != other.wire)
1991 return wire < other.wire;
1992
1993 if (offset != other.offset)
1994 return offset < other.offset;
1995
1996 if (width != other.width)
1997 return width < other.width;
1998
1999 return data < other.data;
2000 }
2001
2002 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2003 {
2004 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2005 }
2006
2007 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2008 {
2009 if (*this == other)
2010 return false;
2011 return true;
2012 }
2013
2014 RTLIL::SigSpec::SigSpec()
2015 {
2016 width_ = 0;
2017 hash_ = 0;
2018 }
2019
2020 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2021 {
2022 *this = other;
2023 }
2024
2025 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2026 {
2027 cover("kernel.rtlil.sigspec.init.list");
2028
2029 width_ = 0;
2030 hash_ = 0;
2031
2032 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2033 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2034 append(*it);
2035 }
2036
2037 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2038 {
2039 cover("kernel.rtlil.sigspec.assign");
2040
2041 width_ = other.width_;
2042 hash_ = other.hash_;
2043 chunks_ = other.chunks_;
2044 bits_.clear();
2045
2046 if (!other.bits_.empty())
2047 {
2048 RTLIL::SigChunk *last = NULL;
2049 int last_end_offset = 0;
2050
2051 for (auto &bit : other.bits_) {
2052 if (last && bit.wire == last->wire) {
2053 if (bit.wire == NULL) {
2054 last->data.push_back(bit.data);
2055 last->width++;
2056 continue;
2057 } else if (last_end_offset == bit.offset) {
2058 last_end_offset++;
2059 last->width++;
2060 continue;
2061 }
2062 }
2063 chunks_.push_back(bit);
2064 last = &chunks_.back();
2065 last_end_offset = bit.offset + 1;
2066 }
2067
2068 check();
2069 }
2070
2071 return *this;
2072 }
2073
2074 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2075 {
2076 cover("kernel.rtlil.sigspec.init.const");
2077
2078 chunks_.push_back(RTLIL::SigChunk(value));
2079 width_ = chunks_.back().width;
2080 hash_ = 0;
2081 check();
2082 }
2083
2084 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2085 {
2086 cover("kernel.rtlil.sigspec.init.chunk");
2087
2088 chunks_.push_back(chunk);
2089 width_ = chunks_.back().width;
2090 hash_ = 0;
2091 check();
2092 }
2093
2094 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2095 {
2096 cover("kernel.rtlil.sigspec.init.wire");
2097
2098 chunks_.push_back(RTLIL::SigChunk(wire));
2099 width_ = chunks_.back().width;
2100 hash_ = 0;
2101 check();
2102 }
2103
2104 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2105 {
2106 cover("kernel.rtlil.sigspec.init.wire_part");
2107
2108 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2109 width_ = chunks_.back().width;
2110 hash_ = 0;
2111 check();
2112 }
2113
2114 RTLIL::SigSpec::SigSpec(const std::string &str)
2115 {
2116 cover("kernel.rtlil.sigspec.init.str");
2117
2118 chunks_.push_back(RTLIL::SigChunk(str));
2119 width_ = chunks_.back().width;
2120 hash_ = 0;
2121 check();
2122 }
2123
2124 RTLIL::SigSpec::SigSpec(int val, int width)
2125 {
2126 cover("kernel.rtlil.sigspec.init.int");
2127
2128 chunks_.push_back(RTLIL::SigChunk(val, width));
2129 width_ = width;
2130 hash_ = 0;
2131 check();
2132 }
2133
2134 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2135 {
2136 cover("kernel.rtlil.sigspec.init.state");
2137
2138 chunks_.push_back(RTLIL::SigChunk(bit, width));
2139 width_ = width;
2140 hash_ = 0;
2141 check();
2142 }
2143
2144 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2145 {
2146 cover("kernel.rtlil.sigspec.init.bit");
2147
2148 if (bit.wire == NULL)
2149 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2150 else
2151 for (int i = 0; i < width; i++)
2152 chunks_.push_back(bit);
2153 width_ = width;
2154 hash_ = 0;
2155 check();
2156 }
2157
2158 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2159 {
2160 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2161
2162 width_ = 0;
2163 hash_ = 0;
2164 for (auto &c : chunks)
2165 append(c);
2166 check();
2167 }
2168
2169 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2170 {
2171 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2172
2173 width_ = 0;
2174 hash_ = 0;
2175 for (auto &bit : bits)
2176 append_bit(bit);
2177 check();
2178 }
2179
2180 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2181 {
2182 cover("kernel.rtlil.sigspec.init.stdset_bits");
2183
2184 width_ = 0;
2185 hash_ = 0;
2186 for (auto &bit : bits)
2187 append_bit(bit);
2188 check();
2189 }
2190
2191 void RTLIL::SigSpec::pack() const
2192 {
2193 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2194
2195 if (that->bits_.empty())
2196 return;
2197
2198 cover("kernel.rtlil.sigspec.convert.pack");
2199 log_assert(that->chunks_.empty());
2200
2201 std::vector<RTLIL::SigBit> old_bits;
2202 old_bits.swap(that->bits_);
2203
2204 RTLIL::SigChunk *last = NULL;
2205 int last_end_offset = 0;
2206
2207 for (auto &bit : old_bits) {
2208 if (last && bit.wire == last->wire) {
2209 if (bit.wire == NULL) {
2210 last->data.push_back(bit.data);
2211 last->width++;
2212 continue;
2213 } else if (last_end_offset == bit.offset) {
2214 last_end_offset++;
2215 last->width++;
2216 continue;
2217 }
2218 }
2219 that->chunks_.push_back(bit);
2220 last = &that->chunks_.back();
2221 last_end_offset = bit.offset + 1;
2222 }
2223
2224 check();
2225 }
2226
2227 void RTLIL::SigSpec::unpack() const
2228 {
2229 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2230
2231 if (that->chunks_.empty())
2232 return;
2233
2234 cover("kernel.rtlil.sigspec.convert.unpack");
2235 log_assert(that->bits_.empty());
2236
2237 that->bits_.reserve(that->width_);
2238 for (auto &c : that->chunks_)
2239 for (int i = 0; i < c.width; i++)
2240 that->bits_.push_back(RTLIL::SigBit(c, i));
2241
2242 that->chunks_.clear();
2243 that->hash_ = 0;
2244 }
2245
2246 #define DJB2(_hash, _value) (_hash) = (((_hash) << 5) + (_hash)) + (_value)
2247
2248 void RTLIL::SigSpec::hash() const
2249 {
2250 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2251
2252 if (that->hash_ != 0)
2253 return;
2254
2255 cover("kernel.rtlil.sigspec.hash");
2256 that->pack();
2257
2258 that->hash_ = 5381;
2259 for (auto &c : that->chunks_)
2260 if (c.wire == NULL) {
2261 for (auto &v : c.data)
2262 DJB2(that->hash_, v);
2263 } else {
2264 DJB2(that->hash_, c.wire->name.index_);
2265 DJB2(that->hash_, c.offset);
2266 DJB2(that->hash_, c.width);
2267 }
2268
2269 if (that->hash_ == 0)
2270 that->hash_ = 1;
2271 }
2272
2273 void RTLIL::SigSpec::sort()
2274 {
2275 unpack();
2276 cover("kernel.rtlil.sigspec.sort");
2277 std::sort(bits_.begin(), bits_.end());
2278 }
2279
2280 void RTLIL::SigSpec::sort_and_unify()
2281 {
2282 cover("kernel.rtlil.sigspec.sort_and_unify");
2283 *this = this->to_sigbit_set();
2284 }
2285
2286 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2287 {
2288 replace(pattern, with, this);
2289 }
2290
2291 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2292 {
2293 log_assert(pattern.width_ == with.width_);
2294
2295 pattern.unpack();
2296 with.unpack();
2297
2298 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2299
2300 for (int i = 0; i < GetSize(pattern.bits_); i++)
2301 if (pattern.bits_[i].wire != NULL)
2302 rules[pattern.bits_[i]] = with.bits_[i];
2303
2304 replace(rules, other);
2305 }
2306
2307 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2308 {
2309 replace(rules, this);
2310 }
2311
2312 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2313 {
2314 cover("kernel.rtlil.sigspec.replace");
2315
2316 log_assert(other != NULL);
2317 log_assert(width_ == other->width_);
2318
2319 unpack();
2320 other->unpack();
2321
2322 for (int i = 0; i < GetSize(bits_); i++) {
2323 auto it = rules.find(bits_[i]);
2324 if (it != rules.end())
2325 other->bits_[i] = it->second;
2326 }
2327
2328 other->check();
2329 }
2330
2331 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2332 {
2333 remove2(pattern, NULL);
2334 }
2335
2336 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2337 {
2338 RTLIL::SigSpec tmp = *this;
2339 tmp.remove2(pattern, other);
2340 }
2341
2342 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2343 {
2344 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2345 remove2(pattern_bits, other);
2346 }
2347
2348 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2349 {
2350 remove2(pattern, NULL);
2351 }
2352
2353 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2354 {
2355 RTLIL::SigSpec tmp = *this;
2356 tmp.remove2(pattern, other);
2357 }
2358
2359 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2360 {
2361 if (other)
2362 cover("kernel.rtlil.sigspec.remove_other");
2363 else
2364 cover("kernel.rtlil.sigspec.remove");
2365
2366 unpack();
2367
2368 if (other != NULL) {
2369 log_assert(width_ == other->width_);
2370 other->unpack();
2371 }
2372
2373 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2374
2375 new_bits.resize(GetSize(bits_));
2376 if (other != NULL)
2377 new_other_bits.resize(GetSize(bits_));
2378
2379 int k = 0;
2380 for (int i = 0; i < GetSize(bits_); i++) {
2381 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2382 continue;
2383 if (other != NULL)
2384 new_other_bits[k] = other->bits_[i];
2385 new_bits[k++] = bits_[i];
2386 }
2387
2388 new_bits.resize(k);
2389 if (other != NULL)
2390 new_other_bits.resize(k);
2391
2392 bits_.swap(new_bits);
2393 width_ = GetSize(bits_);
2394
2395 if (other != NULL) {
2396 other->bits_.swap(new_other_bits);
2397 other->width_ = GetSize(other->bits_);
2398 }
2399
2400 check();
2401 }
2402
2403 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2404 {
2405 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2406 return extract(pattern_bits, other);
2407 }
2408
2409 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2410 {
2411 if (other)
2412 cover("kernel.rtlil.sigspec.extract_other");
2413 else
2414 cover("kernel.rtlil.sigspec.extract");
2415
2416 log_assert(other == NULL || width_ == other->width_);
2417
2418 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2419 RTLIL::SigSpec ret;
2420
2421 if (other) {
2422 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2423 for (int i = 0; i < width_; i++)
2424 if (bits_match[i].wire && pattern.count(bits_match[i]))
2425 ret.append_bit(bits_other[i]);
2426 } else {
2427 for (int i = 0; i < width_; i++)
2428 if (bits_match[i].wire && pattern.count(bits_match[i]))
2429 ret.append_bit(bits_match[i]);
2430 }
2431
2432 ret.check();
2433 return ret;
2434 }
2435
2436 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2437 {
2438 cover("kernel.rtlil.sigspec.replace_pos");
2439
2440 unpack();
2441 with.unpack();
2442
2443 log_assert(offset >= 0);
2444 log_assert(with.width_ >= 0);
2445 log_assert(offset+with.width_ <= width_);
2446
2447 for (int i = 0; i < with.width_; i++)
2448 bits_.at(offset + i) = with.bits_.at(i);
2449
2450 check();
2451 }
2452
2453 void RTLIL::SigSpec::remove_const()
2454 {
2455 if (packed())
2456 {
2457 cover("kernel.rtlil.sigspec.remove_const.packed");
2458
2459 std::vector<RTLIL::SigChunk> new_chunks;
2460 new_chunks.reserve(GetSize(chunks_));
2461
2462 width_ = 0;
2463 for (auto &chunk : chunks_)
2464 if (chunk.wire != NULL) {
2465 new_chunks.push_back(chunk);
2466 width_ += chunk.width;
2467 }
2468
2469 chunks_.swap(new_chunks);
2470 }
2471 else
2472 {
2473 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2474
2475 std::vector<RTLIL::SigBit> new_bits;
2476 new_bits.reserve(width_);
2477
2478 for (auto &bit : bits_)
2479 if (bit.wire != NULL)
2480 new_bits.push_back(bit);
2481
2482 bits_.swap(new_bits);
2483 width_ = bits_.size();
2484 }
2485
2486 check();
2487 }
2488
2489 void RTLIL::SigSpec::remove(int offset, int length)
2490 {
2491 cover("kernel.rtlil.sigspec.remove_pos");
2492
2493 unpack();
2494
2495 log_assert(offset >= 0);
2496 log_assert(length >= 0);
2497 log_assert(offset + length <= width_);
2498
2499 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2500 width_ = bits_.size();
2501
2502 check();
2503 }
2504
2505 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2506 {
2507 unpack();
2508 cover("kernel.rtlil.sigspec.extract_pos");
2509 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2510 }
2511
2512 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2513 {
2514 if (signal.width_ == 0)
2515 return;
2516
2517 if (width_ == 0) {
2518 *this = signal;
2519 return;
2520 }
2521
2522 cover("kernel.rtlil.sigspec.append");
2523
2524 if (packed() != signal.packed()) {
2525 pack();
2526 signal.pack();
2527 }
2528
2529 if (packed())
2530 for (auto &other_c : signal.chunks_)
2531 {
2532 auto &my_last_c = chunks_.back();
2533 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2534 auto &this_data = my_last_c.data;
2535 auto &other_data = other_c.data;
2536 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2537 my_last_c.width += other_c.width;
2538 } else
2539 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2540 my_last_c.width += other_c.width;
2541 } else
2542 chunks_.push_back(other_c);
2543 }
2544 else
2545 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2546
2547 width_ += signal.width_;
2548 check();
2549 }
2550
2551 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2552 {
2553 if (packed())
2554 {
2555 cover("kernel.rtlil.sigspec.append_bit.packed");
2556
2557 if (chunks_.size() == 0)
2558 chunks_.push_back(bit);
2559 else
2560 if (bit.wire == NULL)
2561 if (chunks_.back().wire == NULL) {
2562 chunks_.back().data.push_back(bit.data);
2563 chunks_.back().width++;
2564 } else
2565 chunks_.push_back(bit);
2566 else
2567 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2568 chunks_.back().width++;
2569 else
2570 chunks_.push_back(bit);
2571 }
2572 else
2573 {
2574 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2575 bits_.push_back(bit);
2576 }
2577
2578 width_++;
2579 check();
2580 }
2581
2582 void RTLIL::SigSpec::extend(int width, bool is_signed)
2583 {
2584 cover("kernel.rtlil.sigspec.extend");
2585
2586 pack();
2587
2588 if (width_ > width)
2589 remove(width, width_ - width);
2590
2591 if (width_ < width) {
2592 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2593 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2594 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2595 padding = RTLIL::SigSpec(RTLIL::State::S0);
2596 while (width_ < width)
2597 append(padding);
2598 }
2599 }
2600
2601 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2602 {
2603 cover("kernel.rtlil.sigspec.extend_u0");
2604
2605 pack();
2606
2607 if (width_ > width)
2608 remove(width, width_ - width);
2609
2610 if (width_ < width) {
2611 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2612 if (!is_signed)
2613 padding = RTLIL::SigSpec(RTLIL::State::S0);
2614 while (width_ < width)
2615 append(padding);
2616 }
2617
2618 }
2619
2620 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2621 {
2622 cover("kernel.rtlil.sigspec.repeat");
2623
2624 RTLIL::SigSpec sig;
2625 for (int i = 0; i < num; i++)
2626 sig.append(*this);
2627 return sig;
2628 }
2629
2630 #ifndef NDEBUG
2631 void RTLIL::SigSpec::check() const
2632 {
2633 if (width_ > 64)
2634 {
2635 cover("kernel.rtlil.sigspec.check.skip");
2636 }
2637 else if (packed())
2638 {
2639 cover("kernel.rtlil.sigspec.check.packed");
2640
2641 int w = 0;
2642 for (size_t i = 0; i < chunks_.size(); i++) {
2643 const RTLIL::SigChunk chunk = chunks_[i];
2644 if (chunk.wire == NULL) {
2645 if (i > 0)
2646 log_assert(chunks_[i-1].wire != NULL);
2647 log_assert(chunk.offset == 0);
2648 log_assert(chunk.data.size() == (size_t)chunk.width);
2649 } else {
2650 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2651 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2652 log_assert(chunk.offset >= 0);
2653 log_assert(chunk.width >= 0);
2654 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2655 log_assert(chunk.data.size() == 0);
2656 }
2657 w += chunk.width;
2658 }
2659 log_assert(w == width_);
2660 log_assert(bits_.empty());
2661 }
2662 else
2663 {
2664 cover("kernel.rtlil.sigspec.check.unpacked");
2665
2666 log_assert(width_ == GetSize(bits_));
2667 log_assert(chunks_.empty());
2668 }
2669 }
2670 #endif
2671
2672 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2673 {
2674 cover("kernel.rtlil.sigspec.comp_lt");
2675
2676 if (this == &other)
2677 return false;
2678
2679 if (width_ != other.width_)
2680 return width_ < other.width_;
2681
2682 pack();
2683 other.pack();
2684
2685 if (chunks_.size() != other.chunks_.size())
2686 return chunks_.size() < other.chunks_.size();
2687
2688 hash();
2689 other.hash();
2690
2691 if (hash_ != other.hash_)
2692 return hash_ < other.hash_;
2693
2694 for (size_t i = 0; i < chunks_.size(); i++)
2695 if (chunks_[i] != other.chunks_[i]) {
2696 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2697 return chunks_[i] < other.chunks_[i];
2698 }
2699
2700 cover("kernel.rtlil.sigspec.comp_lt.equal");
2701 return false;
2702 }
2703
2704 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2705 {
2706 cover("kernel.rtlil.sigspec.comp_eq");
2707
2708 if (this == &other)
2709 return true;
2710
2711 if (width_ != other.width_)
2712 return false;
2713
2714 pack();
2715 other.pack();
2716
2717 if (chunks_.size() != chunks_.size())
2718 return false;
2719
2720 hash();
2721 other.hash();
2722
2723 if (hash_ != other.hash_)
2724 return false;
2725
2726 for (size_t i = 0; i < chunks_.size(); i++)
2727 if (chunks_[i] != other.chunks_[i]) {
2728 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2729 return false;
2730 }
2731
2732 cover("kernel.rtlil.sigspec.comp_eq.equal");
2733 return true;
2734 }
2735
2736 bool RTLIL::SigSpec::is_wire() const
2737 {
2738 cover("kernel.rtlil.sigspec.is_wire");
2739
2740 pack();
2741 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2742 }
2743
2744 bool RTLIL::SigSpec::is_chunk() const
2745 {
2746 cover("kernel.rtlil.sigspec.is_chunk");
2747
2748 pack();
2749 return GetSize(chunks_) == 1;
2750 }
2751
2752 bool RTLIL::SigSpec::is_fully_const() const
2753 {
2754 cover("kernel.rtlil.sigspec.is_fully_const");
2755
2756 pack();
2757 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2758 if (it->width > 0 && it->wire != NULL)
2759 return false;
2760 return true;
2761 }
2762
2763 bool RTLIL::SigSpec::is_fully_def() const
2764 {
2765 cover("kernel.rtlil.sigspec.is_fully_def");
2766
2767 pack();
2768 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2769 if (it->width > 0 && it->wire != NULL)
2770 return false;
2771 for (size_t i = 0; i < it->data.size(); i++)
2772 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
2773 return false;
2774 }
2775 return true;
2776 }
2777
2778 bool RTLIL::SigSpec::is_fully_undef() const
2779 {
2780 cover("kernel.rtlil.sigspec.is_fully_undef");
2781
2782 pack();
2783 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2784 if (it->width > 0 && it->wire != NULL)
2785 return false;
2786 for (size_t i = 0; i < it->data.size(); i++)
2787 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
2788 return false;
2789 }
2790 return true;
2791 }
2792
2793 bool RTLIL::SigSpec::has_marked_bits() const
2794 {
2795 cover("kernel.rtlil.sigspec.has_marked_bits");
2796
2797 pack();
2798 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2799 if (it->width > 0 && it->wire == NULL) {
2800 for (size_t i = 0; i < it->data.size(); i++)
2801 if (it->data[i] == RTLIL::State::Sm)
2802 return true;
2803 }
2804 return false;
2805 }
2806
2807 bool RTLIL::SigSpec::as_bool() const
2808 {
2809 cover("kernel.rtlil.sigspec.as_bool");
2810
2811 pack();
2812 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2813 if (width_)
2814 return RTLIL::Const(chunks_[0].data).as_bool();
2815 return false;
2816 }
2817
2818 int RTLIL::SigSpec::as_int(bool is_signed) const
2819 {
2820 cover("kernel.rtlil.sigspec.as_int");
2821
2822 pack();
2823 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2824 if (width_)
2825 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
2826 return 0;
2827 }
2828
2829 std::string RTLIL::SigSpec::as_string() const
2830 {
2831 cover("kernel.rtlil.sigspec.as_string");
2832
2833 pack();
2834 std::string str;
2835 for (size_t i = chunks_.size(); i > 0; i--) {
2836 const RTLIL::SigChunk &chunk = chunks_[i-1];
2837 if (chunk.wire != NULL)
2838 for (int j = 0; j < chunk.width; j++)
2839 str += "?";
2840 else
2841 str += RTLIL::Const(chunk.data).as_string();
2842 }
2843 return str;
2844 }
2845
2846 RTLIL::Const RTLIL::SigSpec::as_const() const
2847 {
2848 cover("kernel.rtlil.sigspec.as_const");
2849
2850 pack();
2851 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2852 if (width_)
2853 return chunks_[0].data;
2854 return RTLIL::Const();
2855 }
2856
2857 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2858 {
2859 cover("kernel.rtlil.sigspec.as_wire");
2860
2861 pack();
2862 log_assert(is_wire());
2863 return chunks_[0].wire;
2864 }
2865
2866 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2867 {
2868 cover("kernel.rtlil.sigspec.as_chunk");
2869
2870 pack();
2871 log_assert(is_chunk());
2872 return chunks_[0];
2873 }
2874
2875 bool RTLIL::SigSpec::match(std::string pattern) const
2876 {
2877 cover("kernel.rtlil.sigspec.match");
2878
2879 pack();
2880 std::string str = as_string();
2881 log_assert(pattern.size() == str.size());
2882
2883 for (size_t i = 0; i < pattern.size(); i++) {
2884 if (pattern[i] == ' ')
2885 continue;
2886 if (pattern[i] == '*') {
2887 if (str[i] != 'z' && str[i] != 'x')
2888 return false;
2889 continue;
2890 }
2891 if (pattern[i] != str[i])
2892 return false;
2893 }
2894
2895 return true;
2896 }
2897
2898 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2899 {
2900 cover("kernel.rtlil.sigspec.to_sigbit_set");
2901
2902 pack();
2903 std::set<RTLIL::SigBit> sigbits;
2904 for (auto &c : chunks_)
2905 for (int i = 0; i < c.width; i++)
2906 sigbits.insert(RTLIL::SigBit(c, i));
2907 return sigbits;
2908 }
2909
2910 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2911 {
2912 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2913
2914 unpack();
2915 return bits_;
2916 }
2917
2918 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2919 {
2920 cover("kernel.rtlil.sigspec.to_sigbit_map");
2921
2922 unpack();
2923 other.unpack();
2924
2925 log_assert(width_ == other.width_);
2926
2927 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2928 for (int i = 0; i < width_; i++)
2929 new_map[bits_[i]] = other.bits_[i];
2930
2931 return new_map;
2932 }
2933
2934 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2935 {
2936 cover("kernel.rtlil.sigspec.to_single_sigbit");
2937
2938 pack();
2939 log_assert(width_ == 1);
2940 for (auto &c : chunks_)
2941 if (c.width)
2942 return RTLIL::SigBit(c);
2943 log_abort();
2944 }
2945
2946 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2947 {
2948 size_t start = 0, end = 0;
2949 while ((end = text.find(sep, start)) != std::string::npos) {
2950 tokens.push_back(text.substr(start, end - start));
2951 start = end + 1;
2952 }
2953 tokens.push_back(text.substr(start));
2954 }
2955
2956 static int sigspec_parse_get_dummy_line_num()
2957 {
2958 return 0;
2959 }
2960
2961 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2962 {
2963 cover("kernel.rtlil.sigspec.parse");
2964
2965 std::vector<std::string> tokens;
2966 sigspec_parse_split(tokens, str, ',');
2967
2968 sig = RTLIL::SigSpec();
2969 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2970 {
2971 std::string netname = tokens[tokidx];
2972 std::string indices;
2973
2974 if (netname.size() == 0)
2975 continue;
2976
2977 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
2978 cover("kernel.rtlil.sigspec.parse.const");
2979 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2980 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2981 if (ast == NULL)
2982 return false;
2983 sig.append(RTLIL::Const(ast->bits));
2984 delete ast;
2985 continue;
2986 }
2987
2988 if (module == NULL)
2989 return false;
2990
2991 cover("kernel.rtlil.sigspec.parse.net");
2992
2993 if (netname[0] != '$' && netname[0] != '\\')
2994 netname = "\\" + netname;
2995
2996 if (module->wires_.count(netname) == 0) {
2997 size_t indices_pos = netname.size()-1;
2998 if (indices_pos > 2 && netname[indices_pos] == ']')
2999 {
3000 indices_pos--;
3001 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3002 if (indices_pos > 0 && netname[indices_pos] == ':') {
3003 indices_pos--;
3004 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3005 }
3006 if (indices_pos > 0 && netname[indices_pos] == '[') {
3007 indices = netname.substr(indices_pos);
3008 netname = netname.substr(0, indices_pos);
3009 }
3010 }
3011 }
3012
3013 if (module->wires_.count(netname) == 0)
3014 return false;
3015
3016 RTLIL::Wire *wire = module->wires_.at(netname);
3017 if (!indices.empty()) {
3018 std::vector<std::string> index_tokens;
3019 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3020 if (index_tokens.size() == 1) {
3021 cover("kernel.rtlil.sigspec.parse.bit_sel");
3022 int a = atoi(index_tokens.at(0).c_str());
3023 if (a < 0 || a >= wire->width)
3024 return false;
3025 sig.append(RTLIL::SigSpec(wire, a));
3026 } else {
3027 cover("kernel.rtlil.sigspec.parse.part_sel");
3028 int a = atoi(index_tokens.at(0).c_str());
3029 int b = atoi(index_tokens.at(1).c_str());
3030 if (a > b) {
3031 int tmp = a;
3032 a = b, b = tmp;
3033 }
3034 if (a < 0 || a >= wire->width)
3035 return false;
3036 if (b < 0 || b >= wire->width)
3037 return false;
3038 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3039 }
3040 } else
3041 sig.append(wire);
3042 }
3043
3044 return true;
3045 }
3046
3047 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3048 {
3049 if (str.empty() || str[0] != '@')
3050 return parse(sig, module, str);
3051
3052 cover("kernel.rtlil.sigspec.parse.sel");
3053
3054 str = RTLIL::escape_id(str.substr(1));
3055 if (design->selection_vars.count(str) == 0)
3056 return false;
3057
3058 sig = RTLIL::SigSpec();
3059 RTLIL::Selection &sel = design->selection_vars.at(str);
3060 for (auto &it : module->wires_)
3061 if (sel.selected_member(module->name, it.first))
3062 sig.append(it.second);
3063
3064 return true;
3065 }
3066
3067 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3068 {
3069 if (str == "0") {
3070 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3071 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3072 return true;
3073 }
3074
3075 if (str == "~0") {
3076 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3077 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3078 return true;
3079 }
3080
3081 if (lhs.chunks_.size() == 1) {
3082 char *p = (char*)str.c_str(), *endptr;
3083 long int val = strtol(p, &endptr, 10);
3084 if (endptr && endptr != p && *endptr == 0) {
3085 sig = RTLIL::SigSpec(val, lhs.width_);
3086 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3087 return true;
3088 }
3089 }
3090
3091 return parse(sig, module, str);
3092 }
3093
3094 RTLIL::CaseRule::~CaseRule()
3095 {
3096 for (auto it = switches.begin(); it != switches.end(); it++)
3097 delete *it;
3098 }
3099
3100 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3101 {
3102 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3103 new_caserule->compare = compare;
3104 new_caserule->actions = actions;
3105 for (auto &it : switches)
3106 new_caserule->switches.push_back(it->clone());
3107 return new_caserule;
3108 }
3109
3110 RTLIL::SwitchRule::~SwitchRule()
3111 {
3112 for (auto it = cases.begin(); it != cases.end(); it++)
3113 delete *it;
3114 }
3115
3116 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3117 {
3118 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3119 new_switchrule->signal = signal;
3120 new_switchrule->attributes = attributes;
3121 for (auto &it : cases)
3122 new_switchrule->cases.push_back(it->clone());
3123 return new_switchrule;
3124
3125 }
3126
3127 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3128 {
3129 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3130 new_syncrule->type = type;
3131 new_syncrule->signal = signal;
3132 new_syncrule->actions = actions;
3133 return new_syncrule;
3134 }
3135
3136 RTLIL::Process::~Process()
3137 {
3138 for (auto it = syncs.begin(); it != syncs.end(); it++)
3139 delete *it;
3140 }
3141
3142 RTLIL::Process *RTLIL::Process::clone() const
3143 {
3144 RTLIL::Process *new_proc = new RTLIL::Process;
3145
3146 new_proc->name = name;
3147 new_proc->attributes = attributes;
3148
3149 RTLIL::CaseRule *rc_ptr = root_case.clone();
3150 new_proc->root_case = *rc_ptr;
3151 rc_ptr->switches.clear();
3152 delete rc_ptr;
3153
3154 for (auto &it : syncs)
3155 new_proc->syncs.push_back(it->clone());
3156
3157 return new_proc;
3158 }
3159
3160 YOSYS_NAMESPACE_END
3161