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Merge pull request #998 from mdaiter/get_bool_attribute_opts
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else {
222 const auto it = attributes.find(id);
223 if (it != attributes.end())
224 attributes.erase(it);
225 }
226 }
227
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
229 {
230 const auto it = attributes.find(id);
231 if (it == attributes.end())
232 return false;
233 return it->second.as_bool();
234 }
235
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 string attrval;
239 for (auto &s : data) {
240 if (!attrval.empty())
241 attrval += "|";
242 attrval += s;
243 }
244 attributes[id] = RTLIL::Const(attrval);
245 }
246
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 pool<string> union_data = get_strpool_attribute(id);
250 union_data.insert(data.begin(), data.end());
251 if (!union_data.empty())
252 set_strpool_attribute(id, union_data);
253 }
254
255 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
256 {
257 pool<string> data;
258 if (attributes.count(id) != 0)
259 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
260 data.insert(s);
261 return data;
262 }
263
264 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
265 {
266 if (src.empty())
267 attributes.erase("\\src");
268 else
269 attributes["\\src"] = src;
270 }
271
272 std::string RTLIL::AttrObject::get_src_attribute() const
273 {
274 std::string src;
275 if (attributes.count("\\src"))
276 src = attributes.at("\\src").decode_string();
277 return src;
278 }
279
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 if (selected_members.count(mod_name) > 0)
287 return true;
288 return false;
289 }
290
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 return false;
298 }
299
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (full_selection)
303 return true;
304 if (selected_modules.count(mod_name) > 0)
305 return true;
306 if (selected_members.count(mod_name) > 0)
307 if (selected_members.at(mod_name).count(memb_name) > 0)
308 return true;
309 return false;
310 }
311
312 void RTLIL::Selection::optimize(RTLIL::Design *design)
313 {
314 if (full_selection) {
315 selected_modules.clear();
316 selected_members.clear();
317 return;
318 }
319
320 std::vector<RTLIL::IdString> del_list, add_list;
321
322 del_list.clear();
323 for (auto mod_name : selected_modules) {
324 if (design->modules_.count(mod_name) == 0)
325 del_list.push_back(mod_name);
326 selected_members.erase(mod_name);
327 }
328 for (auto mod_name : del_list)
329 selected_modules.erase(mod_name);
330
331 del_list.clear();
332 for (auto &it : selected_members)
333 if (design->modules_.count(it.first) == 0)
334 del_list.push_back(it.first);
335 for (auto mod_name : del_list)
336 selected_members.erase(mod_name);
337
338 for (auto &it : selected_members) {
339 del_list.clear();
340 for (auto memb_name : it.second)
341 if (design->modules_[it.first]->count_id(memb_name) == 0)
342 del_list.push_back(memb_name);
343 for (auto memb_name : del_list)
344 it.second.erase(memb_name);
345 }
346
347 del_list.clear();
348 add_list.clear();
349 for (auto &it : selected_members)
350 if (it.second.size() == 0)
351 del_list.push_back(it.first);
352 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
353 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
354 add_list.push_back(it.first);
355 for (auto mod_name : del_list)
356 selected_members.erase(mod_name);
357 for (auto mod_name : add_list) {
358 selected_members.erase(mod_name);
359 selected_modules.insert(mod_name);
360 }
361
362 if (selected_modules.size() == design->modules_.size()) {
363 full_selection = true;
364 selected_modules.clear();
365 selected_members.clear();
366 }
367 }
368
369 RTLIL::Design::Design()
370 {
371 static unsigned int hashidx_count = 123456789;
372 hashidx_count = mkhash_xorshift(hashidx_count);
373 hashidx_ = hashidx_count;
374
375 refcount_modules_ = 0;
376 selection_stack.push_back(RTLIL::Selection());
377
378 #ifdef WITH_PYTHON
379 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
380 #endif
381 }
382
383 RTLIL::Design::~Design()
384 {
385 for (auto it = modules_.begin(); it != modules_.end(); ++it)
386 delete it->second;
387 for (auto n : verilog_packages)
388 delete n;
389 for (auto n : verilog_globals)
390 delete n;
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->erase(hashidx_);
393 #endif
394 }
395
396 #ifdef WITH_PYTHON
397 static std::map<unsigned int, RTLIL::Design*> all_designs;
398 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
399 {
400 return &all_designs;
401 }
402 #endif
403
404 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
405 {
406 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
407 }
408
409 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
410 {
411 return modules_.count(name) ? modules_.at(name) : NULL;
412 }
413
414 RTLIL::Module *RTLIL::Design::top_module()
415 {
416 RTLIL::Module *module = nullptr;
417 int module_count = 0;
418
419 for (auto mod : selected_modules()) {
420 if (mod->get_bool_attribute("\\top"))
421 return mod;
422 module_count++;
423 module = mod;
424 }
425
426 return module_count == 1 ? module : nullptr;
427 }
428
429 void RTLIL::Design::add(RTLIL::Module *module)
430 {
431 log_assert(modules_.count(module->name) == 0);
432 log_assert(refcount_modules_ == 0);
433 modules_[module->name] = module;
434 module->design = this;
435
436 for (auto mon : monitors)
437 mon->notify_module_add(module);
438
439 if (yosys_xtrace) {
440 log("#X# New Module: %s\n", log_id(module));
441 log_backtrace("-X- ", yosys_xtrace-1);
442 }
443 }
444
445 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
446 {
447 log_assert(modules_.count(name) == 0);
448 log_assert(refcount_modules_ == 0);
449
450 RTLIL::Module *module = new RTLIL::Module;
451 modules_[name] = module;
452 module->design = this;
453 module->name = name;
454
455 for (auto mon : monitors)
456 mon->notify_module_add(module);
457
458 if (yosys_xtrace) {
459 log("#X# New Module: %s\n", log_id(module));
460 log_backtrace("-X- ", yosys_xtrace-1);
461 }
462
463 return module;
464 }
465
466 void RTLIL::Design::scratchpad_unset(std::string varname)
467 {
468 scratchpad.erase(varname);
469 }
470
471 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
472 {
473 scratchpad[varname] = stringf("%d", value);
474 }
475
476 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
477 {
478 scratchpad[varname] = value ? "true" : "false";
479 }
480
481 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
482 {
483 scratchpad[varname] = value;
484 }
485
486 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
487 {
488 if (scratchpad.count(varname) == 0)
489 return default_value;
490
491 std::string str = scratchpad.at(varname);
492
493 if (str == "0" || str == "false")
494 return 0;
495
496 if (str == "1" || str == "true")
497 return 1;
498
499 char *endptr = nullptr;
500 long int parsed_value = strtol(str.c_str(), &endptr, 10);
501 return *endptr ? default_value : parsed_value;
502 }
503
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
505 {
506 if (scratchpad.count(varname) == 0)
507 return default_value;
508
509 std::string str = scratchpad.at(varname);
510
511 if (str == "0" || str == "false")
512 return false;
513
514 if (str == "1" || str == "true")
515 return true;
516
517 return default_value;
518 }
519
520 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
521 {
522 if (scratchpad.count(varname) == 0)
523 return default_value;
524 return scratchpad.at(varname);
525 }
526
527 void RTLIL::Design::remove(RTLIL::Module *module)
528 {
529 for (auto mon : monitors)
530 mon->notify_module_del(module);
531
532 if (yosys_xtrace) {
533 log("#X# Remove Module: %s\n", log_id(module));
534 log_backtrace("-X- ", yosys_xtrace-1);
535 }
536
537 log_assert(modules_.at(module->name) == module);
538 modules_.erase(module->name);
539 delete module;
540 }
541
542 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
543 {
544 modules_.erase(module->name);
545 module->name = new_name;
546 add(module);
547 }
548
549 void RTLIL::Design::sort()
550 {
551 scratchpad.sort();
552 modules_.sort(sort_by_id_str());
553 for (auto &it : modules_)
554 it.second->sort();
555 }
556
557 void RTLIL::Design::check()
558 {
559 #ifndef NDEBUG
560 for (auto &it : modules_) {
561 log_assert(this == it.second->design);
562 log_assert(it.first == it.second->name);
563 log_assert(!it.first.empty());
564 it.second->check();
565 }
566 #endif
567 }
568
569 void RTLIL::Design::optimize()
570 {
571 for (auto &it : modules_)
572 it.second->optimize();
573 for (auto &it : selection_stack)
574 it.optimize(this);
575 for (auto &it : selection_vars)
576 it.second.optimize(this);
577 }
578
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
580 {
581 if (!selected_active_module.empty() && mod_name != selected_active_module)
582 return false;
583 if (selection_stack.size() == 0)
584 return true;
585 return selection_stack.back().selected_module(mod_name);
586 }
587
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
589 {
590 if (!selected_active_module.empty() && mod_name != selected_active_module)
591 return false;
592 if (selection_stack.size() == 0)
593 return true;
594 return selection_stack.back().selected_whole_module(mod_name);
595 }
596
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
598 {
599 if (!selected_active_module.empty() && mod_name != selected_active_module)
600 return false;
601 if (selection_stack.size() == 0)
602 return true;
603 return selection_stack.back().selected_member(mod_name, memb_name);
604 }
605
606 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
607 {
608 return selected_module(mod->name);
609 }
610
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
612 {
613 return selected_whole_module(mod->name);
614 }
615
616 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
617 {
618 std::vector<RTLIL::Module*> result;
619 result.reserve(modules_.size());
620 for (auto &it : modules_)
621 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
622 result.push_back(it.second);
623 return result;
624 }
625
626 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
627 {
628 std::vector<RTLIL::Module*> result;
629 result.reserve(modules_.size());
630 for (auto &it : modules_)
631 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
632 result.push_back(it.second);
633 return result;
634 }
635
636 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
637 {
638 std::vector<RTLIL::Module*> result;
639 result.reserve(modules_.size());
640 for (auto &it : modules_)
641 if (it.second->get_blackbox_attribute())
642 continue;
643 else if (selected_whole_module(it.first))
644 result.push_back(it.second);
645 else if (selected_module(it.first))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
647 return result;
648 }
649
650 RTLIL::Module::Module()
651 {
652 static unsigned int hashidx_count = 123456789;
653 hashidx_count = mkhash_xorshift(hashidx_count);
654 hashidx_ = hashidx_count;
655
656 design = nullptr;
657 refcount_wires_ = 0;
658 refcount_cells_ = 0;
659
660 #ifdef WITH_PYTHON
661 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
662 #endif
663 }
664
665 RTLIL::Module::~Module()
666 {
667 for (auto it = wires_.begin(); it != wires_.end(); ++it)
668 delete it->second;
669 for (auto it = memories.begin(); it != memories.end(); ++it)
670 delete it->second;
671 for (auto it = cells_.begin(); it != cells_.end(); ++it)
672 delete it->second;
673 for (auto it = processes.begin(); it != processes.end(); ++it)
674 delete it->second;
675 #ifdef WITH_PYTHON
676 RTLIL::Module::get_all_modules()->erase(hashidx_);
677 #endif
678 }
679
680 #ifdef WITH_PYTHON
681 static std::map<unsigned int, RTLIL::Module*> all_modules;
682 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
683 {
684 return &all_modules;
685 }
686 #endif
687
688 void RTLIL::Module::makeblackbox()
689 {
690 pool<RTLIL::Wire*> delwires;
691
692 for (auto it = wires_.begin(); it != wires_.end(); ++it)
693 if (!it->second->port_input && !it->second->port_output)
694 delwires.insert(it->second);
695
696 for (auto it = memories.begin(); it != memories.end(); ++it)
697 delete it->second;
698 memories.clear();
699
700 for (auto it = cells_.begin(); it != cells_.end(); ++it)
701 delete it->second;
702 cells_.clear();
703
704 for (auto it = processes.begin(); it != processes.end(); ++it)
705 delete it->second;
706 processes.clear();
707
708 remove(delwires);
709 set_bool_attribute("\\blackbox");
710 }
711
712 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
713 {
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
715 }
716
717 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
718 {
719 if (mayfail)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
722 }
723
724
725 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
726 {
727 if (mayfail)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
730 }
731
732 size_t RTLIL::Module::count_id(RTLIL::IdString id)
733 {
734 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
735 }
736
737 #ifndef NDEBUG
738 namespace {
739 struct InternalCellChecker
740 {
741 RTLIL::Module *module;
742 RTLIL::Cell *cell;
743 pool<RTLIL::IdString> expected_params, expected_ports;
744
745 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
746
747 void error(int linenr)
748 {
749 std::stringstream buf;
750 ILANG_BACKEND::dump_cell(buf, " ", cell);
751
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module ? module->name.c_str() : "", module ? "." : "",
754 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
755 }
756
757 int param(const char *name)
758 {
759 if (cell->parameters.count(name) == 0)
760 error(__LINE__);
761 expected_params.insert(name);
762 return cell->parameters.at(name).as_int();
763 }
764
765 int param_bool(const char *name)
766 {
767 int v = param(name);
768 if (cell->parameters.at(name).bits.size() > 32)
769 error(__LINE__);
770 if (v != 0 && v != 1)
771 error(__LINE__);
772 return v;
773 }
774
775 void param_bits(const char *name, int width)
776 {
777 param(name);
778 if (int(cell->parameters.at(name).bits.size()) != width)
779 error(__LINE__);
780 }
781
782 void port(const char *name, int width)
783 {
784 if (!cell->hasPort(name))
785 error(__LINE__);
786 if (cell->getPort(name).size() != width)
787 error(__LINE__);
788 expected_ports.insert(name);
789 }
790
791 void check_expected(bool check_matched_sign = true)
792 {
793 for (auto &para : cell->parameters)
794 if (expected_params.count(para.first) == 0)
795 error(__LINE__);
796 for (auto &conn : cell->connections())
797 if (expected_ports.count(conn.first) == 0)
798 error(__LINE__);
799
800 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
801 bool a_is_signed = param("\\A_SIGNED") != 0;
802 bool b_is_signed = param("\\B_SIGNED") != 0;
803 if (a_is_signed != b_is_signed)
804 error(__LINE__);
805 }
806 }
807
808 void check_gate(const char *ports)
809 {
810 if (cell->parameters.size() != 0)
811 error(__LINE__);
812
813 for (const char *p = ports; *p; p++) {
814 char portname[3] = { '\\', *p, 0 };
815 if (!cell->hasPort(portname))
816 error(__LINE__);
817 if (cell->getPort(portname).size() != 1)
818 error(__LINE__);
819 }
820
821 for (auto &conn : cell->connections()) {
822 if (conn.first.size() != 2 || conn.first[0] != '\\')
823 error(__LINE__);
824 if (strchr(ports, conn.first[1]) == NULL)
825 error(__LINE__);
826 }
827 }
828
829 void check()
830 {
831 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
832 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
833 return;
834
835 if (cell->type.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
839 check_expected();
840 return;
841 }
842
843 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
857 check_expected();
858 return;
859 }
860
861 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
868 return;
869 }
870
871 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell->type != "$pow");
888 return;
889 }
890
891 if (cell->type == "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
904 port("\\CI", 1);
905 port("\\CO", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
915 port("\\CI", 1);
916 port("\\BI", 1);
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
920 check_expected();
921 return;
922 }
923
924 if (cell->type == "$macc") {
925 param("\\CONFIG");
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
930 check_expected();
931 Macc().from_cell(cell);
932 return;
933 }
934
935 if (cell->type == "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
939 check_expected();
940 return;
941 }
942
943 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
950 return;
951 }
952
953 if (cell->type == "$slice") {
954 param("\\OFFSET");
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
958 error(__LINE__);
959 check_expected();
960 return;
961 }
962
963 if (cell->type == "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
974 port("\\S", 1);
975 port("\\Y", param("\\WIDTH"));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
985 check_expected();
986 return;
987 }
988
989 if (cell->type == "$lut") {
990 param("\\LUT");
991 port("\\A", param("\\WIDTH"));
992 port("\\Y", 1);
993 check_expected();
994 return;
995 }
996
997 if (cell->type == "$sop") {
998 param("\\DEPTH");
999 param("\\TABLE");
1000 port("\\A", param("\\WIDTH"));
1001 port("\\Y", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1012 check_expected();
1013 return;
1014 }
1015
1016 if (cell->type == "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == "$dff") {
1024 param_bool("\\CLK_POLARITY");
1025 port("\\CLK", 1);
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1028 check_expected();
1029 return;
1030 }
1031
1032 if (cell->type == "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1035 port("\\CLK", 1);
1036 port("\\EN", 1);
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1047 port("\\CLK", 1);
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1070 port("\\EN", 1);
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1081 port("\\EN", 1);
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == "$fsm") {
1091 param("\\NAME");
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1101 port("\\CLK", 1);
1102 port("\\ARST", 1);
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == "$memrd") {
1110 param("\\MEMID");
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1114 port("\\CLK", 1);
1115 port("\\EN", 1);
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == "$memwr") {
1123 param("\\MEMID");
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1127 port("\\CLK", 1);
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1131 check_expected();
1132 return;
1133 }
1134
1135 if (cell->type == "$meminit") {
1136 param("\\MEMID");
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == "$mem") {
1145 param("\\MEMID");
1146 param("\\SIZE");
1147 param("\\OFFSET");
1148 param("\\INIT");
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1169 port("\\EN", 1);
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1175 port("\\A", 1);
1176 port("\\EN", 1);
1177 check_expected();
1178 return;
1179 }
1180
1181 if (cell->type == "$initstate") {
1182 port("\\Y", 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1189 check_expected();
1190 return;
1191 }
1192
1193 if (cell->type == "$equiv") {
1194 port("\\A", 1);
1195 port("\\B", 1);
1196 port("\\Y", 1);
1197 check_expected();
1198 return;
1199 }
1200
1201 if (cell->type.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1211 port("\\EN", 1);
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell->type == "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1220 }
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == "$specrule") {
1226 param("\\TYPE");
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1231 param("\\T_LIMIT");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1242 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1243 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1253 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1254 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1255 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1256
1257 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1258
1259 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1260 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1261 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1262
1263 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1264 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1265 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1266 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1267
1268 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1269 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1270 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1271
1272 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1273 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1274 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1275 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1276
1277 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1281 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1282 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1283 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1284 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1285
1286 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1290 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1291 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1292 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1293 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1294
1295 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1296 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1297
1298 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1302 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1303 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1304 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1305 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1306
1307 error(__LINE__);
1308 }
1309 };
1310 }
1311 #endif
1312
1313 void RTLIL::Module::sort()
1314 {
1315 wires_.sort(sort_by_id_str());
1316 cells_.sort(sort_by_id_str());
1317 avail_parameters.sort(sort_by_id_str());
1318 memories.sort(sort_by_id_str());
1319 processes.sort(sort_by_id_str());
1320 for (auto &it : cells_)
1321 it.second->sort();
1322 for (auto &it : wires_)
1323 it.second->attributes.sort(sort_by_id_str());
1324 for (auto &it : memories)
1325 it.second->attributes.sort(sort_by_id_str());
1326 }
1327
1328 void RTLIL::Module::check()
1329 {
1330 #ifndef NDEBUG
1331 std::vector<bool> ports_declared;
1332 for (auto &it : wires_) {
1333 log_assert(this == it.second->module);
1334 log_assert(it.first == it.second->name);
1335 log_assert(!it.first.empty());
1336 log_assert(it.second->width >= 0);
1337 log_assert(it.second->port_id >= 0);
1338 for (auto &it2 : it.second->attributes)
1339 log_assert(!it2.first.empty());
1340 if (it.second->port_id) {
1341 log_assert(GetSize(ports) >= it.second->port_id);
1342 log_assert(ports.at(it.second->port_id-1) == it.first);
1343 log_assert(it.second->port_input || it.second->port_output);
1344 if (GetSize(ports_declared) < it.second->port_id)
1345 ports_declared.resize(it.second->port_id);
1346 log_assert(ports_declared[it.second->port_id-1] == false);
1347 ports_declared[it.second->port_id-1] = true;
1348 } else
1349 log_assert(!it.second->port_input && !it.second->port_output);
1350 }
1351 for (auto port_declared : ports_declared)
1352 log_assert(port_declared == true);
1353 log_assert(GetSize(ports) == GetSize(ports_declared));
1354
1355 for (auto &it : memories) {
1356 log_assert(it.first == it.second->name);
1357 log_assert(!it.first.empty());
1358 log_assert(it.second->width >= 0);
1359 log_assert(it.second->size >= 0);
1360 for (auto &it2 : it.second->attributes)
1361 log_assert(!it2.first.empty());
1362 }
1363
1364 for (auto &it : cells_) {
1365 log_assert(this == it.second->module);
1366 log_assert(it.first == it.second->name);
1367 log_assert(!it.first.empty());
1368 log_assert(!it.second->type.empty());
1369 for (auto &it2 : it.second->connections()) {
1370 log_assert(!it2.first.empty());
1371 it2.second.check();
1372 }
1373 for (auto &it2 : it.second->attributes)
1374 log_assert(!it2.first.empty());
1375 for (auto &it2 : it.second->parameters)
1376 log_assert(!it2.first.empty());
1377 InternalCellChecker checker(this, it.second);
1378 checker.check();
1379 }
1380
1381 for (auto &it : processes) {
1382 log_assert(it.first == it.second->name);
1383 log_assert(!it.first.empty());
1384 // FIXME: More checks here..
1385 }
1386
1387 for (auto &it : connections_) {
1388 log_assert(it.first.size() == it.second.size());
1389 log_assert(!it.first.has_const());
1390 it.first.check();
1391 it.second.check();
1392 }
1393
1394 for (auto &it : attributes)
1395 log_assert(!it.first.empty());
1396 #endif
1397 }
1398
1399 void RTLIL::Module::optimize()
1400 {
1401 }
1402
1403 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1404 {
1405 log_assert(new_mod->refcount_wires_ == 0);
1406 log_assert(new_mod->refcount_cells_ == 0);
1407
1408 new_mod->avail_parameters = avail_parameters;
1409
1410 for (auto &conn : connections_)
1411 new_mod->connect(conn);
1412
1413 for (auto &attr : attributes)
1414 new_mod->attributes[attr.first] = attr.second;
1415
1416 for (auto &it : wires_)
1417 new_mod->addWire(it.first, it.second);
1418
1419 for (auto &it : memories)
1420 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1421
1422 for (auto &it : cells_)
1423 new_mod->addCell(it.first, it.second);
1424
1425 for (auto &it : processes)
1426 new_mod->processes[it.first] = it.second->clone();
1427
1428 struct RewriteSigSpecWorker
1429 {
1430 RTLIL::Module *mod;
1431 void operator()(RTLIL::SigSpec &sig)
1432 {
1433 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1434 for (auto &c : chunks)
1435 if (c.wire != NULL)
1436 c.wire = mod->wires_.at(c.wire->name);
1437 sig = chunks;
1438 }
1439 };
1440
1441 RewriteSigSpecWorker rewriteSigSpecWorker;
1442 rewriteSigSpecWorker.mod = new_mod;
1443 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1444 new_mod->fixup_ports();
1445 }
1446
1447 RTLIL::Module *RTLIL::Module::clone() const
1448 {
1449 RTLIL::Module *new_mod = new RTLIL::Module;
1450 new_mod->name = name;
1451 cloneInto(new_mod);
1452 return new_mod;
1453 }
1454
1455 bool RTLIL::Module::has_memories() const
1456 {
1457 return !memories.empty();
1458 }
1459
1460 bool RTLIL::Module::has_processes() const
1461 {
1462 return !processes.empty();
1463 }
1464
1465 bool RTLIL::Module::has_memories_warn() const
1466 {
1467 if (!memories.empty())
1468 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1469 return !memories.empty();
1470 }
1471
1472 bool RTLIL::Module::has_processes_warn() const
1473 {
1474 if (!processes.empty())
1475 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1476 return !processes.empty();
1477 }
1478
1479 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1480 {
1481 std::vector<RTLIL::Wire*> result;
1482 result.reserve(wires_.size());
1483 for (auto &it : wires_)
1484 if (design->selected(this, it.second))
1485 result.push_back(it.second);
1486 return result;
1487 }
1488
1489 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1490 {
1491 std::vector<RTLIL::Cell*> result;
1492 result.reserve(wires_.size());
1493 for (auto &it : cells_)
1494 if (design->selected(this, it.second))
1495 result.push_back(it.second);
1496 return result;
1497 }
1498
1499 void RTLIL::Module::add(RTLIL::Wire *wire)
1500 {
1501 log_assert(!wire->name.empty());
1502 log_assert(count_id(wire->name) == 0);
1503 log_assert(refcount_wires_ == 0);
1504 wires_[wire->name] = wire;
1505 wire->module = this;
1506 }
1507
1508 void RTLIL::Module::add(RTLIL::Cell *cell)
1509 {
1510 log_assert(!cell->name.empty());
1511 log_assert(count_id(cell->name) == 0);
1512 log_assert(refcount_cells_ == 0);
1513 cells_[cell->name] = cell;
1514 cell->module = this;
1515 }
1516
1517 namespace {
1518 struct DeleteWireWorker
1519 {
1520 RTLIL::Module *module;
1521 const pool<RTLIL::Wire*> *wires_p;
1522
1523 void operator()(RTLIL::SigSpec &sig) {
1524 std::vector<RTLIL::SigChunk> chunks = sig;
1525 for (auto &c : chunks)
1526 if (c.wire != NULL && wires_p->count(c.wire)) {
1527 c.wire = module->addWire(NEW_ID, c.width);
1528 c.offset = 0;
1529 }
1530 sig = chunks;
1531 }
1532 };
1533 }
1534
1535 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1536 {
1537 log_assert(refcount_wires_ == 0);
1538
1539 DeleteWireWorker delete_wire_worker;
1540 delete_wire_worker.module = this;
1541 delete_wire_worker.wires_p = &wires;
1542 rewrite_sigspecs(delete_wire_worker);
1543
1544 for (auto &it : wires) {
1545 log_assert(wires_.count(it->name) != 0);
1546 wires_.erase(it->name);
1547 delete it;
1548 }
1549 }
1550
1551 void RTLIL::Module::remove(RTLIL::Cell *cell)
1552 {
1553 while (!cell->connections_.empty())
1554 cell->unsetPort(cell->connections_.begin()->first);
1555
1556 log_assert(cells_.count(cell->name) != 0);
1557 log_assert(refcount_cells_ == 0);
1558 cells_.erase(cell->name);
1559 delete cell;
1560 }
1561
1562 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1563 {
1564 log_assert(wires_[wire->name] == wire);
1565 log_assert(refcount_wires_ == 0);
1566 wires_.erase(wire->name);
1567 wire->name = new_name;
1568 add(wire);
1569 }
1570
1571 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1572 {
1573 log_assert(cells_[cell->name] == cell);
1574 log_assert(refcount_wires_ == 0);
1575 cells_.erase(cell->name);
1576 cell->name = new_name;
1577 add(cell);
1578 }
1579
1580 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1581 {
1582 log_assert(count_id(old_name) != 0);
1583 if (wires_.count(old_name))
1584 rename(wires_.at(old_name), new_name);
1585 else if (cells_.count(old_name))
1586 rename(cells_.at(old_name), new_name);
1587 else
1588 log_abort();
1589 }
1590
1591 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1592 {
1593 log_assert(wires_[w1->name] == w1);
1594 log_assert(wires_[w2->name] == w2);
1595 log_assert(refcount_wires_ == 0);
1596
1597 wires_.erase(w1->name);
1598 wires_.erase(w2->name);
1599
1600 std::swap(w1->name, w2->name);
1601
1602 wires_[w1->name] = w1;
1603 wires_[w2->name] = w2;
1604 }
1605
1606 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1607 {
1608 log_assert(cells_[c1->name] == c1);
1609 log_assert(cells_[c2->name] == c2);
1610 log_assert(refcount_cells_ == 0);
1611
1612 cells_.erase(c1->name);
1613 cells_.erase(c2->name);
1614
1615 std::swap(c1->name, c2->name);
1616
1617 cells_[c1->name] = c1;
1618 cells_[c2->name] = c2;
1619 }
1620
1621 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1622 {
1623 int index = 0;
1624 return uniquify(name, index);
1625 }
1626
1627 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1628 {
1629 if (index == 0) {
1630 if (count_id(name) == 0)
1631 return name;
1632 index++;
1633 }
1634
1635 while (1) {
1636 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1637 if (count_id(new_name) == 0)
1638 return new_name;
1639 index++;
1640 }
1641 }
1642
1643 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1644 {
1645 if (a->port_id && !b->port_id)
1646 return true;
1647 if (!a->port_id && b->port_id)
1648 return false;
1649
1650 if (a->port_id == b->port_id)
1651 return a->name < b->name;
1652 return a->port_id < b->port_id;
1653 }
1654
1655 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1656 {
1657 for (auto mon : monitors)
1658 mon->notify_connect(this, conn);
1659
1660 if (design)
1661 for (auto mon : design->monitors)
1662 mon->notify_connect(this, conn);
1663
1664 // ignore all attempts to assign constants to other constants
1665 if (conn.first.has_const()) {
1666 RTLIL::SigSig new_conn;
1667 for (int i = 0; i < GetSize(conn.first); i++)
1668 if (conn.first[i].wire) {
1669 new_conn.first.append(conn.first[i]);
1670 new_conn.second.append(conn.second[i]);
1671 }
1672 if (GetSize(new_conn.first))
1673 connect(new_conn);
1674 return;
1675 }
1676
1677 if (yosys_xtrace) {
1678 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1679 log_backtrace("-X- ", yosys_xtrace-1);
1680 }
1681
1682 log_assert(GetSize(conn.first) == GetSize(conn.second));
1683 connections_.push_back(conn);
1684 }
1685
1686 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1687 {
1688 connect(RTLIL::SigSig(lhs, rhs));
1689 }
1690
1691 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1692 {
1693 for (auto mon : monitors)
1694 mon->notify_connect(this, new_conn);
1695
1696 if (design)
1697 for (auto mon : design->monitors)
1698 mon->notify_connect(this, new_conn);
1699
1700 if (yosys_xtrace) {
1701 log("#X# New connections vector in %s:\n", log_id(this));
1702 for (auto &conn: new_conn)
1703 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1704 log_backtrace("-X- ", yosys_xtrace-1);
1705 }
1706
1707 connections_ = new_conn;
1708 }
1709
1710 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1711 {
1712 return connections_;
1713 }
1714
1715 void RTLIL::Module::fixup_ports()
1716 {
1717 std::vector<RTLIL::Wire*> all_ports;
1718
1719 for (auto &w : wires_)
1720 if (w.second->port_input || w.second->port_output)
1721 all_ports.push_back(w.second);
1722 else
1723 w.second->port_id = 0;
1724
1725 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1726
1727 ports.clear();
1728 for (size_t i = 0; i < all_ports.size(); i++) {
1729 ports.push_back(all_ports[i]->name);
1730 all_ports[i]->port_id = i+1;
1731 }
1732 }
1733
1734 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1735 {
1736 RTLIL::Wire *wire = new RTLIL::Wire;
1737 wire->name = name;
1738 wire->width = width;
1739 add(wire);
1740 return wire;
1741 }
1742
1743 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1744 {
1745 RTLIL::Wire *wire = addWire(name);
1746 wire->width = other->width;
1747 wire->start_offset = other->start_offset;
1748 wire->port_id = other->port_id;
1749 wire->port_input = other->port_input;
1750 wire->port_output = other->port_output;
1751 wire->upto = other->upto;
1752 wire->attributes = other->attributes;
1753 return wire;
1754 }
1755
1756 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1757 {
1758 RTLIL::Cell *cell = new RTLIL::Cell;
1759 cell->name = name;
1760 cell->type = type;
1761 add(cell);
1762 return cell;
1763 }
1764
1765 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1766 {
1767 RTLIL::Cell *cell = addCell(name, other->type);
1768 cell->connections_ = other->connections_;
1769 cell->parameters = other->parameters;
1770 cell->attributes = other->attributes;
1771 return cell;
1772 }
1773
1774 #define DEF_METHOD(_func, _y_size, _type) \
1775 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1776 RTLIL::Cell *cell = addCell(name, _type); \
1777 cell->parameters["\\A_SIGNED"] = is_signed; \
1778 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1779 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1780 cell->setPort("\\A", sig_a); \
1781 cell->setPort("\\Y", sig_y); \
1782 cell->set_src_attribute(src); \
1783 return cell; \
1784 } \
1785 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1786 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1787 add ## _func(name, sig_a, sig_y, is_signed, src); \
1788 return sig_y; \
1789 }
1790 DEF_METHOD(Not, sig_a.size(), "$not")
1791 DEF_METHOD(Pos, sig_a.size(), "$pos")
1792 DEF_METHOD(Neg, sig_a.size(), "$neg")
1793 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1794 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1795 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1796 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1797 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1798 DEF_METHOD(LogicNot, 1, "$logic_not")
1799 #undef DEF_METHOD
1800
1801 #define DEF_METHOD(_func, _y_size, _type) \
1802 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1803 RTLIL::Cell *cell = addCell(name, _type); \
1804 cell->parameters["\\A_SIGNED"] = is_signed; \
1805 cell->parameters["\\B_SIGNED"] = is_signed; \
1806 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1807 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1808 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1809 cell->setPort("\\A", sig_a); \
1810 cell->setPort("\\B", sig_b); \
1811 cell->setPort("\\Y", sig_y); \
1812 cell->set_src_attribute(src); \
1813 return cell; \
1814 } \
1815 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1816 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1817 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1818 return sig_y; \
1819 }
1820 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1821 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1822 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1823 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1824 DEF_METHOD(Shl, sig_a.size(), "$shl")
1825 DEF_METHOD(Shr, sig_a.size(), "$shr")
1826 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1827 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1828 DEF_METHOD(Shift, sig_a.size(), "$shift")
1829 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1830 DEF_METHOD(Lt, 1, "$lt")
1831 DEF_METHOD(Le, 1, "$le")
1832 DEF_METHOD(Eq, 1, "$eq")
1833 DEF_METHOD(Ne, 1, "$ne")
1834 DEF_METHOD(Eqx, 1, "$eqx")
1835 DEF_METHOD(Nex, 1, "$nex")
1836 DEF_METHOD(Ge, 1, "$ge")
1837 DEF_METHOD(Gt, 1, "$gt")
1838 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1839 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1840 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1841 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1842 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1843 DEF_METHOD(LogicAnd, 1, "$logic_and")
1844 DEF_METHOD(LogicOr, 1, "$logic_or")
1845 #undef DEF_METHOD
1846
1847 #define DEF_METHOD(_func, _type, _pmux) \
1848 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1849 RTLIL::Cell *cell = addCell(name, _type); \
1850 cell->parameters["\\WIDTH"] = sig_a.size(); \
1851 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1852 cell->setPort("\\A", sig_a); \
1853 cell->setPort("\\B", sig_b); \
1854 cell->setPort("\\S", sig_s); \
1855 cell->setPort("\\Y", sig_y); \
1856 cell->set_src_attribute(src); \
1857 return cell; \
1858 } \
1859 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1860 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1861 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1862 return sig_y; \
1863 }
1864 DEF_METHOD(Mux, "$mux", 0)
1865 DEF_METHOD(Pmux, "$pmux", 1)
1866 #undef DEF_METHOD
1867
1868 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1869 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1870 RTLIL::Cell *cell = addCell(name, _type); \
1871 cell->setPort("\\" #_P1, sig1); \
1872 cell->setPort("\\" #_P2, sig2); \
1873 cell->set_src_attribute(src); \
1874 return cell; \
1875 } \
1876 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1877 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1878 add ## _func(name, sig1, sig2, src); \
1879 return sig2; \
1880 }
1881 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1882 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1883 RTLIL::Cell *cell = addCell(name, _type); \
1884 cell->setPort("\\" #_P1, sig1); \
1885 cell->setPort("\\" #_P2, sig2); \
1886 cell->setPort("\\" #_P3, sig3); \
1887 cell->set_src_attribute(src); \
1888 return cell; \
1889 } \
1890 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1891 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1892 add ## _func(name, sig1, sig2, sig3, src); \
1893 return sig3; \
1894 }
1895 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1896 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1897 RTLIL::Cell *cell = addCell(name, _type); \
1898 cell->setPort("\\" #_P1, sig1); \
1899 cell->setPort("\\" #_P2, sig2); \
1900 cell->setPort("\\" #_P3, sig3); \
1901 cell->setPort("\\" #_P4, sig4); \
1902 cell->set_src_attribute(src); \
1903 return cell; \
1904 } \
1905 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1906 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1907 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1908 return sig4; \
1909 }
1910 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1911 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1912 RTLIL::Cell *cell = addCell(name, _type); \
1913 cell->setPort("\\" #_P1, sig1); \
1914 cell->setPort("\\" #_P2, sig2); \
1915 cell->setPort("\\" #_P3, sig3); \
1916 cell->setPort("\\" #_P4, sig4); \
1917 cell->setPort("\\" #_P5, sig5); \
1918 cell->set_src_attribute(src); \
1919 return cell; \
1920 } \
1921 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1922 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1923 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1924 return sig5; \
1925 }
1926 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1927 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1928 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1929 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1930 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1931 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1932 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1933 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1934 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1935 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1936 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1937 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1938 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1939 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1940 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1941 #undef DEF_METHOD_2
1942 #undef DEF_METHOD_3
1943 #undef DEF_METHOD_4
1944 #undef DEF_METHOD_5
1945
1946 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1947 {
1948 RTLIL::Cell *cell = addCell(name, "$pow");
1949 cell->parameters["\\A_SIGNED"] = a_signed;
1950 cell->parameters["\\B_SIGNED"] = b_signed;
1951 cell->parameters["\\A_WIDTH"] = sig_a.size();
1952 cell->parameters["\\B_WIDTH"] = sig_b.size();
1953 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1954 cell->setPort("\\A", sig_a);
1955 cell->setPort("\\B", sig_b);
1956 cell->setPort("\\Y", sig_y);
1957 cell->set_src_attribute(src);
1958 return cell;
1959 }
1960
1961 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1962 {
1963 RTLIL::Cell *cell = addCell(name, "$slice");
1964 cell->parameters["\\A_WIDTH"] = sig_a.size();
1965 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1966 cell->parameters["\\OFFSET"] = offset;
1967 cell->setPort("\\A", sig_a);
1968 cell->setPort("\\Y", sig_y);
1969 cell->set_src_attribute(src);
1970 return cell;
1971 }
1972
1973 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1974 {
1975 RTLIL::Cell *cell = addCell(name, "$concat");
1976 cell->parameters["\\A_WIDTH"] = sig_a.size();
1977 cell->parameters["\\B_WIDTH"] = sig_b.size();
1978 cell->setPort("\\A", sig_a);
1979 cell->setPort("\\B", sig_b);
1980 cell->setPort("\\Y", sig_y);
1981 cell->set_src_attribute(src);
1982 return cell;
1983 }
1984
1985 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1986 {
1987 RTLIL::Cell *cell = addCell(name, "$lut");
1988 cell->parameters["\\LUT"] = lut;
1989 cell->parameters["\\WIDTH"] = sig_a.size();
1990 cell->setPort("\\A", sig_a);
1991 cell->setPort("\\Y", sig_y);
1992 cell->set_src_attribute(src);
1993 return cell;
1994 }
1995
1996 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1997 {
1998 RTLIL::Cell *cell = addCell(name, "$tribuf");
1999 cell->parameters["\\WIDTH"] = sig_a.size();
2000 cell->setPort("\\A", sig_a);
2001 cell->setPort("\\EN", sig_en);
2002 cell->setPort("\\Y", sig_y);
2003 cell->set_src_attribute(src);
2004 return cell;
2005 }
2006
2007 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2008 {
2009 RTLIL::Cell *cell = addCell(name, "$assert");
2010 cell->setPort("\\A", sig_a);
2011 cell->setPort("\\EN", sig_en);
2012 cell->set_src_attribute(src);
2013 return cell;
2014 }
2015
2016 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2017 {
2018 RTLIL::Cell *cell = addCell(name, "$assume");
2019 cell->setPort("\\A", sig_a);
2020 cell->setPort("\\EN", sig_en);
2021 cell->set_src_attribute(src);
2022 return cell;
2023 }
2024
2025 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2026 {
2027 RTLIL::Cell *cell = addCell(name, "$live");
2028 cell->setPort("\\A", sig_a);
2029 cell->setPort("\\EN", sig_en);
2030 cell->set_src_attribute(src);
2031 return cell;
2032 }
2033
2034 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2035 {
2036 RTLIL::Cell *cell = addCell(name, "$fair");
2037 cell->setPort("\\A", sig_a);
2038 cell->setPort("\\EN", sig_en);
2039 cell->set_src_attribute(src);
2040 return cell;
2041 }
2042
2043 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2044 {
2045 RTLIL::Cell *cell = addCell(name, "$cover");
2046 cell->setPort("\\A", sig_a);
2047 cell->setPort("\\EN", sig_en);
2048 cell->set_src_attribute(src);
2049 return cell;
2050 }
2051
2052 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2053 {
2054 RTLIL::Cell *cell = addCell(name, "$equiv");
2055 cell->setPort("\\A", sig_a);
2056 cell->setPort("\\B", sig_b);
2057 cell->setPort("\\Y", sig_y);
2058 cell->set_src_attribute(src);
2059 return cell;
2060 }
2061
2062 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2063 {
2064 RTLIL::Cell *cell = addCell(name, "$sr");
2065 cell->parameters["\\SET_POLARITY"] = set_polarity;
2066 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2067 cell->parameters["\\WIDTH"] = sig_q.size();
2068 cell->setPort("\\SET", sig_set);
2069 cell->setPort("\\CLR", sig_clr);
2070 cell->setPort("\\Q", sig_q);
2071 cell->set_src_attribute(src);
2072 return cell;
2073 }
2074
2075 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2076 {
2077 RTLIL::Cell *cell = addCell(name, "$ff");
2078 cell->parameters["\\WIDTH"] = sig_q.size();
2079 cell->setPort("\\D", sig_d);
2080 cell->setPort("\\Q", sig_q);
2081 cell->set_src_attribute(src);
2082 return cell;
2083 }
2084
2085 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2086 {
2087 RTLIL::Cell *cell = addCell(name, "$dff");
2088 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2089 cell->parameters["\\WIDTH"] = sig_q.size();
2090 cell->setPort("\\CLK", sig_clk);
2091 cell->setPort("\\D", sig_d);
2092 cell->setPort("\\Q", sig_q);
2093 cell->set_src_attribute(src);
2094 return cell;
2095 }
2096
2097 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2098 {
2099 RTLIL::Cell *cell = addCell(name, "$dffe");
2100 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2101 cell->parameters["\\EN_POLARITY"] = en_polarity;
2102 cell->parameters["\\WIDTH"] = sig_q.size();
2103 cell->setPort("\\CLK", sig_clk);
2104 cell->setPort("\\EN", sig_en);
2105 cell->setPort("\\D", sig_d);
2106 cell->setPort("\\Q", sig_q);
2107 cell->set_src_attribute(src);
2108 return cell;
2109 }
2110
2111 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2112 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2113 {
2114 RTLIL::Cell *cell = addCell(name, "$dffsr");
2115 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2116 cell->parameters["\\SET_POLARITY"] = set_polarity;
2117 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2118 cell->parameters["\\WIDTH"] = sig_q.size();
2119 cell->setPort("\\CLK", sig_clk);
2120 cell->setPort("\\SET", sig_set);
2121 cell->setPort("\\CLR", sig_clr);
2122 cell->setPort("\\D", sig_d);
2123 cell->setPort("\\Q", sig_q);
2124 cell->set_src_attribute(src);
2125 return cell;
2126 }
2127
2128 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2129 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2130 {
2131 RTLIL::Cell *cell = addCell(name, "$adff");
2132 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2133 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2134 cell->parameters["\\ARST_VALUE"] = arst_value;
2135 cell->parameters["\\WIDTH"] = sig_q.size();
2136 cell->setPort("\\CLK", sig_clk);
2137 cell->setPort("\\ARST", sig_arst);
2138 cell->setPort("\\D", sig_d);
2139 cell->setPort("\\Q", sig_q);
2140 cell->set_src_attribute(src);
2141 return cell;
2142 }
2143
2144 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2145 {
2146 RTLIL::Cell *cell = addCell(name, "$dlatch");
2147 cell->parameters["\\EN_POLARITY"] = en_polarity;
2148 cell->parameters["\\WIDTH"] = sig_q.size();
2149 cell->setPort("\\EN", sig_en);
2150 cell->setPort("\\D", sig_d);
2151 cell->setPort("\\Q", sig_q);
2152 cell->set_src_attribute(src);
2153 return cell;
2154 }
2155
2156 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2157 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2158 {
2159 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2160 cell->parameters["\\EN_POLARITY"] = en_polarity;
2161 cell->parameters["\\SET_POLARITY"] = set_polarity;
2162 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2163 cell->parameters["\\WIDTH"] = sig_q.size();
2164 cell->setPort("\\EN", sig_en);
2165 cell->setPort("\\SET", sig_set);
2166 cell->setPort("\\CLR", sig_clr);
2167 cell->setPort("\\D", sig_d);
2168 cell->setPort("\\Q", sig_q);
2169 cell->set_src_attribute(src);
2170 return cell;
2171 }
2172
2173 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2174 {
2175 RTLIL::Cell *cell = addCell(name, "$_FF_");
2176 cell->setPort("\\D", sig_d);
2177 cell->setPort("\\Q", sig_q);
2178 cell->set_src_attribute(src);
2179 return cell;
2180 }
2181
2182 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2183 {
2184 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2185 cell->setPort("\\C", sig_clk);
2186 cell->setPort("\\D", sig_d);
2187 cell->setPort("\\Q", sig_q);
2188 cell->set_src_attribute(src);
2189 return cell;
2190 }
2191
2192 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2193 {
2194 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2195 cell->setPort("\\C", sig_clk);
2196 cell->setPort("\\E", sig_en);
2197 cell->setPort("\\D", sig_d);
2198 cell->setPort("\\Q", sig_q);
2199 cell->set_src_attribute(src);
2200 return cell;
2201 }
2202
2203 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2204 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2205 {
2206 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2207 cell->setPort("\\C", sig_clk);
2208 cell->setPort("\\S", sig_set);
2209 cell->setPort("\\R", sig_clr);
2210 cell->setPort("\\D", sig_d);
2211 cell->setPort("\\Q", sig_q);
2212 cell->set_src_attribute(src);
2213 return cell;
2214 }
2215
2216 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2217 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2218 {
2219 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2220 cell->setPort("\\C", sig_clk);
2221 cell->setPort("\\R", sig_arst);
2222 cell->setPort("\\D", sig_d);
2223 cell->setPort("\\Q", sig_q);
2224 cell->set_src_attribute(src);
2225 return cell;
2226 }
2227
2228 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2229 {
2230 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2231 cell->setPort("\\E", sig_en);
2232 cell->setPort("\\D", sig_d);
2233 cell->setPort("\\Q", sig_q);
2234 cell->set_src_attribute(src);
2235 return cell;
2236 }
2237
2238 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2239 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2240 {
2241 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2242 cell->setPort("\\E", sig_en);
2243 cell->setPort("\\S", sig_set);
2244 cell->setPort("\\R", sig_clr);
2245 cell->setPort("\\D", sig_d);
2246 cell->setPort("\\Q", sig_q);
2247 cell->set_src_attribute(src);
2248 return cell;
2249 }
2250
2251 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2252 {
2253 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2254 Cell *cell = addCell(name, "$anyconst");
2255 cell->setParam("\\WIDTH", width);
2256 cell->setPort("\\Y", sig);
2257 cell->set_src_attribute(src);
2258 return sig;
2259 }
2260
2261 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2262 {
2263 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2264 Cell *cell = addCell(name, "$anyseq");
2265 cell->setParam("\\WIDTH", width);
2266 cell->setPort("\\Y", sig);
2267 cell->set_src_attribute(src);
2268 return sig;
2269 }
2270
2271 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2272 {
2273 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2274 Cell *cell = addCell(name, "$allconst");
2275 cell->setParam("\\WIDTH", width);
2276 cell->setPort("\\Y", sig);
2277 cell->set_src_attribute(src);
2278 return sig;
2279 }
2280
2281 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2282 {
2283 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2284 Cell *cell = addCell(name, "$allseq");
2285 cell->setParam("\\WIDTH", width);
2286 cell->setPort("\\Y", sig);
2287 cell->set_src_attribute(src);
2288 return sig;
2289 }
2290
2291 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2292 {
2293 RTLIL::SigSpec sig = addWire(NEW_ID);
2294 Cell *cell = addCell(name, "$initstate");
2295 cell->setPort("\\Y", sig);
2296 cell->set_src_attribute(src);
2297 return sig;
2298 }
2299
2300 RTLIL::Wire::Wire()
2301 {
2302 static unsigned int hashidx_count = 123456789;
2303 hashidx_count = mkhash_xorshift(hashidx_count);
2304 hashidx_ = hashidx_count;
2305
2306 module = nullptr;
2307 width = 1;
2308 start_offset = 0;
2309 port_id = 0;
2310 port_input = false;
2311 port_output = false;
2312 upto = false;
2313
2314 #ifdef WITH_PYTHON
2315 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2316 #endif
2317 }
2318
2319 RTLIL::Wire::~Wire()
2320 {
2321 #ifdef WITH_PYTHON
2322 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2323 #endif
2324 }
2325
2326 #ifdef WITH_PYTHON
2327 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2328 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2329 {
2330 return &all_wires;
2331 }
2332 #endif
2333
2334 RTLIL::Memory::Memory()
2335 {
2336 static unsigned int hashidx_count = 123456789;
2337 hashidx_count = mkhash_xorshift(hashidx_count);
2338 hashidx_ = hashidx_count;
2339
2340 width = 1;
2341 start_offset = 0;
2342 size = 0;
2343 #ifdef WITH_PYTHON
2344 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2345 #endif
2346 }
2347
2348 RTLIL::Cell::Cell() : module(nullptr)
2349 {
2350 static unsigned int hashidx_count = 123456789;
2351 hashidx_count = mkhash_xorshift(hashidx_count);
2352 hashidx_ = hashidx_count;
2353
2354 // log("#memtrace# %p\n", this);
2355 memhasher();
2356
2357 #ifdef WITH_PYTHON
2358 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2359 #endif
2360 }
2361
2362 RTLIL::Cell::~Cell()
2363 {
2364 #ifdef WITH_PYTHON
2365 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2366 #endif
2367 }
2368
2369 #ifdef WITH_PYTHON
2370 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2371 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2372 {
2373 return &all_cells;
2374 }
2375 #endif
2376
2377 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2378 {
2379 return connections_.count(portname) != 0;
2380 }
2381
2382 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2383 {
2384 RTLIL::SigSpec signal;
2385 auto conn_it = connections_.find(portname);
2386
2387 if (conn_it != connections_.end())
2388 {
2389 for (auto mon : module->monitors)
2390 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2391
2392 if (module->design)
2393 for (auto mon : module->design->monitors)
2394 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2395
2396 if (yosys_xtrace) {
2397 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2398 log_backtrace("-X- ", yosys_xtrace-1);
2399 }
2400
2401 connections_.erase(conn_it);
2402 }
2403 }
2404
2405 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2406 {
2407 auto conn_it = connections_.find(portname);
2408
2409 if (conn_it == connections_.end()) {
2410 connections_[portname] = RTLIL::SigSpec();
2411 conn_it = connections_.find(portname);
2412 log_assert(conn_it != connections_.end());
2413 } else
2414 if (conn_it->second == signal)
2415 return;
2416
2417 for (auto mon : module->monitors)
2418 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2419
2420 if (module->design)
2421 for (auto mon : module->design->monitors)
2422 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2423
2424 if (yosys_xtrace) {
2425 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2426 log_backtrace("-X- ", yosys_xtrace-1);
2427 }
2428
2429 conn_it->second = signal;
2430 }
2431
2432 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2433 {
2434 return connections_.at(portname);
2435 }
2436
2437 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2438 {
2439 return connections_;
2440 }
2441
2442 bool RTLIL::Cell::known() const
2443 {
2444 if (yosys_celltypes.cell_known(type))
2445 return true;
2446 if (module && module->design && module->design->module(type))
2447 return true;
2448 return false;
2449 }
2450
2451 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2452 {
2453 if (yosys_celltypes.cell_known(type))
2454 return yosys_celltypes.cell_input(type, portname);
2455 if (module && module->design) {
2456 RTLIL::Module *m = module->design->module(type);
2457 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2458 return w && w->port_input;
2459 }
2460 return false;
2461 }
2462
2463 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2464 {
2465 if (yosys_celltypes.cell_known(type))
2466 return yosys_celltypes.cell_output(type, portname);
2467 if (module && module->design) {
2468 RTLIL::Module *m = module->design->module(type);
2469 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2470 return w && w->port_output;
2471 }
2472 return false;
2473 }
2474
2475 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2476 {
2477 return parameters.count(paramname) != 0;
2478 }
2479
2480 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2481 {
2482 parameters.erase(paramname);
2483 }
2484
2485 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2486 {
2487 parameters[paramname] = value;
2488 }
2489
2490 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2491 {
2492 return parameters.at(paramname);
2493 }
2494
2495 void RTLIL::Cell::sort()
2496 {
2497 connections_.sort(sort_by_id_str());
2498 parameters.sort(sort_by_id_str());
2499 attributes.sort(sort_by_id_str());
2500 }
2501
2502 void RTLIL::Cell::check()
2503 {
2504 #ifndef NDEBUG
2505 InternalCellChecker checker(NULL, this);
2506 checker.check();
2507 #endif
2508 }
2509
2510 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2511 {
2512 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2513 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2514 return;
2515
2516 if (type == "$mux" || type == "$pmux") {
2517 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2518 if (type == "$pmux")
2519 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2520 check();
2521 return;
2522 }
2523
2524 if (type == "$lut" || type == "$sop") {
2525 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2526 return;
2527 }
2528
2529 if (type == "$fa") {
2530 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2531 return;
2532 }
2533
2534 if (type == "$lcu") {
2535 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2536 return;
2537 }
2538
2539 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2540
2541 if (connections_.count("\\A")) {
2542 if (signedness_ab) {
2543 if (set_a_signed)
2544 parameters["\\A_SIGNED"] = true;
2545 else if (parameters.count("\\A_SIGNED") == 0)
2546 parameters["\\A_SIGNED"] = false;
2547 }
2548 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2549 }
2550
2551 if (connections_.count("\\B")) {
2552 if (signedness_ab) {
2553 if (set_b_signed)
2554 parameters["\\B_SIGNED"] = true;
2555 else if (parameters.count("\\B_SIGNED") == 0)
2556 parameters["\\B_SIGNED"] = false;
2557 }
2558 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2559 }
2560
2561 if (connections_.count("\\Y"))
2562 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2563
2564 if (connections_.count("\\Q"))
2565 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2566
2567 check();
2568 }
2569
2570 RTLIL::SigChunk::SigChunk()
2571 {
2572 wire = NULL;
2573 width = 0;
2574 offset = 0;
2575 }
2576
2577 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2578 {
2579 wire = NULL;
2580 data = value.bits;
2581 width = GetSize(data);
2582 offset = 0;
2583 }
2584
2585 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2586 {
2587 log_assert(wire != nullptr);
2588 this->wire = wire;
2589 this->width = wire->width;
2590 this->offset = 0;
2591 }
2592
2593 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2594 {
2595 log_assert(wire != nullptr);
2596 this->wire = wire;
2597 this->width = width;
2598 this->offset = offset;
2599 }
2600
2601 RTLIL::SigChunk::SigChunk(const std::string &str)
2602 {
2603 wire = NULL;
2604 data = RTLIL::Const(str).bits;
2605 width = GetSize(data);
2606 offset = 0;
2607 }
2608
2609 RTLIL::SigChunk::SigChunk(int val, int width)
2610 {
2611 wire = NULL;
2612 data = RTLIL::Const(val, width).bits;
2613 this->width = GetSize(data);
2614 offset = 0;
2615 }
2616
2617 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2618 {
2619 wire = NULL;
2620 data = RTLIL::Const(bit, width).bits;
2621 this->width = GetSize(data);
2622 offset = 0;
2623 }
2624
2625 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2626 {
2627 wire = bit.wire;
2628 offset = 0;
2629 if (wire == NULL)
2630 data = RTLIL::Const(bit.data).bits;
2631 else
2632 offset = bit.offset;
2633 width = 1;
2634 }
2635
2636 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2637 {
2638 wire = sigchunk.wire;
2639 data = sigchunk.data;
2640 width = sigchunk.width;
2641 offset = sigchunk.offset;
2642 }
2643
2644 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2645 {
2646 RTLIL::SigChunk ret;
2647 if (wire) {
2648 ret.wire = wire;
2649 ret.offset = this->offset + offset;
2650 ret.width = length;
2651 } else {
2652 for (int i = 0; i < length; i++)
2653 ret.data.push_back(data[offset+i]);
2654 ret.width = length;
2655 }
2656 return ret;
2657 }
2658
2659 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2660 {
2661 if (wire && other.wire)
2662 if (wire->name != other.wire->name)
2663 return wire->name < other.wire->name;
2664
2665 if (wire != other.wire)
2666 return wire < other.wire;
2667
2668 if (offset != other.offset)
2669 return offset < other.offset;
2670
2671 if (width != other.width)
2672 return width < other.width;
2673
2674 return data < other.data;
2675 }
2676
2677 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2678 {
2679 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2680 }
2681
2682 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2683 {
2684 if (*this == other)
2685 return false;
2686 return true;
2687 }
2688
2689 RTLIL::SigSpec::SigSpec()
2690 {
2691 width_ = 0;
2692 hash_ = 0;
2693 }
2694
2695 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2696 {
2697 *this = other;
2698 }
2699
2700 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2701 {
2702 cover("kernel.rtlil.sigspec.init.list");
2703
2704 width_ = 0;
2705 hash_ = 0;
2706
2707 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2708 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2709 append(*it);
2710 }
2711
2712 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2713 {
2714 cover("kernel.rtlil.sigspec.assign");
2715
2716 width_ = other.width_;
2717 hash_ = other.hash_;
2718 chunks_ = other.chunks_;
2719 bits_.clear();
2720
2721 if (!other.bits_.empty())
2722 {
2723 RTLIL::SigChunk *last = NULL;
2724 int last_end_offset = 0;
2725
2726 for (auto &bit : other.bits_) {
2727 if (last && bit.wire == last->wire) {
2728 if (bit.wire == NULL) {
2729 last->data.push_back(bit.data);
2730 last->width++;
2731 continue;
2732 } else if (last_end_offset == bit.offset) {
2733 last_end_offset++;
2734 last->width++;
2735 continue;
2736 }
2737 }
2738 chunks_.push_back(bit);
2739 last = &chunks_.back();
2740 last_end_offset = bit.offset + 1;
2741 }
2742
2743 check();
2744 }
2745
2746 return *this;
2747 }
2748
2749 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2750 {
2751 cover("kernel.rtlil.sigspec.init.const");
2752
2753 chunks_.push_back(RTLIL::SigChunk(value));
2754 width_ = chunks_.back().width;
2755 hash_ = 0;
2756 check();
2757 }
2758
2759 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2760 {
2761 cover("kernel.rtlil.sigspec.init.chunk");
2762
2763 chunks_.push_back(chunk);
2764 width_ = chunks_.back().width;
2765 hash_ = 0;
2766 check();
2767 }
2768
2769 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2770 {
2771 cover("kernel.rtlil.sigspec.init.wire");
2772
2773 chunks_.push_back(RTLIL::SigChunk(wire));
2774 width_ = chunks_.back().width;
2775 hash_ = 0;
2776 check();
2777 }
2778
2779 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2780 {
2781 cover("kernel.rtlil.sigspec.init.wire_part");
2782
2783 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2784 width_ = chunks_.back().width;
2785 hash_ = 0;
2786 check();
2787 }
2788
2789 RTLIL::SigSpec::SigSpec(const std::string &str)
2790 {
2791 cover("kernel.rtlil.sigspec.init.str");
2792
2793 chunks_.push_back(RTLIL::SigChunk(str));
2794 width_ = chunks_.back().width;
2795 hash_ = 0;
2796 check();
2797 }
2798
2799 RTLIL::SigSpec::SigSpec(int val, int width)
2800 {
2801 cover("kernel.rtlil.sigspec.init.int");
2802
2803 chunks_.push_back(RTLIL::SigChunk(val, width));
2804 width_ = width;
2805 hash_ = 0;
2806 check();
2807 }
2808
2809 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2810 {
2811 cover("kernel.rtlil.sigspec.init.state");
2812
2813 chunks_.push_back(RTLIL::SigChunk(bit, width));
2814 width_ = width;
2815 hash_ = 0;
2816 check();
2817 }
2818
2819 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2820 {
2821 cover("kernel.rtlil.sigspec.init.bit");
2822
2823 if (bit.wire == NULL)
2824 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2825 else
2826 for (int i = 0; i < width; i++)
2827 chunks_.push_back(bit);
2828 width_ = width;
2829 hash_ = 0;
2830 check();
2831 }
2832
2833 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2834 {
2835 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2836
2837 width_ = 0;
2838 hash_ = 0;
2839 for (auto &c : chunks)
2840 append(c);
2841 check();
2842 }
2843
2844 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2845 {
2846 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2847
2848 width_ = 0;
2849 hash_ = 0;
2850 for (auto &bit : bits)
2851 append_bit(bit);
2852 check();
2853 }
2854
2855 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2856 {
2857 cover("kernel.rtlil.sigspec.init.pool_bits");
2858
2859 width_ = 0;
2860 hash_ = 0;
2861 for (auto &bit : bits)
2862 append_bit(bit);
2863 check();
2864 }
2865
2866 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2867 {
2868 cover("kernel.rtlil.sigspec.init.stdset_bits");
2869
2870 width_ = 0;
2871 hash_ = 0;
2872 for (auto &bit : bits)
2873 append_bit(bit);
2874 check();
2875 }
2876
2877 RTLIL::SigSpec::SigSpec(bool bit)
2878 {
2879 cover("kernel.rtlil.sigspec.init.bool");
2880
2881 width_ = 0;
2882 hash_ = 0;
2883 append_bit(bit);
2884 check();
2885 }
2886
2887 void RTLIL::SigSpec::pack() const
2888 {
2889 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2890
2891 if (that->bits_.empty())
2892 return;
2893
2894 cover("kernel.rtlil.sigspec.convert.pack");
2895 log_assert(that->chunks_.empty());
2896
2897 std::vector<RTLIL::SigBit> old_bits;
2898 old_bits.swap(that->bits_);
2899
2900 RTLIL::SigChunk *last = NULL;
2901 int last_end_offset = 0;
2902
2903 for (auto &bit : old_bits) {
2904 if (last && bit.wire == last->wire) {
2905 if (bit.wire == NULL) {
2906 last->data.push_back(bit.data);
2907 last->width++;
2908 continue;
2909 } else if (last_end_offset == bit.offset) {
2910 last_end_offset++;
2911 last->width++;
2912 continue;
2913 }
2914 }
2915 that->chunks_.push_back(bit);
2916 last = &that->chunks_.back();
2917 last_end_offset = bit.offset + 1;
2918 }
2919
2920 check();
2921 }
2922
2923 void RTLIL::SigSpec::unpack() const
2924 {
2925 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2926
2927 if (that->chunks_.empty())
2928 return;
2929
2930 cover("kernel.rtlil.sigspec.convert.unpack");
2931 log_assert(that->bits_.empty());
2932
2933 that->bits_.reserve(that->width_);
2934 for (auto &c : that->chunks_)
2935 for (int i = 0; i < c.width; i++)
2936 that->bits_.push_back(RTLIL::SigBit(c, i));
2937
2938 that->chunks_.clear();
2939 that->hash_ = 0;
2940 }
2941
2942 void RTLIL::SigSpec::updhash() const
2943 {
2944 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2945
2946 if (that->hash_ != 0)
2947 return;
2948
2949 cover("kernel.rtlil.sigspec.hash");
2950 that->pack();
2951
2952 that->hash_ = mkhash_init;
2953 for (auto &c : that->chunks_)
2954 if (c.wire == NULL) {
2955 for (auto &v : c.data)
2956 that->hash_ = mkhash(that->hash_, v);
2957 } else {
2958 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2959 that->hash_ = mkhash(that->hash_, c.offset);
2960 that->hash_ = mkhash(that->hash_, c.width);
2961 }
2962
2963 if (that->hash_ == 0)
2964 that->hash_ = 1;
2965 }
2966
2967 void RTLIL::SigSpec::sort()
2968 {
2969 unpack();
2970 cover("kernel.rtlil.sigspec.sort");
2971 std::sort(bits_.begin(), bits_.end());
2972 }
2973
2974 void RTLIL::SigSpec::sort_and_unify()
2975 {
2976 unpack();
2977 cover("kernel.rtlil.sigspec.sort_and_unify");
2978
2979 // A copy of the bits vector is used to prevent duplicating the logic from
2980 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2981 // that isn't showing up as significant in profiles.
2982 std::vector<SigBit> unique_bits = bits_;
2983 std::sort(unique_bits.begin(), unique_bits.end());
2984 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2985 unique_bits.erase(last, unique_bits.end());
2986
2987 *this = unique_bits;
2988 }
2989
2990 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2991 {
2992 replace(pattern, with, this);
2993 }
2994
2995 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2996 {
2997 log_assert(other != NULL);
2998 log_assert(width_ == other->width_);
2999 log_assert(pattern.width_ == with.width_);
3000
3001 pattern.unpack();
3002 with.unpack();
3003 unpack();
3004 other->unpack();
3005
3006 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3007 if (pattern.bits_[i].wire != NULL) {
3008 for (int j = 0; j < GetSize(bits_); j++) {
3009 if (bits_[j] == pattern.bits_[i]) {
3010 other->bits_[j] = with.bits_[i];
3011 }
3012 }
3013 }
3014 }
3015
3016 other->check();
3017 }
3018
3019 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3020 {
3021 replace(rules, this);
3022 }
3023
3024 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3025 {
3026 cover("kernel.rtlil.sigspec.replace_dict");
3027
3028 log_assert(other != NULL);
3029 log_assert(width_ == other->width_);
3030
3031 unpack();
3032 other->unpack();
3033
3034 for (int i = 0; i < GetSize(bits_); i++) {
3035 auto it = rules.find(bits_[i]);
3036 if (it != rules.end())
3037 other->bits_[i] = it->second;
3038 }
3039
3040 other->check();
3041 }
3042
3043 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3044 {
3045 replace(rules, this);
3046 }
3047
3048 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3049 {
3050 cover("kernel.rtlil.sigspec.replace_map");
3051
3052 log_assert(other != NULL);
3053 log_assert(width_ == other->width_);
3054
3055 unpack();
3056 other->unpack();
3057
3058 for (int i = 0; i < GetSize(bits_); i++) {
3059 auto it = rules.find(bits_[i]);
3060 if (it != rules.end())
3061 other->bits_[i] = it->second;
3062 }
3063
3064 other->check();
3065 }
3066
3067 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3068 {
3069 remove2(pattern, NULL);
3070 }
3071
3072 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3073 {
3074 RTLIL::SigSpec tmp = *this;
3075 tmp.remove2(pattern, other);
3076 }
3077
3078 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3079 {
3080 if (other)
3081 cover("kernel.rtlil.sigspec.remove_other");
3082 else
3083 cover("kernel.rtlil.sigspec.remove");
3084
3085 unpack();
3086 if (other != NULL) {
3087 log_assert(width_ == other->width_);
3088 other->unpack();
3089 }
3090
3091 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3092 {
3093 if (bits_[i].wire == NULL) continue;
3094
3095 for (auto &pattern_chunk : pattern.chunks())
3096 if (bits_[i].wire == pattern_chunk.wire &&
3097 bits_[i].offset >= pattern_chunk.offset &&
3098 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3099 bits_.erase(bits_.begin() + i);
3100 width_--;
3101 if (other != NULL) {
3102 other->bits_.erase(other->bits_.begin() + i);
3103 other->width_--;
3104 }
3105 break;
3106 }
3107 }
3108
3109 check();
3110 }
3111
3112 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3113 {
3114 remove2(pattern, NULL);
3115 }
3116
3117 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3118 {
3119 RTLIL::SigSpec tmp = *this;
3120 tmp.remove2(pattern, other);
3121 }
3122
3123 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3124 {
3125 if (other)
3126 cover("kernel.rtlil.sigspec.remove_other");
3127 else
3128 cover("kernel.rtlil.sigspec.remove");
3129
3130 unpack();
3131
3132 if (other != NULL) {
3133 log_assert(width_ == other->width_);
3134 other->unpack();
3135 }
3136
3137 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3138 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3139 bits_.erase(bits_.begin() + i);
3140 width_--;
3141 if (other != NULL) {
3142 other->bits_.erase(other->bits_.begin() + i);
3143 other->width_--;
3144 }
3145 }
3146 }
3147
3148 check();
3149 }
3150
3151 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3152 {
3153 if (other)
3154 cover("kernel.rtlil.sigspec.remove_other");
3155 else
3156 cover("kernel.rtlil.sigspec.remove");
3157
3158 unpack();
3159
3160 if (other != NULL) {
3161 log_assert(width_ == other->width_);
3162 other->unpack();
3163 }
3164
3165 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3166 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3167 bits_.erase(bits_.begin() + i);
3168 width_--;
3169 if (other != NULL) {
3170 other->bits_.erase(other->bits_.begin() + i);
3171 other->width_--;
3172 }
3173 }
3174 }
3175
3176 check();
3177 }
3178
3179 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3180 {
3181 if (other)
3182 cover("kernel.rtlil.sigspec.extract_other");
3183 else
3184 cover("kernel.rtlil.sigspec.extract");
3185
3186 log_assert(other == NULL || width_ == other->width_);
3187
3188 RTLIL::SigSpec ret;
3189 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3190
3191 for (auto& pattern_chunk : pattern.chunks()) {
3192 if (other) {
3193 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3194 for (int i = 0; i < width_; i++)
3195 if (bits_match[i].wire &&
3196 bits_match[i].wire == pattern_chunk.wire &&
3197 bits_match[i].offset >= pattern_chunk.offset &&
3198 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3199 ret.append_bit(bits_other[i]);
3200 } else {
3201 for (int i = 0; i < width_; i++)
3202 if (bits_match[i].wire &&
3203 bits_match[i].wire == pattern_chunk.wire &&
3204 bits_match[i].offset >= pattern_chunk.offset &&
3205 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3206 ret.append_bit(bits_match[i]);
3207 }
3208 }
3209
3210 ret.check();
3211 return ret;
3212 }
3213
3214 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3215 {
3216 if (other)
3217 cover("kernel.rtlil.sigspec.extract_other");
3218 else
3219 cover("kernel.rtlil.sigspec.extract");
3220
3221 log_assert(other == NULL || width_ == other->width_);
3222
3223 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3224 RTLIL::SigSpec ret;
3225
3226 if (other) {
3227 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3228 for (int i = 0; i < width_; i++)
3229 if (bits_match[i].wire && pattern.count(bits_match[i]))
3230 ret.append_bit(bits_other[i]);
3231 } else {
3232 for (int i = 0; i < width_; i++)
3233 if (bits_match[i].wire && pattern.count(bits_match[i]))
3234 ret.append_bit(bits_match[i]);
3235 }
3236
3237 ret.check();
3238 return ret;
3239 }
3240
3241 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3242 {
3243 cover("kernel.rtlil.sigspec.replace_pos");
3244
3245 unpack();
3246 with.unpack();
3247
3248 log_assert(offset >= 0);
3249 log_assert(with.width_ >= 0);
3250 log_assert(offset+with.width_ <= width_);
3251
3252 for (int i = 0; i < with.width_; i++)
3253 bits_.at(offset + i) = with.bits_.at(i);
3254
3255 check();
3256 }
3257
3258 void RTLIL::SigSpec::remove_const()
3259 {
3260 if (packed())
3261 {
3262 cover("kernel.rtlil.sigspec.remove_const.packed");
3263
3264 std::vector<RTLIL::SigChunk> new_chunks;
3265 new_chunks.reserve(GetSize(chunks_));
3266
3267 width_ = 0;
3268 for (auto &chunk : chunks_)
3269 if (chunk.wire != NULL) {
3270 new_chunks.push_back(chunk);
3271 width_ += chunk.width;
3272 }
3273
3274 chunks_.swap(new_chunks);
3275 }
3276 else
3277 {
3278 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3279
3280 std::vector<RTLIL::SigBit> new_bits;
3281 new_bits.reserve(width_);
3282
3283 for (auto &bit : bits_)
3284 if (bit.wire != NULL)
3285 new_bits.push_back(bit);
3286
3287 bits_.swap(new_bits);
3288 width_ = bits_.size();
3289 }
3290
3291 check();
3292 }
3293
3294 void RTLIL::SigSpec::remove(int offset, int length)
3295 {
3296 cover("kernel.rtlil.sigspec.remove_pos");
3297
3298 unpack();
3299
3300 log_assert(offset >= 0);
3301 log_assert(length >= 0);
3302 log_assert(offset + length <= width_);
3303
3304 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3305 width_ = bits_.size();
3306
3307 check();
3308 }
3309
3310 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3311 {
3312 unpack();
3313 cover("kernel.rtlil.sigspec.extract_pos");
3314 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3315 }
3316
3317 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3318 {
3319 if (signal.width_ == 0)
3320 return;
3321
3322 if (width_ == 0) {
3323 *this = signal;
3324 return;
3325 }
3326
3327 cover("kernel.rtlil.sigspec.append");
3328
3329 if (packed() != signal.packed()) {
3330 pack();
3331 signal.pack();
3332 }
3333
3334 if (packed())
3335 for (auto &other_c : signal.chunks_)
3336 {
3337 auto &my_last_c = chunks_.back();
3338 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3339 auto &this_data = my_last_c.data;
3340 auto &other_data = other_c.data;
3341 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3342 my_last_c.width += other_c.width;
3343 } else
3344 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3345 my_last_c.width += other_c.width;
3346 } else
3347 chunks_.push_back(other_c);
3348 }
3349 else
3350 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3351
3352 width_ += signal.width_;
3353 check();
3354 }
3355
3356 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3357 {
3358 if (packed())
3359 {
3360 cover("kernel.rtlil.sigspec.append_bit.packed");
3361
3362 if (chunks_.size() == 0)
3363 chunks_.push_back(bit);
3364 else
3365 if (bit.wire == NULL)
3366 if (chunks_.back().wire == NULL) {
3367 chunks_.back().data.push_back(bit.data);
3368 chunks_.back().width++;
3369 } else
3370 chunks_.push_back(bit);
3371 else
3372 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3373 chunks_.back().width++;
3374 else
3375 chunks_.push_back(bit);
3376 }
3377 else
3378 {
3379 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3380 bits_.push_back(bit);
3381 }
3382
3383 width_++;
3384 check();
3385 }
3386
3387 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3388 {
3389 cover("kernel.rtlil.sigspec.extend_u0");
3390
3391 pack();
3392
3393 if (width_ > width)
3394 remove(width, width_ - width);
3395
3396 if (width_ < width) {
3397 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3398 if (!is_signed)
3399 padding = RTLIL::State::S0;
3400 while (width_ < width)
3401 append(padding);
3402 }
3403
3404 }
3405
3406 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3407 {
3408 cover("kernel.rtlil.sigspec.repeat");
3409
3410 RTLIL::SigSpec sig;
3411 for (int i = 0; i < num; i++)
3412 sig.append(*this);
3413 return sig;
3414 }
3415
3416 #ifndef NDEBUG
3417 void RTLIL::SigSpec::check() const
3418 {
3419 if (width_ > 64)
3420 {
3421 cover("kernel.rtlil.sigspec.check.skip");
3422 }
3423 else if (packed())
3424 {
3425 cover("kernel.rtlil.sigspec.check.packed");
3426
3427 int w = 0;
3428 for (size_t i = 0; i < chunks_.size(); i++) {
3429 const RTLIL::SigChunk chunk = chunks_[i];
3430 if (chunk.wire == NULL) {
3431 if (i > 0)
3432 log_assert(chunks_[i-1].wire != NULL);
3433 log_assert(chunk.offset == 0);
3434 log_assert(chunk.data.size() == (size_t)chunk.width);
3435 } else {
3436 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3437 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3438 log_assert(chunk.offset >= 0);
3439 log_assert(chunk.width >= 0);
3440 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3441 log_assert(chunk.data.size() == 0);
3442 }
3443 w += chunk.width;
3444 }
3445 log_assert(w == width_);
3446 log_assert(bits_.empty());
3447 }
3448 else
3449 {
3450 cover("kernel.rtlil.sigspec.check.unpacked");
3451
3452 log_assert(width_ == GetSize(bits_));
3453 log_assert(chunks_.empty());
3454 }
3455 }
3456 #endif
3457
3458 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3459 {
3460 cover("kernel.rtlil.sigspec.comp_lt");
3461
3462 if (this == &other)
3463 return false;
3464
3465 if (width_ != other.width_)
3466 return width_ < other.width_;
3467
3468 pack();
3469 other.pack();
3470
3471 if (chunks_.size() != other.chunks_.size())
3472 return chunks_.size() < other.chunks_.size();
3473
3474 updhash();
3475 other.updhash();
3476
3477 if (hash_ != other.hash_)
3478 return hash_ < other.hash_;
3479
3480 for (size_t i = 0; i < chunks_.size(); i++)
3481 if (chunks_[i] != other.chunks_[i]) {
3482 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3483 return chunks_[i] < other.chunks_[i];
3484 }
3485
3486 cover("kernel.rtlil.sigspec.comp_lt.equal");
3487 return false;
3488 }
3489
3490 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3491 {
3492 cover("kernel.rtlil.sigspec.comp_eq");
3493
3494 if (this == &other)
3495 return true;
3496
3497 if (width_ != other.width_)
3498 return false;
3499
3500 pack();
3501 other.pack();
3502
3503 if (chunks_.size() != other.chunks_.size())
3504 return false;
3505
3506 updhash();
3507 other.updhash();
3508
3509 if (hash_ != other.hash_)
3510 return false;
3511
3512 for (size_t i = 0; i < chunks_.size(); i++)
3513 if (chunks_[i] != other.chunks_[i]) {
3514 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3515 return false;
3516 }
3517
3518 cover("kernel.rtlil.sigspec.comp_eq.equal");
3519 return true;
3520 }
3521
3522 bool RTLIL::SigSpec::is_wire() const
3523 {
3524 cover("kernel.rtlil.sigspec.is_wire");
3525
3526 pack();
3527 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3528 }
3529
3530 bool RTLIL::SigSpec::is_chunk() const
3531 {
3532 cover("kernel.rtlil.sigspec.is_chunk");
3533
3534 pack();
3535 return GetSize(chunks_) == 1;
3536 }
3537
3538 bool RTLIL::SigSpec::is_fully_const() const
3539 {
3540 cover("kernel.rtlil.sigspec.is_fully_const");
3541
3542 pack();
3543 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3544 if (it->width > 0 && it->wire != NULL)
3545 return false;
3546 return true;
3547 }
3548
3549 bool RTLIL::SigSpec::is_fully_zero() const
3550 {
3551 cover("kernel.rtlil.sigspec.is_fully_zero");
3552
3553 pack();
3554 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3555 if (it->width > 0 && it->wire != NULL)
3556 return false;
3557 for (size_t i = 0; i < it->data.size(); i++)
3558 if (it->data[i] != RTLIL::State::S0)
3559 return false;
3560 }
3561 return true;
3562 }
3563
3564 bool RTLIL::SigSpec::is_fully_ones() const
3565 {
3566 cover("kernel.rtlil.sigspec.is_fully_ones");
3567
3568 pack();
3569 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3570 if (it->width > 0 && it->wire != NULL)
3571 return false;
3572 for (size_t i = 0; i < it->data.size(); i++)
3573 if (it->data[i] != RTLIL::State::S1)
3574 return false;
3575 }
3576 return true;
3577 }
3578
3579 bool RTLIL::SigSpec::is_fully_def() const
3580 {
3581 cover("kernel.rtlil.sigspec.is_fully_def");
3582
3583 pack();
3584 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3585 if (it->width > 0 && it->wire != NULL)
3586 return false;
3587 for (size_t i = 0; i < it->data.size(); i++)
3588 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3589 return false;
3590 }
3591 return true;
3592 }
3593
3594 bool RTLIL::SigSpec::is_fully_undef() const
3595 {
3596 cover("kernel.rtlil.sigspec.is_fully_undef");
3597
3598 pack();
3599 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3600 if (it->width > 0 && it->wire != NULL)
3601 return false;
3602 for (size_t i = 0; i < it->data.size(); i++)
3603 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3604 return false;
3605 }
3606 return true;
3607 }
3608
3609 bool RTLIL::SigSpec::has_const() const
3610 {
3611 cover("kernel.rtlil.sigspec.has_const");
3612
3613 pack();
3614 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3615 if (it->width > 0 && it->wire == NULL)
3616 return true;
3617 return false;
3618 }
3619
3620 bool RTLIL::SigSpec::has_marked_bits() const
3621 {
3622 cover("kernel.rtlil.sigspec.has_marked_bits");
3623
3624 pack();
3625 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3626 if (it->width > 0 && it->wire == NULL) {
3627 for (size_t i = 0; i < it->data.size(); i++)
3628 if (it->data[i] == RTLIL::State::Sm)
3629 return true;
3630 }
3631 return false;
3632 }
3633
3634 bool RTLIL::SigSpec::as_bool() const
3635 {
3636 cover("kernel.rtlil.sigspec.as_bool");
3637
3638 pack();
3639 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3640 if (width_)
3641 return RTLIL::Const(chunks_[0].data).as_bool();
3642 return false;
3643 }
3644
3645 int RTLIL::SigSpec::as_int(bool is_signed) const
3646 {
3647 cover("kernel.rtlil.sigspec.as_int");
3648
3649 pack();
3650 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3651 if (width_)
3652 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3653 return 0;
3654 }
3655
3656 std::string RTLIL::SigSpec::as_string() const
3657 {
3658 cover("kernel.rtlil.sigspec.as_string");
3659
3660 pack();
3661 std::string str;
3662 for (size_t i = chunks_.size(); i > 0; i--) {
3663 const RTLIL::SigChunk &chunk = chunks_[i-1];
3664 if (chunk.wire != NULL)
3665 for (int j = 0; j < chunk.width; j++)
3666 str += "?";
3667 else
3668 str += RTLIL::Const(chunk.data).as_string();
3669 }
3670 return str;
3671 }
3672
3673 RTLIL::Const RTLIL::SigSpec::as_const() const
3674 {
3675 cover("kernel.rtlil.sigspec.as_const");
3676
3677 pack();
3678 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3679 if (width_)
3680 return chunks_[0].data;
3681 return RTLIL::Const();
3682 }
3683
3684 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3685 {
3686 cover("kernel.rtlil.sigspec.as_wire");
3687
3688 pack();
3689 log_assert(is_wire());
3690 return chunks_[0].wire;
3691 }
3692
3693 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3694 {
3695 cover("kernel.rtlil.sigspec.as_chunk");
3696
3697 pack();
3698 log_assert(is_chunk());
3699 return chunks_[0];
3700 }
3701
3702 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3703 {
3704 cover("kernel.rtlil.sigspec.as_bit");
3705
3706 log_assert(width_ == 1);
3707 if (packed())
3708 return RTLIL::SigBit(*chunks_.begin());
3709 else
3710 return bits_[0];
3711 }
3712
3713 bool RTLIL::SigSpec::match(std::string pattern) const
3714 {
3715 cover("kernel.rtlil.sigspec.match");
3716
3717 pack();
3718 std::string str = as_string();
3719 log_assert(pattern.size() == str.size());
3720
3721 for (size_t i = 0; i < pattern.size(); i++) {
3722 if (pattern[i] == ' ')
3723 continue;
3724 if (pattern[i] == '*') {
3725 if (str[i] != 'z' && str[i] != 'x')
3726 return false;
3727 continue;
3728 }
3729 if (pattern[i] != str[i])
3730 return false;
3731 }
3732
3733 return true;
3734 }
3735
3736 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3737 {
3738 cover("kernel.rtlil.sigspec.to_sigbit_set");
3739
3740 pack();
3741 std::set<RTLIL::SigBit> sigbits;
3742 for (auto &c : chunks_)
3743 for (int i = 0; i < c.width; i++)
3744 sigbits.insert(RTLIL::SigBit(c, i));
3745 return sigbits;
3746 }
3747
3748 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3749 {
3750 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3751
3752 pack();
3753 pool<RTLIL::SigBit> sigbits;
3754 for (auto &c : chunks_)
3755 for (int i = 0; i < c.width; i++)
3756 sigbits.insert(RTLIL::SigBit(c, i));
3757 return sigbits;
3758 }
3759
3760 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3761 {
3762 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3763
3764 unpack();
3765 return bits_;
3766 }
3767
3768 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3769 {
3770 cover("kernel.rtlil.sigspec.to_sigbit_map");
3771
3772 unpack();
3773 other.unpack();
3774
3775 log_assert(width_ == other.width_);
3776
3777 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3778 for (int i = 0; i < width_; i++)
3779 new_map[bits_[i]] = other.bits_[i];
3780
3781 return new_map;
3782 }
3783
3784 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3785 {
3786 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3787
3788 unpack();
3789 other.unpack();
3790
3791 log_assert(width_ == other.width_);
3792
3793 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3794 for (int i = 0; i < width_; i++)
3795 new_map[bits_[i]] = other.bits_[i];
3796
3797 return new_map;
3798 }
3799
3800 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3801 {
3802 size_t start = 0, end = 0;
3803 while ((end = text.find(sep, start)) != std::string::npos) {
3804 tokens.push_back(text.substr(start, end - start));
3805 start = end + 1;
3806 }
3807 tokens.push_back(text.substr(start));
3808 }
3809
3810 static int sigspec_parse_get_dummy_line_num()
3811 {
3812 return 0;
3813 }
3814
3815 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3816 {
3817 cover("kernel.rtlil.sigspec.parse");
3818
3819 AST::current_filename = "input";
3820 AST::use_internal_line_num();
3821 AST::set_line_num(0);
3822
3823 std::vector<std::string> tokens;
3824 sigspec_parse_split(tokens, str, ',');
3825
3826 sig = RTLIL::SigSpec();
3827 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3828 {
3829 std::string netname = tokens[tokidx];
3830 std::string indices;
3831
3832 if (netname.size() == 0)
3833 continue;
3834
3835 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3836 cover("kernel.rtlil.sigspec.parse.const");
3837 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3838 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3839 if (ast == NULL)
3840 return false;
3841 sig.append(RTLIL::Const(ast->bits));
3842 delete ast;
3843 continue;
3844 }
3845
3846 if (module == NULL)
3847 return false;
3848
3849 cover("kernel.rtlil.sigspec.parse.net");
3850
3851 if (netname[0] != '$' && netname[0] != '\\')
3852 netname = "\\" + netname;
3853
3854 if (module->wires_.count(netname) == 0) {
3855 size_t indices_pos = netname.size()-1;
3856 if (indices_pos > 2 && netname[indices_pos] == ']')
3857 {
3858 indices_pos--;
3859 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3860 if (indices_pos > 0 && netname[indices_pos] == ':') {
3861 indices_pos--;
3862 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3863 }
3864 if (indices_pos > 0 && netname[indices_pos] == '[') {
3865 indices = netname.substr(indices_pos);
3866 netname = netname.substr(0, indices_pos);
3867 }
3868 }
3869 }
3870
3871 if (module->wires_.count(netname) == 0)
3872 return false;
3873
3874 RTLIL::Wire *wire = module->wires_.at(netname);
3875 if (!indices.empty()) {
3876 std::vector<std::string> index_tokens;
3877 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3878 if (index_tokens.size() == 1) {
3879 cover("kernel.rtlil.sigspec.parse.bit_sel");
3880 int a = atoi(index_tokens.at(0).c_str());
3881 if (a < 0 || a >= wire->width)
3882 return false;
3883 sig.append(RTLIL::SigSpec(wire, a));
3884 } else {
3885 cover("kernel.rtlil.sigspec.parse.part_sel");
3886 int a = atoi(index_tokens.at(0).c_str());
3887 int b = atoi(index_tokens.at(1).c_str());
3888 if (a > b) {
3889 int tmp = a;
3890 a = b, b = tmp;
3891 }
3892 if (a < 0 || a >= wire->width)
3893 return false;
3894 if (b < 0 || b >= wire->width)
3895 return false;
3896 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3897 }
3898 } else
3899 sig.append(wire);
3900 }
3901
3902 return true;
3903 }
3904
3905 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3906 {
3907 if (str.empty() || str[0] != '@')
3908 return parse(sig, module, str);
3909
3910 cover("kernel.rtlil.sigspec.parse.sel");
3911
3912 str = RTLIL::escape_id(str.substr(1));
3913 if (design->selection_vars.count(str) == 0)
3914 return false;
3915
3916 sig = RTLIL::SigSpec();
3917 RTLIL::Selection &sel = design->selection_vars.at(str);
3918 for (auto &it : module->wires_)
3919 if (sel.selected_member(module->name, it.first))
3920 sig.append(it.second);
3921
3922 return true;
3923 }
3924
3925 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3926 {
3927 if (str == "0") {
3928 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3929 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3930 return true;
3931 }
3932
3933 if (str == "~0") {
3934 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3935 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3936 return true;
3937 }
3938
3939 if (lhs.chunks_.size() == 1) {
3940 char *p = (char*)str.c_str(), *endptr;
3941 long int val = strtol(p, &endptr, 10);
3942 if (endptr && endptr != p && *endptr == 0) {
3943 sig = RTLIL::SigSpec(val, lhs.width_);
3944 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3945 return true;
3946 }
3947 }
3948
3949 return parse(sig, module, str);
3950 }
3951
3952 RTLIL::CaseRule::~CaseRule()
3953 {
3954 for (auto it = switches.begin(); it != switches.end(); it++)
3955 delete *it;
3956 }
3957
3958 bool RTLIL::CaseRule::empty() const
3959 {
3960 return actions.empty() && switches.empty();
3961 }
3962
3963 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3964 {
3965 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3966 new_caserule->compare = compare;
3967 new_caserule->actions = actions;
3968 for (auto &it : switches)
3969 new_caserule->switches.push_back(it->clone());
3970 return new_caserule;
3971 }
3972
3973 RTLIL::SwitchRule::~SwitchRule()
3974 {
3975 for (auto it = cases.begin(); it != cases.end(); it++)
3976 delete *it;
3977 }
3978
3979 bool RTLIL::SwitchRule::empty() const
3980 {
3981 return cases.empty();
3982 }
3983
3984 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3985 {
3986 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3987 new_switchrule->signal = signal;
3988 new_switchrule->attributes = attributes;
3989 for (auto &it : cases)
3990 new_switchrule->cases.push_back(it->clone());
3991 return new_switchrule;
3992
3993 }
3994
3995 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3996 {
3997 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3998 new_syncrule->type = type;
3999 new_syncrule->signal = signal;
4000 new_syncrule->actions = actions;
4001 return new_syncrule;
4002 }
4003
4004 RTLIL::Process::~Process()
4005 {
4006 for (auto it = syncs.begin(); it != syncs.end(); it++)
4007 delete *it;
4008 }
4009
4010 RTLIL::Process *RTLIL::Process::clone() const
4011 {
4012 RTLIL::Process *new_proc = new RTLIL::Process;
4013
4014 new_proc->name = name;
4015 new_proc->attributes = attributes;
4016
4017 RTLIL::CaseRule *rc_ptr = root_case.clone();
4018 new_proc->root_case = *rc_ptr;
4019 rc_ptr->switches.clear();
4020 delete rc_ptr;
4021
4022 for (auto &it : syncs)
4023 new_proc->syncs.push_back(it->clone());
4024
4025 return new_proc;
4026 }
4027
4028 #ifdef WITH_PYTHON
4029 RTLIL::Memory::~Memory()
4030 {
4031 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4032 }
4033 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4034 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4035 {
4036 return &all_memorys;
4037 }
4038 #endif
4039 YOSYS_NAMESPACE_END