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Merge pull request #1846 from dh73/ast_fe
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 IdString RTLIL::ID::A;
45 IdString RTLIL::ID::B;
46 IdString RTLIL::ID::Y;
47 IdString RTLIL::ID::keep;
48 IdString RTLIL::ID::whitebox;
49 IdString RTLIL::ID::blackbox;
50 dict<std::string, std::string> RTLIL::constpad;
51
52 RTLIL::Const::Const()
53 {
54 flags = RTLIL::CONST_FLAG_NONE;
55 }
56
57 RTLIL::Const::Const(std::string str)
58 {
59 flags = RTLIL::CONST_FLAG_STRING;
60 for (int i = str.size()-1; i >= 0; i--) {
61 unsigned char ch = str[i];
62 for (int j = 0; j < 8; j++) {
63 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
64 ch = ch >> 1;
65 }
66 }
67 }
68
69 RTLIL::Const::Const(int val, int width)
70 {
71 flags = RTLIL::CONST_FLAG_NONE;
72 for (int i = 0; i < width; i++) {
73 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
74 val = val >> 1;
75 }
76 }
77
78 RTLIL::Const::Const(RTLIL::State bit, int width)
79 {
80 flags = RTLIL::CONST_FLAG_NONE;
81 for (int i = 0; i < width; i++)
82 bits.push_back(bit);
83 }
84
85 RTLIL::Const::Const(const std::vector<bool> &bits)
86 {
87 flags = RTLIL::CONST_FLAG_NONE;
88 for (const auto &b : bits)
89 this->bits.emplace_back(b ? State::S1 : State::S0);
90 }
91
92 RTLIL::Const::Const(const RTLIL::Const &c)
93 {
94 flags = c.flags;
95 for (const auto &b : c.bits)
96 this->bits.push_back(b);
97 }
98
99 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
100 {
101 if (bits.size() != other.bits.size())
102 return bits.size() < other.bits.size();
103 for (size_t i = 0; i < bits.size(); i++)
104 if (bits[i] != other.bits[i])
105 return bits[i] < other.bits[i];
106 return false;
107 }
108
109 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
110 {
111 return bits == other.bits;
112 }
113
114 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
115 {
116 return bits != other.bits;
117 }
118
119 bool RTLIL::Const::as_bool() const
120 {
121 for (size_t i = 0; i < bits.size(); i++)
122 if (bits[i] == State::S1)
123 return true;
124 return false;
125 }
126
127 int RTLIL::Const::as_int(bool is_signed) const
128 {
129 int32_t ret = 0;
130 for (size_t i = 0; i < bits.size() && i < 32; i++)
131 if (bits[i] == State::S1)
132 ret |= 1 << i;
133 if (is_signed && bits.back() == State::S1)
134 for (size_t i = bits.size(); i < 32; i++)
135 ret |= 1 << i;
136 return ret;
137 }
138
139 std::string RTLIL::Const::as_string() const
140 {
141 std::string ret;
142 ret.reserve(bits.size());
143 for (size_t i = bits.size(); i > 0; i--)
144 switch (bits[i-1]) {
145 case S0: ret += "0"; break;
146 case S1: ret += "1"; break;
147 case Sx: ret += "x"; break;
148 case Sz: ret += "z"; break;
149 case Sa: ret += "-"; break;
150 case Sm: ret += "m"; break;
151 }
152 return ret;
153 }
154
155 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
156 {
157 Const c;
158 c.bits.reserve(str.size());
159 for (auto it = str.rbegin(); it != str.rend(); it++)
160 switch (*it) {
161 case '0': c.bits.push_back(State::S0); break;
162 case '1': c.bits.push_back(State::S1); break;
163 case 'x': c.bits.push_back(State::Sx); break;
164 case 'z': c.bits.push_back(State::Sz); break;
165 case 'm': c.bits.push_back(State::Sm); break;
166 default: c.bits.push_back(State::Sa);
167 }
168 return c;
169 }
170
171 std::string RTLIL::Const::decode_string() const
172 {
173 std::string string;
174 string.reserve(GetSize(bits)/8);
175 for (int i = 0; i < GetSize(bits); i += 8) {
176 char ch = 0;
177 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
178 if (bits[i + j] == RTLIL::State::S1)
179 ch |= 1 << j;
180 if (ch != 0)
181 string.append({ch});
182 }
183 std::reverse(string.begin(), string.end());
184 return string;
185 }
186
187 bool RTLIL::Const::is_fully_zero() const
188 {
189 cover("kernel.rtlil.const.is_fully_zero");
190
191 for (const auto &bit : bits)
192 if (bit != RTLIL::State::S0)
193 return false;
194
195 return true;
196 }
197
198 bool RTLIL::Const::is_fully_ones() const
199 {
200 cover("kernel.rtlil.const.is_fully_ones");
201
202 for (const auto &bit : bits)
203 if (bit != RTLIL::State::S1)
204 return false;
205
206 return true;
207 }
208
209 bool RTLIL::Const::is_fully_def() const
210 {
211 cover("kernel.rtlil.const.is_fully_def");
212
213 for (const auto &bit : bits)
214 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
215 return false;
216
217 return true;
218 }
219
220 bool RTLIL::Const::is_fully_undef() const
221 {
222 cover("kernel.rtlil.const.is_fully_undef");
223
224 for (const auto &bit : bits)
225 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
226 return false;
227
228 return true;
229 }
230
231 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
232 {
233 if (value)
234 attributes[id] = RTLIL::Const(1);
235 else
236 attributes.erase(id);
237 }
238
239 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
240 {
241 const auto it = attributes.find(id);
242 if (it == attributes.end())
243 return false;
244 return it->second.as_bool();
245 }
246
247 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 string attrval;
250 for (const auto &s : data) {
251 if (!attrval.empty())
252 attrval += "|";
253 attrval += s;
254 }
255 attributes[id] = RTLIL::Const(attrval);
256 }
257
258 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
259 {
260 pool<string> union_data = get_strpool_attribute(id);
261 union_data.insert(data.begin(), data.end());
262 if (!union_data.empty())
263 set_strpool_attribute(id, union_data);
264 }
265
266 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
267 {
268 pool<string> data;
269 if (attributes.count(id) != 0)
270 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
271 data.insert(s);
272 return data;
273 }
274
275 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
276 {
277 if (src.empty())
278 attributes.erase(ID(src));
279 else
280 attributes[ID(src)] = src;
281 }
282
283 std::string RTLIL::AttrObject::get_src_attribute() const
284 {
285 std::string src;
286 const auto it = attributes.find(ID(src));
287 if (it != attributes.end())
288 src = it->second.decode_string();
289 return src;
290 }
291
292 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
293 {
294 if (full_selection)
295 return true;
296 if (selected_modules.count(mod_name) > 0)
297 return true;
298 if (selected_members.count(mod_name) > 0)
299 return true;
300 return false;
301 }
302
303 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
304 {
305 if (full_selection)
306 return true;
307 if (selected_modules.count(mod_name) > 0)
308 return true;
309 return false;
310 }
311
312 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
313 {
314 if (full_selection)
315 return true;
316 if (selected_modules.count(mod_name) > 0)
317 return true;
318 if (selected_members.count(mod_name) > 0)
319 if (selected_members.at(mod_name).count(memb_name) > 0)
320 return true;
321 return false;
322 }
323
324 void RTLIL::Selection::optimize(RTLIL::Design *design)
325 {
326 if (full_selection) {
327 selected_modules.clear();
328 selected_members.clear();
329 return;
330 }
331
332 std::vector<RTLIL::IdString> del_list, add_list;
333
334 del_list.clear();
335 for (auto mod_name : selected_modules) {
336 if (design->modules_.count(mod_name) == 0)
337 del_list.push_back(mod_name);
338 selected_members.erase(mod_name);
339 }
340 for (auto mod_name : del_list)
341 selected_modules.erase(mod_name);
342
343 del_list.clear();
344 for (auto &it : selected_members)
345 if (design->modules_.count(it.first) == 0)
346 del_list.push_back(it.first);
347 for (auto mod_name : del_list)
348 selected_members.erase(mod_name);
349
350 for (auto &it : selected_members) {
351 del_list.clear();
352 for (auto memb_name : it.second)
353 if (design->modules_[it.first]->count_id(memb_name) == 0)
354 del_list.push_back(memb_name);
355 for (auto memb_name : del_list)
356 it.second.erase(memb_name);
357 }
358
359 del_list.clear();
360 add_list.clear();
361 for (auto &it : selected_members)
362 if (it.second.size() == 0)
363 del_list.push_back(it.first);
364 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
365 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
366 add_list.push_back(it.first);
367 for (auto mod_name : del_list)
368 selected_members.erase(mod_name);
369 for (auto mod_name : add_list) {
370 selected_members.erase(mod_name);
371 selected_modules.insert(mod_name);
372 }
373
374 if (selected_modules.size() == design->modules_.size()) {
375 full_selection = true;
376 selected_modules.clear();
377 selected_members.clear();
378 }
379 }
380
381 RTLIL::Design::Design()
382 : verilog_defines (new define_map_t)
383 {
384 static unsigned int hashidx_count = 123456789;
385 hashidx_count = mkhash_xorshift(hashidx_count);
386 hashidx_ = hashidx_count;
387
388 refcount_modules_ = 0;
389 selection_stack.push_back(RTLIL::Selection());
390
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
393 #endif
394 }
395
396 RTLIL::Design::~Design()
397 {
398 for (auto it = modules_.begin(); it != modules_.end(); ++it)
399 delete it->second;
400 for (auto n : verilog_packages)
401 delete n;
402 for (auto n : verilog_globals)
403 delete n;
404 #ifdef WITH_PYTHON
405 RTLIL::Design::get_all_designs()->erase(hashidx_);
406 #endif
407 }
408
409 #ifdef WITH_PYTHON
410 static std::map<unsigned int, RTLIL::Design*> all_designs;
411 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
412 {
413 return &all_designs;
414 }
415 #endif
416
417 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
418 {
419 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
420 }
421
422 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
423 {
424 return modules_.count(name) ? modules_.at(name) : NULL;
425 }
426
427 RTLIL::Module *RTLIL::Design::top_module()
428 {
429 RTLIL::Module *module = nullptr;
430 int module_count = 0;
431
432 for (auto mod : selected_modules()) {
433 if (mod->get_bool_attribute(ID(top)))
434 return mod;
435 module_count++;
436 module = mod;
437 }
438
439 return module_count == 1 ? module : nullptr;
440 }
441
442 void RTLIL::Design::add(RTLIL::Module *module)
443 {
444 log_assert(modules_.count(module->name) == 0);
445 log_assert(refcount_modules_ == 0);
446 modules_[module->name] = module;
447 module->design = this;
448
449 for (auto mon : monitors)
450 mon->notify_module_add(module);
451
452 if (yosys_xtrace) {
453 log("#X# New Module: %s\n", log_id(module));
454 log_backtrace("-X- ", yosys_xtrace-1);
455 }
456 }
457
458 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
459 {
460 log_assert(modules_.count(name) == 0);
461 log_assert(refcount_modules_ == 0);
462
463 RTLIL::Module *module = new RTLIL::Module;
464 modules_[name] = module;
465 module->design = this;
466 module->name = name;
467
468 for (auto mon : monitors)
469 mon->notify_module_add(module);
470
471 if (yosys_xtrace) {
472 log("#X# New Module: %s\n", log_id(module));
473 log_backtrace("-X- ", yosys_xtrace-1);
474 }
475
476 return module;
477 }
478
479 void RTLIL::Design::scratchpad_unset(const std::string &varname)
480 {
481 scratchpad.erase(varname);
482 }
483
484 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
485 {
486 scratchpad[varname] = stringf("%d", value);
487 }
488
489 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
490 {
491 scratchpad[varname] = value ? "true" : "false";
492 }
493
494 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
495 {
496 scratchpad[varname] = std::move(value);
497 }
498
499 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
500 {
501 auto it = scratchpad.find(varname);
502 if (it == scratchpad.end())
503 return default_value;
504
505 const std::string &str = it->second;
506
507 if (str == "0" || str == "false")
508 return 0;
509
510 if (str == "1" || str == "true")
511 return 1;
512
513 char *endptr = nullptr;
514 long int parsed_value = strtol(str.c_str(), &endptr, 10);
515 return *endptr ? default_value : parsed_value;
516 }
517
518 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
519 {
520 auto it = scratchpad.find(varname);
521 if (it == scratchpad.end())
522 return default_value;
523
524 const std::string &str = it->second;
525
526 if (str == "0" || str == "false")
527 return false;
528
529 if (str == "1" || str == "true")
530 return true;
531
532 return default_value;
533 }
534
535 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
536 {
537 auto it = scratchpad.find(varname);
538 if (it == scratchpad.end())
539 return default_value;
540
541 return it->second;
542 }
543
544 void RTLIL::Design::remove(RTLIL::Module *module)
545 {
546 for (auto mon : monitors)
547 mon->notify_module_del(module);
548
549 if (yosys_xtrace) {
550 log("#X# Remove Module: %s\n", log_id(module));
551 log_backtrace("-X- ", yosys_xtrace-1);
552 }
553
554 log_assert(modules_.at(module->name) == module);
555 modules_.erase(module->name);
556 delete module;
557 }
558
559 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
560 {
561 modules_.erase(module->name);
562 module->name = new_name;
563 add(module);
564 }
565
566 void RTLIL::Design::sort()
567 {
568 scratchpad.sort();
569 modules_.sort(sort_by_id_str());
570 for (auto &it : modules_)
571 it.second->sort();
572 }
573
574 void RTLIL::Design::check()
575 {
576 #ifndef NDEBUG
577 for (auto &it : modules_) {
578 log_assert(this == it.second->design);
579 log_assert(it.first == it.second->name);
580 log_assert(!it.first.empty());
581 it.second->check();
582 }
583 #endif
584 }
585
586 void RTLIL::Design::optimize()
587 {
588 for (auto &it : modules_)
589 it.second->optimize();
590 for (auto &it : selection_stack)
591 it.optimize(this);
592 for (auto &it : selection_vars)
593 it.second.optimize(this);
594 }
595
596 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
597 {
598 if (!selected_active_module.empty() && mod_name != selected_active_module)
599 return false;
600 if (selection_stack.size() == 0)
601 return true;
602 return selection_stack.back().selected_module(mod_name);
603 }
604
605 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
606 {
607 if (!selected_active_module.empty() && mod_name != selected_active_module)
608 return false;
609 if (selection_stack.size() == 0)
610 return true;
611 return selection_stack.back().selected_whole_module(mod_name);
612 }
613
614 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
615 {
616 if (!selected_active_module.empty() && mod_name != selected_active_module)
617 return false;
618 if (selection_stack.size() == 0)
619 return true;
620 return selection_stack.back().selected_member(mod_name, memb_name);
621 }
622
623 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
624 {
625 return selected_module(mod->name);
626 }
627
628 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
629 {
630 return selected_whole_module(mod->name);
631 }
632
633 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
634 {
635 std::vector<RTLIL::Module*> result;
636 result.reserve(modules_.size());
637 for (auto &it : modules_)
638 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
639 result.push_back(it.second);
640 return result;
641 }
642
643 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
644 {
645 std::vector<RTLIL::Module*> result;
646 result.reserve(modules_.size());
647 for (auto &it : modules_)
648 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
649 result.push_back(it.second);
650 return result;
651 }
652
653 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
654 {
655 std::vector<RTLIL::Module*> result;
656 result.reserve(modules_.size());
657 for (auto &it : modules_)
658 if (it.second->get_blackbox_attribute())
659 continue;
660 else if (selected_whole_module(it.first))
661 result.push_back(it.second);
662 else if (selected_module(it.first))
663 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
664 return result;
665 }
666
667 RTLIL::Module::Module()
668 {
669 static unsigned int hashidx_count = 123456789;
670 hashidx_count = mkhash_xorshift(hashidx_count);
671 hashidx_ = hashidx_count;
672
673 design = nullptr;
674 refcount_wires_ = 0;
675 refcount_cells_ = 0;
676
677 #ifdef WITH_PYTHON
678 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
679 #endif
680 }
681
682 RTLIL::Module::~Module()
683 {
684 for (auto it = wires_.begin(); it != wires_.end(); ++it)
685 delete it->second;
686 for (auto it = memories.begin(); it != memories.end(); ++it)
687 delete it->second;
688 for (auto it = cells_.begin(); it != cells_.end(); ++it)
689 delete it->second;
690 for (auto it = processes.begin(); it != processes.end(); ++it)
691 delete it->second;
692 #ifdef WITH_PYTHON
693 RTLIL::Module::get_all_modules()->erase(hashidx_);
694 #endif
695 }
696
697 #ifdef WITH_PYTHON
698 static std::map<unsigned int, RTLIL::Module*> all_modules;
699 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
700 {
701 return &all_modules;
702 }
703 #endif
704
705 void RTLIL::Module::makeblackbox()
706 {
707 pool<RTLIL::Wire*> delwires;
708
709 for (auto it = wires_.begin(); it != wires_.end(); ++it)
710 if (!it->second->port_input && !it->second->port_output)
711 delwires.insert(it->second);
712
713 for (auto it = memories.begin(); it != memories.end(); ++it)
714 delete it->second;
715 memories.clear();
716
717 for (auto it = cells_.begin(); it != cells_.end(); ++it)
718 delete it->second;
719 cells_.clear();
720
721 for (auto it = processes.begin(); it != processes.end(); ++it)
722 delete it->second;
723 processes.clear();
724
725 remove(delwires);
726 set_bool_attribute(ID::blackbox);
727 }
728
729 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
730 {
731 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
732 }
733
734 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
735 {
736 if (mayfail)
737 return RTLIL::IdString();
738 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
739 }
740
741
742 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
743 {
744 if (mayfail)
745 return RTLIL::IdString();
746 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
747 }
748
749 size_t RTLIL::Module::count_id(RTLIL::IdString id)
750 {
751 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
752 }
753
754 #ifndef NDEBUG
755 namespace {
756 struct InternalCellChecker
757 {
758 RTLIL::Module *module;
759 RTLIL::Cell *cell;
760 pool<RTLIL::IdString> expected_params, expected_ports;
761
762 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
763
764 void error(int linenr)
765 {
766 std::stringstream buf;
767 ILANG_BACKEND::dump_cell(buf, " ", cell);
768
769 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
770 module ? module->name.c_str() : "", module ? "." : "",
771 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
772 }
773
774 int param(RTLIL::IdString name)
775 {
776 auto it = cell->parameters.find(name);
777 if (it == cell->parameters.end())
778 error(__LINE__);
779 expected_params.insert(name);
780 return it->second.as_int();
781 }
782
783 int param_bool(RTLIL::IdString name)
784 {
785 int v = param(name);
786 if (GetSize(cell->parameters.at(name)) > 32)
787 error(__LINE__);
788 if (v != 0 && v != 1)
789 error(__LINE__);
790 return v;
791 }
792
793 int param_bool(RTLIL::IdString name, bool expected)
794 {
795 int v = param_bool(name);
796 if (v != expected)
797 error(__LINE__);
798 return v;
799 }
800
801 void param_bits(RTLIL::IdString name, int width)
802 {
803 param(name);
804 if (GetSize(cell->parameters.at(name).bits) != width)
805 error(__LINE__);
806 }
807
808 void port(RTLIL::IdString name, int width)
809 {
810 auto it = cell->connections_.find(name);
811 if (it == cell->connections_.end())
812 error(__LINE__);
813 if (GetSize(it->second) != width)
814 error(__LINE__);
815 expected_ports.insert(name);
816 }
817
818 void check_expected(bool check_matched_sign = false)
819 {
820 for (auto &para : cell->parameters)
821 if (expected_params.count(para.first) == 0)
822 error(__LINE__);
823 for (auto &conn : cell->connections())
824 if (expected_ports.count(conn.first) == 0)
825 error(__LINE__);
826
827 if (check_matched_sign) {
828 log_assert(expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) != 0);
829 bool a_is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
830 bool b_is_signed = cell->parameters.at(ID(B_SIGNED)).as_bool();
831 if (a_is_signed != b_is_signed)
832 error(__LINE__);
833 }
834 }
835
836 void check()
837 {
838 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
839 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
840 return;
841
842 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
843 param_bool(ID(A_SIGNED));
844 port(ID::A, param(ID(A_WIDTH)));
845 port(ID::Y, param(ID(Y_WIDTH)));
846 check_expected();
847 return;
848 }
849
850 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
851 param_bool(ID(A_SIGNED));
852 param_bool(ID(B_SIGNED));
853 port(ID::A, param(ID(A_WIDTH)));
854 port(ID::B, param(ID(B_WIDTH)));
855 port(ID::Y, param(ID(Y_WIDTH)));
856 check_expected(true);
857 return;
858 }
859
860 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
861 param_bool(ID(A_SIGNED));
862 port(ID::A, param(ID(A_WIDTH)));
863 port(ID::Y, param(ID(Y_WIDTH)));
864 check_expected();
865 return;
866 }
867
868 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
869 param_bool(ID(A_SIGNED));
870 param_bool(ID(B_SIGNED), /*expected=*/false);
871 port(ID::A, param(ID(A_WIDTH)));
872 port(ID::B, param(ID(B_WIDTH)));
873 port(ID::Y, param(ID(Y_WIDTH)));
874 check_expected(/*check_matched_sign=*/false);
875 return;
876 }
877
878 if (cell->type.in(ID($shift), ID($shiftx))) {
879 param_bool(ID(A_SIGNED));
880 param_bool(ID(B_SIGNED));
881 port(ID::A, param(ID(A_WIDTH)));
882 port(ID::B, param(ID(B_WIDTH)));
883 port(ID::Y, param(ID(Y_WIDTH)));
884 check_expected(/*check_matched_sign=*/false);
885 return;
886 }
887
888 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
889 param_bool(ID(A_SIGNED));
890 param_bool(ID(B_SIGNED));
891 port(ID::A, param(ID(A_WIDTH)));
892 port(ID::B, param(ID(B_WIDTH)));
893 port(ID::Y, param(ID(Y_WIDTH)));
894 check_expected(true);
895 return;
896 }
897
898 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
899 param_bool(ID(A_SIGNED));
900 param_bool(ID(B_SIGNED));
901 port(ID::A, param(ID(A_WIDTH)));
902 port(ID::B, param(ID(B_WIDTH)));
903 port(ID::Y, param(ID(Y_WIDTH)));
904 check_expected(cell->type != ID($pow));
905 return;
906 }
907
908 if (cell->type == ID($fa)) {
909 port(ID::A, param(ID(WIDTH)));
910 port(ID::B, param(ID(WIDTH)));
911 port(ID(C), param(ID(WIDTH)));
912 port(ID(X), param(ID(WIDTH)));
913 port(ID::Y, param(ID(WIDTH)));
914 check_expected();
915 return;
916 }
917
918 if (cell->type == ID($lcu)) {
919 port(ID(P), param(ID(WIDTH)));
920 port(ID(G), param(ID(WIDTH)));
921 port(ID(CI), 1);
922 port(ID(CO), param(ID(WIDTH)));
923 check_expected();
924 return;
925 }
926
927 if (cell->type == ID($alu)) {
928 param_bool(ID(A_SIGNED));
929 param_bool(ID(B_SIGNED));
930 port(ID::A, param(ID(A_WIDTH)));
931 port(ID::B, param(ID(B_WIDTH)));
932 port(ID(CI), 1);
933 port(ID(BI), 1);
934 port(ID(X), param(ID(Y_WIDTH)));
935 port(ID::Y, param(ID(Y_WIDTH)));
936 port(ID(CO), param(ID(Y_WIDTH)));
937 check_expected(true);
938 return;
939 }
940
941 if (cell->type == ID($macc)) {
942 param(ID(CONFIG));
943 param(ID(CONFIG_WIDTH));
944 port(ID::A, param(ID(A_WIDTH)));
945 port(ID::B, param(ID(B_WIDTH)));
946 port(ID::Y, param(ID(Y_WIDTH)));
947 check_expected();
948 Macc().from_cell(cell);
949 return;
950 }
951
952 if (cell->type == ID($logic_not)) {
953 param_bool(ID(A_SIGNED));
954 port(ID::A, param(ID(A_WIDTH)));
955 port(ID::Y, param(ID(Y_WIDTH)));
956 check_expected();
957 return;
958 }
959
960 if (cell->type.in(ID($logic_and), ID($logic_or))) {
961 param_bool(ID(A_SIGNED));
962 param_bool(ID(B_SIGNED));
963 port(ID::A, param(ID(A_WIDTH)));
964 port(ID::B, param(ID(B_WIDTH)));
965 port(ID::Y, param(ID(Y_WIDTH)));
966 check_expected(/*check_matched_sign=*/false);
967 return;
968 }
969
970 if (cell->type == ID($slice)) {
971 param(ID(OFFSET));
972 port(ID::A, param(ID(A_WIDTH)));
973 port(ID::Y, param(ID(Y_WIDTH)));
974 if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
975 error(__LINE__);
976 check_expected();
977 return;
978 }
979
980 if (cell->type == ID($concat)) {
981 port(ID::A, param(ID(A_WIDTH)));
982 port(ID::B, param(ID(B_WIDTH)));
983 port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
984 check_expected();
985 return;
986 }
987
988 if (cell->type == ID($mux)) {
989 port(ID::A, param(ID(WIDTH)));
990 port(ID::B, param(ID(WIDTH)));
991 port(ID(S), 1);
992 port(ID::Y, param(ID(WIDTH)));
993 check_expected();
994 return;
995 }
996
997 if (cell->type == ID($pmux)) {
998 port(ID::A, param(ID(WIDTH)));
999 port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
1000 port(ID(S), param(ID(S_WIDTH)));
1001 port(ID::Y, param(ID(WIDTH)));
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == ID($lut)) {
1007 param(ID(LUT));
1008 port(ID::A, param(ID(WIDTH)));
1009 port(ID::Y, 1);
1010 check_expected();
1011 return;
1012 }
1013
1014 if (cell->type == ID($sop)) {
1015 param(ID(DEPTH));
1016 param(ID(TABLE));
1017 port(ID::A, param(ID(WIDTH)));
1018 port(ID::Y, 1);
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == ID($sr)) {
1024 param_bool(ID(SET_POLARITY));
1025 param_bool(ID(CLR_POLARITY));
1026 port(ID(SET), param(ID(WIDTH)));
1027 port(ID(CLR), param(ID(WIDTH)));
1028 port(ID(Q), param(ID(WIDTH)));
1029 check_expected();
1030 return;
1031 }
1032
1033 if (cell->type == ID($ff)) {
1034 port(ID(D), param(ID(WIDTH)));
1035 port(ID(Q), param(ID(WIDTH)));
1036 check_expected();
1037 return;
1038 }
1039
1040 if (cell->type == ID($dff)) {
1041 param_bool(ID(CLK_POLARITY));
1042 port(ID(CLK), 1);
1043 port(ID(D), param(ID(WIDTH)));
1044 port(ID(Q), param(ID(WIDTH)));
1045 check_expected();
1046 return;
1047 }
1048
1049 if (cell->type == ID($dffe)) {
1050 param_bool(ID(CLK_POLARITY));
1051 param_bool(ID(EN_POLARITY));
1052 port(ID(CLK), 1);
1053 port(ID(EN), 1);
1054 port(ID(D), param(ID(WIDTH)));
1055 port(ID(Q), param(ID(WIDTH)));
1056 check_expected();
1057 return;
1058 }
1059
1060 if (cell->type == ID($dffsr)) {
1061 param_bool(ID(CLK_POLARITY));
1062 param_bool(ID(SET_POLARITY));
1063 param_bool(ID(CLR_POLARITY));
1064 port(ID(CLK), 1);
1065 port(ID(SET), param(ID(WIDTH)));
1066 port(ID(CLR), param(ID(WIDTH)));
1067 port(ID(D), param(ID(WIDTH)));
1068 port(ID(Q), param(ID(WIDTH)));
1069 check_expected();
1070 return;
1071 }
1072
1073 if (cell->type == ID($adff)) {
1074 param_bool(ID(CLK_POLARITY));
1075 param_bool(ID(ARST_POLARITY));
1076 param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
1077 port(ID(CLK), 1);
1078 port(ID(ARST), 1);
1079 port(ID(D), param(ID(WIDTH)));
1080 port(ID(Q), param(ID(WIDTH)));
1081 check_expected();
1082 return;
1083 }
1084
1085 if (cell->type == ID($dlatch)) {
1086 param_bool(ID(EN_POLARITY));
1087 port(ID(EN), 1);
1088 port(ID(D), param(ID(WIDTH)));
1089 port(ID(Q), param(ID(WIDTH)));
1090 check_expected();
1091 return;
1092 }
1093
1094 if (cell->type == ID($dlatchsr)) {
1095 param_bool(ID(EN_POLARITY));
1096 param_bool(ID(SET_POLARITY));
1097 param_bool(ID(CLR_POLARITY));
1098 port(ID(EN), 1);
1099 port(ID(SET), param(ID(WIDTH)));
1100 port(ID(CLR), param(ID(WIDTH)));
1101 port(ID(D), param(ID(WIDTH)));
1102 port(ID(Q), param(ID(WIDTH)));
1103 check_expected();
1104 return;
1105 }
1106
1107 if (cell->type == ID($fsm)) {
1108 param(ID(NAME));
1109 param_bool(ID(CLK_POLARITY));
1110 param_bool(ID(ARST_POLARITY));
1111 param(ID(STATE_BITS));
1112 param(ID(STATE_NUM));
1113 param(ID(STATE_NUM_LOG2));
1114 param(ID(STATE_RST));
1115 param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
1116 param(ID(TRANS_NUM));
1117 param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
1118 port(ID(CLK), 1);
1119 port(ID(ARST), 1);
1120 port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
1121 port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
1122 check_expected();
1123 return;
1124 }
1125
1126 if (cell->type == ID($memrd)) {
1127 param(ID(MEMID));
1128 param_bool(ID(CLK_ENABLE));
1129 param_bool(ID(CLK_POLARITY));
1130 param_bool(ID(TRANSPARENT));
1131 port(ID(CLK), 1);
1132 port(ID(EN), 1);
1133 port(ID(ADDR), param(ID(ABITS)));
1134 port(ID(DATA), param(ID(WIDTH)));
1135 check_expected();
1136 return;
1137 }
1138
1139 if (cell->type == ID($memwr)) {
1140 param(ID(MEMID));
1141 param_bool(ID(CLK_ENABLE));
1142 param_bool(ID(CLK_POLARITY));
1143 param(ID(PRIORITY));
1144 port(ID(CLK), 1);
1145 port(ID(EN), param(ID(WIDTH)));
1146 port(ID(ADDR), param(ID(ABITS)));
1147 port(ID(DATA), param(ID(WIDTH)));
1148 check_expected();
1149 return;
1150 }
1151
1152 if (cell->type == ID($meminit)) {
1153 param(ID(MEMID));
1154 param(ID(PRIORITY));
1155 port(ID(ADDR), param(ID(ABITS)));
1156 port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
1157 check_expected();
1158 return;
1159 }
1160
1161 if (cell->type == ID($mem)) {
1162 param(ID(MEMID));
1163 param(ID(SIZE));
1164 param(ID(OFFSET));
1165 param(ID(INIT));
1166 param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
1167 param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
1168 param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
1169 param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
1170 param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
1171 port(ID(RD_CLK), param(ID(RD_PORTS)));
1172 port(ID(RD_EN), param(ID(RD_PORTS)));
1173 port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
1174 port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
1175 port(ID(WR_CLK), param(ID(WR_PORTS)));
1176 port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1177 port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
1178 port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1179 check_expected();
1180 return;
1181 }
1182
1183 if (cell->type == ID($tribuf)) {
1184 port(ID::A, param(ID(WIDTH)));
1185 port(ID::Y, param(ID(WIDTH)));
1186 port(ID(EN), 1);
1187 check_expected();
1188 return;
1189 }
1190
1191 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1192 port(ID::A, 1);
1193 port(ID(EN), 1);
1194 check_expected();
1195 return;
1196 }
1197
1198 if (cell->type == ID($initstate)) {
1199 port(ID::Y, 1);
1200 check_expected();
1201 return;
1202 }
1203
1204 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1205 port(ID::Y, param(ID(WIDTH)));
1206 check_expected();
1207 return;
1208 }
1209
1210 if (cell->type == ID($equiv)) {
1211 port(ID::A, 1);
1212 port(ID::B, 1);
1213 port(ID::Y, 1);
1214 check_expected();
1215 return;
1216 }
1217
1218 if (cell->type.in(ID($specify2), ID($specify3))) {
1219 param_bool(ID(FULL));
1220 param_bool(ID(SRC_DST_PEN));
1221 param_bool(ID(SRC_DST_POL));
1222 param(ID(T_RISE_MIN));
1223 param(ID(T_RISE_TYP));
1224 param(ID(T_RISE_MAX));
1225 param(ID(T_FALL_MIN));
1226 param(ID(T_FALL_TYP));
1227 param(ID(T_FALL_MAX));
1228 port(ID(EN), 1);
1229 port(ID(SRC), param(ID(SRC_WIDTH)));
1230 port(ID(DST), param(ID(DST_WIDTH)));
1231 if (cell->type == ID($specify3)) {
1232 param_bool(ID(EDGE_EN));
1233 param_bool(ID(EDGE_POL));
1234 param_bool(ID(DAT_DST_PEN));
1235 param_bool(ID(DAT_DST_POL));
1236 port(ID(DAT), param(ID(DST_WIDTH)));
1237 }
1238 check_expected();
1239 return;
1240 }
1241
1242 if (cell->type == ID($specrule)) {
1243 param(ID(TYPE));
1244 param_bool(ID(SRC_PEN));
1245 param_bool(ID(SRC_POL));
1246 param_bool(ID(DST_PEN));
1247 param_bool(ID(DST_POL));
1248 param(ID(T_LIMIT_MIN));
1249 param(ID(T_LIMIT_TYP));
1250 param(ID(T_LIMIT_MAX));
1251 param(ID(T_LIMIT2_MIN));
1252 param(ID(T_LIMIT2_TYP));
1253 param(ID(T_LIMIT2_MAX));
1254 port(ID(SRC_EN), 1);
1255 port(ID(DST_EN), 1);
1256 port(ID(SRC), param(ID(SRC_WIDTH)));
1257 port(ID(DST), param(ID(DST_WIDTH)));
1258 check_expected();
1259 return;
1260 }
1261
1262 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1263 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1264 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1265 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1266 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1267 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1268 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1269 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1270 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1271 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1272 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; }
1273 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; }
1274 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; }
1275 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; }
1276 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; }
1277 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; }
1278
1279 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID(E),1); check_expected(); return; }
1280
1281 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(S),1); port(ID(T),1); port(ID::Y,1); check_expected(); return; }
1282 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID::Y,1); check_expected(); return; }
1283 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(I),1); port(ID(J),1); port(ID(K),1); port(ID(L),1); port(ID(M),1); port(ID(N),1); port(ID(O),1); port(ID(P),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID(V),1); port(ID::Y,1); check_expected(); return; }
1284
1285 if (cell->type == ID($_SR_NN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
1286 if (cell->type == ID($_SR_NP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
1287 if (cell->type == ID($_SR_PN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
1288 if (cell->type == ID($_SR_PP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
1289
1290 if (cell->type == ID($_FF_)) { port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1291 if (cell->type == ID($_DFF_N_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; }
1292 if (cell->type == ID($_DFF_P_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; }
1293
1294 if (cell->type == ID($_DFFE_NN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
1295 if (cell->type == ID($_DFFE_NP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
1296 if (cell->type == ID($_DFFE_PN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
1297 if (cell->type == ID($_DFFE_PP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
1298
1299 if (cell->type == ID($_DFF_NN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1300 if (cell->type == ID($_DFF_NN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1301 if (cell->type == ID($_DFF_NP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1302 if (cell->type == ID($_DFF_NP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1303 if (cell->type == ID($_DFF_PN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1304 if (cell->type == ID($_DFF_PN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1305 if (cell->type == ID($_DFF_PP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1306 if (cell->type == ID($_DFF_PP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
1307
1308 if (cell->type == ID($_DFFSR_NNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1309 if (cell->type == ID($_DFFSR_NNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1310 if (cell->type == ID($_DFFSR_NPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1311 if (cell->type == ID($_DFFSR_NPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1312 if (cell->type == ID($_DFFSR_PNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1313 if (cell->type == ID($_DFFSR_PNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1314 if (cell->type == ID($_DFFSR_PPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1315 if (cell->type == ID($_DFFSR_PPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1316
1317 if (cell->type == ID($_DLATCH_N_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1318 if (cell->type == ID($_DLATCH_P_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1319
1320 if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1321 if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1322 if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1323 if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1324 if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1325 if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1326 if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1327 if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
1328
1329 error(__LINE__);
1330 }
1331 };
1332 }
1333 #endif
1334
1335 void RTLIL::Module::sort()
1336 {
1337 wires_.sort(sort_by_id_str());
1338 cells_.sort(sort_by_id_str());
1339 avail_parameters.sort(sort_by_id_str());
1340 memories.sort(sort_by_id_str());
1341 processes.sort(sort_by_id_str());
1342 for (auto &it : cells_)
1343 it.second->sort();
1344 for (auto &it : wires_)
1345 it.second->attributes.sort(sort_by_id_str());
1346 for (auto &it : memories)
1347 it.second->attributes.sort(sort_by_id_str());
1348 }
1349
1350 void RTLIL::Module::check()
1351 {
1352 #ifndef NDEBUG
1353 std::vector<bool> ports_declared;
1354 for (auto &it : wires_) {
1355 log_assert(this == it.second->module);
1356 log_assert(it.first == it.second->name);
1357 log_assert(!it.first.empty());
1358 log_assert(it.second->width >= 0);
1359 log_assert(it.second->port_id >= 0);
1360 for (auto &it2 : it.second->attributes)
1361 log_assert(!it2.first.empty());
1362 if (it.second->port_id) {
1363 log_assert(GetSize(ports) >= it.second->port_id);
1364 log_assert(ports.at(it.second->port_id-1) == it.first);
1365 log_assert(it.second->port_input || it.second->port_output);
1366 if (GetSize(ports_declared) < it.second->port_id)
1367 ports_declared.resize(it.second->port_id);
1368 log_assert(ports_declared[it.second->port_id-1] == false);
1369 ports_declared[it.second->port_id-1] = true;
1370 } else
1371 log_assert(!it.second->port_input && !it.second->port_output);
1372 }
1373 for (auto port_declared : ports_declared)
1374 log_assert(port_declared == true);
1375 log_assert(GetSize(ports) == GetSize(ports_declared));
1376
1377 for (auto &it : memories) {
1378 log_assert(it.first == it.second->name);
1379 log_assert(!it.first.empty());
1380 log_assert(it.second->width >= 0);
1381 log_assert(it.second->size >= 0);
1382 for (auto &it2 : it.second->attributes)
1383 log_assert(!it2.first.empty());
1384 }
1385
1386 for (auto &it : cells_) {
1387 log_assert(this == it.second->module);
1388 log_assert(it.first == it.second->name);
1389 log_assert(!it.first.empty());
1390 log_assert(!it.second->type.empty());
1391 for (auto &it2 : it.second->connections()) {
1392 log_assert(!it2.first.empty());
1393 it2.second.check();
1394 }
1395 for (auto &it2 : it.second->attributes)
1396 log_assert(!it2.first.empty());
1397 for (auto &it2 : it.second->parameters)
1398 log_assert(!it2.first.empty());
1399 InternalCellChecker checker(this, it.second);
1400 checker.check();
1401 }
1402
1403 for (auto &it : processes) {
1404 log_assert(it.first == it.second->name);
1405 log_assert(!it.first.empty());
1406 log_assert(it.second->root_case.compare.empty());
1407 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1408 for (size_t i = 0; i < all_cases.size(); i++) {
1409 for (auto &switch_it : all_cases[i]->switches) {
1410 for (auto &case_it : switch_it->cases) {
1411 for (auto &compare_it : case_it->compare) {
1412 log_assert(switch_it->signal.size() == compare_it.size());
1413 }
1414 all_cases.push_back(case_it);
1415 }
1416 }
1417 }
1418 for (auto &sync_it : it.second->syncs) {
1419 switch (sync_it->type) {
1420 case SyncType::ST0:
1421 case SyncType::ST1:
1422 case SyncType::STp:
1423 case SyncType::STn:
1424 case SyncType::STe:
1425 log_assert(!sync_it->signal.empty());
1426 break;
1427 case SyncType::STa:
1428 case SyncType::STg:
1429 case SyncType::STi:
1430 log_assert(sync_it->signal.empty());
1431 break;
1432 }
1433 }
1434 }
1435
1436 for (auto &it : connections_) {
1437 log_assert(it.first.size() == it.second.size());
1438 log_assert(!it.first.has_const());
1439 it.first.check();
1440 it.second.check();
1441 }
1442
1443 for (auto &it : attributes)
1444 log_assert(!it.first.empty());
1445 #endif
1446 }
1447
1448 void RTLIL::Module::optimize()
1449 {
1450 }
1451
1452 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1453 {
1454 log_assert(new_mod->refcount_wires_ == 0);
1455 log_assert(new_mod->refcount_cells_ == 0);
1456
1457 new_mod->avail_parameters = avail_parameters;
1458
1459 for (auto &conn : connections_)
1460 new_mod->connect(conn);
1461
1462 for (auto &attr : attributes)
1463 new_mod->attributes[attr.first] = attr.second;
1464
1465 for (auto &it : wires_)
1466 new_mod->addWire(it.first, it.second);
1467
1468 for (auto &it : memories)
1469 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1470
1471 for (auto &it : cells_)
1472 new_mod->addCell(it.first, it.second);
1473
1474 for (auto &it : processes)
1475 new_mod->processes[it.first] = it.second->clone();
1476
1477 struct RewriteSigSpecWorker
1478 {
1479 RTLIL::Module *mod;
1480 void operator()(RTLIL::SigSpec &sig)
1481 {
1482 sig.pack();
1483 for (auto &c : sig.chunks_)
1484 if (c.wire != NULL)
1485 c.wire = mod->wires_.at(c.wire->name);
1486 }
1487 };
1488
1489 RewriteSigSpecWorker rewriteSigSpecWorker;
1490 rewriteSigSpecWorker.mod = new_mod;
1491 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1492 new_mod->fixup_ports();
1493 }
1494
1495 RTLIL::Module *RTLIL::Module::clone() const
1496 {
1497 RTLIL::Module *new_mod = new RTLIL::Module;
1498 new_mod->name = name;
1499 cloneInto(new_mod);
1500 return new_mod;
1501 }
1502
1503 bool RTLIL::Module::has_memories() const
1504 {
1505 return !memories.empty();
1506 }
1507
1508 bool RTLIL::Module::has_processes() const
1509 {
1510 return !processes.empty();
1511 }
1512
1513 bool RTLIL::Module::has_memories_warn() const
1514 {
1515 if (!memories.empty())
1516 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1517 return !memories.empty();
1518 }
1519
1520 bool RTLIL::Module::has_processes_warn() const
1521 {
1522 if (!processes.empty())
1523 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1524 return !processes.empty();
1525 }
1526
1527 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1528 {
1529 std::vector<RTLIL::Wire*> result;
1530 result.reserve(wires_.size());
1531 for (auto &it : wires_)
1532 if (design->selected(this, it.second))
1533 result.push_back(it.second);
1534 return result;
1535 }
1536
1537 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1538 {
1539 std::vector<RTLIL::Cell*> result;
1540 result.reserve(cells_.size());
1541 for (auto &it : cells_)
1542 if (design->selected(this, it.second))
1543 result.push_back(it.second);
1544 return result;
1545 }
1546
1547 void RTLIL::Module::add(RTLIL::Wire *wire)
1548 {
1549 log_assert(!wire->name.empty());
1550 log_assert(count_id(wire->name) == 0);
1551 log_assert(refcount_wires_ == 0);
1552 wires_[wire->name] = wire;
1553 wire->module = this;
1554 }
1555
1556 void RTLIL::Module::add(RTLIL::Cell *cell)
1557 {
1558 log_assert(!cell->name.empty());
1559 log_assert(count_id(cell->name) == 0);
1560 log_assert(refcount_cells_ == 0);
1561 cells_[cell->name] = cell;
1562 cell->module = this;
1563 }
1564
1565 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1566 {
1567 log_assert(refcount_wires_ == 0);
1568
1569 struct DeleteWireWorker
1570 {
1571 RTLIL::Module *module;
1572 const pool<RTLIL::Wire*> *wires_p;
1573
1574 void operator()(RTLIL::SigSpec &sig) {
1575 sig.pack();
1576 for (auto &c : sig.chunks_)
1577 if (c.wire != NULL && wires_p->count(c.wire)) {
1578 c.wire = module->addWire(NEW_ID, c.width);
1579 c.offset = 0;
1580 }
1581 }
1582
1583 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1584 log_assert(GetSize(lhs) == GetSize(rhs));
1585 lhs.unpack();
1586 rhs.unpack();
1587 for (int i = 0; i < GetSize(lhs); i++) {
1588 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1589 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1590 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1591 lhs_bit = State::Sx;
1592 rhs_bit = State::Sx;
1593 }
1594 }
1595 }
1596 };
1597
1598 DeleteWireWorker delete_wire_worker;
1599 delete_wire_worker.module = this;
1600 delete_wire_worker.wires_p = &wires;
1601 rewrite_sigspecs2(delete_wire_worker);
1602
1603 for (auto &it : wires) {
1604 log_assert(wires_.count(it->name) != 0);
1605 wires_.erase(it->name);
1606 delete it;
1607 }
1608 }
1609
1610 void RTLIL::Module::remove(RTLIL::Cell *cell)
1611 {
1612 while (!cell->connections_.empty())
1613 cell->unsetPort(cell->connections_.begin()->first);
1614
1615 log_assert(cells_.count(cell->name) != 0);
1616 log_assert(refcount_cells_ == 0);
1617 cells_.erase(cell->name);
1618 delete cell;
1619 }
1620
1621 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1622 {
1623 log_assert(wires_[wire->name] == wire);
1624 log_assert(refcount_wires_ == 0);
1625 wires_.erase(wire->name);
1626 wire->name = new_name;
1627 add(wire);
1628 }
1629
1630 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1631 {
1632 log_assert(cells_[cell->name] == cell);
1633 log_assert(refcount_wires_ == 0);
1634 cells_.erase(cell->name);
1635 cell->name = new_name;
1636 add(cell);
1637 }
1638
1639 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1640 {
1641 log_assert(count_id(old_name) != 0);
1642 if (wires_.count(old_name))
1643 rename(wires_.at(old_name), new_name);
1644 else if (cells_.count(old_name))
1645 rename(cells_.at(old_name), new_name);
1646 else
1647 log_abort();
1648 }
1649
1650 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1651 {
1652 log_assert(wires_[w1->name] == w1);
1653 log_assert(wires_[w2->name] == w2);
1654 log_assert(refcount_wires_ == 0);
1655
1656 wires_.erase(w1->name);
1657 wires_.erase(w2->name);
1658
1659 std::swap(w1->name, w2->name);
1660
1661 wires_[w1->name] = w1;
1662 wires_[w2->name] = w2;
1663 }
1664
1665 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1666 {
1667 log_assert(cells_[c1->name] == c1);
1668 log_assert(cells_[c2->name] == c2);
1669 log_assert(refcount_cells_ == 0);
1670
1671 cells_.erase(c1->name);
1672 cells_.erase(c2->name);
1673
1674 std::swap(c1->name, c2->name);
1675
1676 cells_[c1->name] = c1;
1677 cells_[c2->name] = c2;
1678 }
1679
1680 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1681 {
1682 int index = 0;
1683 return uniquify(name, index);
1684 }
1685
1686 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1687 {
1688 if (index == 0) {
1689 if (count_id(name) == 0)
1690 return name;
1691 index++;
1692 }
1693
1694 while (1) {
1695 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1696 if (count_id(new_name) == 0)
1697 return new_name;
1698 index++;
1699 }
1700 }
1701
1702 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1703 {
1704 if (a->port_id && !b->port_id)
1705 return true;
1706 if (!a->port_id && b->port_id)
1707 return false;
1708
1709 if (a->port_id == b->port_id)
1710 return a->name < b->name;
1711 return a->port_id < b->port_id;
1712 }
1713
1714 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1715 {
1716 for (auto mon : monitors)
1717 mon->notify_connect(this, conn);
1718
1719 if (design)
1720 for (auto mon : design->monitors)
1721 mon->notify_connect(this, conn);
1722
1723 // ignore all attempts to assign constants to other constants
1724 if (conn.first.has_const()) {
1725 RTLIL::SigSig new_conn;
1726 for (int i = 0; i < GetSize(conn.first); i++)
1727 if (conn.first[i].wire) {
1728 new_conn.first.append(conn.first[i]);
1729 new_conn.second.append(conn.second[i]);
1730 }
1731 if (GetSize(new_conn.first))
1732 connect(new_conn);
1733 return;
1734 }
1735
1736 if (yosys_xtrace) {
1737 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1738 log_backtrace("-X- ", yosys_xtrace-1);
1739 }
1740
1741 log_assert(GetSize(conn.first) == GetSize(conn.second));
1742 connections_.push_back(conn);
1743 }
1744
1745 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1746 {
1747 connect(RTLIL::SigSig(lhs, rhs));
1748 }
1749
1750 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1751 {
1752 for (auto mon : monitors)
1753 mon->notify_connect(this, new_conn);
1754
1755 if (design)
1756 for (auto mon : design->monitors)
1757 mon->notify_connect(this, new_conn);
1758
1759 if (yosys_xtrace) {
1760 log("#X# New connections vector in %s:\n", log_id(this));
1761 for (auto &conn: new_conn)
1762 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1763 log_backtrace("-X- ", yosys_xtrace-1);
1764 }
1765
1766 connections_ = new_conn;
1767 }
1768
1769 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1770 {
1771 return connections_;
1772 }
1773
1774 void RTLIL::Module::fixup_ports()
1775 {
1776 std::vector<RTLIL::Wire*> all_ports;
1777
1778 for (auto &w : wires_)
1779 if (w.second->port_input || w.second->port_output)
1780 all_ports.push_back(w.second);
1781 else
1782 w.second->port_id = 0;
1783
1784 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1785
1786 ports.clear();
1787 for (size_t i = 0; i < all_ports.size(); i++) {
1788 ports.push_back(all_ports[i]->name);
1789 all_ports[i]->port_id = i+1;
1790 }
1791 }
1792
1793 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1794 {
1795 RTLIL::Wire *wire = new RTLIL::Wire;
1796 wire->name = name;
1797 wire->width = width;
1798 add(wire);
1799 return wire;
1800 }
1801
1802 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1803 {
1804 RTLIL::Wire *wire = addWire(name);
1805 wire->width = other->width;
1806 wire->start_offset = other->start_offset;
1807 wire->port_id = other->port_id;
1808 wire->port_input = other->port_input;
1809 wire->port_output = other->port_output;
1810 wire->upto = other->upto;
1811 wire->attributes = other->attributes;
1812 return wire;
1813 }
1814
1815 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1816 {
1817 RTLIL::Cell *cell = new RTLIL::Cell;
1818 cell->name = name;
1819 cell->type = type;
1820 add(cell);
1821 return cell;
1822 }
1823
1824 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1825 {
1826 RTLIL::Cell *cell = addCell(name, other->type);
1827 cell->connections_ = other->connections_;
1828 cell->parameters = other->parameters;
1829 cell->attributes = other->attributes;
1830 return cell;
1831 }
1832
1833 #define DEF_METHOD(_func, _y_size, _type) \
1834 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1835 RTLIL::Cell *cell = addCell(name, _type); \
1836 cell->parameters[ID(A_SIGNED)] = is_signed; \
1837 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1838 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1839 cell->setPort(ID::A, sig_a); \
1840 cell->setPort(ID::Y, sig_y); \
1841 cell->set_src_attribute(src); \
1842 return cell; \
1843 } \
1844 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1845 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1846 add ## _func(name, sig_a, sig_y, is_signed, src); \
1847 return sig_y; \
1848 }
1849 DEF_METHOD(Not, sig_a.size(), ID($not))
1850 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1851 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1852 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1853 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1854 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1855 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1856 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1857 DEF_METHOD(LogicNot, 1, ID($logic_not))
1858 #undef DEF_METHOD
1859
1860 #define DEF_METHOD(_func, _y_size, _type) \
1861 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1862 RTLIL::Cell *cell = addCell(name, _type); \
1863 cell->parameters[ID(A_SIGNED)] = is_signed; \
1864 cell->parameters[ID(B_SIGNED)] = is_signed; \
1865 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1866 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1867 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1868 cell->setPort(ID::A, sig_a); \
1869 cell->setPort(ID::B, sig_b); \
1870 cell->setPort(ID::Y, sig_y); \
1871 cell->set_src_attribute(src); \
1872 return cell; \
1873 } \
1874 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1875 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1876 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1877 return sig_y; \
1878 }
1879 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1880 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1881 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1882 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1883 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1884 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1885 DEF_METHOD(Lt, 1, ID($lt))
1886 DEF_METHOD(Le, 1, ID($le))
1887 DEF_METHOD(Eq, 1, ID($eq))
1888 DEF_METHOD(Ne, 1, ID($ne))
1889 DEF_METHOD(Eqx, 1, ID($eqx))
1890 DEF_METHOD(Nex, 1, ID($nex))
1891 DEF_METHOD(Ge, 1, ID($ge))
1892 DEF_METHOD(Gt, 1, ID($gt))
1893 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1894 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1895 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1896 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1897 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1898 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1899 DEF_METHOD(LogicOr, 1, ID($logic_or))
1900 #undef DEF_METHOD
1901
1902 #define DEF_METHOD(_func, _y_size, _type) \
1903 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1904 RTLIL::Cell *cell = addCell(name, _type); \
1905 cell->parameters[ID(A_SIGNED)] = is_signed; \
1906 cell->parameters[ID(B_SIGNED)] = false; \
1907 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1908 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1909 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1910 cell->setPort(ID::A, sig_a); \
1911 cell->setPort(ID::B, sig_b); \
1912 cell->setPort(ID::Y, sig_y); \
1913 cell->set_src_attribute(src); \
1914 return cell; \
1915 } \
1916 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1917 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1918 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1919 return sig_y; \
1920 }
1921 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1922 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1923 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1924 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1925 #undef DEF_METHOD
1926
1927 #define DEF_METHOD(_func, _type, _pmux) \
1928 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1929 RTLIL::Cell *cell = addCell(name, _type); \
1930 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1931 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1932 cell->setPort(ID::A, sig_a); \
1933 cell->setPort(ID::B, sig_b); \
1934 cell->setPort(ID(S), sig_s); \
1935 cell->setPort(ID::Y, sig_y); \
1936 cell->set_src_attribute(src); \
1937 return cell; \
1938 } \
1939 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1940 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1941 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1942 return sig_y; \
1943 }
1944 DEF_METHOD(Mux, ID($mux), 0)
1945 DEF_METHOD(Pmux, ID($pmux), 1)
1946 #undef DEF_METHOD
1947
1948 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1949 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1950 RTLIL::Cell *cell = addCell(name, _type); \
1951 cell->setPort("\\" #_P1, sig1); \
1952 cell->setPort("\\" #_P2, sig2); \
1953 cell->set_src_attribute(src); \
1954 return cell; \
1955 } \
1956 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
1957 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1958 add ## _func(name, sig1, sig2, src); \
1959 return sig2; \
1960 }
1961 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1962 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
1963 RTLIL::Cell *cell = addCell(name, _type); \
1964 cell->setPort("\\" #_P1, sig1); \
1965 cell->setPort("\\" #_P2, sig2); \
1966 cell->setPort("\\" #_P3, sig3); \
1967 cell->set_src_attribute(src); \
1968 return cell; \
1969 } \
1970 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1971 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1972 add ## _func(name, sig1, sig2, sig3, src); \
1973 return sig3; \
1974 }
1975 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1976 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
1977 RTLIL::Cell *cell = addCell(name, _type); \
1978 cell->setPort("\\" #_P1, sig1); \
1979 cell->setPort("\\" #_P2, sig2); \
1980 cell->setPort("\\" #_P3, sig3); \
1981 cell->setPort("\\" #_P4, sig4); \
1982 cell->set_src_attribute(src); \
1983 return cell; \
1984 } \
1985 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
1986 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1987 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1988 return sig4; \
1989 }
1990 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1991 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
1992 RTLIL::Cell *cell = addCell(name, _type); \
1993 cell->setPort("\\" #_P1, sig1); \
1994 cell->setPort("\\" #_P2, sig2); \
1995 cell->setPort("\\" #_P3, sig3); \
1996 cell->setPort("\\" #_P4, sig4); \
1997 cell->setPort("\\" #_P5, sig5); \
1998 cell->set_src_attribute(src); \
1999 return cell; \
2000 } \
2001 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2002 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2003 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2004 return sig5; \
2005 }
2006 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2007 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2008 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2009 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2010 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2011 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2012 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2013 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2014 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2015 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2016 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2017 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2018 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2019 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2020 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2021 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2022 #undef DEF_METHOD_2
2023 #undef DEF_METHOD_3
2024 #undef DEF_METHOD_4
2025 #undef DEF_METHOD_5
2026
2027 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2028 {
2029 RTLIL::Cell *cell = addCell(name, ID($pow));
2030 cell->parameters[ID(A_SIGNED)] = a_signed;
2031 cell->parameters[ID(B_SIGNED)] = b_signed;
2032 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2033 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2034 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2035 cell->setPort(ID::A, sig_a);
2036 cell->setPort(ID::B, sig_b);
2037 cell->setPort(ID::Y, sig_y);
2038 cell->set_src_attribute(src);
2039 return cell;
2040 }
2041
2042 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2043 {
2044 RTLIL::Cell *cell = addCell(name, ID($slice));
2045 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2046 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2047 cell->parameters[ID(OFFSET)] = offset;
2048 cell->setPort(ID::A, sig_a);
2049 cell->setPort(ID::Y, sig_y);
2050 cell->set_src_attribute(src);
2051 return cell;
2052 }
2053
2054 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2055 {
2056 RTLIL::Cell *cell = addCell(name, ID($concat));
2057 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2058 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2059 cell->setPort(ID::A, sig_a);
2060 cell->setPort(ID::B, sig_b);
2061 cell->setPort(ID::Y, sig_y);
2062 cell->set_src_attribute(src);
2063 return cell;
2064 }
2065
2066 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2067 {
2068 RTLIL::Cell *cell = addCell(name, ID($lut));
2069 cell->parameters[ID(LUT)] = lut;
2070 cell->parameters[ID(WIDTH)] = sig_a.size();
2071 cell->setPort(ID::A, sig_a);
2072 cell->setPort(ID::Y, sig_y);
2073 cell->set_src_attribute(src);
2074 return cell;
2075 }
2076
2077 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2078 {
2079 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2080 cell->parameters[ID(WIDTH)] = sig_a.size();
2081 cell->setPort(ID::A, sig_a);
2082 cell->setPort(ID(EN), sig_en);
2083 cell->setPort(ID::Y, sig_y);
2084 cell->set_src_attribute(src);
2085 return cell;
2086 }
2087
2088 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2089 {
2090 RTLIL::Cell *cell = addCell(name, ID($assert));
2091 cell->setPort(ID::A, sig_a);
2092 cell->setPort(ID(EN), sig_en);
2093 cell->set_src_attribute(src);
2094 return cell;
2095 }
2096
2097 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2098 {
2099 RTLIL::Cell *cell = addCell(name, ID($assume));
2100 cell->setPort(ID::A, sig_a);
2101 cell->setPort(ID(EN), sig_en);
2102 cell->set_src_attribute(src);
2103 return cell;
2104 }
2105
2106 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2107 {
2108 RTLIL::Cell *cell = addCell(name, ID($live));
2109 cell->setPort(ID::A, sig_a);
2110 cell->setPort(ID(EN), sig_en);
2111 cell->set_src_attribute(src);
2112 return cell;
2113 }
2114
2115 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2116 {
2117 RTLIL::Cell *cell = addCell(name, ID($fair));
2118 cell->setPort(ID::A, sig_a);
2119 cell->setPort(ID(EN), sig_en);
2120 cell->set_src_attribute(src);
2121 return cell;
2122 }
2123
2124 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2125 {
2126 RTLIL::Cell *cell = addCell(name, ID($cover));
2127 cell->setPort(ID::A, sig_a);
2128 cell->setPort(ID(EN), sig_en);
2129 cell->set_src_attribute(src);
2130 return cell;
2131 }
2132
2133 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2134 {
2135 RTLIL::Cell *cell = addCell(name, ID($equiv));
2136 cell->setPort(ID::A, sig_a);
2137 cell->setPort(ID::B, sig_b);
2138 cell->setPort(ID::Y, sig_y);
2139 cell->set_src_attribute(src);
2140 return cell;
2141 }
2142
2143 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2144 {
2145 RTLIL::Cell *cell = addCell(name, ID($sr));
2146 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2147 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2148 cell->parameters[ID(WIDTH)] = sig_q.size();
2149 cell->setPort(ID(SET), sig_set);
2150 cell->setPort(ID(CLR), sig_clr);
2151 cell->setPort(ID(Q), sig_q);
2152 cell->set_src_attribute(src);
2153 return cell;
2154 }
2155
2156 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2157 {
2158 RTLIL::Cell *cell = addCell(name, ID($ff));
2159 cell->parameters[ID(WIDTH)] = sig_q.size();
2160 cell->setPort(ID(D), sig_d);
2161 cell->setPort(ID(Q), sig_q);
2162 cell->set_src_attribute(src);
2163 return cell;
2164 }
2165
2166 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2167 {
2168 RTLIL::Cell *cell = addCell(name, ID($dff));
2169 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2170 cell->parameters[ID(WIDTH)] = sig_q.size();
2171 cell->setPort(ID(CLK), sig_clk);
2172 cell->setPort(ID(D), sig_d);
2173 cell->setPort(ID(Q), sig_q);
2174 cell->set_src_attribute(src);
2175 return cell;
2176 }
2177
2178 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2179 {
2180 RTLIL::Cell *cell = addCell(name, ID($dffe));
2181 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2182 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2183 cell->parameters[ID(WIDTH)] = sig_q.size();
2184 cell->setPort(ID(CLK), sig_clk);
2185 cell->setPort(ID(EN), sig_en);
2186 cell->setPort(ID(D), sig_d);
2187 cell->setPort(ID(Q), sig_q);
2188 cell->set_src_attribute(src);
2189 return cell;
2190 }
2191
2192 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2193 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2194 {
2195 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2196 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2197 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2198 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2199 cell->parameters[ID(WIDTH)] = sig_q.size();
2200 cell->setPort(ID(CLK), sig_clk);
2201 cell->setPort(ID(SET), sig_set);
2202 cell->setPort(ID(CLR), sig_clr);
2203 cell->setPort(ID(D), sig_d);
2204 cell->setPort(ID(Q), sig_q);
2205 cell->set_src_attribute(src);
2206 return cell;
2207 }
2208
2209 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2210 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2211 {
2212 RTLIL::Cell *cell = addCell(name, ID($adff));
2213 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2214 cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
2215 cell->parameters[ID(ARST_VALUE)] = arst_value;
2216 cell->parameters[ID(WIDTH)] = sig_q.size();
2217 cell->setPort(ID(CLK), sig_clk);
2218 cell->setPort(ID(ARST), sig_arst);
2219 cell->setPort(ID(D), sig_d);
2220 cell->setPort(ID(Q), sig_q);
2221 cell->set_src_attribute(src);
2222 return cell;
2223 }
2224
2225 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2226 {
2227 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2228 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2229 cell->parameters[ID(WIDTH)] = sig_q.size();
2230 cell->setPort(ID(EN), sig_en);
2231 cell->setPort(ID(D), sig_d);
2232 cell->setPort(ID(Q), sig_q);
2233 cell->set_src_attribute(src);
2234 return cell;
2235 }
2236
2237 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2238 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2239 {
2240 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2241 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2242 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2243 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2244 cell->parameters[ID(WIDTH)] = sig_q.size();
2245 cell->setPort(ID(EN), sig_en);
2246 cell->setPort(ID(SET), sig_set);
2247 cell->setPort(ID(CLR), sig_clr);
2248 cell->setPort(ID(D), sig_d);
2249 cell->setPort(ID(Q), sig_q);
2250 cell->set_src_attribute(src);
2251 return cell;
2252 }
2253
2254 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2255 {
2256 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2257 cell->setPort(ID(D), sig_d);
2258 cell->setPort(ID(Q), sig_q);
2259 cell->set_src_attribute(src);
2260 return cell;
2261 }
2262
2263 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2264 {
2265 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2266 cell->setPort(ID(C), sig_clk);
2267 cell->setPort(ID(D), sig_d);
2268 cell->setPort(ID(Q), sig_q);
2269 cell->set_src_attribute(src);
2270 return cell;
2271 }
2272
2273 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2274 {
2275 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2276 cell->setPort(ID(C), sig_clk);
2277 cell->setPort(ID(E), sig_en);
2278 cell->setPort(ID(D), sig_d);
2279 cell->setPort(ID(Q), sig_q);
2280 cell->set_src_attribute(src);
2281 return cell;
2282 }
2283
2284 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2285 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2286 {
2287 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2288 cell->setPort(ID(C), sig_clk);
2289 cell->setPort(ID(S), sig_set);
2290 cell->setPort(ID(R), sig_clr);
2291 cell->setPort(ID(D), sig_d);
2292 cell->setPort(ID(Q), sig_q);
2293 cell->set_src_attribute(src);
2294 return cell;
2295 }
2296
2297 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2298 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2299 {
2300 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2301 cell->setPort(ID(C), sig_clk);
2302 cell->setPort(ID(R), sig_arst);
2303 cell->setPort(ID(D), sig_d);
2304 cell->setPort(ID(Q), sig_q);
2305 cell->set_src_attribute(src);
2306 return cell;
2307 }
2308
2309 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2310 {
2311 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2312 cell->setPort(ID(E), sig_en);
2313 cell->setPort(ID(D), sig_d);
2314 cell->setPort(ID(Q), sig_q);
2315 cell->set_src_attribute(src);
2316 return cell;
2317 }
2318
2319 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2320 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2321 {
2322 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2323 cell->setPort(ID(E), sig_en);
2324 cell->setPort(ID(S), sig_set);
2325 cell->setPort(ID(R), sig_clr);
2326 cell->setPort(ID(D), sig_d);
2327 cell->setPort(ID(Q), sig_q);
2328 cell->set_src_attribute(src);
2329 return cell;
2330 }
2331
2332 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2333 {
2334 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2335 Cell *cell = addCell(name, ID($anyconst));
2336 cell->setParam(ID(WIDTH), width);
2337 cell->setPort(ID::Y, sig);
2338 cell->set_src_attribute(src);
2339 return sig;
2340 }
2341
2342 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2343 {
2344 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2345 Cell *cell = addCell(name, ID($anyseq));
2346 cell->setParam(ID(WIDTH), width);
2347 cell->setPort(ID::Y, sig);
2348 cell->set_src_attribute(src);
2349 return sig;
2350 }
2351
2352 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2353 {
2354 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2355 Cell *cell = addCell(name, ID($allconst));
2356 cell->setParam(ID(WIDTH), width);
2357 cell->setPort(ID::Y, sig);
2358 cell->set_src_attribute(src);
2359 return sig;
2360 }
2361
2362 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2363 {
2364 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2365 Cell *cell = addCell(name, ID($allseq));
2366 cell->setParam(ID(WIDTH), width);
2367 cell->setPort(ID::Y, sig);
2368 cell->set_src_attribute(src);
2369 return sig;
2370 }
2371
2372 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2373 {
2374 RTLIL::SigSpec sig = addWire(NEW_ID);
2375 Cell *cell = addCell(name, ID($initstate));
2376 cell->setPort(ID::Y, sig);
2377 cell->set_src_attribute(src);
2378 return sig;
2379 }
2380
2381 RTLIL::Wire::Wire()
2382 {
2383 static unsigned int hashidx_count = 123456789;
2384 hashidx_count = mkhash_xorshift(hashidx_count);
2385 hashidx_ = hashidx_count;
2386
2387 module = nullptr;
2388 width = 1;
2389 start_offset = 0;
2390 port_id = 0;
2391 port_input = false;
2392 port_output = false;
2393 upto = false;
2394
2395 #ifdef WITH_PYTHON
2396 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2397 #endif
2398 }
2399
2400 RTLIL::Wire::~Wire()
2401 {
2402 #ifdef WITH_PYTHON
2403 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2404 #endif
2405 }
2406
2407 #ifdef WITH_PYTHON
2408 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2409 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2410 {
2411 return &all_wires;
2412 }
2413 #endif
2414
2415 RTLIL::Memory::Memory()
2416 {
2417 static unsigned int hashidx_count = 123456789;
2418 hashidx_count = mkhash_xorshift(hashidx_count);
2419 hashidx_ = hashidx_count;
2420
2421 width = 1;
2422 start_offset = 0;
2423 size = 0;
2424 #ifdef WITH_PYTHON
2425 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2426 #endif
2427 }
2428
2429 RTLIL::Cell::Cell() : module(nullptr)
2430 {
2431 static unsigned int hashidx_count = 123456789;
2432 hashidx_count = mkhash_xorshift(hashidx_count);
2433 hashidx_ = hashidx_count;
2434
2435 // log("#memtrace# %p\n", this);
2436 memhasher();
2437
2438 #ifdef WITH_PYTHON
2439 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2440 #endif
2441 }
2442
2443 RTLIL::Cell::~Cell()
2444 {
2445 #ifdef WITH_PYTHON
2446 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2447 #endif
2448 }
2449
2450 #ifdef WITH_PYTHON
2451 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2452 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2453 {
2454 return &all_cells;
2455 }
2456 #endif
2457
2458 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2459 {
2460 return connections_.count(portname) != 0;
2461 }
2462
2463 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2464 {
2465 RTLIL::SigSpec signal;
2466 auto conn_it = connections_.find(portname);
2467
2468 if (conn_it != connections_.end())
2469 {
2470 for (auto mon : module->monitors)
2471 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2472
2473 if (module->design)
2474 for (auto mon : module->design->monitors)
2475 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2476
2477 if (yosys_xtrace) {
2478 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2479 log_backtrace("-X- ", yosys_xtrace-1);
2480 }
2481
2482 connections_.erase(conn_it);
2483 }
2484 }
2485
2486 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2487 {
2488 auto r = connections_.insert(portname);
2489 auto conn_it = r.first;
2490 if (!r.second && conn_it->second == signal)
2491 return;
2492
2493 for (auto mon : module->monitors)
2494 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2495
2496 if (module->design)
2497 for (auto mon : module->design->monitors)
2498 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2499
2500 if (yosys_xtrace) {
2501 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2502 log_backtrace("-X- ", yosys_xtrace-1);
2503 }
2504
2505 conn_it->second = std::move(signal);
2506 }
2507
2508 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2509 {
2510 return connections_.at(portname);
2511 }
2512
2513 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2514 {
2515 return connections_;
2516 }
2517
2518 bool RTLIL::Cell::known() const
2519 {
2520 if (yosys_celltypes.cell_known(type))
2521 return true;
2522 if (module && module->design && module->design->module(type))
2523 return true;
2524 return false;
2525 }
2526
2527 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2528 {
2529 if (yosys_celltypes.cell_known(type))
2530 return yosys_celltypes.cell_input(type, portname);
2531 if (module && module->design) {
2532 RTLIL::Module *m = module->design->module(type);
2533 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2534 return w && w->port_input;
2535 }
2536 return false;
2537 }
2538
2539 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2540 {
2541 if (yosys_celltypes.cell_known(type))
2542 return yosys_celltypes.cell_output(type, portname);
2543 if (module && module->design) {
2544 RTLIL::Module *m = module->design->module(type);
2545 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2546 return w && w->port_output;
2547 }
2548 return false;
2549 }
2550
2551 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2552 {
2553 return parameters.count(paramname) != 0;
2554 }
2555
2556 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2557 {
2558 parameters.erase(paramname);
2559 }
2560
2561 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2562 {
2563 parameters[paramname] = std::move(value);
2564 }
2565
2566 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2567 {
2568 return parameters.at(paramname);
2569 }
2570
2571 void RTLIL::Cell::sort()
2572 {
2573 connections_.sort(sort_by_id_str());
2574 parameters.sort(sort_by_id_str());
2575 attributes.sort(sort_by_id_str());
2576 }
2577
2578 void RTLIL::Cell::check()
2579 {
2580 #ifndef NDEBUG
2581 InternalCellChecker checker(NULL, this);
2582 checker.check();
2583 #endif
2584 }
2585
2586 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2587 {
2588 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2589 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2590 return;
2591
2592 if (type == ID($mux) || type == ID($pmux)) {
2593 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2594 if (type == ID($pmux))
2595 parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
2596 check();
2597 return;
2598 }
2599
2600 if (type == ID($lut) || type == ID($sop)) {
2601 parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
2602 return;
2603 }
2604
2605 if (type == ID($fa)) {
2606 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2607 return;
2608 }
2609
2610 if (type == ID($lcu)) {
2611 parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
2612 return;
2613 }
2614
2615 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2616
2617 if (connections_.count(ID::A)) {
2618 if (signedness_ab) {
2619 if (set_a_signed)
2620 parameters[ID(A_SIGNED)] = true;
2621 else if (parameters.count(ID(A_SIGNED)) == 0)
2622 parameters[ID(A_SIGNED)] = false;
2623 }
2624 parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
2625 }
2626
2627 if (connections_.count(ID::B)) {
2628 if (signedness_ab) {
2629 if (set_b_signed)
2630 parameters[ID(B_SIGNED)] = true;
2631 else if (parameters.count(ID(B_SIGNED)) == 0)
2632 parameters[ID(B_SIGNED)] = false;
2633 }
2634 parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
2635 }
2636
2637 if (connections_.count(ID::Y))
2638 parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
2639
2640 if (connections_.count(ID(Q)))
2641 parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
2642
2643 check();
2644 }
2645
2646 RTLIL::SigChunk::SigChunk()
2647 {
2648 wire = NULL;
2649 width = 0;
2650 offset = 0;
2651 }
2652
2653 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2654 {
2655 wire = NULL;
2656 data = value.bits;
2657 width = GetSize(data);
2658 offset = 0;
2659 }
2660
2661 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2662 {
2663 log_assert(wire != nullptr);
2664 this->wire = wire;
2665 this->width = wire->width;
2666 this->offset = 0;
2667 }
2668
2669 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2670 {
2671 log_assert(wire != nullptr);
2672 this->wire = wire;
2673 this->width = width;
2674 this->offset = offset;
2675 }
2676
2677 RTLIL::SigChunk::SigChunk(const std::string &str)
2678 {
2679 wire = NULL;
2680 data = RTLIL::Const(str).bits;
2681 width = GetSize(data);
2682 offset = 0;
2683 }
2684
2685 RTLIL::SigChunk::SigChunk(int val, int width)
2686 {
2687 wire = NULL;
2688 data = RTLIL::Const(val, width).bits;
2689 this->width = GetSize(data);
2690 offset = 0;
2691 }
2692
2693 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2694 {
2695 wire = NULL;
2696 data = RTLIL::Const(bit, width).bits;
2697 this->width = GetSize(data);
2698 offset = 0;
2699 }
2700
2701 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2702 {
2703 wire = bit.wire;
2704 offset = 0;
2705 if (wire == NULL)
2706 data = RTLIL::Const(bit.data).bits;
2707 else
2708 offset = bit.offset;
2709 width = 1;
2710 }
2711
2712 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2713 {
2714 *this = sigchunk;
2715 }
2716
2717 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2718 {
2719 RTLIL::SigChunk ret;
2720 if (wire) {
2721 ret.wire = wire;
2722 ret.offset = this->offset + offset;
2723 ret.width = length;
2724 } else {
2725 for (int i = 0; i < length; i++)
2726 ret.data.push_back(data[offset+i]);
2727 ret.width = length;
2728 }
2729 return ret;
2730 }
2731
2732 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2733 {
2734 if (wire && other.wire)
2735 if (wire->name != other.wire->name)
2736 return wire->name < other.wire->name;
2737
2738 if (wire != other.wire)
2739 return wire < other.wire;
2740
2741 if (offset != other.offset)
2742 return offset < other.offset;
2743
2744 if (width != other.width)
2745 return width < other.width;
2746
2747 return data < other.data;
2748 }
2749
2750 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2751 {
2752 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2753 }
2754
2755 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2756 {
2757 if (*this == other)
2758 return false;
2759 return true;
2760 }
2761
2762 RTLIL::SigSpec::SigSpec()
2763 {
2764 width_ = 0;
2765 hash_ = 0;
2766 }
2767
2768 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2769 {
2770 *this = other;
2771 }
2772
2773 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2774 {
2775 cover("kernel.rtlil.sigspec.init.list");
2776
2777 width_ = 0;
2778 hash_ = 0;
2779
2780 log_assert(parts.size() > 0);
2781 auto ie = parts.begin();
2782 auto it = ie + parts.size() - 1;
2783 while (it >= ie)
2784 append(*it--);
2785 }
2786
2787 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2788 {
2789 cover("kernel.rtlil.sigspec.assign");
2790
2791 width_ = other.width_;
2792 hash_ = other.hash_;
2793 chunks_ = other.chunks_;
2794 bits_ = other.bits_;
2795 return *this;
2796 }
2797
2798 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2799 {
2800 cover("kernel.rtlil.sigspec.init.const");
2801
2802 chunks_.emplace_back(value);
2803 width_ = chunks_.back().width;
2804 hash_ = 0;
2805 check();
2806 }
2807
2808 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2809 {
2810 cover("kernel.rtlil.sigspec.init.chunk");
2811
2812 chunks_.emplace_back(chunk);
2813 width_ = chunks_.back().width;
2814 hash_ = 0;
2815 check();
2816 }
2817
2818 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2819 {
2820 cover("kernel.rtlil.sigspec.init.wire");
2821
2822 chunks_.emplace_back(wire);
2823 width_ = chunks_.back().width;
2824 hash_ = 0;
2825 check();
2826 }
2827
2828 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2829 {
2830 cover("kernel.rtlil.sigspec.init.wire_part");
2831
2832 chunks_.emplace_back(wire, offset, width);
2833 width_ = chunks_.back().width;
2834 hash_ = 0;
2835 check();
2836 }
2837
2838 RTLIL::SigSpec::SigSpec(const std::string &str)
2839 {
2840 cover("kernel.rtlil.sigspec.init.str");
2841
2842 chunks_.emplace_back(str);
2843 width_ = chunks_.back().width;
2844 hash_ = 0;
2845 check();
2846 }
2847
2848 RTLIL::SigSpec::SigSpec(int val, int width)
2849 {
2850 cover("kernel.rtlil.sigspec.init.int");
2851
2852 chunks_.emplace_back(val, width);
2853 width_ = width;
2854 hash_ = 0;
2855 check();
2856 }
2857
2858 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2859 {
2860 cover("kernel.rtlil.sigspec.init.state");
2861
2862 chunks_.emplace_back(bit, width);
2863 width_ = width;
2864 hash_ = 0;
2865 check();
2866 }
2867
2868 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2869 {
2870 cover("kernel.rtlil.sigspec.init.bit");
2871
2872 if (bit.wire == NULL)
2873 chunks_.emplace_back(bit.data, width);
2874 else
2875 for (int i = 0; i < width; i++)
2876 chunks_.push_back(bit);
2877 width_ = width;
2878 hash_ = 0;
2879 check();
2880 }
2881
2882 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2883 {
2884 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2885
2886 width_ = 0;
2887 hash_ = 0;
2888 for (const auto &c : chunks)
2889 append(c);
2890 check();
2891 }
2892
2893 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2894 {
2895 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2896
2897 width_ = 0;
2898 hash_ = 0;
2899 for (const auto &bit : bits)
2900 append(bit);
2901 check();
2902 }
2903
2904 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2905 {
2906 cover("kernel.rtlil.sigspec.init.pool_bits");
2907
2908 width_ = 0;
2909 hash_ = 0;
2910 for (const auto &bit : bits)
2911 append(bit);
2912 check();
2913 }
2914
2915 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2916 {
2917 cover("kernel.rtlil.sigspec.init.stdset_bits");
2918
2919 width_ = 0;
2920 hash_ = 0;
2921 for (const auto &bit : bits)
2922 append(bit);
2923 check();
2924 }
2925
2926 RTLIL::SigSpec::SigSpec(bool bit)
2927 {
2928 cover("kernel.rtlil.sigspec.init.bool");
2929
2930 width_ = 0;
2931 hash_ = 0;
2932 append(SigBit(bit));
2933 check();
2934 }
2935
2936 void RTLIL::SigSpec::pack() const
2937 {
2938 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2939
2940 if (that->bits_.empty())
2941 return;
2942
2943 cover("kernel.rtlil.sigspec.convert.pack");
2944 log_assert(that->chunks_.empty());
2945
2946 std::vector<RTLIL::SigBit> old_bits;
2947 old_bits.swap(that->bits_);
2948
2949 RTLIL::SigChunk *last = NULL;
2950 int last_end_offset = 0;
2951
2952 for (auto &bit : old_bits) {
2953 if (last && bit.wire == last->wire) {
2954 if (bit.wire == NULL) {
2955 last->data.push_back(bit.data);
2956 last->width++;
2957 continue;
2958 } else if (last_end_offset == bit.offset) {
2959 last_end_offset++;
2960 last->width++;
2961 continue;
2962 }
2963 }
2964 that->chunks_.push_back(bit);
2965 last = &that->chunks_.back();
2966 last_end_offset = bit.offset + 1;
2967 }
2968
2969 check();
2970 }
2971
2972 void RTLIL::SigSpec::unpack() const
2973 {
2974 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2975
2976 if (that->chunks_.empty())
2977 return;
2978
2979 cover("kernel.rtlil.sigspec.convert.unpack");
2980 log_assert(that->bits_.empty());
2981
2982 that->bits_.reserve(that->width_);
2983 for (auto &c : that->chunks_)
2984 for (int i = 0; i < c.width; i++)
2985 that->bits_.emplace_back(c, i);
2986
2987 that->chunks_.clear();
2988 that->hash_ = 0;
2989 }
2990
2991 void RTLIL::SigSpec::updhash() const
2992 {
2993 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2994
2995 if (that->hash_ != 0)
2996 return;
2997
2998 cover("kernel.rtlil.sigspec.hash");
2999 that->pack();
3000
3001 that->hash_ = mkhash_init;
3002 for (auto &c : that->chunks_)
3003 if (c.wire == NULL) {
3004 for (auto &v : c.data)
3005 that->hash_ = mkhash(that->hash_, v);
3006 } else {
3007 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3008 that->hash_ = mkhash(that->hash_, c.offset);
3009 that->hash_ = mkhash(that->hash_, c.width);
3010 }
3011
3012 if (that->hash_ == 0)
3013 that->hash_ = 1;
3014 }
3015
3016 void RTLIL::SigSpec::sort()
3017 {
3018 unpack();
3019 cover("kernel.rtlil.sigspec.sort");
3020 std::sort(bits_.begin(), bits_.end());
3021 }
3022
3023 void RTLIL::SigSpec::sort_and_unify()
3024 {
3025 unpack();
3026 cover("kernel.rtlil.sigspec.sort_and_unify");
3027
3028 // A copy of the bits vector is used to prevent duplicating the logic from
3029 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3030 // that isn't showing up as significant in profiles.
3031 std::vector<SigBit> unique_bits = bits_;
3032 std::sort(unique_bits.begin(), unique_bits.end());
3033 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3034 unique_bits.erase(last, unique_bits.end());
3035
3036 *this = unique_bits;
3037 }
3038
3039 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3040 {
3041 replace(pattern, with, this);
3042 }
3043
3044 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3045 {
3046 log_assert(other != NULL);
3047 log_assert(width_ == other->width_);
3048 log_assert(pattern.width_ == with.width_);
3049
3050 pattern.unpack();
3051 with.unpack();
3052 unpack();
3053 other->unpack();
3054
3055 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3056 if (pattern.bits_[i].wire != NULL) {
3057 for (int j = 0; j < GetSize(bits_); j++) {
3058 if (bits_[j] == pattern.bits_[i]) {
3059 other->bits_[j] = with.bits_[i];
3060 }
3061 }
3062 }
3063 }
3064
3065 other->check();
3066 }
3067
3068 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3069 {
3070 replace(rules, this);
3071 }
3072
3073 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3074 {
3075 cover("kernel.rtlil.sigspec.replace_dict");
3076
3077 log_assert(other != NULL);
3078 log_assert(width_ == other->width_);
3079
3080 if (rules.empty()) return;
3081 unpack();
3082 other->unpack();
3083
3084 for (int i = 0; i < GetSize(bits_); i++) {
3085 auto it = rules.find(bits_[i]);
3086 if (it != rules.end())
3087 other->bits_[i] = it->second;
3088 }
3089
3090 other->check();
3091 }
3092
3093 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3094 {
3095 replace(rules, this);
3096 }
3097
3098 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3099 {
3100 cover("kernel.rtlil.sigspec.replace_map");
3101
3102 log_assert(other != NULL);
3103 log_assert(width_ == other->width_);
3104
3105 if (rules.empty()) return;
3106 unpack();
3107 other->unpack();
3108
3109 for (int i = 0; i < GetSize(bits_); i++) {
3110 auto it = rules.find(bits_[i]);
3111 if (it != rules.end())
3112 other->bits_[i] = it->second;
3113 }
3114
3115 other->check();
3116 }
3117
3118 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3119 {
3120 remove2(pattern, NULL);
3121 }
3122
3123 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3124 {
3125 RTLIL::SigSpec tmp = *this;
3126 tmp.remove2(pattern, other);
3127 }
3128
3129 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3130 {
3131 if (other)
3132 cover("kernel.rtlil.sigspec.remove_other");
3133 else
3134 cover("kernel.rtlil.sigspec.remove");
3135
3136 unpack();
3137 if (other != NULL) {
3138 log_assert(width_ == other->width_);
3139 other->unpack();
3140 }
3141
3142 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3143 {
3144 if (bits_[i].wire == NULL) continue;
3145
3146 for (auto &pattern_chunk : pattern.chunks())
3147 if (bits_[i].wire == pattern_chunk.wire &&
3148 bits_[i].offset >= pattern_chunk.offset &&
3149 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3150 bits_.erase(bits_.begin() + i);
3151 width_--;
3152 if (other != NULL) {
3153 other->bits_.erase(other->bits_.begin() + i);
3154 other->width_--;
3155 }
3156 break;
3157 }
3158 }
3159
3160 check();
3161 }
3162
3163 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3164 {
3165 remove2(pattern, NULL);
3166 }
3167
3168 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3169 {
3170 RTLIL::SigSpec tmp = *this;
3171 tmp.remove2(pattern, other);
3172 }
3173
3174 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3175 {
3176 if (other)
3177 cover("kernel.rtlil.sigspec.remove_other");
3178 else
3179 cover("kernel.rtlil.sigspec.remove");
3180
3181 unpack();
3182
3183 if (other != NULL) {
3184 log_assert(width_ == other->width_);
3185 other->unpack();
3186 }
3187
3188 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3189 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3190 bits_.erase(bits_.begin() + i);
3191 width_--;
3192 if (other != NULL) {
3193 other->bits_.erase(other->bits_.begin() + i);
3194 other->width_--;
3195 }
3196 }
3197 }
3198
3199 check();
3200 }
3201
3202 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3203 {
3204 if (other)
3205 cover("kernel.rtlil.sigspec.remove_other");
3206 else
3207 cover("kernel.rtlil.sigspec.remove");
3208
3209 unpack();
3210
3211 if (other != NULL) {
3212 log_assert(width_ == other->width_);
3213 other->unpack();
3214 }
3215
3216 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3217 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3218 bits_.erase(bits_.begin() + i);
3219 width_--;
3220 if (other != NULL) {
3221 other->bits_.erase(other->bits_.begin() + i);
3222 other->width_--;
3223 }
3224 }
3225 }
3226
3227 check();
3228 }
3229
3230 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3231 {
3232 if (other)
3233 cover("kernel.rtlil.sigspec.extract_other");
3234 else
3235 cover("kernel.rtlil.sigspec.extract");
3236
3237 log_assert(other == NULL || width_ == other->width_);
3238
3239 RTLIL::SigSpec ret;
3240 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3241
3242 for (auto& pattern_chunk : pattern.chunks()) {
3243 if (other) {
3244 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3245 for (int i = 0; i < width_; i++)
3246 if (bits_match[i].wire &&
3247 bits_match[i].wire == pattern_chunk.wire &&
3248 bits_match[i].offset >= pattern_chunk.offset &&
3249 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3250 ret.append(bits_other[i]);
3251 } else {
3252 for (int i = 0; i < width_; i++)
3253 if (bits_match[i].wire &&
3254 bits_match[i].wire == pattern_chunk.wire &&
3255 bits_match[i].offset >= pattern_chunk.offset &&
3256 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3257 ret.append(bits_match[i]);
3258 }
3259 }
3260
3261 ret.check();
3262 return ret;
3263 }
3264
3265 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3266 {
3267 if (other)
3268 cover("kernel.rtlil.sigspec.extract_other");
3269 else
3270 cover("kernel.rtlil.sigspec.extract");
3271
3272 log_assert(other == NULL || width_ == other->width_);
3273
3274 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3275 RTLIL::SigSpec ret;
3276
3277 if (other) {
3278 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3279 for (int i = 0; i < width_; i++)
3280 if (bits_match[i].wire && pattern.count(bits_match[i]))
3281 ret.append(bits_other[i]);
3282 } else {
3283 for (int i = 0; i < width_; i++)
3284 if (bits_match[i].wire && pattern.count(bits_match[i]))
3285 ret.append(bits_match[i]);
3286 }
3287
3288 ret.check();
3289 return ret;
3290 }
3291
3292 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3293 {
3294 cover("kernel.rtlil.sigspec.replace_pos");
3295
3296 unpack();
3297 with.unpack();
3298
3299 log_assert(offset >= 0);
3300 log_assert(with.width_ >= 0);
3301 log_assert(offset+with.width_ <= width_);
3302
3303 for (int i = 0; i < with.width_; i++)
3304 bits_.at(offset + i) = with.bits_.at(i);
3305
3306 check();
3307 }
3308
3309 void RTLIL::SigSpec::remove_const()
3310 {
3311 if (packed())
3312 {
3313 cover("kernel.rtlil.sigspec.remove_const.packed");
3314
3315 std::vector<RTLIL::SigChunk> new_chunks;
3316 new_chunks.reserve(GetSize(chunks_));
3317
3318 width_ = 0;
3319 for (auto &chunk : chunks_)
3320 if (chunk.wire != NULL) {
3321 new_chunks.push_back(chunk);
3322 width_ += chunk.width;
3323 }
3324
3325 chunks_.swap(new_chunks);
3326 }
3327 else
3328 {
3329 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3330
3331 std::vector<RTLIL::SigBit> new_bits;
3332 new_bits.reserve(width_);
3333
3334 for (auto &bit : bits_)
3335 if (bit.wire != NULL)
3336 new_bits.push_back(bit);
3337
3338 bits_.swap(new_bits);
3339 width_ = bits_.size();
3340 }
3341
3342 check();
3343 }
3344
3345 void RTLIL::SigSpec::remove(int offset, int length)
3346 {
3347 cover("kernel.rtlil.sigspec.remove_pos");
3348
3349 unpack();
3350
3351 log_assert(offset >= 0);
3352 log_assert(length >= 0);
3353 log_assert(offset + length <= width_);
3354
3355 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3356 width_ = bits_.size();
3357
3358 check();
3359 }
3360
3361 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3362 {
3363 unpack();
3364 cover("kernel.rtlil.sigspec.extract_pos");
3365 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3366 }
3367
3368 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3369 {
3370 if (signal.width_ == 0)
3371 return;
3372
3373 if (width_ == 0) {
3374 *this = signal;
3375 return;
3376 }
3377
3378 cover("kernel.rtlil.sigspec.append");
3379
3380 if (packed() != signal.packed()) {
3381 pack();
3382 signal.pack();
3383 }
3384
3385 if (packed())
3386 for (auto &other_c : signal.chunks_)
3387 {
3388 auto &my_last_c = chunks_.back();
3389 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3390 auto &this_data = my_last_c.data;
3391 auto &other_data = other_c.data;
3392 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3393 my_last_c.width += other_c.width;
3394 } else
3395 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3396 my_last_c.width += other_c.width;
3397 } else
3398 chunks_.push_back(other_c);
3399 }
3400 else
3401 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3402
3403 width_ += signal.width_;
3404 check();
3405 }
3406
3407 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3408 {
3409 if (packed())
3410 {
3411 cover("kernel.rtlil.sigspec.append_bit.packed");
3412
3413 if (chunks_.size() == 0)
3414 chunks_.push_back(bit);
3415 else
3416 if (bit.wire == NULL)
3417 if (chunks_.back().wire == NULL) {
3418 chunks_.back().data.push_back(bit.data);
3419 chunks_.back().width++;
3420 } else
3421 chunks_.push_back(bit);
3422 else
3423 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3424 chunks_.back().width++;
3425 else
3426 chunks_.push_back(bit);
3427 }
3428 else
3429 {
3430 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3431 bits_.push_back(bit);
3432 }
3433
3434 width_++;
3435 check();
3436 }
3437
3438 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3439 {
3440 cover("kernel.rtlil.sigspec.extend_u0");
3441
3442 pack();
3443
3444 if (width_ > width)
3445 remove(width, width_ - width);
3446
3447 if (width_ < width) {
3448 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3449 if (!is_signed)
3450 padding = RTLIL::State::S0;
3451 while (width_ < width)
3452 append(padding);
3453 }
3454
3455 }
3456
3457 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3458 {
3459 cover("kernel.rtlil.sigspec.repeat");
3460
3461 RTLIL::SigSpec sig;
3462 for (int i = 0; i < num; i++)
3463 sig.append(*this);
3464 return sig;
3465 }
3466
3467 #ifndef NDEBUG
3468 void RTLIL::SigSpec::check() const
3469 {
3470 if (width_ > 64)
3471 {
3472 cover("kernel.rtlil.sigspec.check.skip");
3473 }
3474 else if (packed())
3475 {
3476 cover("kernel.rtlil.sigspec.check.packed");
3477
3478 int w = 0;
3479 for (size_t i = 0; i < chunks_.size(); i++) {
3480 const RTLIL::SigChunk &chunk = chunks_[i];
3481 if (chunk.wire == NULL) {
3482 if (i > 0)
3483 log_assert(chunks_[i-1].wire != NULL);
3484 log_assert(chunk.offset == 0);
3485 log_assert(chunk.data.size() == (size_t)chunk.width);
3486 } else {
3487 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3488 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3489 log_assert(chunk.offset >= 0);
3490 log_assert(chunk.width >= 0);
3491 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3492 log_assert(chunk.data.size() == 0);
3493 }
3494 w += chunk.width;
3495 }
3496 log_assert(w == width_);
3497 log_assert(bits_.empty());
3498 }
3499 else
3500 {
3501 cover("kernel.rtlil.sigspec.check.unpacked");
3502
3503 log_assert(width_ == GetSize(bits_));
3504 log_assert(chunks_.empty());
3505 }
3506 }
3507 #endif
3508
3509 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3510 {
3511 cover("kernel.rtlil.sigspec.comp_lt");
3512
3513 if (this == &other)
3514 return false;
3515
3516 if (width_ != other.width_)
3517 return width_ < other.width_;
3518
3519 pack();
3520 other.pack();
3521
3522 if (chunks_.size() != other.chunks_.size())
3523 return chunks_.size() < other.chunks_.size();
3524
3525 updhash();
3526 other.updhash();
3527
3528 if (hash_ != other.hash_)
3529 return hash_ < other.hash_;
3530
3531 for (size_t i = 0; i < chunks_.size(); i++)
3532 if (chunks_[i] != other.chunks_[i]) {
3533 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3534 return chunks_[i] < other.chunks_[i];
3535 }
3536
3537 cover("kernel.rtlil.sigspec.comp_lt.equal");
3538 return false;
3539 }
3540
3541 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3542 {
3543 cover("kernel.rtlil.sigspec.comp_eq");
3544
3545 if (this == &other)
3546 return true;
3547
3548 if (width_ != other.width_)
3549 return false;
3550
3551 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3552 // since the RHS will contain one SigChunk of width 0 causing
3553 // the size check below to fail
3554 if (width_ == 0)
3555 return true;
3556
3557 pack();
3558 other.pack();
3559
3560 if (chunks_.size() != other.chunks_.size())
3561 return false;
3562
3563 updhash();
3564 other.updhash();
3565
3566 if (hash_ != other.hash_)
3567 return false;
3568
3569 for (size_t i = 0; i < chunks_.size(); i++)
3570 if (chunks_[i] != other.chunks_[i]) {
3571 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3572 return false;
3573 }
3574
3575 cover("kernel.rtlil.sigspec.comp_eq.equal");
3576 return true;
3577 }
3578
3579 bool RTLIL::SigSpec::is_wire() const
3580 {
3581 cover("kernel.rtlil.sigspec.is_wire");
3582
3583 pack();
3584 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3585 }
3586
3587 bool RTLIL::SigSpec::is_chunk() const
3588 {
3589 cover("kernel.rtlil.sigspec.is_chunk");
3590
3591 pack();
3592 return GetSize(chunks_) == 1;
3593 }
3594
3595 bool RTLIL::SigSpec::is_fully_const() const
3596 {
3597 cover("kernel.rtlil.sigspec.is_fully_const");
3598
3599 pack();
3600 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3601 if (it->width > 0 && it->wire != NULL)
3602 return false;
3603 return true;
3604 }
3605
3606 bool RTLIL::SigSpec::is_fully_zero() const
3607 {
3608 cover("kernel.rtlil.sigspec.is_fully_zero");
3609
3610 pack();
3611 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3612 if (it->width > 0 && it->wire != NULL)
3613 return false;
3614 for (size_t i = 0; i < it->data.size(); i++)
3615 if (it->data[i] != RTLIL::State::S0)
3616 return false;
3617 }
3618 return true;
3619 }
3620
3621 bool RTLIL::SigSpec::is_fully_ones() const
3622 {
3623 cover("kernel.rtlil.sigspec.is_fully_ones");
3624
3625 pack();
3626 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3627 if (it->width > 0 && it->wire != NULL)
3628 return false;
3629 for (size_t i = 0; i < it->data.size(); i++)
3630 if (it->data[i] != RTLIL::State::S1)
3631 return false;
3632 }
3633 return true;
3634 }
3635
3636 bool RTLIL::SigSpec::is_fully_def() const
3637 {
3638 cover("kernel.rtlil.sigspec.is_fully_def");
3639
3640 pack();
3641 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3642 if (it->width > 0 && it->wire != NULL)
3643 return false;
3644 for (size_t i = 0; i < it->data.size(); i++)
3645 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3646 return false;
3647 }
3648 return true;
3649 }
3650
3651 bool RTLIL::SigSpec::is_fully_undef() const
3652 {
3653 cover("kernel.rtlil.sigspec.is_fully_undef");
3654
3655 pack();
3656 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3657 if (it->width > 0 && it->wire != NULL)
3658 return false;
3659 for (size_t i = 0; i < it->data.size(); i++)
3660 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3661 return false;
3662 }
3663 return true;
3664 }
3665
3666 bool RTLIL::SigSpec::has_const() const
3667 {
3668 cover("kernel.rtlil.sigspec.has_const");
3669
3670 pack();
3671 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3672 if (it->width > 0 && it->wire == NULL)
3673 return true;
3674 return false;
3675 }
3676
3677 bool RTLIL::SigSpec::has_marked_bits() const
3678 {
3679 cover("kernel.rtlil.sigspec.has_marked_bits");
3680
3681 pack();
3682 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3683 if (it->width > 0 && it->wire == NULL) {
3684 for (size_t i = 0; i < it->data.size(); i++)
3685 if (it->data[i] == RTLIL::State::Sm)
3686 return true;
3687 }
3688 return false;
3689 }
3690
3691 bool RTLIL::SigSpec::as_bool() const
3692 {
3693 cover("kernel.rtlil.sigspec.as_bool");
3694
3695 pack();
3696 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3697 if (width_)
3698 return RTLIL::Const(chunks_[0].data).as_bool();
3699 return false;
3700 }
3701
3702 int RTLIL::SigSpec::as_int(bool is_signed) const
3703 {
3704 cover("kernel.rtlil.sigspec.as_int");
3705
3706 pack();
3707 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3708 if (width_)
3709 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3710 return 0;
3711 }
3712
3713 std::string RTLIL::SigSpec::as_string() const
3714 {
3715 cover("kernel.rtlil.sigspec.as_string");
3716
3717 pack();
3718 std::string str;
3719 str.reserve(size());
3720 for (size_t i = chunks_.size(); i > 0; i--) {
3721 const RTLIL::SigChunk &chunk = chunks_[i-1];
3722 if (chunk.wire != NULL)
3723 str.append(chunk.width, '?');
3724 else
3725 str += RTLIL::Const(chunk.data).as_string();
3726 }
3727 return str;
3728 }
3729
3730 RTLIL::Const RTLIL::SigSpec::as_const() const
3731 {
3732 cover("kernel.rtlil.sigspec.as_const");
3733
3734 pack();
3735 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3736 if (width_)
3737 return chunks_[0].data;
3738 return RTLIL::Const();
3739 }
3740
3741 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3742 {
3743 cover("kernel.rtlil.sigspec.as_wire");
3744
3745 pack();
3746 log_assert(is_wire());
3747 return chunks_[0].wire;
3748 }
3749
3750 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3751 {
3752 cover("kernel.rtlil.sigspec.as_chunk");
3753
3754 pack();
3755 log_assert(is_chunk());
3756 return chunks_[0];
3757 }
3758
3759 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3760 {
3761 cover("kernel.rtlil.sigspec.as_bit");
3762
3763 log_assert(width_ == 1);
3764 if (packed())
3765 return RTLIL::SigBit(*chunks_.begin());
3766 else
3767 return bits_[0];
3768 }
3769
3770 bool RTLIL::SigSpec::match(const char* pattern) const
3771 {
3772 cover("kernel.rtlil.sigspec.match");
3773
3774 unpack();
3775 log_assert(int(strlen(pattern)) == GetSize(bits_));
3776
3777 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3778 if (*pattern == ' ')
3779 continue;
3780 if (*pattern == '*') {
3781 if (*it != State::Sz && *it != State::Sx)
3782 return false;
3783 continue;
3784 }
3785 if (*pattern == '0') {
3786 if (*it != State::S0)
3787 return false;
3788 } else
3789 if (*pattern == '1') {
3790 if (*it != State::S1)
3791 return false;
3792 } else
3793 log_abort();
3794 }
3795
3796 return true;
3797 }
3798
3799 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3800 {
3801 cover("kernel.rtlil.sigspec.to_sigbit_set");
3802
3803 pack();
3804 std::set<RTLIL::SigBit> sigbits;
3805 for (auto &c : chunks_)
3806 for (int i = 0; i < c.width; i++)
3807 sigbits.insert(RTLIL::SigBit(c, i));
3808 return sigbits;
3809 }
3810
3811 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3812 {
3813 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3814
3815 pack();
3816 pool<RTLIL::SigBit> sigbits;
3817 sigbits.reserve(size());
3818 for (auto &c : chunks_)
3819 for (int i = 0; i < c.width; i++)
3820 sigbits.insert(RTLIL::SigBit(c, i));
3821 return sigbits;
3822 }
3823
3824 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3825 {
3826 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3827
3828 unpack();
3829 return bits_;
3830 }
3831
3832 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3833 {
3834 cover("kernel.rtlil.sigspec.to_sigbit_map");
3835
3836 unpack();
3837 other.unpack();
3838
3839 log_assert(width_ == other.width_);
3840
3841 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3842 for (int i = 0; i < width_; i++)
3843 new_map[bits_[i]] = other.bits_[i];
3844
3845 return new_map;
3846 }
3847
3848 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3849 {
3850 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3851
3852 unpack();
3853 other.unpack();
3854
3855 log_assert(width_ == other.width_);
3856
3857 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3858 new_map.reserve(size());
3859 for (int i = 0; i < width_; i++)
3860 new_map[bits_[i]] = other.bits_[i];
3861
3862 return new_map;
3863 }
3864
3865 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3866 {
3867 size_t start = 0, end = 0;
3868 while ((end = text.find(sep, start)) != std::string::npos) {
3869 tokens.push_back(text.substr(start, end - start));
3870 start = end + 1;
3871 }
3872 tokens.push_back(text.substr(start));
3873 }
3874
3875 static int sigspec_parse_get_dummy_line_num()
3876 {
3877 return 0;
3878 }
3879
3880 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3881 {
3882 cover("kernel.rtlil.sigspec.parse");
3883
3884 AST::current_filename = "input";
3885
3886 std::vector<std::string> tokens;
3887 sigspec_parse_split(tokens, str, ',');
3888
3889 sig = RTLIL::SigSpec();
3890 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3891 {
3892 std::string netname = tokens[tokidx];
3893 std::string indices;
3894
3895 if (netname.size() == 0)
3896 continue;
3897
3898 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3899 cover("kernel.rtlil.sigspec.parse.const");
3900 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3901 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3902 if (ast == NULL)
3903 return false;
3904 sig.append(RTLIL::Const(ast->bits));
3905 delete ast;
3906 continue;
3907 }
3908
3909 if (module == NULL)
3910 return false;
3911
3912 cover("kernel.rtlil.sigspec.parse.net");
3913
3914 if (netname[0] != '$' && netname[0] != '\\')
3915 netname = "\\" + netname;
3916
3917 if (module->wires_.count(netname) == 0) {
3918 size_t indices_pos = netname.size()-1;
3919 if (indices_pos > 2 && netname[indices_pos] == ']')
3920 {
3921 indices_pos--;
3922 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3923 if (indices_pos > 0 && netname[indices_pos] == ':') {
3924 indices_pos--;
3925 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3926 }
3927 if (indices_pos > 0 && netname[indices_pos] == '[') {
3928 indices = netname.substr(indices_pos);
3929 netname = netname.substr(0, indices_pos);
3930 }
3931 }
3932 }
3933
3934 if (module->wires_.count(netname) == 0)
3935 return false;
3936
3937 RTLIL::Wire *wire = module->wires_.at(netname);
3938 if (!indices.empty()) {
3939 std::vector<std::string> index_tokens;
3940 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3941 if (index_tokens.size() == 1) {
3942 cover("kernel.rtlil.sigspec.parse.bit_sel");
3943 int a = atoi(index_tokens.at(0).c_str());
3944 if (a < 0 || a >= wire->width)
3945 return false;
3946 sig.append(RTLIL::SigSpec(wire, a));
3947 } else {
3948 cover("kernel.rtlil.sigspec.parse.part_sel");
3949 int a = atoi(index_tokens.at(0).c_str());
3950 int b = atoi(index_tokens.at(1).c_str());
3951 if (a > b) {
3952 int tmp = a;
3953 a = b, b = tmp;
3954 }
3955 if (a < 0 || a >= wire->width)
3956 return false;
3957 if (b < 0 || b >= wire->width)
3958 return false;
3959 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3960 }
3961 } else
3962 sig.append(wire);
3963 }
3964
3965 return true;
3966 }
3967
3968 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3969 {
3970 if (str.empty() || str[0] != '@')
3971 return parse(sig, module, str);
3972
3973 cover("kernel.rtlil.sigspec.parse.sel");
3974
3975 str = RTLIL::escape_id(str.substr(1));
3976 if (design->selection_vars.count(str) == 0)
3977 return false;
3978
3979 sig = RTLIL::SigSpec();
3980 RTLIL::Selection &sel = design->selection_vars.at(str);
3981 for (auto &it : module->wires_)
3982 if (sel.selected_member(module->name, it.first))
3983 sig.append(it.second);
3984
3985 return true;
3986 }
3987
3988 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3989 {
3990 if (str == "0") {
3991 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3992 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3993 return true;
3994 }
3995
3996 if (str == "~0") {
3997 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3998 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3999 return true;
4000 }
4001
4002 if (lhs.chunks_.size() == 1) {
4003 char *p = (char*)str.c_str(), *endptr;
4004 long int val = strtol(p, &endptr, 10);
4005 if (endptr && endptr != p && *endptr == 0) {
4006 sig = RTLIL::SigSpec(val, lhs.width_);
4007 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4008 return true;
4009 }
4010 }
4011
4012 return parse(sig, module, str);
4013 }
4014
4015 RTLIL::CaseRule::~CaseRule()
4016 {
4017 for (auto it = switches.begin(); it != switches.end(); it++)
4018 delete *it;
4019 }
4020
4021 bool RTLIL::CaseRule::empty() const
4022 {
4023 return actions.empty() && switches.empty();
4024 }
4025
4026 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4027 {
4028 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4029 new_caserule->compare = compare;
4030 new_caserule->actions = actions;
4031 for (auto &it : switches)
4032 new_caserule->switches.push_back(it->clone());
4033 return new_caserule;
4034 }
4035
4036 RTLIL::SwitchRule::~SwitchRule()
4037 {
4038 for (auto it = cases.begin(); it != cases.end(); it++)
4039 delete *it;
4040 }
4041
4042 bool RTLIL::SwitchRule::empty() const
4043 {
4044 return cases.empty();
4045 }
4046
4047 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4048 {
4049 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4050 new_switchrule->signal = signal;
4051 new_switchrule->attributes = attributes;
4052 for (auto &it : cases)
4053 new_switchrule->cases.push_back(it->clone());
4054 return new_switchrule;
4055
4056 }
4057
4058 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4059 {
4060 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4061 new_syncrule->type = type;
4062 new_syncrule->signal = signal;
4063 new_syncrule->actions = actions;
4064 return new_syncrule;
4065 }
4066
4067 RTLIL::Process::~Process()
4068 {
4069 for (auto it = syncs.begin(); it != syncs.end(); it++)
4070 delete *it;
4071 }
4072
4073 RTLIL::Process *RTLIL::Process::clone() const
4074 {
4075 RTLIL::Process *new_proc = new RTLIL::Process;
4076
4077 new_proc->name = name;
4078 new_proc->attributes = attributes;
4079
4080 RTLIL::CaseRule *rc_ptr = root_case.clone();
4081 new_proc->root_case = *rc_ptr;
4082 rc_ptr->switches.clear();
4083 delete rc_ptr;
4084
4085 for (auto &it : syncs)
4086 new_proc->syncs.push_back(it->clone());
4087
4088 return new_proc;
4089 }
4090
4091 #ifdef WITH_PYTHON
4092 RTLIL::Memory::~Memory()
4093 {
4094 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4095 }
4096 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4097 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4098 {
4099 return &all_memorys;
4100 }
4101 #endif
4102 YOSYS_NAMESPACE_END