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Added some missing "const" in rtlil.h
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <assert.h>
27 #include <string.h>
28 #include <algorithm>
29
30 int RTLIL::autoidx = 1;
31
32 RTLIL::Const::Const()
33 {
34 flags = RTLIL::CONST_FLAG_NONE;
35 }
36
37 RTLIL::Const::Const(std::string str)
38 {
39 flags = RTLIL::CONST_FLAG_STRING;
40 for (int i = str.size()-1; i >= 0; i--) {
41 unsigned char ch = str[i];
42 for (int j = 0; j < 8; j++) {
43 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
44 ch = ch >> 1;
45 }
46 }
47 }
48
49 RTLIL::Const::Const(int val, int width)
50 {
51 flags = RTLIL::CONST_FLAG_NONE;
52 for (int i = 0; i < width; i++) {
53 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
54 val = val >> 1;
55 }
56 }
57
58 RTLIL::Const::Const(RTLIL::State bit, int width)
59 {
60 flags = RTLIL::CONST_FLAG_NONE;
61 for (int i = 0; i < width; i++)
62 bits.push_back(bit);
63 }
64
65 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
66 {
67 if (bits.size() != other.bits.size())
68 return bits.size() < other.bits.size();
69 for (size_t i = 0; i < bits.size(); i++)
70 if (bits[i] != other.bits[i])
71 return bits[i] < other.bits[i];
72 return false;
73 }
74
75 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
76 {
77 return bits == other.bits;
78 }
79
80 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
81 {
82 return bits != other.bits;
83 }
84
85 bool RTLIL::Const::as_bool() const
86 {
87 for (size_t i = 0; i < bits.size(); i++)
88 if (bits[i] == RTLIL::S1)
89 return true;
90 return false;
91 }
92
93 int RTLIL::Const::as_int() const
94 {
95 int ret = 0;
96 for (size_t i = 0; i < bits.size() && i < 32; i++)
97 if (bits[i] == RTLIL::S1)
98 ret |= 1 << i;
99 return ret;
100 }
101
102 std::string RTLIL::Const::as_string() const
103 {
104 std::string ret;
105 for (size_t i = bits.size(); i > 0; i--)
106 switch (bits[i-1]) {
107 case S0: ret += "0"; break;
108 case S1: ret += "1"; break;
109 case Sx: ret += "x"; break;
110 case Sz: ret += "z"; break;
111 case Sa: ret += "-"; break;
112 case Sm: ret += "m"; break;
113 }
114 return ret;
115 }
116
117 std::string RTLIL::Const::decode_string() const
118 {
119 std::string string;
120 std::vector <char> string_chars;
121 for (int i = 0; i < int (bits.size()); i += 8) {
122 char ch = 0;
123 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
124 if (bits[i + j] == RTLIL::State::S1)
125 ch |= 1 << j;
126 if (ch != 0)
127 string_chars.push_back(ch);
128 }
129 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
130 string += string_chars[i];
131 return string;
132 }
133
134 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
135 {
136 if (full_selection)
137 return true;
138 if (selected_modules.count(mod_name) > 0)
139 return true;
140 if (selected_members.count(mod_name) > 0)
141 return true;
142 return false;
143 }
144
145 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
146 {
147 if (full_selection)
148 return true;
149 if (selected_modules.count(mod_name) > 0)
150 return true;
151 return false;
152 }
153
154 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
155 {
156 if (full_selection)
157 return true;
158 if (selected_modules.count(mod_name) > 0)
159 return true;
160 if (selected_members.count(mod_name) > 0)
161 if (selected_members.at(mod_name).count(memb_name) > 0)
162 return true;
163 return false;
164 }
165
166 void RTLIL::Selection::optimize(RTLIL::Design *design)
167 {
168 if (full_selection) {
169 selected_modules.clear();
170 selected_members.clear();
171 return;
172 }
173
174 std::vector<RTLIL::IdString> del_list, add_list;
175
176 del_list.clear();
177 for (auto mod_name : selected_modules) {
178 if (design->modules.count(mod_name) == 0)
179 del_list.push_back(mod_name);
180 selected_members.erase(mod_name);
181 }
182 for (auto mod_name : del_list)
183 selected_modules.erase(mod_name);
184
185 del_list.clear();
186 for (auto &it : selected_members)
187 if (design->modules.count(it.first) == 0)
188 del_list.push_back(it.first);
189 for (auto mod_name : del_list)
190 selected_members.erase(mod_name);
191
192 for (auto &it : selected_members) {
193 del_list.clear();
194 for (auto memb_name : it.second)
195 if (design->modules[it.first]->count_id(memb_name) == 0)
196 del_list.push_back(memb_name);
197 for (auto memb_name : del_list)
198 it.second.erase(memb_name);
199 }
200
201 del_list.clear();
202 add_list.clear();
203 for (auto &it : selected_members)
204 if (it.second.size() == 0)
205 del_list.push_back(it.first);
206 else if (it.second.size() == design->modules[it.first]->wires.size() + design->modules[it.first]->memories.size() +
207 design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size())
208 add_list.push_back(it.first);
209 for (auto mod_name : del_list)
210 selected_members.erase(mod_name);
211 for (auto mod_name : add_list) {
212 selected_members.erase(mod_name);
213 selected_modules.insert(mod_name);
214 }
215
216 if (selected_modules.size() == design->modules.size()) {
217 full_selection = true;
218 selected_modules.clear();
219 selected_members.clear();
220 }
221 }
222
223 RTLIL::Design::~Design()
224 {
225 for (auto it = modules.begin(); it != modules.end(); it++)
226 delete it->second;
227 }
228
229 void RTLIL::Design::check()
230 {
231 #ifndef NDEBUG
232 for (auto &it : modules) {
233 assert(it.first == it.second->name);
234 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
235 it.second->check();
236 }
237 #endif
238 }
239
240 void RTLIL::Design::optimize()
241 {
242 for (auto &it : modules)
243 it.second->optimize();
244 for (auto &it : selection_stack)
245 it.optimize(this);
246 for (auto &it : selection_vars)
247 it.second.optimize(this);
248 }
249
250 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
251 {
252 if (!selected_active_module.empty() && mod_name != selected_active_module)
253 return false;
254 if (selection_stack.size() == 0)
255 return true;
256 return selection_stack.back().selected_module(mod_name);
257 }
258
259 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
260 {
261 if (!selected_active_module.empty() && mod_name != selected_active_module)
262 return false;
263 if (selection_stack.size() == 0)
264 return true;
265 return selection_stack.back().selected_whole_module(mod_name);
266 }
267
268 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
269 {
270 if (!selected_active_module.empty() && mod_name != selected_active_module)
271 return false;
272 if (selection_stack.size() == 0)
273 return true;
274 return selection_stack.back().selected_member(mod_name, memb_name);
275 }
276
277 RTLIL::Module::~Module()
278 {
279 for (auto it = wires.begin(); it != wires.end(); it++)
280 delete it->second;
281 for (auto it = memories.begin(); it != memories.end(); it++)
282 delete it->second;
283 for (auto it = cells.begin(); it != cells.end(); it++)
284 delete it->second;
285 for (auto it = processes.begin(); it != processes.end(); it++)
286 delete it->second;
287 }
288
289 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
290 {
291 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
292 }
293
294 size_t RTLIL::Module::count_id(RTLIL::IdString id)
295 {
296 return wires.count(id) + memories.count(id) + cells.count(id) + processes.count(id);
297 }
298
299 #ifndef NDEBUG
300 namespace {
301 struct InternalCellChecker
302 {
303 RTLIL::Module *module;
304 RTLIL::Cell *cell;
305 std::set<RTLIL::IdString> expected_params, expected_ports;
306
307 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
308
309 void error(int linenr)
310 {
311 char *ptr;
312 size_t size;
313
314 FILE *f = open_memstream(&ptr, &size);
315 ILANG_BACKEND::dump_cell(f, " ", cell);
316 fputc(0, f);
317 fclose(f);
318
319 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
320 module ? module->name.c_str() : "", module ? "." : "",
321 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
322 }
323
324 int param(const char *name)
325 {
326 if (cell->parameters.count(name) == 0)
327 error(__LINE__);
328 expected_params.insert(name);
329 return cell->parameters.at(name).as_int();
330 }
331
332 int param_bool(const char *name)
333 {
334 int v = param(name);
335 if (cell->parameters.at(name).bits.size() > 32)
336 error(__LINE__);
337 if (v != 0 && v != 1)
338 error(__LINE__);
339 return v;
340 }
341
342 void param_bits(const char *name, int width)
343 {
344 param(name);
345 if (int(cell->parameters.at(name).bits.size()) != width)
346 error(__LINE__);
347 }
348
349 void port(const char *name, int width)
350 {
351 if (cell->connections_.count(name) == 0)
352 error(__LINE__);
353 if (cell->connections_.at(name).size() != width)
354 error(__LINE__);
355 expected_ports.insert(name);
356 }
357
358 void check_expected(bool check_matched_sign = true)
359 {
360 for (auto &para : cell->parameters)
361 if (expected_params.count(para.first) == 0)
362 error(__LINE__);
363 for (auto &conn : cell->connections_)
364 if (expected_ports.count(conn.first) == 0)
365 error(__LINE__);
366
367 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
368 bool a_is_signed = param("\\A_SIGNED") != 0;
369 bool b_is_signed = param("\\B_SIGNED") != 0;
370 if (a_is_signed != b_is_signed)
371 error(__LINE__);
372 }
373 }
374
375 void check_gate(const char *ports)
376 {
377 if (cell->parameters.size() != 0)
378 error(__LINE__);
379
380 for (const char *p = ports; *p; p++) {
381 char portname[3] = { '\\', *p, 0 };
382 if (cell->connections_.count(portname) == 0)
383 error(__LINE__);
384 if (cell->connections_.at(portname).size() != 1)
385 error(__LINE__);
386 }
387
388 for (auto &conn : cell->connections_) {
389 if (conn.first.size() != 2 || conn.first.at(0) != '\\')
390 error(__LINE__);
391 if (strchr(ports, conn.first.at(1)) == NULL)
392 error(__LINE__);
393 }
394 }
395
396 void check()
397 {
398 if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
399 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:")
400 return;
401
402 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
403 param_bool("\\A_SIGNED");
404 port("\\A", param("\\A_WIDTH"));
405 port("\\Y", param("\\Y_WIDTH"));
406 check_expected();
407 return;
408 }
409
410 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
411 param_bool("\\A_SIGNED");
412 param_bool("\\B_SIGNED");
413 port("\\A", param("\\A_WIDTH"));
414 port("\\B", param("\\B_WIDTH"));
415 port("\\Y", param("\\Y_WIDTH"));
416 check_expected();
417 return;
418 }
419
420 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
421 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
422 param_bool("\\A_SIGNED");
423 port("\\A", param("\\A_WIDTH"));
424 port("\\Y", param("\\Y_WIDTH"));
425 check_expected();
426 return;
427 }
428
429 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
430 param_bool("\\A_SIGNED");
431 param_bool("\\B_SIGNED");
432 port("\\A", param("\\A_WIDTH"));
433 port("\\B", param("\\B_WIDTH"));
434 port("\\Y", param("\\Y_WIDTH"));
435 check_expected(false);
436 return;
437 }
438
439 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
440 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
441 param_bool("\\A_SIGNED");
442 param_bool("\\B_SIGNED");
443 port("\\A", param("\\A_WIDTH"));
444 port("\\B", param("\\B_WIDTH"));
445 port("\\Y", param("\\Y_WIDTH"));
446 check_expected();
447 return;
448 }
449
450 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
451 cell->type == "$mod" || cell->type == "$pow") {
452 param_bool("\\A_SIGNED");
453 param_bool("\\B_SIGNED");
454 port("\\A", param("\\A_WIDTH"));
455 port("\\B", param("\\B_WIDTH"));
456 port("\\Y", param("\\Y_WIDTH"));
457 check_expected(cell->type != "$pow");
458 return;
459 }
460
461 if (cell->type == "$logic_not") {
462 param_bool("\\A_SIGNED");
463 port("\\A", param("\\A_WIDTH"));
464 port("\\Y", param("\\Y_WIDTH"));
465 check_expected();
466 return;
467 }
468
469 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
470 param_bool("\\A_SIGNED");
471 param_bool("\\B_SIGNED");
472 port("\\A", param("\\A_WIDTH"));
473 port("\\B", param("\\B_WIDTH"));
474 port("\\Y", param("\\Y_WIDTH"));
475 check_expected(false);
476 return;
477 }
478
479 if (cell->type == "$slice") {
480 param("\\OFFSET");
481 port("\\A", param("\\A_WIDTH"));
482 port("\\Y", param("\\Y_WIDTH"));
483 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
484 error(__LINE__);
485 check_expected();
486 return;
487 }
488
489 if (cell->type == "$concat") {
490 port("\\A", param("\\A_WIDTH"));
491 port("\\B", param("\\B_WIDTH"));
492 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
493 check_expected();
494 return;
495 }
496
497 if (cell->type == "$mux") {
498 port("\\A", param("\\WIDTH"));
499 port("\\B", param("\\WIDTH"));
500 port("\\S", 1);
501 port("\\Y", param("\\WIDTH"));
502 check_expected();
503 return;
504 }
505
506 if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
507 port("\\A", param("\\WIDTH"));
508 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
509 port("\\S", param("\\S_WIDTH"));
510 port("\\Y", param("\\WIDTH"));
511 check_expected();
512 return;
513 }
514
515 if (cell->type == "$lut") {
516 param("\\LUT");
517 port("\\I", param("\\WIDTH"));
518 port("\\O", 1);
519 check_expected();
520 return;
521 }
522
523 if (cell->type == "$sr") {
524 param_bool("\\SET_POLARITY");
525 param_bool("\\CLR_POLARITY");
526 port("\\SET", param("\\WIDTH"));
527 port("\\CLR", param("\\WIDTH"));
528 port("\\Q", param("\\WIDTH"));
529 check_expected();
530 return;
531 }
532
533 if (cell->type == "$dff") {
534 param_bool("\\CLK_POLARITY");
535 port("\\CLK", 1);
536 port("\\D", param("\\WIDTH"));
537 port("\\Q", param("\\WIDTH"));
538 check_expected();
539 return;
540 }
541
542 if (cell->type == "$dffsr") {
543 param_bool("\\CLK_POLARITY");
544 param_bool("\\SET_POLARITY");
545 param_bool("\\CLR_POLARITY");
546 port("\\CLK", 1);
547 port("\\SET", param("\\WIDTH"));
548 port("\\CLR", param("\\WIDTH"));
549 port("\\D", param("\\WIDTH"));
550 port("\\Q", param("\\WIDTH"));
551 check_expected();
552 return;
553 }
554
555 if (cell->type == "$adff") {
556 param_bool("\\CLK_POLARITY");
557 param_bool("\\ARST_POLARITY");
558 param_bits("\\ARST_VALUE", param("\\WIDTH"));
559 port("\\CLK", 1);
560 port("\\ARST", 1);
561 port("\\D", param("\\WIDTH"));
562 port("\\Q", param("\\WIDTH"));
563 check_expected();
564 return;
565 }
566
567 if (cell->type == "$dlatch") {
568 param_bool("\\EN_POLARITY");
569 port("\\EN", 1);
570 port("\\D", param("\\WIDTH"));
571 port("\\Q", param("\\WIDTH"));
572 check_expected();
573 return;
574 }
575
576 if (cell->type == "$dlatchsr") {
577 param_bool("\\EN_POLARITY");
578 param_bool("\\SET_POLARITY");
579 param_bool("\\CLR_POLARITY");
580 port("\\EN", 1);
581 port("\\SET", param("\\WIDTH"));
582 port("\\CLR", param("\\WIDTH"));
583 port("\\D", param("\\WIDTH"));
584 port("\\Q", param("\\WIDTH"));
585 check_expected();
586 return;
587 }
588
589 if (cell->type == "$fsm") {
590 param("\\NAME");
591 param_bool("\\CLK_POLARITY");
592 param_bool("\\ARST_POLARITY");
593 param("\\STATE_BITS");
594 param("\\STATE_NUM");
595 param("\\STATE_NUM_LOG2");
596 param("\\STATE_RST");
597 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
598 param("\\TRANS_NUM");
599 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
600 port("\\CLK", 1);
601 port("\\ARST", 1);
602 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
603 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
604 check_expected();
605 return;
606 }
607
608 if (cell->type == "$memrd") {
609 param("\\MEMID");
610 param_bool("\\CLK_ENABLE");
611 param_bool("\\CLK_POLARITY");
612 param_bool("\\TRANSPARENT");
613 port("\\CLK", 1);
614 port("\\ADDR", param("\\ABITS"));
615 port("\\DATA", param("\\WIDTH"));
616 check_expected();
617 return;
618 }
619
620 if (cell->type == "$memwr") {
621 param("\\MEMID");
622 param_bool("\\CLK_ENABLE");
623 param_bool("\\CLK_POLARITY");
624 param("\\PRIORITY");
625 port("\\CLK", 1);
626 port("\\EN", param("\\WIDTH"));
627 port("\\ADDR", param("\\ABITS"));
628 port("\\DATA", param("\\WIDTH"));
629 check_expected();
630 return;
631 }
632
633 if (cell->type == "$mem") {
634 param("\\MEMID");
635 param("\\SIZE");
636 param("\\OFFSET");
637 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
638 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
639 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
640 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
641 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
642 port("\\RD_CLK", param("\\RD_PORTS"));
643 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
644 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
645 port("\\WR_CLK", param("\\WR_PORTS"));
646 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
647 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
648 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
649 check_expected();
650 return;
651 }
652
653 if (cell->type == "$assert") {
654 port("\\A", 1);
655 port("\\EN", 1);
656 check_expected();
657 return;
658 }
659
660 if (cell->type == "$_INV_") { check_gate("AY"); return; }
661 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
662 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
663 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
664 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
665
666 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
667 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
668 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
669 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
670
671 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
672 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
673
674 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
675 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
676 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
677 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
678 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
679 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
680 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
681 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
682
683 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
684 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
685 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
686 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
687 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
688 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
689 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
690 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
691
692 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
693 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
694
695 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
696 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
697 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
698 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
699 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
700 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
701 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
702 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
703
704 error(__LINE__);
705 }
706 };
707 }
708 #endif
709
710 void RTLIL::Module::check()
711 {
712 #ifndef NDEBUG
713 for (auto &it : wires) {
714 assert(it.first == it.second->name);
715 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
716 assert(it.second->width >= 0);
717 assert(it.second->port_id >= 0);
718 for (auto &it2 : it.second->attributes) {
719 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
720 }
721 }
722
723 for (auto &it : memories) {
724 assert(it.first == it.second->name);
725 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
726 assert(it.second->width >= 0);
727 assert(it.second->size >= 0);
728 for (auto &it2 : it.second->attributes) {
729 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
730 }
731 }
732
733 for (auto &it : cells) {
734 assert(it.first == it.second->name);
735 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
736 assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
737 for (auto &it2 : it.second->connections_) {
738 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
739 it2.second.check();
740 }
741 for (auto &it2 : it.second->attributes) {
742 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
743 }
744 for (auto &it2 : it.second->parameters) {
745 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
746 }
747 InternalCellChecker checker(this, it.second);
748 checker.check();
749 }
750
751 for (auto &it : processes) {
752 assert(it.first == it.second->name);
753 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
754 // FIXME: More checks here..
755 }
756
757 for (auto &it : connections_) {
758 assert(it.first.size() == it.second.size());
759 it.first.check();
760 it.second.check();
761 }
762
763 for (auto &it : attributes) {
764 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
765 }
766 #endif
767 }
768
769 void RTLIL::Module::optimize()
770 {
771 }
772
773 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
774 {
775 new_mod->name = name;
776 new_mod->connections_ = connections_;
777 new_mod->attributes = attributes;
778
779 for (auto &it : wires)
780 new_mod->wires[it.first] = new RTLIL::Wire(*it.second);
781
782 for (auto &it : memories)
783 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
784
785 for (auto &it : cells)
786 new_mod->addCell(it.first, it.second);
787
788 for (auto &it : processes)
789 new_mod->processes[it.first] = it.second->clone();
790
791 struct RewriteSigSpecWorker
792 {
793 RTLIL::Module *mod;
794 void operator()(RTLIL::SigSpec &sig)
795 {
796 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
797 for (auto &c : chunks)
798 if (c.wire != NULL)
799 c.wire = mod->wires.at(c.wire->name);
800 sig = chunks;
801 }
802 };
803
804 RewriteSigSpecWorker rewriteSigSpecWorker;
805 rewriteSigSpecWorker.mod = new_mod;
806 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
807 }
808
809 RTLIL::Module *RTLIL::Module::clone() const
810 {
811 RTLIL::Module *new_mod = new RTLIL::Module;
812 cloneInto(new_mod);
813 return new_mod;
814 }
815
816 void RTLIL::Module::add(RTLIL::Wire *wire)
817 {
818 assert(!wire->name.empty());
819 assert(count_id(wire->name) == 0);
820 wires[wire->name] = wire;
821 }
822
823 void RTLIL::Module::add(RTLIL::Cell *cell)
824 {
825 assert(!cell->name.empty());
826 assert(count_id(cell->name) == 0);
827 cells[cell->name] = cell;
828 }
829
830 void RTLIL::Module::remove(RTLIL::Cell *cell)
831 {
832 assert(cells.count(cell->name) != 0);
833 cells.erase(cell->name);
834 delete cell;
835 }
836
837 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
838 {
839 assert(wires[wire->name] == wire);
840 wires.erase(wire->name);
841 wire->name = new_name;
842 add(wire);
843 }
844
845 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
846 {
847 assert(cells[cell->name] == cell);
848 cells.erase(cell->name);
849 cell->name = new_name;
850 add(cell);
851 }
852
853 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
854 {
855 assert(count_id(old_name) != 0);
856 if (wires.count(old_name))
857 rename(wires.at(old_name), new_name);
858 else if (cells.count(old_name))
859 rename(cells.at(old_name), new_name);
860 else
861 log_abort();
862 }
863
864 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
865 {
866 if (a->port_id && !b->port_id)
867 return true;
868 if (!a->port_id && b->port_id)
869 return false;
870
871 if (a->port_id == b->port_id)
872 return a->name < b->name;
873 return a->port_id < b->port_id;
874 }
875
876 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
877 {
878 connections_.push_back(conn);
879 }
880
881 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
882 {
883 connections_.push_back(RTLIL::SigSig(lhs, rhs));
884 }
885
886 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
887 {
888 return connections_;
889 }
890
891 void RTLIL::Module::fixup_ports()
892 {
893 std::vector<RTLIL::Wire*> all_ports;
894
895 for (auto &w : wires)
896 if (w.second->port_input || w.second->port_output)
897 all_ports.push_back(w.second);
898 else
899 w.second->port_id = 0;
900
901 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
902 for (size_t i = 0; i < all_ports.size(); i++)
903 all_ports[i]->port_id = i+1;
904 }
905
906 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
907 {
908 RTLIL::Wire *wire = new RTLIL::Wire;
909 wire->name = name;
910 wire->width = width;
911 add(wire);
912 return wire;
913 }
914
915 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
916 {
917 RTLIL::Cell *cell = new RTLIL::Cell;
918 cell->name = name;
919 cell->type = type;
920 add(cell);
921 return cell;
922 }
923
924 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
925 {
926 RTLIL::Cell *cell = addCell(name, other->type);
927 cell->connections_ = other->connections_;
928 cell->parameters = other->parameters;
929 cell->attributes = other->attributes;
930 return cell;
931 }
932
933 #define DEF_METHOD(_func, _y_size, _type) \
934 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
935 RTLIL::Cell *cell = new RTLIL::Cell; \
936 cell->name = name; \
937 cell->type = _type; \
938 cell->parameters["\\A_SIGNED"] = is_signed; \
939 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
940 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
941 cell->connections_["\\A"] = sig_a; \
942 cell->connections_["\\Y"] = sig_y; \
943 add(cell); \
944 return cell; \
945 } \
946 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
947 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
948 add ## _func(name, sig_a, sig_y, is_signed); \
949 return sig_y; \
950 }
951 DEF_METHOD(Not, sig_a.size(), "$not")
952 DEF_METHOD(Pos, sig_a.size(), "$pos")
953 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
954 DEF_METHOD(Neg, sig_a.size(), "$neg")
955 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
956 DEF_METHOD(ReduceOr, 1, "$reduce_or")
957 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
958 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
959 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
960 DEF_METHOD(LogicNot, 1, "$logic_not")
961 #undef DEF_METHOD
962
963 #define DEF_METHOD(_func, _y_size, _type) \
964 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
965 RTLIL::Cell *cell = new RTLIL::Cell; \
966 cell->name = name; \
967 cell->type = _type; \
968 cell->parameters["\\A_SIGNED"] = is_signed; \
969 cell->parameters["\\B_SIGNED"] = is_signed; \
970 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
971 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
972 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
973 cell->connections_["\\A"] = sig_a; \
974 cell->connections_["\\B"] = sig_b; \
975 cell->connections_["\\Y"] = sig_y; \
976 add(cell); \
977 return cell; \
978 } \
979 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
980 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
981 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
982 return sig_y; \
983 }
984 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
985 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
986 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
987 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
988 DEF_METHOD(Shl, sig_a.size(), "$shl")
989 DEF_METHOD(Shr, sig_a.size(), "$shr")
990 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
991 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
992 DEF_METHOD(Lt, 1, "$lt")
993 DEF_METHOD(Le, 1, "$le")
994 DEF_METHOD(Eq, 1, "$eq")
995 DEF_METHOD(Ne, 1, "$ne")
996 DEF_METHOD(Eqx, 1, "$eqx")
997 DEF_METHOD(Nex, 1, "$nex")
998 DEF_METHOD(Ge, 1, "$ge")
999 DEF_METHOD(Gt, 1, "$gt")
1000 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1001 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1002 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1003 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1004 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1005 DEF_METHOD(LogicAnd, 1, "$logic_and")
1006 DEF_METHOD(LogicOr, 1, "$logic_or")
1007 #undef DEF_METHOD
1008
1009 #define DEF_METHOD(_func, _type, _pmux) \
1010 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1011 RTLIL::Cell *cell = new RTLIL::Cell; \
1012 cell->name = name; \
1013 cell->type = _type; \
1014 cell->parameters["\\WIDTH"] = sig_a.size(); \
1015 cell->parameters["\\WIDTH"] = sig_b.size(); \
1016 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1017 cell->connections_["\\A"] = sig_a; \
1018 cell->connections_["\\B"] = sig_b; \
1019 cell->connections_["\\S"] = sig_s; \
1020 cell->connections_["\\Y"] = sig_y; \
1021 add(cell); \
1022 return cell; \
1023 } \
1024 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1025 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1026 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1027 return sig_y; \
1028 }
1029 DEF_METHOD(Mux, "$mux", 0)
1030 DEF_METHOD(Pmux, "$pmux", 1)
1031 DEF_METHOD(SafePmux, "$safe_pmux", 1)
1032 #undef DEF_METHOD
1033
1034 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1035 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1036 RTLIL::Cell *cell = new RTLIL::Cell; \
1037 cell->name = name; \
1038 cell->type = _type; \
1039 cell->connections_["\\" #_P1] = sig1; \
1040 cell->connections_["\\" #_P2] = sig2; \
1041 add(cell); \
1042 return cell; \
1043 } \
1044 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1045 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1046 add ## _func(name, sig1, sig2); \
1047 return sig2; \
1048 }
1049 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1050 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1051 RTLIL::Cell *cell = new RTLIL::Cell; \
1052 cell->name = name; \
1053 cell->type = _type; \
1054 cell->connections_["\\" #_P1] = sig1; \
1055 cell->connections_["\\" #_P2] = sig2; \
1056 cell->connections_["\\" #_P3] = sig3; \
1057 add(cell); \
1058 return cell; \
1059 } \
1060 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1061 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1062 add ## _func(name, sig1, sig2, sig3); \
1063 return sig3; \
1064 }
1065 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1066 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1067 RTLIL::Cell *cell = new RTLIL::Cell; \
1068 cell->name = name; \
1069 cell->type = _type; \
1070 cell->connections_["\\" #_P1] = sig1; \
1071 cell->connections_["\\" #_P2] = sig2; \
1072 cell->connections_["\\" #_P3] = sig3; \
1073 cell->connections_["\\" #_P4] = sig4; \
1074 add(cell); \
1075 return cell; \
1076 } \
1077 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1078 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1079 add ## _func(name, sig1, sig2, sig3, sig4); \
1080 return sig4; \
1081 }
1082 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1083 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1084 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1085 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1086 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1087 #undef DEF_METHOD_2
1088 #undef DEF_METHOD_3
1089 #undef DEF_METHOD_4
1090
1091 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1092 {
1093 RTLIL::Cell *cell = new RTLIL::Cell;
1094 cell->name = name;
1095 cell->type = "$pow";
1096 cell->parameters["\\A_SIGNED"] = a_signed;
1097 cell->parameters["\\B_SIGNED"] = b_signed;
1098 cell->parameters["\\A_WIDTH"] = sig_a.size();
1099 cell->parameters["\\B_WIDTH"] = sig_b.size();
1100 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1101 cell->connections_["\\A"] = sig_a;
1102 cell->connections_["\\B"] = sig_b;
1103 cell->connections_["\\Y"] = sig_y;
1104 add(cell);
1105 return cell;
1106 }
1107
1108 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1109 {
1110 RTLIL::Cell *cell = new RTLIL::Cell;
1111 cell->name = name;
1112 cell->type = "$slice";
1113 cell->parameters["\\A_WIDTH"] = sig_a.size();
1114 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1115 cell->parameters["\\OFFSET"] = offset;
1116 cell->connections_["\\A"] = sig_a;
1117 cell->connections_["\\Y"] = sig_y;
1118 add(cell);
1119 return cell;
1120 }
1121
1122 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1123 {
1124 RTLIL::Cell *cell = new RTLIL::Cell;
1125 cell->name = name;
1126 cell->type = "$concat";
1127 cell->parameters["\\A_WIDTH"] = sig_a.size();
1128 cell->parameters["\\B_WIDTH"] = sig_b.size();
1129 cell->connections_["\\A"] = sig_a;
1130 cell->connections_["\\B"] = sig_b;
1131 cell->connections_["\\Y"] = sig_y;
1132 add(cell);
1133 return cell;
1134 }
1135
1136 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1137 {
1138 RTLIL::Cell *cell = new RTLIL::Cell;
1139 cell->name = name;
1140 cell->type = "$lut";
1141 cell->parameters["\\LUT"] = lut;
1142 cell->parameters["\\WIDTH"] = sig_i.size();
1143 cell->connections_["\\I"] = sig_i;
1144 cell->connections_["\\O"] = sig_o;
1145 add(cell);
1146 return cell;
1147 }
1148
1149 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1150 {
1151 RTLIL::Cell *cell = new RTLIL::Cell;
1152 cell->name = name;
1153 cell->type = "$assert";
1154 cell->connections_["\\A"] = sig_a;
1155 cell->connections_["\\EN"] = sig_en;
1156 add(cell);
1157 return cell;
1158 }
1159
1160 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1161 {
1162 RTLIL::Cell *cell = new RTLIL::Cell;
1163 cell->name = name;
1164 cell->type = "$sr";
1165 cell->parameters["\\SET_POLARITY"] = set_polarity;
1166 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1167 cell->parameters["\\WIDTH"] = sig_q.size();
1168 cell->connections_["\\SET"] = sig_set;
1169 cell->connections_["\\CLR"] = sig_clr;
1170 cell->connections_["\\Q"] = sig_q;
1171 add(cell);
1172 return cell;
1173 }
1174
1175 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1176 {
1177 RTLIL::Cell *cell = new RTLIL::Cell;
1178 cell->name = name;
1179 cell->type = "$dff";
1180 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1181 cell->parameters["\\WIDTH"] = sig_q.size();
1182 cell->connections_["\\CLK"] = sig_clk;
1183 cell->connections_["\\D"] = sig_d;
1184 cell->connections_["\\Q"] = sig_q;
1185 add(cell);
1186 return cell;
1187 }
1188
1189 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1190 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1191 {
1192 RTLIL::Cell *cell = new RTLIL::Cell;
1193 cell->name = name;
1194 cell->type = "$dffsr";
1195 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1196 cell->parameters["\\SET_POLARITY"] = set_polarity;
1197 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1198 cell->parameters["\\WIDTH"] = sig_q.size();
1199 cell->connections_["\\CLK"] = sig_clk;
1200 cell->connections_["\\SET"] = sig_set;
1201 cell->connections_["\\CLR"] = sig_clr;
1202 cell->connections_["\\D"] = sig_d;
1203 cell->connections_["\\Q"] = sig_q;
1204 add(cell);
1205 return cell;
1206 }
1207
1208 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1209 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1210 {
1211 RTLIL::Cell *cell = new RTLIL::Cell;
1212 cell->name = name;
1213 cell->type = "$adff";
1214 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1215 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1216 cell->parameters["\\ARST_VALUE"] = arst_value;
1217 cell->parameters["\\WIDTH"] = sig_q.size();
1218 cell->connections_["\\CLK"] = sig_clk;
1219 cell->connections_["\\ARST"] = sig_arst;
1220 cell->connections_["\\D"] = sig_d;
1221 cell->connections_["\\Q"] = sig_q;
1222 add(cell);
1223 return cell;
1224 }
1225
1226 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1227 {
1228 RTLIL::Cell *cell = new RTLIL::Cell;
1229 cell->name = name;
1230 cell->type = "$dlatch";
1231 cell->parameters["\\EN_POLARITY"] = en_polarity;
1232 cell->parameters["\\WIDTH"] = sig_q.size();
1233 cell->connections_["\\EN"] = sig_en;
1234 cell->connections_["\\D"] = sig_d;
1235 cell->connections_["\\Q"] = sig_q;
1236 add(cell);
1237 return cell;
1238 }
1239
1240 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1241 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1242 {
1243 RTLIL::Cell *cell = new RTLIL::Cell;
1244 cell->name = name;
1245 cell->type = "$dlatchsr";
1246 cell->parameters["\\EN_POLARITY"] = en_polarity;
1247 cell->parameters["\\SET_POLARITY"] = set_polarity;
1248 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1249 cell->parameters["\\WIDTH"] = sig_q.size();
1250 cell->connections_["\\EN"] = sig_en;
1251 cell->connections_["\\SET"] = sig_set;
1252 cell->connections_["\\CLR"] = sig_clr;
1253 cell->connections_["\\D"] = sig_d;
1254 cell->connections_["\\Q"] = sig_q;
1255 add(cell);
1256 return cell;
1257 }
1258
1259 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1260 {
1261 RTLIL::Cell *cell = new RTLIL::Cell;
1262 cell->name = name;
1263 cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
1264 cell->connections_["\\C"] = sig_clk;
1265 cell->connections_["\\D"] = sig_d;
1266 cell->connections_["\\Q"] = sig_q;
1267 add(cell);
1268 return cell;
1269 }
1270
1271 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1272 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1273 {
1274 RTLIL::Cell *cell = new RTLIL::Cell;
1275 cell->name = name;
1276 cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1277 cell->connections_["\\C"] = sig_clk;
1278 cell->connections_["\\S"] = sig_set;
1279 cell->connections_["\\R"] = sig_clr;
1280 cell->connections_["\\D"] = sig_d;
1281 cell->connections_["\\Q"] = sig_q;
1282 add(cell);
1283 return cell;
1284 }
1285
1286 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1287 bool arst_value, bool clk_polarity, bool arst_polarity)
1288 {
1289 RTLIL::Cell *cell = new RTLIL::Cell;
1290 cell->name = name;
1291 cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
1292 cell->connections_["\\C"] = sig_clk;
1293 cell->connections_["\\R"] = sig_arst;
1294 cell->connections_["\\D"] = sig_d;
1295 cell->connections_["\\Q"] = sig_q;
1296 add(cell);
1297 return cell;
1298 }
1299
1300 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1301 {
1302 RTLIL::Cell *cell = new RTLIL::Cell;
1303 cell->name = name;
1304 cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
1305 cell->connections_["\\E"] = sig_en;
1306 cell->connections_["\\D"] = sig_d;
1307 cell->connections_["\\Q"] = sig_q;
1308 add(cell);
1309 return cell;
1310 }
1311
1312 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1313 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1314 {
1315 RTLIL::Cell *cell = new RTLIL::Cell;
1316 cell->name = name;
1317 cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1318 cell->connections_["\\E"] = sig_en;
1319 cell->connections_["\\S"] = sig_set;
1320 cell->connections_["\\R"] = sig_clr;
1321 cell->connections_["\\D"] = sig_d;
1322 cell->connections_["\\Q"] = sig_q;
1323 add(cell);
1324 return cell;
1325 }
1326
1327
1328 RTLIL::Wire::Wire()
1329 {
1330 width = 1;
1331 start_offset = 0;
1332 port_id = 0;
1333 port_input = false;
1334 port_output = false;
1335 }
1336
1337 RTLIL::Memory::Memory()
1338 {
1339 width = 1;
1340 size = 0;
1341 }
1342
1343 void RTLIL::Cell::unset(RTLIL::IdString portname)
1344 {
1345 connections_.erase(portname);
1346 }
1347
1348 void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
1349 {
1350 connections_[portname] = signal;
1351 }
1352
1353 const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
1354 {
1355 return connections_.at(portname);
1356 }
1357
1358 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1359 {
1360 return connections_;
1361 }
1362
1363 void RTLIL::Cell::check()
1364 {
1365 #ifndef NDEBUG
1366 InternalCellChecker checker(NULL, this);
1367 checker.check();
1368 #endif
1369 }
1370
1371 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1372 {
1373 if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1374 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:")
1375 return;
1376
1377 if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
1378 {
1379 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1380 if (type == "$pmux" || type == "$safe_pmux")
1381 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1382 check();
1383 return;
1384 }
1385
1386 bool signedness_ab = type != "$slice" && type != "$concat";
1387
1388 if (connections_.count("\\A")) {
1389 if (signedness_ab) {
1390 if (set_a_signed)
1391 parameters["\\A_SIGNED"] = true;
1392 else if (parameters.count("\\A_SIGNED") == 0)
1393 parameters["\\A_SIGNED"] = false;
1394 }
1395 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1396 }
1397
1398 if (connections_.count("\\B")) {
1399 if (signedness_ab) {
1400 if (set_b_signed)
1401 parameters["\\B_SIGNED"] = true;
1402 else if (parameters.count("\\B_SIGNED") == 0)
1403 parameters["\\B_SIGNED"] = false;
1404 }
1405 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1406 }
1407
1408 if (connections_.count("\\Y"))
1409 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1410
1411 check();
1412 }
1413
1414 RTLIL::SigChunk::SigChunk()
1415 {
1416 wire = NULL;
1417 width = 0;
1418 offset = 0;
1419 }
1420
1421 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1422 {
1423 wire = NULL;
1424 data = value;
1425 width = data.bits.size();
1426 offset = 0;
1427 }
1428
1429 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1430 {
1431 this->wire = wire;
1432 this->width = wire->width;
1433 this->offset = 0;
1434 }
1435
1436 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1437 {
1438 this->wire = wire;
1439 this->width = width;
1440 this->offset = offset;
1441 }
1442
1443 RTLIL::SigChunk::SigChunk(const std::string &str)
1444 {
1445 wire = NULL;
1446 data = RTLIL::Const(str);
1447 width = data.bits.size();
1448 offset = 0;
1449 }
1450
1451 RTLIL::SigChunk::SigChunk(int val, int width)
1452 {
1453 wire = NULL;
1454 data = RTLIL::Const(val, width);
1455 this->width = data.bits.size();
1456 offset = 0;
1457 }
1458
1459 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1460 {
1461 wire = NULL;
1462 data = RTLIL::Const(bit, width);
1463 this->width = data.bits.size();
1464 offset = 0;
1465 }
1466
1467 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1468 {
1469 wire = bit.wire;
1470 if (wire == NULL)
1471 data = RTLIL::Const(bit.data);
1472 offset = bit.offset;
1473 width = 1;
1474 }
1475
1476 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1477 {
1478 RTLIL::SigChunk ret;
1479 if (wire) {
1480 ret.wire = wire;
1481 ret.offset = this->offset + offset;
1482 ret.width = length;
1483 } else {
1484 for (int i = 0; i < length; i++)
1485 ret.data.bits.push_back(data.bits[offset+i]);
1486 ret.width = length;
1487 }
1488 return ret;
1489 }
1490
1491 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1492 {
1493 if (wire && other.wire)
1494 if (wire->name != other.wire->name)
1495 return wire->name < other.wire->name;
1496
1497 if (wire != other.wire)
1498 return wire < other.wire;
1499
1500 if (offset != other.offset)
1501 return offset < other.offset;
1502
1503 if (width != other.width)
1504 return width < other.width;
1505
1506 return data.bits < other.data.bits;
1507 }
1508
1509 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1510 {
1511 if (wire != other.wire || width != other.width || offset != other.offset)
1512 return false;
1513 if (data.bits != other.data.bits)
1514 return false;
1515 return true;
1516 }
1517
1518 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1519 {
1520 if (*this == other)
1521 return false;
1522 return true;
1523 }
1524
1525 RTLIL::SigSpec::SigSpec()
1526 {
1527 width_ = 0;
1528 hash_ = 0;
1529 }
1530
1531 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1532 {
1533 *this = other;
1534 }
1535
1536 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1537 {
1538 cover("kernel.rtlil.sigspec.assign");
1539
1540 width_ = other.width_;
1541 hash_ = other.hash_;
1542 chunks_ = other.chunks_;
1543 bits_.clear();
1544
1545 if (!other.bits_.empty())
1546 {
1547 RTLIL::SigChunk *last = NULL;
1548 int last_end_offset = 0;
1549
1550 for (auto &bit : other.bits_) {
1551 if (last && bit.wire == last->wire) {
1552 if (bit.wire == NULL) {
1553 last->data.bits.push_back(bit.data);
1554 last->width++;
1555 continue;
1556 } else if (last_end_offset == bit.offset) {
1557 last_end_offset++;
1558 last->width++;
1559 continue;
1560 }
1561 }
1562 chunks_.push_back(bit);
1563 last = &chunks_.back();
1564 last_end_offset = bit.offset + 1;
1565 }
1566
1567 check();
1568 }
1569
1570 return *this;
1571 }
1572
1573 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1574 {
1575 chunks_.push_back(RTLIL::SigChunk(value));
1576 width_ = chunks_.back().width;
1577 hash_ = 0;
1578 check();
1579 }
1580
1581 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1582 {
1583 chunks_.push_back(chunk);
1584 width_ = chunks_.back().width;
1585 hash_ = 0;
1586 check();
1587 }
1588
1589 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1590 {
1591 chunks_.push_back(RTLIL::SigChunk(wire));
1592 width_ = chunks_.back().width;
1593 hash_ = 0;
1594 check();
1595 }
1596
1597 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1598 {
1599 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1600 width_ = chunks_.back().width;
1601 hash_ = 0;
1602 check();
1603 }
1604
1605 RTLIL::SigSpec::SigSpec(const std::string &str)
1606 {
1607 chunks_.push_back(RTLIL::SigChunk(str));
1608 width_ = chunks_.back().width;
1609 hash_ = 0;
1610 check();
1611 }
1612
1613 RTLIL::SigSpec::SigSpec(int val, int width)
1614 {
1615 chunks_.push_back(RTLIL::SigChunk(val, width));
1616 width_ = width;
1617 hash_ = 0;
1618 check();
1619 }
1620
1621 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1622 {
1623 chunks_.push_back(RTLIL::SigChunk(bit, width));
1624 width_ = width;
1625 hash_ = 0;
1626 check();
1627 }
1628
1629 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1630 {
1631 if (bit.wire == NULL)
1632 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1633 else
1634 for (int i = 0; i < width; i++)
1635 chunks_.push_back(bit);
1636 width_ = width;
1637 hash_ = 0;
1638 check();
1639 }
1640
1641 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1642 {
1643 width_ = 0;
1644 hash_ = 0;
1645 for (auto &c : chunks)
1646 append(c);
1647 check();
1648 }
1649
1650 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1651 {
1652 width_ = 0;
1653 hash_ = 0;
1654 for (auto &bit : bits)
1655 append_bit(bit);
1656 check();
1657 }
1658
1659 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1660 {
1661 width_ = 0;
1662 hash_ = 0;
1663 for (auto &bit : bits)
1664 append_bit(bit);
1665 check();
1666 }
1667
1668 void RTLIL::SigSpec::pack() const
1669 {
1670 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1671
1672 if (that->bits_.empty())
1673 return;
1674
1675 cover("kernel.rtlil.sigspec.convert.pack");
1676 log_assert(that->chunks_.empty());
1677
1678 std::vector<RTLIL::SigBit> old_bits;
1679 old_bits.swap(that->bits_);
1680
1681 RTLIL::SigChunk *last = NULL;
1682 int last_end_offset = 0;
1683
1684 for (auto &bit : old_bits) {
1685 if (last && bit.wire == last->wire) {
1686 if (bit.wire == NULL) {
1687 last->data.bits.push_back(bit.data);
1688 last->width++;
1689 continue;
1690 } else if (last_end_offset == bit.offset) {
1691 last_end_offset++;
1692 last->width++;
1693 continue;
1694 }
1695 }
1696 that->chunks_.push_back(bit);
1697 last = &that->chunks_.back();
1698 last_end_offset = bit.offset + 1;
1699 }
1700
1701 check();
1702 }
1703
1704 void RTLIL::SigSpec::unpack() const
1705 {
1706 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1707
1708 if (that->chunks_.empty())
1709 return;
1710
1711 cover("kernel.rtlil.sigspec.convert.unpack");
1712 log_assert(that->bits_.empty());
1713
1714 that->bits_.reserve(that->width_);
1715 for (auto &c : that->chunks_)
1716 for (int i = 0; i < c.width; i++)
1717 that->bits_.push_back(RTLIL::SigBit(c, i));
1718
1719 that->chunks_.clear();
1720 that->hash_ = 0;
1721 }
1722
1723 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
1724
1725 void RTLIL::SigSpec::hash() const
1726 {
1727 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1728
1729 if (that->hash_ != 0)
1730 return;
1731
1732 cover("kernel.rtlil.sigspec.hash");
1733 that->pack();
1734
1735 that->hash_ = 5381;
1736 for (auto &c : that->chunks_)
1737 if (c.wire == NULL) {
1738 for (auto &v : c.data.bits)
1739 DJB2(that->hash_, v);
1740 } else {
1741 for (auto &v : c.wire->name)
1742 DJB2(that->hash_, v);
1743 DJB2(that->hash_, c.offset);
1744 DJB2(that->hash_, c.width);
1745 }
1746
1747 if (that->hash_ == 0)
1748 that->hash_ = 1;
1749 }
1750
1751 void RTLIL::SigSpec::sort()
1752 {
1753 unpack();
1754 cover("kernel.rtlil.sigspec.sort");
1755 std::sort(bits_.begin(), bits_.end());
1756 }
1757
1758 void RTLIL::SigSpec::sort_and_unify()
1759 {
1760 cover("kernel.rtlil.sigspec.sort_and_unify");
1761 *this = this->to_sigbit_set();
1762 }
1763
1764 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
1765 {
1766 replace(pattern, with, this);
1767 }
1768
1769 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
1770 {
1771 cover("kernel.rtlil.sigspec.replace");
1772
1773 unpack();
1774 pattern.unpack();
1775 with.unpack();
1776
1777 assert(other != NULL);
1778 assert(width_ == other->width_);
1779 other->unpack();
1780
1781 assert(pattern.width_ == with.width_);
1782
1783 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
1784 for (int i = 0; i < SIZE(pattern.bits_); i++)
1785 if (pattern.bits_[i].wire != NULL)
1786 pattern_map[pattern.bits_[i]] = with.bits_[i];
1787
1788 for (int i = 0; i < SIZE(bits_); i++)
1789 if (pattern_map.count(bits_[i]))
1790 other->bits_[i] = pattern_map.at(bits_[i]);
1791
1792 other->check();
1793 }
1794
1795 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
1796 {
1797 remove2(pattern, NULL);
1798 }
1799
1800 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
1801 {
1802 RTLIL::SigSpec tmp = *this;
1803 tmp.remove2(pattern, other);
1804 }
1805
1806 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
1807 {
1808 if (other)
1809 cover("kernel.rtlil.sigspec.remove_other");
1810 else
1811 cover("kernel.rtlil.sigspec.remove");
1812
1813 unpack();
1814
1815 if (other != NULL) {
1816 assert(width_ == other->width_);
1817 other->unpack();
1818 }
1819
1820 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
1821 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
1822
1823 for (int i = 0; i < SIZE(bits_); i++) {
1824 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
1825 continue;
1826 if (other != NULL)
1827 new_other_bits.push_back(other->bits_[i]);
1828 new_bits.push_back(bits_[i]);
1829 }
1830
1831 bits_.swap(new_bits);
1832 width_ = SIZE(bits_);
1833
1834 if (other != NULL) {
1835 other->bits_.swap(new_other_bits);
1836 other->width_ = SIZE(other->bits_);
1837 }
1838
1839 check();
1840 }
1841
1842 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
1843 {
1844 if (other)
1845 cover("kernel.rtlil.sigspec.extract_other");
1846 else
1847 cover("kernel.rtlil.sigspec.extract");
1848
1849 pack();
1850 pattern.pack();
1851
1852 if (other != NULL)
1853 other->pack();
1854
1855 assert(other == NULL || width_ == other->width_);
1856
1857 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
1858 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
1859 RTLIL::SigSpec ret;
1860
1861 if (other) {
1862 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
1863 for (int i = 0; i < width_; i++)
1864 if (bits_match[i].wire && pat.count(bits_match[i]))
1865 ret.append_bit(bits_other[i]);
1866 } else {
1867 for (int i = 0; i < width_; i++)
1868 if (bits_match[i].wire && pat.count(bits_match[i]))
1869 ret.append_bit(bits_match[i]);
1870 }
1871
1872 ret.check();
1873 return ret;
1874 }
1875
1876 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
1877 {
1878 cover("kernel.rtlil.sigspec.replace_pos");
1879
1880 unpack();
1881 with.unpack();
1882
1883 assert(offset >= 0);
1884 assert(with.width_ >= 0);
1885 assert(offset+with.width_ <= width_);
1886
1887 for (int i = 0; i < with.width_; i++)
1888 bits_.at(offset + i) = with.bits_.at(i);
1889
1890 check();
1891 }
1892
1893 void RTLIL::SigSpec::remove_const()
1894 {
1895 cover("kernel.rtlil.sigspec.remove_const");
1896
1897 unpack();
1898
1899 std::vector<RTLIL::SigBit> new_bits;
1900 new_bits.reserve(width_);
1901
1902 for (auto &bit : bits_)
1903 if (bit.wire != NULL)
1904 new_bits.push_back(bit);
1905
1906 bits_.swap(new_bits);
1907 width_ = bits_.size();
1908
1909 check();
1910 }
1911
1912 void RTLIL::SigSpec::remove(int offset, int length)
1913 {
1914 cover("kernel.rtlil.sigspec.remove_pos");
1915
1916 unpack();
1917
1918 assert(offset >= 0);
1919 assert(length >= 0);
1920 assert(offset + length <= width_);
1921
1922 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
1923 width_ = bits_.size();
1924
1925 check();
1926 }
1927
1928 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
1929 {
1930 unpack();
1931 cover("kernel.rtlil.sigspec.extract_pos");
1932 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
1933 }
1934
1935 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
1936 {
1937 if (signal.width_ == 0)
1938 return;
1939
1940 if (width_ == 0) {
1941 *this = signal;
1942 return;
1943 }
1944
1945 cover("kernel.rtlil.sigspec.append");
1946
1947 if (packed() != signal.packed()) {
1948 pack();
1949 signal.pack();
1950 }
1951
1952 if (packed())
1953 for (auto &other_c : signal.chunks_)
1954 {
1955 auto &my_last_c = chunks_.back();
1956 if (my_last_c.wire == NULL && other_c.wire == NULL) {
1957 auto &this_data = my_last_c.data.bits;
1958 auto &other_data = other_c.data.bits;
1959 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
1960 my_last_c.width += other_c.width;
1961 } else
1962 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
1963 my_last_c.width += other_c.width;
1964 } else
1965 chunks_.push_back(other_c);
1966 }
1967 else
1968 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
1969
1970 width_ += signal.width_;
1971 check();
1972 }
1973
1974 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
1975 {
1976 if (packed())
1977 {
1978 cover("kernel.rtlil.sigspec.append_bit.packed");
1979
1980 if (chunks_.size() == 0)
1981 chunks_.push_back(bit);
1982 else
1983 if (bit.wire == NULL)
1984 if (chunks_.back().wire == NULL) {
1985 chunks_.back().data.bits.push_back(bit.data);
1986 chunks_.back().width++;
1987 } else
1988 chunks_.push_back(bit);
1989 else
1990 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
1991 chunks_.back().width++;
1992 else
1993 chunks_.push_back(bit);
1994 }
1995 else
1996 {
1997 cover("kernel.rtlil.sigspec.append_bit.unpacked");
1998 bits_.push_back(bit);
1999 }
2000
2001 width_++;
2002 check();
2003 }
2004
2005 void RTLIL::SigSpec::extend(int width, bool is_signed)
2006 {
2007 cover("kernel.rtlil.sigspec.extend");
2008
2009 pack();
2010
2011 if (width_ > width)
2012 remove(width, width_ - width);
2013
2014 if (width_ < width) {
2015 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2016 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2017 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2018 padding = RTLIL::SigSpec(RTLIL::State::S0);
2019 while (width_ < width)
2020 append(padding);
2021 }
2022 }
2023
2024 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2025 {
2026 cover("kernel.rtlil.sigspec.extend_u0");
2027
2028 pack();
2029
2030 if (width_ > width)
2031 remove(width, width_ - width);
2032
2033 if (width_ < width) {
2034 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2035 if (!is_signed)
2036 padding = RTLIL::SigSpec(RTLIL::State::S0);
2037 while (width_ < width)
2038 append(padding);
2039 }
2040
2041 }
2042
2043 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2044 {
2045 cover("kernel.rtlil.sigspec.repeat");
2046
2047 RTLIL::SigSpec sig;
2048 for (int i = 0; i < num; i++)
2049 sig.append(*this);
2050 return sig;
2051 }
2052
2053 #ifndef NDEBUG
2054 void RTLIL::SigSpec::check() const
2055 {
2056 if (width_ > 64)
2057 {
2058 cover("kernel.rtlil.sigspec.check.skip");
2059 }
2060 else if (packed())
2061 {
2062 cover("kernel.rtlil.sigspec.check.packed");
2063
2064 int w = 0;
2065 for (size_t i = 0; i < chunks_.size(); i++) {
2066 const RTLIL::SigChunk chunk = chunks_[i];
2067 if (chunk.wire == NULL) {
2068 if (i > 0)
2069 assert(chunks_[i-1].wire != NULL);
2070 assert(chunk.offset == 0);
2071 assert(chunk.data.bits.size() == (size_t)chunk.width);
2072 } else {
2073 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2074 assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2075 assert(chunk.offset >= 0);
2076 assert(chunk.width >= 0);
2077 assert(chunk.offset + chunk.width <= chunk.wire->width);
2078 assert(chunk.data.bits.size() == 0);
2079 }
2080 w += chunk.width;
2081 }
2082 assert(w == width_);
2083 assert(bits_.empty());
2084 }
2085 else
2086 {
2087 cover("kernel.rtlil.sigspec.check.unpacked");
2088
2089 assert(width_ == SIZE(bits_));
2090 assert(chunks_.empty());
2091 }
2092 }
2093 #endif
2094
2095 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2096 {
2097 cover("kernel.rtlil.sigspec.comp_lt");
2098
2099 if (this == &other)
2100 return false;
2101
2102 if (width_ != other.width_)
2103 return width_ < other.width_;
2104
2105 pack();
2106 other.pack();
2107
2108 if (chunks_.size() != other.chunks_.size())
2109 return chunks_.size() < other.chunks_.size();
2110
2111 hash();
2112 other.hash();
2113
2114 if (hash_ != other.hash_)
2115 return hash_ < other.hash_;
2116
2117 for (size_t i = 0; i < chunks_.size(); i++)
2118 if (chunks_[i] != other.chunks_[i]) {
2119 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2120 return chunks_[i] < other.chunks_[i];
2121 }
2122
2123 cover("kernel.rtlil.sigspec.comp_lt.equal");
2124 return false;
2125 }
2126
2127 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2128 {
2129 cover("kernel.rtlil.sigspec.comp_eq");
2130
2131 if (this == &other)
2132 return true;
2133
2134 if (width_ != other.width_)
2135 return false;
2136
2137 pack();
2138 other.pack();
2139
2140 if (chunks_.size() != chunks_.size())
2141 return false;
2142
2143 hash();
2144 other.hash();
2145
2146 if (hash_ != other.hash_)
2147 return false;
2148
2149 for (size_t i = 0; i < chunks_.size(); i++)
2150 if (chunks_[i] != other.chunks_[i]) {
2151 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2152 return false;
2153 }
2154
2155 cover("kernel.rtlil.sigspec.comp_eq.equal");
2156 return true;
2157 }
2158
2159 bool RTLIL::SigSpec::is_wire() const
2160 {
2161 cover("kernel.rtlil.sigspec.is_wire");
2162
2163 pack();
2164 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2165 }
2166
2167 bool RTLIL::SigSpec::is_chunk() const
2168 {
2169 cover("kernel.rtlil.sigspec.is_chunk");
2170
2171 pack();
2172 return SIZE(chunks_) == 1;
2173 }
2174
2175 bool RTLIL::SigSpec::is_fully_const() const
2176 {
2177 cover("kernel.rtlil.sigspec.is_fully_const");
2178
2179 pack();
2180 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2181 if (it->width > 0 && it->wire != NULL)
2182 return false;
2183 return true;
2184 }
2185
2186 bool RTLIL::SigSpec::is_fully_def() const
2187 {
2188 cover("kernel.rtlil.sigspec.is_fully_def");
2189
2190 pack();
2191 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2192 if (it->width > 0 && it->wire != NULL)
2193 return false;
2194 for (size_t i = 0; i < it->data.bits.size(); i++)
2195 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2196 return false;
2197 }
2198 return true;
2199 }
2200
2201 bool RTLIL::SigSpec::is_fully_undef() const
2202 {
2203 cover("kernel.rtlil.sigspec.is_fully_undef");
2204
2205 pack();
2206 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2207 if (it->width > 0 && it->wire != NULL)
2208 return false;
2209 for (size_t i = 0; i < it->data.bits.size(); i++)
2210 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2211 return false;
2212 }
2213 return true;
2214 }
2215
2216 bool RTLIL::SigSpec::has_marked_bits() const
2217 {
2218 cover("kernel.rtlil.sigspec.has_marked_bits");
2219
2220 pack();
2221 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2222 if (it->width > 0 && it->wire == NULL) {
2223 for (size_t i = 0; i < it->data.bits.size(); i++)
2224 if (it->data.bits[i] == RTLIL::State::Sm)
2225 return true;
2226 }
2227 return false;
2228 }
2229
2230 bool RTLIL::SigSpec::as_bool() const
2231 {
2232 cover("kernel.rtlil.sigspec.as_bool");
2233
2234 pack();
2235 assert(is_fully_const() && SIZE(chunks_) <= 1);
2236 if (width_)
2237 return chunks_[0].data.as_bool();
2238 return false;
2239 }
2240
2241 int RTLIL::SigSpec::as_int() const
2242 {
2243 cover("kernel.rtlil.sigspec.as_int");
2244
2245 pack();
2246 assert(is_fully_const() && SIZE(chunks_) <= 1);
2247 if (width_)
2248 return chunks_[0].data.as_int();
2249 return 0;
2250 }
2251
2252 std::string RTLIL::SigSpec::as_string() const
2253 {
2254 cover("kernel.rtlil.sigspec.as_string");
2255
2256 pack();
2257 std::string str;
2258 for (size_t i = chunks_.size(); i > 0; i--) {
2259 const RTLIL::SigChunk &chunk = chunks_[i-1];
2260 if (chunk.wire != NULL)
2261 for (int j = 0; j < chunk.width; j++)
2262 str += "?";
2263 else
2264 str += chunk.data.as_string();
2265 }
2266 return str;
2267 }
2268
2269 RTLIL::Const RTLIL::SigSpec::as_const() const
2270 {
2271 cover("kernel.rtlil.sigspec.as_const");
2272
2273 pack();
2274 assert(is_fully_const() && SIZE(chunks_) <= 1);
2275 if (width_)
2276 return chunks_[0].data;
2277 return RTLIL::Const();
2278 }
2279
2280 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2281 {
2282 cover("kernel.rtlil.sigspec.as_wire");
2283
2284 pack();
2285 assert(is_wire());
2286 return chunks_[0].wire;
2287 }
2288
2289 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2290 {
2291 cover("kernel.rtlil.sigspec.as_chunk");
2292
2293 pack();
2294 assert(is_chunk());
2295 return chunks_[0];
2296 }
2297
2298 bool RTLIL::SigSpec::match(std::string pattern) const
2299 {
2300 cover("kernel.rtlil.sigspec.match");
2301
2302 pack();
2303 std::string str = as_string();
2304 assert(pattern.size() == str.size());
2305
2306 for (size_t i = 0; i < pattern.size(); i++) {
2307 if (pattern[i] == ' ')
2308 continue;
2309 if (pattern[i] == '*') {
2310 if (str[i] != 'z' && str[i] != 'x')
2311 return false;
2312 continue;
2313 }
2314 if (pattern[i] != str[i])
2315 return false;
2316 }
2317
2318 return true;
2319 }
2320
2321 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2322 {
2323 cover("kernel.rtlil.sigspec.to_sigbit_set");
2324
2325 pack();
2326 std::set<RTLIL::SigBit> sigbits;
2327 for (auto &c : chunks_)
2328 for (int i = 0; i < c.width; i++)
2329 sigbits.insert(RTLIL::SigBit(c, i));
2330 return sigbits;
2331 }
2332
2333 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2334 {
2335 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2336
2337 unpack();
2338 return bits_;
2339 }
2340
2341 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2342 {
2343 cover("kernel.rtlil.sigspec.to_single_sigbit");
2344
2345 pack();
2346 log_assert(width_ == 1);
2347 for (auto &c : chunks_)
2348 if (c.width)
2349 return RTLIL::SigBit(c);
2350 log_abort();
2351 }
2352
2353 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2354 {
2355 size_t start = 0, end = 0;
2356 while ((end = text.find(sep, start)) != std::string::npos) {
2357 tokens.push_back(text.substr(start, end - start));
2358 start = end + 1;
2359 }
2360 tokens.push_back(text.substr(start));
2361 }
2362
2363 static int sigspec_parse_get_dummy_line_num()
2364 {
2365 return 0;
2366 }
2367
2368 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2369 {
2370 cover("kernel.rtlil.sigspec.parse");
2371
2372 std::vector<std::string> tokens;
2373 sigspec_parse_split(tokens, str, ',');
2374
2375 sig = RTLIL::SigSpec();
2376 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2377 {
2378 std::string netname = tokens[tokidx];
2379 std::string indices;
2380
2381 if (netname.size() == 0)
2382 continue;
2383
2384 if ('0' <= netname[0] && netname[0] <= '9') {
2385 cover("kernel.rtlil.sigspec.parse.const");
2386 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2387 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2388 if (ast == NULL)
2389 return false;
2390 sig.append(RTLIL::Const(ast->bits));
2391 delete ast;
2392 continue;
2393 }
2394
2395 if (module == NULL)
2396 return false;
2397
2398 cover("kernel.rtlil.sigspec.parse.net");
2399
2400 if (netname[0] != '$' && netname[0] != '\\')
2401 netname = "\\" + netname;
2402
2403 if (module->wires.count(netname) == 0) {
2404 size_t indices_pos = netname.size()-1;
2405 if (indices_pos > 2 && netname[indices_pos] == ']')
2406 {
2407 indices_pos--;
2408 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2409 if (indices_pos > 0 && netname[indices_pos] == ':') {
2410 indices_pos--;
2411 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2412 }
2413 if (indices_pos > 0 && netname[indices_pos] == '[') {
2414 indices = netname.substr(indices_pos);
2415 netname = netname.substr(0, indices_pos);
2416 }
2417 }
2418 }
2419
2420 if (module->wires.count(netname) == 0)
2421 return false;
2422
2423 RTLIL::Wire *wire = module->wires.at(netname);
2424 if (!indices.empty()) {
2425 std::vector<std::string> index_tokens;
2426 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2427 if (index_tokens.size() == 1) {
2428 cover("kernel.rtlil.sigspec.parse.bit_sel");
2429 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2430 } else {
2431 cover("kernel.rtlil.sigspec.parse.part_sel");
2432 int a = atoi(index_tokens.at(0).c_str());
2433 int b = atoi(index_tokens.at(1).c_str());
2434 if (a > b) {
2435 int tmp = a;
2436 a = b, b = tmp;
2437 }
2438 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2439 }
2440 } else
2441 sig.append(wire);
2442 }
2443
2444 return true;
2445 }
2446
2447 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2448 {
2449 if (str.empty() || str[0] != '@')
2450 return parse(sig, module, str);
2451
2452 cover("kernel.rtlil.sigspec.parse.sel");
2453
2454 str = RTLIL::escape_id(str.substr(1));
2455 if (design->selection_vars.count(str) == 0)
2456 return false;
2457
2458 sig = RTLIL::SigSpec();
2459 RTLIL::Selection &sel = design->selection_vars.at(str);
2460 for (auto &it : module->wires)
2461 if (sel.selected_member(module->name, it.first))
2462 sig.append(it.second);
2463
2464 return true;
2465 }
2466
2467 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2468 {
2469 if (str == "0") {
2470 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2471 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2472 return true;
2473 }
2474
2475 if (str == "~0") {
2476 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2477 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2478 return true;
2479 }
2480
2481 if (lhs.chunks_.size() == 1) {
2482 char *p = (char*)str.c_str(), *endptr;
2483 long long int val = strtoll(p, &endptr, 10);
2484 if (endptr && endptr != p && *endptr == 0) {
2485 sig = RTLIL::SigSpec(val, lhs.width_);
2486 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2487 return true;
2488 }
2489 }
2490
2491 return parse(sig, module, str);
2492 }
2493
2494 RTLIL::CaseRule::~CaseRule()
2495 {
2496 for (auto it = switches.begin(); it != switches.end(); it++)
2497 delete *it;
2498 }
2499
2500 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2501 {
2502 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2503 new_caserule->compare = compare;
2504 new_caserule->actions = actions;
2505 for (auto &it : switches)
2506 new_caserule->switches.push_back(it->clone());
2507 return new_caserule;
2508 }
2509
2510 RTLIL::SwitchRule::~SwitchRule()
2511 {
2512 for (auto it = cases.begin(); it != cases.end(); it++)
2513 delete *it;
2514 }
2515
2516 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2517 {
2518 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2519 new_switchrule->signal = signal;
2520 new_switchrule->attributes = attributes;
2521 for (auto &it : cases)
2522 new_switchrule->cases.push_back(it->clone());
2523 return new_switchrule;
2524
2525 }
2526
2527 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2528 {
2529 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2530 new_syncrule->type = type;
2531 new_syncrule->signal = signal;
2532 new_syncrule->actions = actions;
2533 return new_syncrule;
2534 }
2535
2536 RTLIL::Process::~Process()
2537 {
2538 for (auto it = syncs.begin(); it != syncs.end(); it++)
2539 delete *it;
2540 }
2541
2542 RTLIL::Process *RTLIL::Process::clone() const
2543 {
2544 RTLIL::Process *new_proc = new RTLIL::Process;
2545
2546 new_proc->name = name;
2547 new_proc->attributes = attributes;
2548
2549 RTLIL::CaseRule *rc_ptr = root_case.clone();
2550 new_proc->root_case = *rc_ptr;
2551 rc_ptr->switches.clear();
2552 delete rc_ptr;
2553
2554 for (auto &it : syncs)
2555 new_proc->syncs.push_back(it->clone());
2556
2557 return new_proc;
2558 }
2559