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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "frontends/verilog/verilog_frontend.h"
23 #include "backends/ilang/ilang_backend.h"
24
25 #include <string.h>
26 #include <algorithm>
27
28 YOSYS_NAMESPACE_BEGIN
29
30 std::vector<int> RTLIL::IdString::global_refcount_storage_;
31 std::vector<char*> RTLIL::IdString::global_id_storage_;
32 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
33 std::vector<int> RTLIL::IdString::global_free_idx_list_;
34
35 RTLIL::Const::Const()
36 {
37 flags = RTLIL::CONST_FLAG_NONE;
38 }
39
40 RTLIL::Const::Const(std::string str)
41 {
42 flags = RTLIL::CONST_FLAG_STRING;
43 for (int i = str.size()-1; i >= 0; i--) {
44 unsigned char ch = str[i];
45 for (int j = 0; j < 8; j++) {
46 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
47 ch = ch >> 1;
48 }
49 }
50 }
51
52 RTLIL::Const::Const(int val, int width)
53 {
54 flags = RTLIL::CONST_FLAG_NONE;
55 for (int i = 0; i < width; i++) {
56 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
57 val = val >> 1;
58 }
59 }
60
61 RTLIL::Const::Const(RTLIL::State bit, int width)
62 {
63 flags = RTLIL::CONST_FLAG_NONE;
64 for (int i = 0; i < width; i++)
65 bits.push_back(bit);
66 }
67
68 RTLIL::Const::Const(const std::vector<bool> &bits)
69 {
70 flags = RTLIL::CONST_FLAG_NONE;
71 for (auto b : bits)
72 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
73 }
74
75 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
76 {
77 if (bits.size() != other.bits.size())
78 return bits.size() < other.bits.size();
79 for (size_t i = 0; i < bits.size(); i++)
80 if (bits[i] != other.bits[i])
81 return bits[i] < other.bits[i];
82 return false;
83 }
84
85 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
86 {
87 return bits == other.bits;
88 }
89
90 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
91 {
92 return bits != other.bits;
93 }
94
95 bool RTLIL::Const::as_bool() const
96 {
97 for (size_t i = 0; i < bits.size(); i++)
98 if (bits[i] == RTLIL::S1)
99 return true;
100 return false;
101 }
102
103 int RTLIL::Const::as_int(bool is_signed) const
104 {
105 int32_t ret = 0;
106 for (size_t i = 0; i < bits.size() && i < 32; i++)
107 if (bits[i] == RTLIL::S1)
108 ret |= 1 << i;
109 if (is_signed && bits.back() == RTLIL::S1)
110 for (size_t i = bits.size(); i < 32; i++)
111 ret |= 1 << i;
112 return ret;
113 }
114
115 std::string RTLIL::Const::as_string() const
116 {
117 std::string ret;
118 for (size_t i = bits.size(); i > 0; i--)
119 switch (bits[i-1]) {
120 case S0: ret += "0"; break;
121 case S1: ret += "1"; break;
122 case Sx: ret += "x"; break;
123 case Sz: ret += "z"; break;
124 case Sa: ret += "-"; break;
125 case Sm: ret += "m"; break;
126 }
127 return ret;
128 }
129
130 std::string RTLIL::Const::decode_string() const
131 {
132 std::string string;
133 std::vector <char> string_chars;
134 for (int i = 0; i < int (bits.size()); i += 8) {
135 char ch = 0;
136 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
137 if (bits[i + j] == RTLIL::State::S1)
138 ch |= 1 << j;
139 if (ch != 0)
140 string_chars.push_back(ch);
141 }
142 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
143 string += string_chars[i];
144 return string;
145 }
146
147 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
148 {
149 if (full_selection)
150 return true;
151 if (selected_modules.count(mod_name) > 0)
152 return true;
153 if (selected_members.count(mod_name) > 0)
154 return true;
155 return false;
156 }
157
158 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
159 {
160 if (full_selection)
161 return true;
162 if (selected_modules.count(mod_name) > 0)
163 return true;
164 return false;
165 }
166
167 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
168 {
169 if (full_selection)
170 return true;
171 if (selected_modules.count(mod_name) > 0)
172 return true;
173 if (selected_members.count(mod_name) > 0)
174 if (selected_members.at(mod_name).count(memb_name) > 0)
175 return true;
176 return false;
177 }
178
179 void RTLIL::Selection::optimize(RTLIL::Design *design)
180 {
181 if (full_selection) {
182 selected_modules.clear();
183 selected_members.clear();
184 return;
185 }
186
187 std::vector<RTLIL::IdString> del_list, add_list;
188
189 del_list.clear();
190 for (auto mod_name : selected_modules) {
191 if (design->modules_.count(mod_name) == 0)
192 del_list.push_back(mod_name);
193 selected_members.erase(mod_name);
194 }
195 for (auto mod_name : del_list)
196 selected_modules.erase(mod_name);
197
198 del_list.clear();
199 for (auto &it : selected_members)
200 if (design->modules_.count(it.first) == 0)
201 del_list.push_back(it.first);
202 for (auto mod_name : del_list)
203 selected_members.erase(mod_name);
204
205 for (auto &it : selected_members) {
206 del_list.clear();
207 for (auto memb_name : it.second)
208 if (design->modules_[it.first]->count_id(memb_name) == 0)
209 del_list.push_back(memb_name);
210 for (auto memb_name : del_list)
211 it.second.erase(memb_name);
212 }
213
214 del_list.clear();
215 add_list.clear();
216 for (auto &it : selected_members)
217 if (it.second.size() == 0)
218 del_list.push_back(it.first);
219 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
220 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
221 add_list.push_back(it.first);
222 for (auto mod_name : del_list)
223 selected_members.erase(mod_name);
224 for (auto mod_name : add_list) {
225 selected_members.erase(mod_name);
226 selected_modules.insert(mod_name);
227 }
228
229 if (selected_modules.size() == design->modules_.size()) {
230 full_selection = true;
231 selected_modules.clear();
232 selected_members.clear();
233 }
234 }
235
236 RTLIL::Design::Design()
237 {
238 refcount_modules_ = 0;
239 selection_stack.push_back(RTLIL::Selection());
240 }
241
242 RTLIL::Design::~Design()
243 {
244 for (auto it = modules_.begin(); it != modules_.end(); it++)
245 delete it->second;
246 }
247
248 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
249 {
250 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
251 }
252
253 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
254 {
255 return modules_.count(name) ? modules_.at(name) : NULL;
256 }
257
258 void RTLIL::Design::add(RTLIL::Module *module)
259 {
260 log_assert(modules_.count(module->name) == 0);
261 log_assert(refcount_modules_ == 0);
262 modules_[module->name] = module;
263 module->design = this;
264
265 for (auto mon : monitors)
266 mon->notify_module_add(module);
267 }
268
269 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
270 {
271 log_assert(modules_.count(name) == 0);
272 log_assert(refcount_modules_ == 0);
273
274 RTLIL::Module *module = new RTLIL::Module;
275 modules_[name] = module;
276 module->design = this;
277 module->name = name;
278
279 for (auto mon : monitors)
280 mon->notify_module_add(module);
281
282 return module;
283 }
284
285 void RTLIL::Design::scratchpad_unset(std::string varname)
286 {
287 scratchpad.erase(varname);
288 }
289
290 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
291 {
292 scratchpad[varname] = stringf("%d", value);
293 }
294
295 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
296 {
297 scratchpad[varname] = value ? "true" : "false";
298 }
299
300 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
301 {
302 scratchpad[varname] = value;
303 }
304
305 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
306 {
307 if (scratchpad.count(varname) == 0)
308 return default_value;
309
310 std::string str = scratchpad.at(varname);
311
312 if (str == "0" || str == "false")
313 return 0;
314
315 if (str == "1" || str == "true")
316 return 1;
317
318 char *endptr = nullptr;
319 long int parsed_value = strtol(str.c_str(), &endptr, 10);
320 return *endptr ? default_value : parsed_value;
321 }
322
323 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
324 {
325 if (scratchpad.count(varname) == 0)
326 return default_value;
327
328 std::string str = scratchpad.at(varname);
329
330 if (str == "0" || str == "false")
331 return false;
332
333 if (str == "1" || str == "true")
334 return true;
335
336 return default_value;
337 }
338
339 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
340 {
341 if (scratchpad.count(varname) == 0)
342 return default_value;
343 return scratchpad.at(varname);
344 }
345
346 void RTLIL::Design::remove(RTLIL::Module *module)
347 {
348 for (auto mon : monitors)
349 mon->notify_module_del(module);
350
351 log_assert(modules_.at(module->name) == module);
352 modules_.erase(module->name);
353 delete module;
354 }
355
356 void RTLIL::Design::check()
357 {
358 #ifndef NDEBUG
359 for (auto &it : modules_) {
360 log_assert(this == it.second->design);
361 log_assert(it.first == it.second->name);
362 log_assert(!it.first.empty());
363 it.second->check();
364 }
365 #endif
366 }
367
368 void RTLIL::Design::optimize()
369 {
370 for (auto &it : modules_)
371 it.second->optimize();
372 for (auto &it : selection_stack)
373 it.optimize(this);
374 for (auto &it : selection_vars)
375 it.second.optimize(this);
376 }
377
378 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
379 {
380 if (!selected_active_module.empty() && mod_name != selected_active_module)
381 return false;
382 if (selection_stack.size() == 0)
383 return true;
384 return selection_stack.back().selected_module(mod_name);
385 }
386
387 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
388 {
389 if (!selected_active_module.empty() && mod_name != selected_active_module)
390 return false;
391 if (selection_stack.size() == 0)
392 return true;
393 return selection_stack.back().selected_whole_module(mod_name);
394 }
395
396 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
397 {
398 if (!selected_active_module.empty() && mod_name != selected_active_module)
399 return false;
400 if (selection_stack.size() == 0)
401 return true;
402 return selection_stack.back().selected_member(mod_name, memb_name);
403 }
404
405 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
406 {
407 return selected_module(mod->name);
408 }
409
410 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
411 {
412 return selected_whole_module(mod->name);
413 }
414
415 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
416 {
417 std::vector<RTLIL::Module*> result;
418 result.reserve(modules_.size());
419 for (auto &it : modules_)
420 if (selected_module(it.first))
421 result.push_back(it.second);
422 return result;
423 }
424
425 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
426 {
427 std::vector<RTLIL::Module*> result;
428 result.reserve(modules_.size());
429 for (auto &it : modules_)
430 if (selected_whole_module(it.first))
431 result.push_back(it.second);
432 return result;
433 }
434
435 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
436 {
437 std::vector<RTLIL::Module*> result;
438 result.reserve(modules_.size());
439 for (auto &it : modules_)
440 if (selected_whole_module(it.first))
441 result.push_back(it.second);
442 else if (selected_module(it.first))
443 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
444 return result;
445 }
446
447 RTLIL::Module::Module()
448 {
449 design = nullptr;
450 refcount_wires_ = 0;
451 refcount_cells_ = 0;
452 }
453
454 RTLIL::Module::~Module()
455 {
456 for (auto it = wires_.begin(); it != wires_.end(); it++)
457 delete it->second;
458 for (auto it = memories.begin(); it != memories.end(); it++)
459 delete it->second;
460 for (auto it = cells_.begin(); it != cells_.end(); it++)
461 delete it->second;
462 for (auto it = processes.begin(); it != processes.end(); it++)
463 delete it->second;
464 }
465
466 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
467 {
468 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
469 }
470
471 size_t RTLIL::Module::count_id(RTLIL::IdString id)
472 {
473 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
474 }
475
476 #ifndef NDEBUG
477 namespace {
478 struct InternalCellChecker
479 {
480 RTLIL::Module *module;
481 RTLIL::Cell *cell;
482 std::set<RTLIL::IdString> expected_params, expected_ports;
483
484 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
485
486 void error(int linenr)
487 {
488 std::stringstream buf;
489 ILANG_BACKEND::dump_cell(buf, " ", cell);
490
491 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
492 module ? module->name.c_str() : "", module ? "." : "",
493 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
494 }
495
496 int param(const char *name)
497 {
498 if (cell->parameters.count(name) == 0)
499 error(__LINE__);
500 expected_params.insert(name);
501 return cell->parameters.at(name).as_int();
502 }
503
504 int param_bool(const char *name)
505 {
506 int v = param(name);
507 if (cell->parameters.at(name).bits.size() > 32)
508 error(__LINE__);
509 if (v != 0 && v != 1)
510 error(__LINE__);
511 return v;
512 }
513
514 void param_bits(const char *name, int width)
515 {
516 param(name);
517 if (int(cell->parameters.at(name).bits.size()) != width)
518 error(__LINE__);
519 }
520
521 void port(const char *name, int width)
522 {
523 if (!cell->hasPort(name))
524 error(__LINE__);
525 if (cell->getPort(name).size() != width)
526 error(__LINE__);
527 expected_ports.insert(name);
528 }
529
530 void check_expected(bool check_matched_sign = true)
531 {
532 for (auto &para : cell->parameters)
533 if (expected_params.count(para.first) == 0)
534 error(__LINE__);
535 for (auto &conn : cell->connections())
536 if (expected_ports.count(conn.first) == 0)
537 error(__LINE__);
538
539 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
540 bool a_is_signed = param("\\A_SIGNED") != 0;
541 bool b_is_signed = param("\\B_SIGNED") != 0;
542 if (a_is_signed != b_is_signed)
543 error(__LINE__);
544 }
545 }
546
547 void check_gate(const char *ports)
548 {
549 if (cell->parameters.size() != 0)
550 error(__LINE__);
551
552 for (const char *p = ports; *p; p++) {
553 char portname[3] = { '\\', *p, 0 };
554 if (!cell->hasPort(portname))
555 error(__LINE__);
556 if (cell->getPort(portname).size() != 1)
557 error(__LINE__);
558 }
559
560 for (auto &conn : cell->connections()) {
561 if (conn.first.size() != 2 || conn.first[0] != '\\')
562 error(__LINE__);
563 if (strchr(ports, conn.first[1]) == NULL)
564 error(__LINE__);
565 }
566 }
567
568 void check()
569 {
570 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
571 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
572 return;
573
574 if (cell->type.in("$not", "$pos", "$neg")) {
575 param_bool("\\A_SIGNED");
576 port("\\A", param("\\A_WIDTH"));
577 port("\\Y", param("\\Y_WIDTH"));
578 check_expected();
579 return;
580 }
581
582 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
583 param_bool("\\A_SIGNED");
584 param_bool("\\B_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\B", param("\\B_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 check_expected();
589 return;
590 }
591
592 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
593 param_bool("\\A_SIGNED");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\Y", param("\\Y_WIDTH"));
596 check_expected();
597 return;
598 }
599
600 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
601 param_bool("\\A_SIGNED");
602 param_bool("\\B_SIGNED");
603 port("\\A", param("\\A_WIDTH"));
604 port("\\B", param("\\B_WIDTH"));
605 port("\\Y", param("\\Y_WIDTH"));
606 check_expected(false);
607 return;
608 }
609
610 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
611 param_bool("\\A_SIGNED");
612 param_bool("\\B_SIGNED");
613 port("\\A", param("\\A_WIDTH"));
614 port("\\B", param("\\B_WIDTH"));
615 port("\\Y", param("\\Y_WIDTH"));
616 check_expected();
617 return;
618 }
619
620 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
621 param_bool("\\A_SIGNED");
622 param_bool("\\B_SIGNED");
623 port("\\A", param("\\A_WIDTH"));
624 port("\\B", param("\\B_WIDTH"));
625 port("\\Y", param("\\Y_WIDTH"));
626 check_expected(cell->type != "$pow");
627 return;
628 }
629
630 if (cell->type == "$fa") {
631 port("\\A", param("\\WIDTH"));
632 port("\\B", param("\\WIDTH"));
633 port("\\C", param("\\WIDTH"));
634 port("\\X", param("\\WIDTH"));
635 port("\\Y", param("\\WIDTH"));
636 check_expected();
637 return;
638 }
639
640 if (cell->type == "$lcu") {
641 port("\\P", param("\\WIDTH"));
642 port("\\G", param("\\WIDTH"));
643 port("\\CI", 1);
644 port("\\CO", param("\\WIDTH"));
645 check_expected();
646 return;
647 }
648
649 if (cell->type == "$alu") {
650 param_bool("\\A_SIGNED");
651 param_bool("\\B_SIGNED");
652 port("\\A", param("\\A_WIDTH"));
653 port("\\B", param("\\B_WIDTH"));
654 port("\\CI", 1);
655 port("\\BI", 1);
656 port("\\X", param("\\Y_WIDTH"));
657 port("\\Y", param("\\Y_WIDTH"));
658 port("\\CO", param("\\Y_WIDTH"));
659 check_expected();
660 return;
661 }
662
663 if (cell->type == "$macc") {
664 param("\\CONFIG");
665 param("\\CONFIG_WIDTH");
666 port("\\A", param("\\A_WIDTH"));
667 port("\\B", param("\\B_WIDTH"));
668 port("\\Y", param("\\Y_WIDTH"));
669 check_expected();
670 Macc().from_cell(cell);
671 return;
672 }
673
674 if (cell->type == "$logic_not") {
675 param_bool("\\A_SIGNED");
676 port("\\A", param("\\A_WIDTH"));
677 port("\\Y", param("\\Y_WIDTH"));
678 check_expected();
679 return;
680 }
681
682 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
683 param_bool("\\A_SIGNED");
684 param_bool("\\B_SIGNED");
685 port("\\A", param("\\A_WIDTH"));
686 port("\\B", param("\\B_WIDTH"));
687 port("\\Y", param("\\Y_WIDTH"));
688 check_expected(false);
689 return;
690 }
691
692 if (cell->type == "$slice") {
693 param("\\OFFSET");
694 port("\\A", param("\\A_WIDTH"));
695 port("\\Y", param("\\Y_WIDTH"));
696 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
697 error(__LINE__);
698 check_expected();
699 return;
700 }
701
702 if (cell->type == "$concat") {
703 port("\\A", param("\\A_WIDTH"));
704 port("\\B", param("\\B_WIDTH"));
705 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
706 check_expected();
707 return;
708 }
709
710 if (cell->type == "$mux") {
711 port("\\A", param("\\WIDTH"));
712 port("\\B", param("\\WIDTH"));
713 port("\\S", 1);
714 port("\\Y", param("\\WIDTH"));
715 check_expected();
716 return;
717 }
718
719 if (cell->type == "$pmux") {
720 port("\\A", param("\\WIDTH"));
721 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
722 port("\\S", param("\\S_WIDTH"));
723 port("\\Y", param("\\WIDTH"));
724 check_expected();
725 return;
726 }
727
728 if (cell->type == "$lut") {
729 param("\\LUT");
730 port("\\A", param("\\WIDTH"));
731 port("\\Y", 1);
732 check_expected();
733 return;
734 }
735
736 if (cell->type == "$sr") {
737 param_bool("\\SET_POLARITY");
738 param_bool("\\CLR_POLARITY");
739 port("\\SET", param("\\WIDTH"));
740 port("\\CLR", param("\\WIDTH"));
741 port("\\Q", param("\\WIDTH"));
742 check_expected();
743 return;
744 }
745
746 if (cell->type == "$dff") {
747 param_bool("\\CLK_POLARITY");
748 port("\\CLK", 1);
749 port("\\D", param("\\WIDTH"));
750 port("\\Q", param("\\WIDTH"));
751 check_expected();
752 return;
753 }
754
755 if (cell->type == "$dffsr") {
756 param_bool("\\CLK_POLARITY");
757 param_bool("\\SET_POLARITY");
758 param_bool("\\CLR_POLARITY");
759 port("\\CLK", 1);
760 port("\\SET", param("\\WIDTH"));
761 port("\\CLR", param("\\WIDTH"));
762 port("\\D", param("\\WIDTH"));
763 port("\\Q", param("\\WIDTH"));
764 check_expected();
765 return;
766 }
767
768 if (cell->type == "$adff") {
769 param_bool("\\CLK_POLARITY");
770 param_bool("\\ARST_POLARITY");
771 param_bits("\\ARST_VALUE", param("\\WIDTH"));
772 port("\\CLK", 1);
773 port("\\ARST", 1);
774 port("\\D", param("\\WIDTH"));
775 port("\\Q", param("\\WIDTH"));
776 check_expected();
777 return;
778 }
779
780 if (cell->type == "$dlatch") {
781 param_bool("\\EN_POLARITY");
782 port("\\EN", 1);
783 port("\\D", param("\\WIDTH"));
784 port("\\Q", param("\\WIDTH"));
785 check_expected();
786 return;
787 }
788
789 if (cell->type == "$dlatchsr") {
790 param_bool("\\EN_POLARITY");
791 param_bool("\\SET_POLARITY");
792 param_bool("\\CLR_POLARITY");
793 port("\\EN", 1);
794 port("\\SET", param("\\WIDTH"));
795 port("\\CLR", param("\\WIDTH"));
796 port("\\D", param("\\WIDTH"));
797 port("\\Q", param("\\WIDTH"));
798 check_expected();
799 return;
800 }
801
802 if (cell->type == "$fsm") {
803 param("\\NAME");
804 param_bool("\\CLK_POLARITY");
805 param_bool("\\ARST_POLARITY");
806 param("\\STATE_BITS");
807 param("\\STATE_NUM");
808 param("\\STATE_NUM_LOG2");
809 param("\\STATE_RST");
810 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
811 param("\\TRANS_NUM");
812 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
813 port("\\CLK", 1);
814 port("\\ARST", 1);
815 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
816 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
817 check_expected();
818 return;
819 }
820
821 if (cell->type == "$memrd") {
822 param("\\MEMID");
823 param_bool("\\CLK_ENABLE");
824 param_bool("\\CLK_POLARITY");
825 param_bool("\\TRANSPARENT");
826 port("\\CLK", 1);
827 port("\\ADDR", param("\\ABITS"));
828 port("\\DATA", param("\\WIDTH"));
829 check_expected();
830 return;
831 }
832
833 if (cell->type == "$memwr") {
834 param("\\MEMID");
835 param_bool("\\CLK_ENABLE");
836 param_bool("\\CLK_POLARITY");
837 param("\\PRIORITY");
838 port("\\CLK", 1);
839 port("\\EN", param("\\WIDTH"));
840 port("\\ADDR", param("\\ABITS"));
841 port("\\DATA", param("\\WIDTH"));
842 check_expected();
843 return;
844 }
845
846 if (cell->type == "$mem") {
847 param("\\MEMID");
848 param("\\SIZE");
849 param("\\OFFSET");
850 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
851 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
852 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
853 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
854 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
855 port("\\RD_CLK", param("\\RD_PORTS"));
856 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
857 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
858 port("\\WR_CLK", param("\\WR_PORTS"));
859 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
860 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
861 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
862 check_expected();
863 return;
864 }
865
866 if (cell->type == "$assert") {
867 port("\\A", 1);
868 port("\\EN", 1);
869 check_expected();
870 return;
871 }
872
873 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
874 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
875 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
876 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
877 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
878 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
879 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
880 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
881 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
882 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
883 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
884 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
885
886 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
887 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
888 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
889 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
890
891 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
892 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
893
894 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
895 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
896 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
897 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
898 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
899 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
900 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
901 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
902
903 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
904 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
905 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
906 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
907 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
908 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
909 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
910 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
911
912 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
913 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
914
915 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
916 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
917 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
918 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
919 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
920 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
921 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
922 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
923
924 error(__LINE__);
925 }
926 };
927 }
928 #endif
929
930 void RTLIL::Module::check()
931 {
932 #ifndef NDEBUG
933 std::vector<bool> ports_declared;
934 for (auto &it : wires_) {
935 log_assert(this == it.second->module);
936 log_assert(it.first == it.second->name);
937 log_assert(!it.first.empty());
938 log_assert(it.second->width >= 0);
939 log_assert(it.second->port_id >= 0);
940 for (auto &it2 : it.second->attributes)
941 log_assert(!it2.first.empty());
942 if (it.second->port_id) {
943 log_assert(SIZE(ports) >= it.second->port_id);
944 log_assert(ports.at(it.second->port_id-1) == it.first);
945 log_assert(it.second->port_input || it.second->port_output);
946 if (SIZE(ports_declared) < it.second->port_id)
947 ports_declared.resize(it.second->port_id);
948 log_assert(ports_declared[it.second->port_id-1] == false);
949 ports_declared[it.second->port_id-1] = true;
950 } else
951 log_assert(!it.second->port_input && !it.second->port_output);
952 }
953 for (auto port_declared : ports_declared)
954 log_assert(port_declared == true);
955 log_assert(SIZE(ports) == SIZE(ports_declared));
956
957 for (auto &it : memories) {
958 log_assert(it.first == it.second->name);
959 log_assert(!it.first.empty());
960 log_assert(it.second->width >= 0);
961 log_assert(it.second->size >= 0);
962 for (auto &it2 : it.second->attributes)
963 log_assert(!it2.first.empty());
964 }
965
966 for (auto &it : cells_) {
967 log_assert(this == it.second->module);
968 log_assert(it.first == it.second->name);
969 log_assert(!it.first.empty());
970 log_assert(!it.second->type.empty());
971 for (auto &it2 : it.second->connections()) {
972 log_assert(!it2.first.empty());
973 it2.second.check();
974 }
975 for (auto &it2 : it.second->attributes)
976 log_assert(!it2.first.empty());
977 for (auto &it2 : it.second->parameters)
978 log_assert(!it2.first.empty());
979 InternalCellChecker checker(this, it.second);
980 checker.check();
981 }
982
983 for (auto &it : processes) {
984 log_assert(it.first == it.second->name);
985 log_assert(!it.first.empty());
986 // FIXME: More checks here..
987 }
988
989 for (auto &it : connections_) {
990 log_assert(it.first.size() == it.second.size());
991 it.first.check();
992 it.second.check();
993 }
994
995 for (auto &it : attributes)
996 log_assert(!it.first.empty());
997 #endif
998 }
999
1000 void RTLIL::Module::optimize()
1001 {
1002 }
1003
1004 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1005 {
1006 log_assert(new_mod->refcount_wires_ == 0);
1007 log_assert(new_mod->refcount_cells_ == 0);
1008
1009 new_mod->connections_ = connections_;
1010 new_mod->attributes = attributes;
1011
1012 for (auto &it : wires_)
1013 new_mod->addWire(it.first, it.second);
1014
1015 for (auto &it : memories)
1016 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1017
1018 for (auto &it : cells_)
1019 new_mod->addCell(it.first, it.second);
1020
1021 for (auto &it : processes)
1022 new_mod->processes[it.first] = it.second->clone();
1023
1024 struct RewriteSigSpecWorker
1025 {
1026 RTLIL::Module *mod;
1027 void operator()(RTLIL::SigSpec &sig)
1028 {
1029 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1030 for (auto &c : chunks)
1031 if (c.wire != NULL)
1032 c.wire = mod->wires_.at(c.wire->name);
1033 sig = chunks;
1034 }
1035 };
1036
1037 RewriteSigSpecWorker rewriteSigSpecWorker;
1038 rewriteSigSpecWorker.mod = new_mod;
1039 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1040 new_mod->fixup_ports();
1041 }
1042
1043 RTLIL::Module *RTLIL::Module::clone() const
1044 {
1045 RTLIL::Module *new_mod = new RTLIL::Module;
1046 new_mod->name = name;
1047 cloneInto(new_mod);
1048 return new_mod;
1049 }
1050
1051 bool RTLIL::Module::has_memories() const
1052 {
1053 return !memories.empty();
1054 }
1055
1056 bool RTLIL::Module::has_processes() const
1057 {
1058 return !processes.empty();
1059 }
1060
1061 bool RTLIL::Module::has_memories_warn() const
1062 {
1063 if (!memories.empty())
1064 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1065 return !memories.empty();
1066 }
1067
1068 bool RTLIL::Module::has_processes_warn() const
1069 {
1070 if (!processes.empty())
1071 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1072 return !processes.empty();
1073 }
1074
1075 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1076 {
1077 std::vector<RTLIL::Wire*> result;
1078 result.reserve(wires_.size());
1079 for (auto &it : wires_)
1080 if (design->selected(this, it.second))
1081 result.push_back(it.second);
1082 return result;
1083 }
1084
1085 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1086 {
1087 std::vector<RTLIL::Cell*> result;
1088 result.reserve(wires_.size());
1089 for (auto &it : cells_)
1090 if (design->selected(this, it.second))
1091 result.push_back(it.second);
1092 return result;
1093 }
1094
1095 void RTLIL::Module::add(RTLIL::Wire *wire)
1096 {
1097 log_assert(!wire->name.empty());
1098 log_assert(count_id(wire->name) == 0);
1099 log_assert(refcount_wires_ == 0);
1100 wires_[wire->name] = wire;
1101 wire->module = this;
1102 }
1103
1104 void RTLIL::Module::add(RTLIL::Cell *cell)
1105 {
1106 log_assert(!cell->name.empty());
1107 log_assert(count_id(cell->name) == 0);
1108 log_assert(refcount_cells_ == 0);
1109 cells_[cell->name] = cell;
1110 cell->module = this;
1111 }
1112
1113 namespace {
1114 struct DeleteWireWorker
1115 {
1116 RTLIL::Module *module;
1117 const std::set<RTLIL::Wire*> *wires_p;
1118
1119 void operator()(RTLIL::SigSpec &sig) {
1120 std::vector<RTLIL::SigChunk> chunks = sig;
1121 for (auto &c : chunks)
1122 if (c.wire != NULL && wires_p->count(c.wire)) {
1123 c.wire = module->addWire(NEW_ID, c.width);
1124 c.offset = 0;
1125 }
1126 sig = chunks;
1127 }
1128 };
1129 }
1130
1131 #if 0
1132 void RTLIL::Module::remove(RTLIL::Wire *wire)
1133 {
1134 std::setPort<RTLIL::Wire*> wires_;
1135 wires_.insert(wire);
1136 remove(wires_);
1137 }
1138 #endif
1139
1140 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1141 {
1142 log_assert(refcount_wires_ == 0);
1143
1144 DeleteWireWorker delete_wire_worker;
1145 delete_wire_worker.module = this;
1146 delete_wire_worker.wires_p = &wires;
1147 rewrite_sigspecs(delete_wire_worker);
1148
1149 for (auto &it : wires) {
1150 log_assert(wires_.count(it->name) != 0);
1151 wires_.erase(it->name);
1152 delete it;
1153 }
1154 }
1155
1156 void RTLIL::Module::remove(RTLIL::Cell *cell)
1157 {
1158 while (!cell->connections_.empty())
1159 cell->unsetPort(cell->connections_.begin()->first);
1160
1161 log_assert(cells_.count(cell->name) != 0);
1162 log_assert(refcount_cells_ == 0);
1163 cells_.erase(cell->name);
1164 delete cell;
1165 }
1166
1167 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1168 {
1169 log_assert(wires_[wire->name] == wire);
1170 log_assert(refcount_wires_ == 0);
1171 wires_.erase(wire->name);
1172 wire->name = new_name;
1173 add(wire);
1174 }
1175
1176 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1177 {
1178 log_assert(cells_[cell->name] == cell);
1179 log_assert(refcount_wires_ == 0);
1180 cells_.erase(cell->name);
1181 cell->name = new_name;
1182 add(cell);
1183 }
1184
1185 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1186 {
1187 log_assert(count_id(old_name) != 0);
1188 if (wires_.count(old_name))
1189 rename(wires_.at(old_name), new_name);
1190 else if (cells_.count(old_name))
1191 rename(cells_.at(old_name), new_name);
1192 else
1193 log_abort();
1194 }
1195
1196 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1197 {
1198 log_assert(wires_[w1->name] == w1);
1199 log_assert(wires_[w2->name] == w2);
1200 log_assert(refcount_wires_ == 0);
1201
1202 wires_.erase(w1->name);
1203 wires_.erase(w2->name);
1204
1205 std::swap(w1->name, w2->name);
1206
1207 wires_[w1->name] = w1;
1208 wires_[w2->name] = w2;
1209 }
1210
1211 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1212 {
1213 log_assert(cells_[c1->name] == c1);
1214 log_assert(cells_[c2->name] == c2);
1215 log_assert(refcount_cells_ == 0);
1216
1217 cells_.erase(c1->name);
1218 cells_.erase(c2->name);
1219
1220 std::swap(c1->name, c2->name);
1221
1222 cells_[c1->name] = c1;
1223 cells_[c2->name] = c2;
1224 }
1225
1226 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1227 {
1228 int index = 0;
1229 return uniquify(name, index);
1230 }
1231
1232 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1233 {
1234 if (index == 0) {
1235 if (count_id(name) == 0)
1236 return name;
1237 index++;
1238 }
1239
1240 while (1) {
1241 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1242 if (count_id(new_name) == 0)
1243 return new_name;
1244 index++;
1245 }
1246 }
1247
1248 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1249 {
1250 if (a->port_id && !b->port_id)
1251 return true;
1252 if (!a->port_id && b->port_id)
1253 return false;
1254
1255 if (a->port_id == b->port_id)
1256 return a->name < b->name;
1257 return a->port_id < b->port_id;
1258 }
1259
1260 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1261 {
1262 for (auto mon : monitors)
1263 mon->notify_connect(this, conn);
1264
1265 if (design)
1266 for (auto mon : design->monitors)
1267 mon->notify_connect(this, conn);
1268
1269 connections_.push_back(conn);
1270 }
1271
1272 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1273 {
1274 connect(RTLIL::SigSig(lhs, rhs));
1275 }
1276
1277 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1278 {
1279 for (auto mon : monitors)
1280 mon->notify_connect(this, new_conn);
1281
1282 if (design)
1283 for (auto mon : design->monitors)
1284 mon->notify_connect(this, new_conn);
1285
1286 connections_ = new_conn;
1287 }
1288
1289 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1290 {
1291 return connections_;
1292 }
1293
1294 void RTLIL::Module::fixup_ports()
1295 {
1296 std::vector<RTLIL::Wire*> all_ports;
1297
1298 for (auto &w : wires_)
1299 if (w.second->port_input || w.second->port_output)
1300 all_ports.push_back(w.second);
1301 else
1302 w.second->port_id = 0;
1303
1304 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1305
1306 ports.clear();
1307 for (size_t i = 0; i < all_ports.size(); i++) {
1308 ports.push_back(all_ports[i]->name);
1309 all_ports[i]->port_id = i+1;
1310 }
1311 }
1312
1313 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1314 {
1315 RTLIL::Wire *wire = new RTLIL::Wire;
1316 wire->name = name;
1317 wire->width = width;
1318 add(wire);
1319 return wire;
1320 }
1321
1322 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1323 {
1324 RTLIL::Wire *wire = addWire(name);
1325 wire->width = other->width;
1326 wire->start_offset = other->start_offset;
1327 wire->port_id = other->port_id;
1328 wire->port_input = other->port_input;
1329 wire->port_output = other->port_output;
1330 wire->upto = other->upto;
1331 wire->attributes = other->attributes;
1332 return wire;
1333 }
1334
1335 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1336 {
1337 RTLIL::Cell *cell = new RTLIL::Cell;
1338 cell->name = name;
1339 cell->type = type;
1340 add(cell);
1341 return cell;
1342 }
1343
1344 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1345 {
1346 RTLIL::Cell *cell = addCell(name, other->type);
1347 cell->connections_ = other->connections_;
1348 cell->parameters = other->parameters;
1349 cell->attributes = other->attributes;
1350 return cell;
1351 }
1352
1353 #define DEF_METHOD(_func, _y_size, _type) \
1354 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1355 RTLIL::Cell *cell = addCell(name, _type); \
1356 cell->parameters["\\A_SIGNED"] = is_signed; \
1357 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1358 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1359 cell->setPort("\\A", sig_a); \
1360 cell->setPort("\\Y", sig_y); \
1361 return cell; \
1362 } \
1363 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1364 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1365 add ## _func(name, sig_a, sig_y, is_signed); \
1366 return sig_y; \
1367 }
1368 DEF_METHOD(Not, sig_a.size(), "$not")
1369 DEF_METHOD(Pos, sig_a.size(), "$pos")
1370 DEF_METHOD(Neg, sig_a.size(), "$neg")
1371 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1372 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1373 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1374 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1375 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1376 DEF_METHOD(LogicNot, 1, "$logic_not")
1377 #undef DEF_METHOD
1378
1379 #define DEF_METHOD(_func, _y_size, _type) \
1380 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1381 RTLIL::Cell *cell = addCell(name, _type); \
1382 cell->parameters["\\A_SIGNED"] = is_signed; \
1383 cell->parameters["\\B_SIGNED"] = is_signed; \
1384 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1385 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1386 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1387 cell->setPort("\\A", sig_a); \
1388 cell->setPort("\\B", sig_b); \
1389 cell->setPort("\\Y", sig_y); \
1390 return cell; \
1391 } \
1392 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1393 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1394 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1395 return sig_y; \
1396 }
1397 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1398 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1399 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1400 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1401 DEF_METHOD(Shl, sig_a.size(), "$shl")
1402 DEF_METHOD(Shr, sig_a.size(), "$shr")
1403 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1404 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1405 DEF_METHOD(Shift, sig_a.size(), "$shift")
1406 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1407 DEF_METHOD(Lt, 1, "$lt")
1408 DEF_METHOD(Le, 1, "$le")
1409 DEF_METHOD(Eq, 1, "$eq")
1410 DEF_METHOD(Ne, 1, "$ne")
1411 DEF_METHOD(Eqx, 1, "$eqx")
1412 DEF_METHOD(Nex, 1, "$nex")
1413 DEF_METHOD(Ge, 1, "$ge")
1414 DEF_METHOD(Gt, 1, "$gt")
1415 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1416 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1417 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1418 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1419 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1420 DEF_METHOD(LogicAnd, 1, "$logic_and")
1421 DEF_METHOD(LogicOr, 1, "$logic_or")
1422 #undef DEF_METHOD
1423
1424 #define DEF_METHOD(_func, _type, _pmux) \
1425 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1426 RTLIL::Cell *cell = addCell(name, _type); \
1427 cell->parameters["\\WIDTH"] = sig_a.size(); \
1428 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1429 cell->setPort("\\A", sig_a); \
1430 cell->setPort("\\B", sig_b); \
1431 cell->setPort("\\S", sig_s); \
1432 cell->setPort("\\Y", sig_y); \
1433 return cell; \
1434 } \
1435 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1436 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1437 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1438 return sig_y; \
1439 }
1440 DEF_METHOD(Mux, "$mux", 0)
1441 DEF_METHOD(Pmux, "$pmux", 1)
1442 #undef DEF_METHOD
1443
1444 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1445 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1446 RTLIL::Cell *cell = addCell(name, _type); \
1447 cell->setPort("\\" #_P1, sig1); \
1448 cell->setPort("\\" #_P2, sig2); \
1449 return cell; \
1450 } \
1451 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1452 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1453 add ## _func(name, sig1, sig2); \
1454 return sig2; \
1455 }
1456 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1457 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1458 RTLIL::Cell *cell = addCell(name, _type); \
1459 cell->setPort("\\" #_P1, sig1); \
1460 cell->setPort("\\" #_P2, sig2); \
1461 cell->setPort("\\" #_P3, sig3); \
1462 return cell; \
1463 } \
1464 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1465 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1466 add ## _func(name, sig1, sig2, sig3); \
1467 return sig3; \
1468 }
1469 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1470 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1471 RTLIL::Cell *cell = addCell(name, _type); \
1472 cell->setPort("\\" #_P1, sig1); \
1473 cell->setPort("\\" #_P2, sig2); \
1474 cell->setPort("\\" #_P3, sig3); \
1475 cell->setPort("\\" #_P4, sig4); \
1476 return cell; \
1477 } \
1478 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1479 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1480 add ## _func(name, sig1, sig2, sig3, sig4); \
1481 return sig4; \
1482 }
1483 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1484 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1485 RTLIL::Cell *cell = addCell(name, _type); \
1486 cell->setPort("\\" #_P1, sig1); \
1487 cell->setPort("\\" #_P2, sig2); \
1488 cell->setPort("\\" #_P3, sig3); \
1489 cell->setPort("\\" #_P4, sig4); \
1490 cell->setPort("\\" #_P5, sig5); \
1491 return cell; \
1492 } \
1493 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1494 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1495 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1496 return sig5; \
1497 }
1498 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1499 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1500 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1501 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1502 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1503 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1504 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1505 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1506 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1507 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1508 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1509 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1510 #undef DEF_METHOD_2
1511 #undef DEF_METHOD_3
1512 #undef DEF_METHOD_4
1513 #undef DEF_METHOD_5
1514
1515 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1516 {
1517 RTLIL::Cell *cell = addCell(name, "$pow");
1518 cell->parameters["\\A_SIGNED"] = a_signed;
1519 cell->parameters["\\B_SIGNED"] = b_signed;
1520 cell->parameters["\\A_WIDTH"] = sig_a.size();
1521 cell->parameters["\\B_WIDTH"] = sig_b.size();
1522 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1523 cell->setPort("\\A", sig_a);
1524 cell->setPort("\\B", sig_b);
1525 cell->setPort("\\Y", sig_y);
1526 return cell;
1527 }
1528
1529 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1530 {
1531 RTLIL::Cell *cell = addCell(name, "$slice");
1532 cell->parameters["\\A_WIDTH"] = sig_a.size();
1533 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1534 cell->parameters["\\OFFSET"] = offset;
1535 cell->setPort("\\A", sig_a);
1536 cell->setPort("\\Y", sig_y);
1537 return cell;
1538 }
1539
1540 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1541 {
1542 RTLIL::Cell *cell = addCell(name, "$concat");
1543 cell->parameters["\\A_WIDTH"] = sig_a.size();
1544 cell->parameters["\\B_WIDTH"] = sig_b.size();
1545 cell->setPort("\\A", sig_a);
1546 cell->setPort("\\B", sig_b);
1547 cell->setPort("\\Y", sig_y);
1548 return cell;
1549 }
1550
1551 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1552 {
1553 RTLIL::Cell *cell = addCell(name, "$lut");
1554 cell->parameters["\\LUT"] = lut;
1555 cell->parameters["\\WIDTH"] = sig_i.size();
1556 cell->setPort("\\A", sig_i);
1557 cell->setPort("\\Y", sig_o);
1558 return cell;
1559 }
1560
1561 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1562 {
1563 RTLIL::Cell *cell = addCell(name, "$assert");
1564 cell->setPort("\\A", sig_a);
1565 cell->setPort("\\EN", sig_en);
1566 return cell;
1567 }
1568
1569 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1570 {
1571 RTLIL::Cell *cell = addCell(name, "$sr");
1572 cell->parameters["\\SET_POLARITY"] = set_polarity;
1573 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1574 cell->parameters["\\WIDTH"] = sig_q.size();
1575 cell->setPort("\\SET", sig_set);
1576 cell->setPort("\\CLR", sig_clr);
1577 cell->setPort("\\Q", sig_q);
1578 return cell;
1579 }
1580
1581 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1582 {
1583 RTLIL::Cell *cell = addCell(name, "$dff");
1584 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1585 cell->parameters["\\WIDTH"] = sig_q.size();
1586 cell->setPort("\\CLK", sig_clk);
1587 cell->setPort("\\D", sig_d);
1588 cell->setPort("\\Q", sig_q);
1589 return cell;
1590 }
1591
1592 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1593 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1594 {
1595 RTLIL::Cell *cell = addCell(name, "$dffsr");
1596 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1597 cell->parameters["\\SET_POLARITY"] = set_polarity;
1598 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1599 cell->parameters["\\WIDTH"] = sig_q.size();
1600 cell->setPort("\\CLK", sig_clk);
1601 cell->setPort("\\SET", sig_set);
1602 cell->setPort("\\CLR", sig_clr);
1603 cell->setPort("\\D", sig_d);
1604 cell->setPort("\\Q", sig_q);
1605 return cell;
1606 }
1607
1608 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1609 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1610 {
1611 RTLIL::Cell *cell = addCell(name, "$adff");
1612 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1613 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1614 cell->parameters["\\ARST_VALUE"] = arst_value;
1615 cell->parameters["\\WIDTH"] = sig_q.size();
1616 cell->setPort("\\CLK", sig_clk);
1617 cell->setPort("\\ARST", sig_arst);
1618 cell->setPort("\\D", sig_d);
1619 cell->setPort("\\Q", sig_q);
1620 return cell;
1621 }
1622
1623 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1624 {
1625 RTLIL::Cell *cell = addCell(name, "$dlatch");
1626 cell->parameters["\\EN_POLARITY"] = en_polarity;
1627 cell->parameters["\\WIDTH"] = sig_q.size();
1628 cell->setPort("\\EN", sig_en);
1629 cell->setPort("\\D", sig_d);
1630 cell->setPort("\\Q", sig_q);
1631 return cell;
1632 }
1633
1634 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1635 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1636 {
1637 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1638 cell->parameters["\\EN_POLARITY"] = en_polarity;
1639 cell->parameters["\\SET_POLARITY"] = set_polarity;
1640 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1641 cell->parameters["\\WIDTH"] = sig_q.size();
1642 cell->setPort("\\EN", sig_en);
1643 cell->setPort("\\SET", sig_set);
1644 cell->setPort("\\CLR", sig_clr);
1645 cell->setPort("\\D", sig_d);
1646 cell->setPort("\\Q", sig_q);
1647 return cell;
1648 }
1649
1650 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1651 {
1652 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1653 cell->setPort("\\C", sig_clk);
1654 cell->setPort("\\D", sig_d);
1655 cell->setPort("\\Q", sig_q);
1656 return cell;
1657 }
1658
1659 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1660 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1661 {
1662 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1663 cell->setPort("\\C", sig_clk);
1664 cell->setPort("\\S", sig_set);
1665 cell->setPort("\\R", sig_clr);
1666 cell->setPort("\\D", sig_d);
1667 cell->setPort("\\Q", sig_q);
1668 return cell;
1669 }
1670
1671 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1672 bool arst_value, bool clk_polarity, bool arst_polarity)
1673 {
1674 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1675 cell->setPort("\\C", sig_clk);
1676 cell->setPort("\\R", sig_arst);
1677 cell->setPort("\\D", sig_d);
1678 cell->setPort("\\Q", sig_q);
1679 return cell;
1680 }
1681
1682 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1683 {
1684 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1685 cell->setPort("\\E", sig_en);
1686 cell->setPort("\\D", sig_d);
1687 cell->setPort("\\Q", sig_q);
1688 return cell;
1689 }
1690
1691 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1692 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1693 {
1694 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1695 cell->setPort("\\E", sig_en);
1696 cell->setPort("\\S", sig_set);
1697 cell->setPort("\\R", sig_clr);
1698 cell->setPort("\\D", sig_d);
1699 cell->setPort("\\Q", sig_q);
1700 return cell;
1701 }
1702
1703
1704 RTLIL::Wire::Wire()
1705 {
1706 module = nullptr;
1707 width = 1;
1708 start_offset = 0;
1709 port_id = 0;
1710 port_input = false;
1711 port_output = false;
1712 upto = false;
1713 }
1714
1715 RTLIL::Memory::Memory()
1716 {
1717 width = 1;
1718 size = 0;
1719 }
1720
1721 RTLIL::Cell::Cell() : module(nullptr)
1722 {
1723 }
1724
1725 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1726 {
1727 return connections_.count(portname) != 0;
1728 }
1729
1730 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1731 {
1732 RTLIL::SigSpec signal;
1733 auto conn_it = connections_.find(portname);
1734
1735 if (conn_it != connections_.end())
1736 {
1737 for (auto mon : module->monitors)
1738 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1739
1740 if (module->design)
1741 for (auto mon : module->design->monitors)
1742 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1743
1744 connections_.erase(conn_it);
1745 }
1746 }
1747
1748 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1749 {
1750 auto conn_it = connections_.find(portname);
1751
1752 if (conn_it == connections_.end()) {
1753 connections_[portname] = RTLIL::SigSpec();
1754 conn_it = connections_.find(portname);
1755 log_assert(conn_it != connections_.end());
1756 }
1757
1758 for (auto mon : module->monitors)
1759 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1760
1761 if (module->design)
1762 for (auto mon : module->design->monitors)
1763 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1764
1765 conn_it->second = signal;
1766 }
1767
1768 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1769 {
1770 return connections_.at(portname);
1771 }
1772
1773 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1774 {
1775 return connections_;
1776 }
1777
1778 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1779 {
1780 return parameters.count(paramname);
1781 }
1782
1783 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1784 {
1785 parameters.erase(paramname);
1786 }
1787
1788 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1789 {
1790 parameters[paramname] = value;
1791 }
1792
1793 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1794 {
1795 return parameters.at(paramname);
1796 }
1797
1798 void RTLIL::Cell::check()
1799 {
1800 #ifndef NDEBUG
1801 InternalCellChecker checker(NULL, this);
1802 checker.check();
1803 #endif
1804 }
1805
1806 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1807 {
1808 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1809 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1810 return;
1811
1812 if (type == "$mux" || type == "$pmux") {
1813 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1814 if (type == "$pmux")
1815 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1816 check();
1817 return;
1818 }
1819
1820 if (type == "$lut") {
1821 parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
1822 return;
1823 }
1824
1825 if (type == "$fa") {
1826 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1827 return;
1828 }
1829
1830 if (type == "$lcu") {
1831 parameters["\\WIDTH"] = SIZE(connections_["\\CO"]);
1832 return;
1833 }
1834
1835 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
1836
1837 if (connections_.count("\\A")) {
1838 if (signedness_ab) {
1839 if (set_a_signed)
1840 parameters["\\A_SIGNED"] = true;
1841 else if (parameters.count("\\A_SIGNED") == 0)
1842 parameters["\\A_SIGNED"] = false;
1843 }
1844 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1845 }
1846
1847 if (connections_.count("\\B")) {
1848 if (signedness_ab) {
1849 if (set_b_signed)
1850 parameters["\\B_SIGNED"] = true;
1851 else if (parameters.count("\\B_SIGNED") == 0)
1852 parameters["\\B_SIGNED"] = false;
1853 }
1854 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1855 }
1856
1857 if (connections_.count("\\Y"))
1858 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1859
1860 check();
1861 }
1862
1863 RTLIL::SigChunk::SigChunk()
1864 {
1865 wire = NULL;
1866 width = 0;
1867 offset = 0;
1868 }
1869
1870 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1871 {
1872 wire = NULL;
1873 data = value.bits;
1874 width = SIZE(data);
1875 offset = 0;
1876 }
1877
1878 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1879 {
1880 log_assert(wire != nullptr);
1881 this->wire = wire;
1882 this->width = wire->width;
1883 this->offset = 0;
1884 }
1885
1886 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1887 {
1888 log_assert(wire != nullptr);
1889 this->wire = wire;
1890 this->width = width;
1891 this->offset = offset;
1892 }
1893
1894 RTLIL::SigChunk::SigChunk(const std::string &str)
1895 {
1896 wire = NULL;
1897 data = RTLIL::Const(str).bits;
1898 width = SIZE(data);
1899 offset = 0;
1900 }
1901
1902 RTLIL::SigChunk::SigChunk(int val, int width)
1903 {
1904 wire = NULL;
1905 data = RTLIL::Const(val, width).bits;
1906 this->width = SIZE(data);
1907 offset = 0;
1908 }
1909
1910 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1911 {
1912 wire = NULL;
1913 data = RTLIL::Const(bit, width).bits;
1914 this->width = SIZE(data);
1915 offset = 0;
1916 }
1917
1918 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1919 {
1920 wire = bit.wire;
1921 offset = 0;
1922 if (wire == NULL)
1923 data = RTLIL::Const(bit.data).bits;
1924 else
1925 offset = bit.offset;
1926 width = 1;
1927 }
1928
1929 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1930 {
1931 RTLIL::SigChunk ret;
1932 if (wire) {
1933 ret.wire = wire;
1934 ret.offset = this->offset + offset;
1935 ret.width = length;
1936 } else {
1937 for (int i = 0; i < length; i++)
1938 ret.data.push_back(data[offset+i]);
1939 ret.width = length;
1940 }
1941 return ret;
1942 }
1943
1944 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1945 {
1946 if (wire && other.wire)
1947 if (wire->name != other.wire->name)
1948 return wire->name < other.wire->name;
1949
1950 if (wire != other.wire)
1951 return wire < other.wire;
1952
1953 if (offset != other.offset)
1954 return offset < other.offset;
1955
1956 if (width != other.width)
1957 return width < other.width;
1958
1959 return data < other.data;
1960 }
1961
1962 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1963 {
1964 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
1965 }
1966
1967 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1968 {
1969 if (*this == other)
1970 return false;
1971 return true;
1972 }
1973
1974 RTLIL::SigSpec::SigSpec()
1975 {
1976 width_ = 0;
1977 hash_ = 0;
1978 }
1979
1980 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1981 {
1982 *this = other;
1983 }
1984
1985 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1986 {
1987 cover("kernel.rtlil.sigspec.init.list");
1988
1989 width_ = 0;
1990 hash_ = 0;
1991
1992 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1993 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1994 append(*it);
1995 }
1996
1997 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1998 {
1999 cover("kernel.rtlil.sigspec.assign");
2000
2001 width_ = other.width_;
2002 hash_ = other.hash_;
2003 chunks_ = other.chunks_;
2004 bits_.clear();
2005
2006 if (!other.bits_.empty())
2007 {
2008 RTLIL::SigChunk *last = NULL;
2009 int last_end_offset = 0;
2010
2011 for (auto &bit : other.bits_) {
2012 if (last && bit.wire == last->wire) {
2013 if (bit.wire == NULL) {
2014 last->data.push_back(bit.data);
2015 last->width++;
2016 continue;
2017 } else if (last_end_offset == bit.offset) {
2018 last_end_offset++;
2019 last->width++;
2020 continue;
2021 }
2022 }
2023 chunks_.push_back(bit);
2024 last = &chunks_.back();
2025 last_end_offset = bit.offset + 1;
2026 }
2027
2028 check();
2029 }
2030
2031 return *this;
2032 }
2033
2034 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2035 {
2036 cover("kernel.rtlil.sigspec.init.const");
2037
2038 chunks_.push_back(RTLIL::SigChunk(value));
2039 width_ = chunks_.back().width;
2040 hash_ = 0;
2041 check();
2042 }
2043
2044 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2045 {
2046 cover("kernel.rtlil.sigspec.init.chunk");
2047
2048 chunks_.push_back(chunk);
2049 width_ = chunks_.back().width;
2050 hash_ = 0;
2051 check();
2052 }
2053
2054 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2055 {
2056 cover("kernel.rtlil.sigspec.init.wire");
2057
2058 chunks_.push_back(RTLIL::SigChunk(wire));
2059 width_ = chunks_.back().width;
2060 hash_ = 0;
2061 check();
2062 }
2063
2064 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2065 {
2066 cover("kernel.rtlil.sigspec.init.wire_part");
2067
2068 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2069 width_ = chunks_.back().width;
2070 hash_ = 0;
2071 check();
2072 }
2073
2074 RTLIL::SigSpec::SigSpec(const std::string &str)
2075 {
2076 cover("kernel.rtlil.sigspec.init.str");
2077
2078 chunks_.push_back(RTLIL::SigChunk(str));
2079 width_ = chunks_.back().width;
2080 hash_ = 0;
2081 check();
2082 }
2083
2084 RTLIL::SigSpec::SigSpec(int val, int width)
2085 {
2086 cover("kernel.rtlil.sigspec.init.int");
2087
2088 chunks_.push_back(RTLIL::SigChunk(val, width));
2089 width_ = width;
2090 hash_ = 0;
2091 check();
2092 }
2093
2094 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2095 {
2096 cover("kernel.rtlil.sigspec.init.state");
2097
2098 chunks_.push_back(RTLIL::SigChunk(bit, width));
2099 width_ = width;
2100 hash_ = 0;
2101 check();
2102 }
2103
2104 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2105 {
2106 cover("kernel.rtlil.sigspec.init.bit");
2107
2108 if (bit.wire == NULL)
2109 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2110 else
2111 for (int i = 0; i < width; i++)
2112 chunks_.push_back(bit);
2113 width_ = width;
2114 hash_ = 0;
2115 check();
2116 }
2117
2118 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2119 {
2120 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2121
2122 width_ = 0;
2123 hash_ = 0;
2124 for (auto &c : chunks)
2125 append(c);
2126 check();
2127 }
2128
2129 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2130 {
2131 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2132
2133 width_ = 0;
2134 hash_ = 0;
2135 for (auto &bit : bits)
2136 append_bit(bit);
2137 check();
2138 }
2139
2140 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2141 {
2142 cover("kernel.rtlil.sigspec.init.stdset_bits");
2143
2144 width_ = 0;
2145 hash_ = 0;
2146 for (auto &bit : bits)
2147 append_bit(bit);
2148 check();
2149 }
2150
2151 void RTLIL::SigSpec::pack() const
2152 {
2153 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2154
2155 if (that->bits_.empty())
2156 return;
2157
2158 cover("kernel.rtlil.sigspec.convert.pack");
2159 log_assert(that->chunks_.empty());
2160
2161 std::vector<RTLIL::SigBit> old_bits;
2162 old_bits.swap(that->bits_);
2163
2164 RTLIL::SigChunk *last = NULL;
2165 int last_end_offset = 0;
2166
2167 for (auto &bit : old_bits) {
2168 if (last && bit.wire == last->wire) {
2169 if (bit.wire == NULL) {
2170 last->data.push_back(bit.data);
2171 last->width++;
2172 continue;
2173 } else if (last_end_offset == bit.offset) {
2174 last_end_offset++;
2175 last->width++;
2176 continue;
2177 }
2178 }
2179 that->chunks_.push_back(bit);
2180 last = &that->chunks_.back();
2181 last_end_offset = bit.offset + 1;
2182 }
2183
2184 check();
2185 }
2186
2187 void RTLIL::SigSpec::unpack() const
2188 {
2189 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2190
2191 if (that->chunks_.empty())
2192 return;
2193
2194 cover("kernel.rtlil.sigspec.convert.unpack");
2195 log_assert(that->bits_.empty());
2196
2197 that->bits_.reserve(that->width_);
2198 for (auto &c : that->chunks_)
2199 for (int i = 0; i < c.width; i++)
2200 that->bits_.push_back(RTLIL::SigBit(c, i));
2201
2202 that->chunks_.clear();
2203 that->hash_ = 0;
2204 }
2205
2206 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2207
2208 void RTLIL::SigSpec::hash() const
2209 {
2210 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2211
2212 if (that->hash_ != 0)
2213 return;
2214
2215 cover("kernel.rtlil.sigspec.hash");
2216 that->pack();
2217
2218 that->hash_ = 5381;
2219 for (auto &c : that->chunks_)
2220 if (c.wire == NULL) {
2221 for (auto &v : c.data)
2222 DJB2(that->hash_, v);
2223 } else {
2224 DJB2(that->hash_, c.wire->name.index_);
2225 DJB2(that->hash_, c.offset);
2226 DJB2(that->hash_, c.width);
2227 }
2228
2229 if (that->hash_ == 0)
2230 that->hash_ = 1;
2231 }
2232
2233 void RTLIL::SigSpec::sort()
2234 {
2235 unpack();
2236 cover("kernel.rtlil.sigspec.sort");
2237 std::sort(bits_.begin(), bits_.end());
2238 }
2239
2240 void RTLIL::SigSpec::sort_and_unify()
2241 {
2242 cover("kernel.rtlil.sigspec.sort_and_unify");
2243 *this = this->to_sigbit_set();
2244 }
2245
2246 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2247 {
2248 replace(pattern, with, this);
2249 }
2250
2251 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2252 {
2253 log_assert(pattern.width_ == with.width_);
2254
2255 pattern.unpack();
2256 with.unpack();
2257
2258 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2259
2260 for (int i = 0; i < SIZE(pattern.bits_); i++)
2261 if (pattern.bits_[i].wire != NULL)
2262 rules[pattern.bits_[i]] = with.bits_[i];
2263
2264 replace(rules, other);
2265 }
2266
2267 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2268 {
2269 replace(rules, this);
2270 }
2271
2272 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2273 {
2274 cover("kernel.rtlil.sigspec.replace");
2275
2276 log_assert(other != NULL);
2277 log_assert(width_ == other->width_);
2278
2279 unpack();
2280 other->unpack();
2281
2282 for (int i = 0; i < SIZE(bits_); i++) {
2283 auto it = rules.find(bits_[i]);
2284 if (it != rules.end())
2285 other->bits_[i] = it->second;
2286 }
2287
2288 other->check();
2289 }
2290
2291 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2292 {
2293 remove2(pattern, NULL);
2294 }
2295
2296 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2297 {
2298 RTLIL::SigSpec tmp = *this;
2299 tmp.remove2(pattern, other);
2300 }
2301
2302 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2303 {
2304 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2305 remove2(pattern_bits, other);
2306 }
2307
2308 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2309 {
2310 remove2(pattern, NULL);
2311 }
2312
2313 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2314 {
2315 RTLIL::SigSpec tmp = *this;
2316 tmp.remove2(pattern, other);
2317 }
2318
2319 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2320 {
2321 if (other)
2322 cover("kernel.rtlil.sigspec.remove_other");
2323 else
2324 cover("kernel.rtlil.sigspec.remove");
2325
2326 unpack();
2327
2328 if (other != NULL) {
2329 log_assert(width_ == other->width_);
2330 other->unpack();
2331 }
2332
2333 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2334
2335 new_bits.resize(SIZE(bits_));
2336 if (other != NULL)
2337 new_other_bits.resize(SIZE(bits_));
2338
2339 int k = 0;
2340 for (int i = 0; i < SIZE(bits_); i++) {
2341 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2342 continue;
2343 if (other != NULL)
2344 new_other_bits[k] = other->bits_[i];
2345 new_bits[k++] = bits_[i];
2346 }
2347
2348 new_bits.resize(k);
2349 if (other != NULL)
2350 new_other_bits.resize(k);
2351
2352 bits_.swap(new_bits);
2353 width_ = SIZE(bits_);
2354
2355 if (other != NULL) {
2356 other->bits_.swap(new_other_bits);
2357 other->width_ = SIZE(other->bits_);
2358 }
2359
2360 check();
2361 }
2362
2363 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2364 {
2365 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2366 return extract(pattern_bits, other);
2367 }
2368
2369 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2370 {
2371 if (other)
2372 cover("kernel.rtlil.sigspec.extract_other");
2373 else
2374 cover("kernel.rtlil.sigspec.extract");
2375
2376 log_assert(other == NULL || width_ == other->width_);
2377
2378 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2379 RTLIL::SigSpec ret;
2380
2381 if (other) {
2382 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2383 for (int i = 0; i < width_; i++)
2384 if (bits_match[i].wire && pattern.count(bits_match[i]))
2385 ret.append_bit(bits_other[i]);
2386 } else {
2387 for (int i = 0; i < width_; i++)
2388 if (bits_match[i].wire && pattern.count(bits_match[i]))
2389 ret.append_bit(bits_match[i]);
2390 }
2391
2392 ret.check();
2393 return ret;
2394 }
2395
2396 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2397 {
2398 cover("kernel.rtlil.sigspec.replace_pos");
2399
2400 unpack();
2401 with.unpack();
2402
2403 log_assert(offset >= 0);
2404 log_assert(with.width_ >= 0);
2405 log_assert(offset+with.width_ <= width_);
2406
2407 for (int i = 0; i < with.width_; i++)
2408 bits_.at(offset + i) = with.bits_.at(i);
2409
2410 check();
2411 }
2412
2413 void RTLIL::SigSpec::remove_const()
2414 {
2415 if (packed())
2416 {
2417 cover("kernel.rtlil.sigspec.remove_const.packed");
2418
2419 std::vector<RTLIL::SigChunk> new_chunks;
2420 new_chunks.reserve(SIZE(chunks_));
2421
2422 width_ = 0;
2423 for (auto &chunk : chunks_)
2424 if (chunk.wire != NULL) {
2425 new_chunks.push_back(chunk);
2426 width_ += chunk.width;
2427 }
2428
2429 chunks_.swap(new_chunks);
2430 }
2431 else
2432 {
2433 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2434
2435 std::vector<RTLIL::SigBit> new_bits;
2436 new_bits.reserve(width_);
2437
2438 for (auto &bit : bits_)
2439 if (bit.wire != NULL)
2440 new_bits.push_back(bit);
2441
2442 bits_.swap(new_bits);
2443 width_ = bits_.size();
2444 }
2445
2446 check();
2447 }
2448
2449 void RTLIL::SigSpec::remove(int offset, int length)
2450 {
2451 cover("kernel.rtlil.sigspec.remove_pos");
2452
2453 unpack();
2454
2455 log_assert(offset >= 0);
2456 log_assert(length >= 0);
2457 log_assert(offset + length <= width_);
2458
2459 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2460 width_ = bits_.size();
2461
2462 check();
2463 }
2464
2465 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2466 {
2467 unpack();
2468 cover("kernel.rtlil.sigspec.extract_pos");
2469 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2470 }
2471
2472 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2473 {
2474 if (signal.width_ == 0)
2475 return;
2476
2477 if (width_ == 0) {
2478 *this = signal;
2479 return;
2480 }
2481
2482 cover("kernel.rtlil.sigspec.append");
2483
2484 if (packed() != signal.packed()) {
2485 pack();
2486 signal.pack();
2487 }
2488
2489 if (packed())
2490 for (auto &other_c : signal.chunks_)
2491 {
2492 auto &my_last_c = chunks_.back();
2493 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2494 auto &this_data = my_last_c.data;
2495 auto &other_data = other_c.data;
2496 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2497 my_last_c.width += other_c.width;
2498 } else
2499 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2500 my_last_c.width += other_c.width;
2501 } else
2502 chunks_.push_back(other_c);
2503 }
2504 else
2505 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2506
2507 width_ += signal.width_;
2508 check();
2509 }
2510
2511 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2512 {
2513 if (packed())
2514 {
2515 cover("kernel.rtlil.sigspec.append_bit.packed");
2516
2517 if (chunks_.size() == 0)
2518 chunks_.push_back(bit);
2519 else
2520 if (bit.wire == NULL)
2521 if (chunks_.back().wire == NULL) {
2522 chunks_.back().data.push_back(bit.data);
2523 chunks_.back().width++;
2524 } else
2525 chunks_.push_back(bit);
2526 else
2527 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2528 chunks_.back().width++;
2529 else
2530 chunks_.push_back(bit);
2531 }
2532 else
2533 {
2534 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2535 bits_.push_back(bit);
2536 }
2537
2538 width_++;
2539 check();
2540 }
2541
2542 void RTLIL::SigSpec::extend(int width, bool is_signed)
2543 {
2544 cover("kernel.rtlil.sigspec.extend");
2545
2546 pack();
2547
2548 if (width_ > width)
2549 remove(width, width_ - width);
2550
2551 if (width_ < width) {
2552 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2553 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2554 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2555 padding = RTLIL::SigSpec(RTLIL::State::S0);
2556 while (width_ < width)
2557 append(padding);
2558 }
2559 }
2560
2561 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2562 {
2563 cover("kernel.rtlil.sigspec.extend_u0");
2564
2565 pack();
2566
2567 if (width_ > width)
2568 remove(width, width_ - width);
2569
2570 if (width_ < width) {
2571 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2572 if (!is_signed)
2573 padding = RTLIL::SigSpec(RTLIL::State::S0);
2574 while (width_ < width)
2575 append(padding);
2576 }
2577
2578 }
2579
2580 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2581 {
2582 cover("kernel.rtlil.sigspec.repeat");
2583
2584 RTLIL::SigSpec sig;
2585 for (int i = 0; i < num; i++)
2586 sig.append(*this);
2587 return sig;
2588 }
2589
2590 #ifndef NDEBUG
2591 void RTLIL::SigSpec::check() const
2592 {
2593 if (width_ > 64)
2594 {
2595 cover("kernel.rtlil.sigspec.check.skip");
2596 }
2597 else if (packed())
2598 {
2599 cover("kernel.rtlil.sigspec.check.packed");
2600
2601 int w = 0;
2602 for (size_t i = 0; i < chunks_.size(); i++) {
2603 const RTLIL::SigChunk chunk = chunks_[i];
2604 if (chunk.wire == NULL) {
2605 if (i > 0)
2606 log_assert(chunks_[i-1].wire != NULL);
2607 log_assert(chunk.offset == 0);
2608 log_assert(chunk.data.size() == (size_t)chunk.width);
2609 } else {
2610 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2611 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2612 log_assert(chunk.offset >= 0);
2613 log_assert(chunk.width >= 0);
2614 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2615 log_assert(chunk.data.size() == 0);
2616 }
2617 w += chunk.width;
2618 }
2619 log_assert(w == width_);
2620 log_assert(bits_.empty());
2621 }
2622 else
2623 {
2624 cover("kernel.rtlil.sigspec.check.unpacked");
2625
2626 log_assert(width_ == SIZE(bits_));
2627 log_assert(chunks_.empty());
2628 }
2629 }
2630 #endif
2631
2632 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2633 {
2634 cover("kernel.rtlil.sigspec.comp_lt");
2635
2636 if (this == &other)
2637 return false;
2638
2639 if (width_ != other.width_)
2640 return width_ < other.width_;
2641
2642 pack();
2643 other.pack();
2644
2645 if (chunks_.size() != other.chunks_.size())
2646 return chunks_.size() < other.chunks_.size();
2647
2648 hash();
2649 other.hash();
2650
2651 if (hash_ != other.hash_)
2652 return hash_ < other.hash_;
2653
2654 for (size_t i = 0; i < chunks_.size(); i++)
2655 if (chunks_[i] != other.chunks_[i]) {
2656 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2657 return chunks_[i] < other.chunks_[i];
2658 }
2659
2660 cover("kernel.rtlil.sigspec.comp_lt.equal");
2661 return false;
2662 }
2663
2664 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2665 {
2666 cover("kernel.rtlil.sigspec.comp_eq");
2667
2668 if (this == &other)
2669 return true;
2670
2671 if (width_ != other.width_)
2672 return false;
2673
2674 pack();
2675 other.pack();
2676
2677 if (chunks_.size() != chunks_.size())
2678 return false;
2679
2680 hash();
2681 other.hash();
2682
2683 if (hash_ != other.hash_)
2684 return false;
2685
2686 for (size_t i = 0; i < chunks_.size(); i++)
2687 if (chunks_[i] != other.chunks_[i]) {
2688 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2689 return false;
2690 }
2691
2692 cover("kernel.rtlil.sigspec.comp_eq.equal");
2693 return true;
2694 }
2695
2696 bool RTLIL::SigSpec::is_wire() const
2697 {
2698 cover("kernel.rtlil.sigspec.is_wire");
2699
2700 pack();
2701 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2702 }
2703
2704 bool RTLIL::SigSpec::is_chunk() const
2705 {
2706 cover("kernel.rtlil.sigspec.is_chunk");
2707
2708 pack();
2709 return SIZE(chunks_) == 1;
2710 }
2711
2712 bool RTLIL::SigSpec::is_fully_const() const
2713 {
2714 cover("kernel.rtlil.sigspec.is_fully_const");
2715
2716 pack();
2717 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2718 if (it->width > 0 && it->wire != NULL)
2719 return false;
2720 return true;
2721 }
2722
2723 bool RTLIL::SigSpec::is_fully_def() const
2724 {
2725 cover("kernel.rtlil.sigspec.is_fully_def");
2726
2727 pack();
2728 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2729 if (it->width > 0 && it->wire != NULL)
2730 return false;
2731 for (size_t i = 0; i < it->data.size(); i++)
2732 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
2733 return false;
2734 }
2735 return true;
2736 }
2737
2738 bool RTLIL::SigSpec::is_fully_undef() const
2739 {
2740 cover("kernel.rtlil.sigspec.is_fully_undef");
2741
2742 pack();
2743 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2744 if (it->width > 0 && it->wire != NULL)
2745 return false;
2746 for (size_t i = 0; i < it->data.size(); i++)
2747 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
2748 return false;
2749 }
2750 return true;
2751 }
2752
2753 bool RTLIL::SigSpec::has_marked_bits() const
2754 {
2755 cover("kernel.rtlil.sigspec.has_marked_bits");
2756
2757 pack();
2758 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2759 if (it->width > 0 && it->wire == NULL) {
2760 for (size_t i = 0; i < it->data.size(); i++)
2761 if (it->data[i] == RTLIL::State::Sm)
2762 return true;
2763 }
2764 return false;
2765 }
2766
2767 bool RTLIL::SigSpec::as_bool() const
2768 {
2769 cover("kernel.rtlil.sigspec.as_bool");
2770
2771 pack();
2772 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2773 if (width_)
2774 return RTLIL::Const(chunks_[0].data).as_bool();
2775 return false;
2776 }
2777
2778 int RTLIL::SigSpec::as_int(bool is_signed) const
2779 {
2780 cover("kernel.rtlil.sigspec.as_int");
2781
2782 pack();
2783 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2784 if (width_)
2785 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
2786 return 0;
2787 }
2788
2789 std::string RTLIL::SigSpec::as_string() const
2790 {
2791 cover("kernel.rtlil.sigspec.as_string");
2792
2793 pack();
2794 std::string str;
2795 for (size_t i = chunks_.size(); i > 0; i--) {
2796 const RTLIL::SigChunk &chunk = chunks_[i-1];
2797 if (chunk.wire != NULL)
2798 for (int j = 0; j < chunk.width; j++)
2799 str += "?";
2800 else
2801 str += RTLIL::Const(chunk.data).as_string();
2802 }
2803 return str;
2804 }
2805
2806 RTLIL::Const RTLIL::SigSpec::as_const() const
2807 {
2808 cover("kernel.rtlil.sigspec.as_const");
2809
2810 pack();
2811 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2812 if (width_)
2813 return chunks_[0].data;
2814 return RTLIL::Const();
2815 }
2816
2817 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2818 {
2819 cover("kernel.rtlil.sigspec.as_wire");
2820
2821 pack();
2822 log_assert(is_wire());
2823 return chunks_[0].wire;
2824 }
2825
2826 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2827 {
2828 cover("kernel.rtlil.sigspec.as_chunk");
2829
2830 pack();
2831 log_assert(is_chunk());
2832 return chunks_[0];
2833 }
2834
2835 bool RTLIL::SigSpec::match(std::string pattern) const
2836 {
2837 cover("kernel.rtlil.sigspec.match");
2838
2839 pack();
2840 std::string str = as_string();
2841 log_assert(pattern.size() == str.size());
2842
2843 for (size_t i = 0; i < pattern.size(); i++) {
2844 if (pattern[i] == ' ')
2845 continue;
2846 if (pattern[i] == '*') {
2847 if (str[i] != 'z' && str[i] != 'x')
2848 return false;
2849 continue;
2850 }
2851 if (pattern[i] != str[i])
2852 return false;
2853 }
2854
2855 return true;
2856 }
2857
2858 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2859 {
2860 cover("kernel.rtlil.sigspec.to_sigbit_set");
2861
2862 pack();
2863 std::set<RTLIL::SigBit> sigbits;
2864 for (auto &c : chunks_)
2865 for (int i = 0; i < c.width; i++)
2866 sigbits.insert(RTLIL::SigBit(c, i));
2867 return sigbits;
2868 }
2869
2870 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2871 {
2872 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2873
2874 unpack();
2875 return bits_;
2876 }
2877
2878 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2879 {
2880 cover("kernel.rtlil.sigspec.to_sigbit_map");
2881
2882 unpack();
2883 other.unpack();
2884
2885 log_assert(width_ == other.width_);
2886
2887 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2888 for (int i = 0; i < width_; i++)
2889 new_map[bits_[i]] = other.bits_[i];
2890
2891 return new_map;
2892 }
2893
2894 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2895 {
2896 cover("kernel.rtlil.sigspec.to_single_sigbit");
2897
2898 pack();
2899 log_assert(width_ == 1);
2900 for (auto &c : chunks_)
2901 if (c.width)
2902 return RTLIL::SigBit(c);
2903 log_abort();
2904 }
2905
2906 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2907 {
2908 size_t start = 0, end = 0;
2909 while ((end = text.find(sep, start)) != std::string::npos) {
2910 tokens.push_back(text.substr(start, end - start));
2911 start = end + 1;
2912 }
2913 tokens.push_back(text.substr(start));
2914 }
2915
2916 static int sigspec_parse_get_dummy_line_num()
2917 {
2918 return 0;
2919 }
2920
2921 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2922 {
2923 cover("kernel.rtlil.sigspec.parse");
2924
2925 std::vector<std::string> tokens;
2926 sigspec_parse_split(tokens, str, ',');
2927
2928 sig = RTLIL::SigSpec();
2929 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2930 {
2931 std::string netname = tokens[tokidx];
2932 std::string indices;
2933
2934 if (netname.size() == 0)
2935 continue;
2936
2937 if ('0' <= netname[0] && netname[0] <= '9') {
2938 cover("kernel.rtlil.sigspec.parse.const");
2939 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2940 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2941 if (ast == NULL)
2942 return false;
2943 sig.append(RTLIL::Const(ast->bits));
2944 delete ast;
2945 continue;
2946 }
2947
2948 if (module == NULL)
2949 return false;
2950
2951 cover("kernel.rtlil.sigspec.parse.net");
2952
2953 if (netname[0] != '$' && netname[0] != '\\')
2954 netname = "\\" + netname;
2955
2956 if (module->wires_.count(netname) == 0) {
2957 size_t indices_pos = netname.size()-1;
2958 if (indices_pos > 2 && netname[indices_pos] == ']')
2959 {
2960 indices_pos--;
2961 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2962 if (indices_pos > 0 && netname[indices_pos] == ':') {
2963 indices_pos--;
2964 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2965 }
2966 if (indices_pos > 0 && netname[indices_pos] == '[') {
2967 indices = netname.substr(indices_pos);
2968 netname = netname.substr(0, indices_pos);
2969 }
2970 }
2971 }
2972
2973 if (module->wires_.count(netname) == 0)
2974 return false;
2975
2976 RTLIL::Wire *wire = module->wires_.at(netname);
2977 if (!indices.empty()) {
2978 std::vector<std::string> index_tokens;
2979 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2980 if (index_tokens.size() == 1) {
2981 cover("kernel.rtlil.sigspec.parse.bit_sel");
2982 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2983 } else {
2984 cover("kernel.rtlil.sigspec.parse.part_sel");
2985 int a = atoi(index_tokens.at(0).c_str());
2986 int b = atoi(index_tokens.at(1).c_str());
2987 if (a > b) {
2988 int tmp = a;
2989 a = b, b = tmp;
2990 }
2991 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2992 }
2993 } else
2994 sig.append(wire);
2995 }
2996
2997 return true;
2998 }
2999
3000 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3001 {
3002 if (str.empty() || str[0] != '@')
3003 return parse(sig, module, str);
3004
3005 cover("kernel.rtlil.sigspec.parse.sel");
3006
3007 str = RTLIL::escape_id(str.substr(1));
3008 if (design->selection_vars.count(str) == 0)
3009 return false;
3010
3011 sig = RTLIL::SigSpec();
3012 RTLIL::Selection &sel = design->selection_vars.at(str);
3013 for (auto &it : module->wires_)
3014 if (sel.selected_member(module->name, it.first))
3015 sig.append(it.second);
3016
3017 return true;
3018 }
3019
3020 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3021 {
3022 if (str == "0") {
3023 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3024 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3025 return true;
3026 }
3027
3028 if (str == "~0") {
3029 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3030 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3031 return true;
3032 }
3033
3034 if (lhs.chunks_.size() == 1) {
3035 char *p = (char*)str.c_str(), *endptr;
3036 long long int val = strtoll(p, &endptr, 10);
3037 if (endptr && endptr != p && *endptr == 0) {
3038 sig = RTLIL::SigSpec(val, lhs.width_);
3039 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3040 return true;
3041 }
3042 }
3043
3044 return parse(sig, module, str);
3045 }
3046
3047 RTLIL::CaseRule::~CaseRule()
3048 {
3049 for (auto it = switches.begin(); it != switches.end(); it++)
3050 delete *it;
3051 }
3052
3053 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3054 {
3055 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3056 new_caserule->compare = compare;
3057 new_caserule->actions = actions;
3058 for (auto &it : switches)
3059 new_caserule->switches.push_back(it->clone());
3060 return new_caserule;
3061 }
3062
3063 RTLIL::SwitchRule::~SwitchRule()
3064 {
3065 for (auto it = cases.begin(); it != cases.end(); it++)
3066 delete *it;
3067 }
3068
3069 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3070 {
3071 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3072 new_switchrule->signal = signal;
3073 new_switchrule->attributes = attributes;
3074 for (auto &it : cases)
3075 new_switchrule->cases.push_back(it->clone());
3076 return new_switchrule;
3077
3078 }
3079
3080 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3081 {
3082 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3083 new_syncrule->type = type;
3084 new_syncrule->signal = signal;
3085 new_syncrule->actions = actions;
3086 return new_syncrule;
3087 }
3088
3089 RTLIL::Process::~Process()
3090 {
3091 for (auto it = syncs.begin(); it != syncs.end(); it++)
3092 delete *it;
3093 }
3094
3095 RTLIL::Process *RTLIL::Process::clone() const
3096 {
3097 RTLIL::Process *new_proc = new RTLIL::Process;
3098
3099 new_proc->name = name;
3100 new_proc->attributes = attributes;
3101
3102 RTLIL::CaseRule *rc_ptr = root_case.clone();
3103 new_proc->root_case = *rc_ptr;
3104 rc_ptr->switches.clear();
3105 delete rc_ptr;
3106
3107 for (auto &it : syncs)
3108 new_proc->syncs.push_back(it->clone());
3109
3110 return new_proc;
3111 }
3112
3113 YOSYS_NAMESPACE_END
3114