2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
32 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
37 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_
[8];
41 int RTLIL::IdString::last_created_idx_ptr_
;
44 IdString
RTLIL::ID::A
;
45 IdString
RTLIL::ID::B
;
46 IdString
RTLIL::ID::Y
;
47 IdString
RTLIL::ID::keep
;
48 IdString
RTLIL::ID::whitebox
;
49 IdString
RTLIL::ID::blackbox
;
50 dict
<std::string
, std::string
> RTLIL::constpad
;
54 flags
= RTLIL::CONST_FLAG_NONE
;
57 RTLIL::Const::Const(std::string str
)
59 flags
= RTLIL::CONST_FLAG_STRING
;
60 for (int i
= str
.size()-1; i
>= 0; i
--) {
61 unsigned char ch
= str
[i
];
62 for (int j
= 0; j
< 8; j
++) {
63 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
69 RTLIL::Const::Const(int val
, int width
)
71 flags
= RTLIL::CONST_FLAG_NONE
;
72 for (int i
= 0; i
< width
; i
++) {
73 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
78 RTLIL::Const::Const(RTLIL::State bit
, int width
)
80 flags
= RTLIL::CONST_FLAG_NONE
;
81 for (int i
= 0; i
< width
; i
++)
85 RTLIL::Const::Const(const std::vector
<bool> &bits
)
87 flags
= RTLIL::CONST_FLAG_NONE
;
89 this->bits
.push_back(b
? State::S1
: State::S0
);
92 RTLIL::Const::Const(const RTLIL::Const
&c
)
96 this->bits
.push_back(b
);
99 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
101 if (bits
.size() != other
.bits
.size())
102 return bits
.size() < other
.bits
.size();
103 for (size_t i
= 0; i
< bits
.size(); i
++)
104 if (bits
[i
] != other
.bits
[i
])
105 return bits
[i
] < other
.bits
[i
];
109 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
111 return bits
== other
.bits
;
114 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
116 return bits
!= other
.bits
;
119 bool RTLIL::Const::as_bool() const
121 for (size_t i
= 0; i
< bits
.size(); i
++)
122 if (bits
[i
] == State::S1
)
127 int RTLIL::Const::as_int(bool is_signed
) const
130 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
131 if (bits
[i
] == State::S1
)
133 if (is_signed
&& bits
.back() == State::S1
)
134 for (size_t i
= bits
.size(); i
< 32; i
++)
139 std::string
RTLIL::Const::as_string() const
142 for (size_t i
= bits
.size(); i
> 0; i
--)
144 case S0
: ret
+= "0"; break;
145 case S1
: ret
+= "1"; break;
146 case Sx
: ret
+= "x"; break;
147 case Sz
: ret
+= "z"; break;
148 case Sa
: ret
+= "-"; break;
149 case Sm
: ret
+= "m"; break;
154 RTLIL::Const
RTLIL::Const::from_string(std::string str
)
157 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
159 case '0': c
.bits
.push_back(State::S0
); break;
160 case '1': c
.bits
.push_back(State::S1
); break;
161 case 'x': c
.bits
.push_back(State::Sx
); break;
162 case 'z': c
.bits
.push_back(State::Sz
); break;
163 case 'm': c
.bits
.push_back(State::Sm
); break;
164 default: c
.bits
.push_back(State::Sa
);
169 std::string
RTLIL::Const::decode_string() const
172 std::vector
<char> string_chars
;
173 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
175 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
176 if (bits
[i
+ j
] == RTLIL::State::S1
)
179 string_chars
.push_back(ch
);
181 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
182 string
+= string_chars
[i
];
186 bool RTLIL::Const::is_fully_zero() const
188 cover("kernel.rtlil.const.is_fully_zero");
190 for (auto bit
: bits
)
191 if (bit
!= RTLIL::State::S0
)
197 bool RTLIL::Const::is_fully_ones() const
199 cover("kernel.rtlil.const.is_fully_ones");
201 for (auto bit
: bits
)
202 if (bit
!= RTLIL::State::S1
)
208 bool RTLIL::Const::is_fully_def() const
210 cover("kernel.rtlil.const.is_fully_def");
212 for (auto bit
: bits
)
213 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
219 bool RTLIL::Const::is_fully_undef() const
221 cover("kernel.rtlil.const.is_fully_undef");
223 for (auto bit
: bits
)
224 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
230 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
233 attributes
[id
] = RTLIL::Const(1);
235 const auto it
= attributes
.find(id
);
236 if (it
!= attributes
.end())
237 attributes
.erase(it
);
241 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
243 const auto it
= attributes
.find(id
);
244 if (it
== attributes
.end())
246 return it
->second
.as_bool();
249 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
252 for (auto &s
: data
) {
253 if (!attrval
.empty())
257 attributes
[id
] = RTLIL::Const(attrval
);
260 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
262 pool
<string
> union_data
= get_strpool_attribute(id
);
263 union_data
.insert(data
.begin(), data
.end());
264 if (!union_data
.empty())
265 set_strpool_attribute(id
, union_data
);
268 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
271 if (attributes
.count(id
) != 0)
272 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
277 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
280 attributes
.erase(ID(src
));
282 attributes
[ID(src
)] = src
;
285 std::string
RTLIL::AttrObject::get_src_attribute() const
288 if (attributes
.count(ID(src
)))
289 src
= attributes
.at(ID(src
)).decode_string();
293 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
297 if (selected_modules
.count(mod_name
) > 0)
299 if (selected_members
.count(mod_name
) > 0)
304 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
308 if (selected_modules
.count(mod_name
) > 0)
313 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
317 if (selected_modules
.count(mod_name
) > 0)
319 if (selected_members
.count(mod_name
) > 0)
320 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
325 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
327 if (full_selection
) {
328 selected_modules
.clear();
329 selected_members
.clear();
333 std::vector
<RTLIL::IdString
> del_list
, add_list
;
336 for (auto mod_name
: selected_modules
) {
337 if (design
->modules_
.count(mod_name
) == 0)
338 del_list
.push_back(mod_name
);
339 selected_members
.erase(mod_name
);
341 for (auto mod_name
: del_list
)
342 selected_modules
.erase(mod_name
);
345 for (auto &it
: selected_members
)
346 if (design
->modules_
.count(it
.first
) == 0)
347 del_list
.push_back(it
.first
);
348 for (auto mod_name
: del_list
)
349 selected_members
.erase(mod_name
);
351 for (auto &it
: selected_members
) {
353 for (auto memb_name
: it
.second
)
354 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
355 del_list
.push_back(memb_name
);
356 for (auto memb_name
: del_list
)
357 it
.second
.erase(memb_name
);
362 for (auto &it
: selected_members
)
363 if (it
.second
.size() == 0)
364 del_list
.push_back(it
.first
);
365 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
366 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
367 add_list
.push_back(it
.first
);
368 for (auto mod_name
: del_list
)
369 selected_members
.erase(mod_name
);
370 for (auto mod_name
: add_list
) {
371 selected_members
.erase(mod_name
);
372 selected_modules
.insert(mod_name
);
375 if (selected_modules
.size() == design
->modules_
.size()) {
376 full_selection
= true;
377 selected_modules
.clear();
378 selected_members
.clear();
382 RTLIL::Design::Design()
383 : verilog_defines (new define_map_t
)
385 static unsigned int hashidx_count
= 123456789;
386 hashidx_count
= mkhash_xorshift(hashidx_count
);
387 hashidx_
= hashidx_count
;
389 refcount_modules_
= 0;
390 selection_stack
.push_back(RTLIL::Selection());
393 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
397 RTLIL::Design::~Design()
399 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
401 for (auto n
: verilog_packages
)
403 for (auto n
: verilog_globals
)
406 RTLIL::Design::get_all_designs()->erase(hashidx_
);
411 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
412 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
418 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
420 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
423 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
425 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
428 RTLIL::Module
*RTLIL::Design::top_module()
430 RTLIL::Module
*module
= nullptr;
431 int module_count
= 0;
433 for (auto mod
: selected_modules()) {
434 if (mod
->get_bool_attribute(ID(top
)))
440 return module_count
== 1 ? module
: nullptr;
443 void RTLIL::Design::add(RTLIL::Module
*module
)
445 log_assert(modules_
.count(module
->name
) == 0);
446 log_assert(refcount_modules_
== 0);
447 modules_
[module
->name
] = module
;
448 module
->design
= this;
450 for (auto mon
: monitors
)
451 mon
->notify_module_add(module
);
454 log("#X# New Module: %s\n", log_id(module
));
455 log_backtrace("-X- ", yosys_xtrace
-1);
459 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
461 log_assert(modules_
.count(name
) == 0);
462 log_assert(refcount_modules_
== 0);
464 RTLIL::Module
*module
= new RTLIL::Module
;
465 modules_
[name
] = module
;
466 module
->design
= this;
469 for (auto mon
: monitors
)
470 mon
->notify_module_add(module
);
473 log("#X# New Module: %s\n", log_id(module
));
474 log_backtrace("-X- ", yosys_xtrace
-1);
480 void RTLIL::Design::scratchpad_unset(std::string varname
)
482 scratchpad
.erase(varname
);
485 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
487 scratchpad
[varname
] = stringf("%d", value
);
490 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
492 scratchpad
[varname
] = value
? "true" : "false";
495 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
497 scratchpad
[varname
] = value
;
500 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
502 if (scratchpad
.count(varname
) == 0)
503 return default_value
;
505 std::string str
= scratchpad
.at(varname
);
507 if (str
== "0" || str
== "false")
510 if (str
== "1" || str
== "true")
513 char *endptr
= nullptr;
514 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
515 return *endptr
? default_value
: parsed_value
;
518 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
520 if (scratchpad
.count(varname
) == 0)
521 return default_value
;
523 std::string str
= scratchpad
.at(varname
);
525 if (str
== "0" || str
== "false")
528 if (str
== "1" || str
== "true")
531 return default_value
;
534 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
536 if (scratchpad
.count(varname
) == 0)
537 return default_value
;
538 return scratchpad
.at(varname
);
541 void RTLIL::Design::remove(RTLIL::Module
*module
)
543 for (auto mon
: monitors
)
544 mon
->notify_module_del(module
);
547 log("#X# Remove Module: %s\n", log_id(module
));
548 log_backtrace("-X- ", yosys_xtrace
-1);
551 log_assert(modules_
.at(module
->name
) == module
);
552 modules_
.erase(module
->name
);
556 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
558 modules_
.erase(module
->name
);
559 module
->name
= new_name
;
563 void RTLIL::Design::sort()
566 modules_
.sort(sort_by_id_str());
567 for (auto &it
: modules_
)
571 void RTLIL::Design::check()
574 for (auto &it
: modules_
) {
575 log_assert(this == it
.second
->design
);
576 log_assert(it
.first
== it
.second
->name
);
577 log_assert(!it
.first
.empty());
583 void RTLIL::Design::optimize()
585 for (auto &it
: modules_
)
586 it
.second
->optimize();
587 for (auto &it
: selection_stack
)
589 for (auto &it
: selection_vars
)
590 it
.second
.optimize(this);
593 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
595 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
597 if (selection_stack
.size() == 0)
599 return selection_stack
.back().selected_module(mod_name
);
602 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
604 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
606 if (selection_stack
.size() == 0)
608 return selection_stack
.back().selected_whole_module(mod_name
);
611 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
613 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
615 if (selection_stack
.size() == 0)
617 return selection_stack
.back().selected_member(mod_name
, memb_name
);
620 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
622 return selected_module(mod
->name
);
625 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
627 return selected_whole_module(mod
->name
);
630 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
632 std::vector
<RTLIL::Module
*> result
;
633 result
.reserve(modules_
.size());
634 for (auto &it
: modules_
)
635 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
636 result
.push_back(it
.second
);
640 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
642 std::vector
<RTLIL::Module
*> result
;
643 result
.reserve(modules_
.size());
644 for (auto &it
: modules_
)
645 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
646 result
.push_back(it
.second
);
650 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
652 std::vector
<RTLIL::Module
*> result
;
653 result
.reserve(modules_
.size());
654 for (auto &it
: modules_
)
655 if (it
.second
->get_blackbox_attribute())
657 else if (selected_whole_module(it
.first
))
658 result
.push_back(it
.second
);
659 else if (selected_module(it
.first
))
660 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
664 RTLIL::Module::Module()
666 static unsigned int hashidx_count
= 123456789;
667 hashidx_count
= mkhash_xorshift(hashidx_count
);
668 hashidx_
= hashidx_count
;
675 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
679 RTLIL::Module::~Module()
681 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
683 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
685 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
687 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
690 RTLIL::Module::get_all_modules()->erase(hashidx_
);
695 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
696 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
702 void RTLIL::Module::makeblackbox()
704 pool
<RTLIL::Wire
*> delwires
;
706 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
707 if (!it
->second
->port_input
&& !it
->second
->port_output
)
708 delwires
.insert(it
->second
);
710 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
714 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
718 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
723 set_bool_attribute(ID::blackbox
);
726 void RTLIL::Module::reprocess_module(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Module
*>)
728 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
731 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, bool mayfail
)
734 return RTLIL::IdString();
735 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
739 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, dict
<RTLIL::IdString
, RTLIL::Module
*>, dict
<RTLIL::IdString
, RTLIL::IdString
>, bool mayfail
)
742 return RTLIL::IdString();
743 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
746 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
748 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
753 struct InternalCellChecker
755 RTLIL::Module
*module
;
757 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
759 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
761 void error(int linenr
)
763 std::stringstream buf
;
764 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
766 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
767 module
? module
->name
.c_str() : "", module
? "." : "",
768 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
771 int param(RTLIL::IdString name
)
773 if (cell
->parameters
.count(name
) == 0)
775 expected_params
.insert(name
);
776 return cell
->parameters
.at(name
).as_int();
779 int param_bool(RTLIL::IdString name
)
782 if (cell
->parameters
.at(name
).bits
.size() > 32)
784 if (v
!= 0 && v
!= 1)
789 int param_bool(RTLIL::IdString name
, bool expected
)
791 int v
= param_bool(name
);
797 void param_bits(RTLIL::IdString name
, int width
)
800 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
804 void port(RTLIL::IdString name
, int width
)
806 if (!cell
->hasPort(name
))
808 if (cell
->getPort(name
).size() != width
)
810 expected_ports
.insert(name
);
813 void check_expected(bool check_matched_sign
= true)
815 for (auto ¶
: cell
->parameters
)
816 if (expected_params
.count(para
.first
) == 0)
818 for (auto &conn
: cell
->connections())
819 if (expected_ports
.count(conn
.first
) == 0)
822 if (expected_params
.count(ID(A_SIGNED
)) != 0 && expected_params
.count(ID(B_SIGNED
)) && check_matched_sign
) {
823 bool a_is_signed
= param(ID(A_SIGNED
)) != 0;
824 bool b_is_signed
= param(ID(B_SIGNED
)) != 0;
825 if (a_is_signed
!= b_is_signed
)
830 void check_gate(const char *ports
)
832 if (cell
->parameters
.size() != 0)
835 for (const char *p
= ports
; *p
; p
++) {
836 char portname
[3] = { '\\', *p
, 0 };
837 if (!cell
->hasPort(portname
))
839 if (cell
->getPort(portname
).size() != 1)
843 for (auto &conn
: cell
->connections()) {
844 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
846 if (strchr(ports
, conn
.first
[1]) == NULL
)
853 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
854 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
857 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
858 param_bool(ID(A_SIGNED
));
859 port(ID::A
, param(ID(A_WIDTH
)));
860 port(ID::Y
, param(ID(Y_WIDTH
)));
865 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
866 param_bool(ID(A_SIGNED
));
867 param_bool(ID(B_SIGNED
));
868 port(ID::A
, param(ID(A_WIDTH
)));
869 port(ID::B
, param(ID(B_WIDTH
)));
870 port(ID::Y
, param(ID(Y_WIDTH
)));
875 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
876 param_bool(ID(A_SIGNED
));
877 port(ID::A
, param(ID(A_WIDTH
)));
878 port(ID::Y
, param(ID(Y_WIDTH
)));
883 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
))) {
884 param_bool(ID(A_SIGNED
));
885 param_bool(ID(B_SIGNED
), /*expected=*/false);
886 port(ID::A
, param(ID(A_WIDTH
)));
887 port(ID::B
, param(ID(B_WIDTH
)));
888 port(ID::Y
, param(ID(Y_WIDTH
)));
889 check_expected(/*check_matched_sign=*/false);
893 if (cell
->type
.in(ID($shift
), ID($shiftx
))) {
894 param_bool(ID(A_SIGNED
));
895 param_bool(ID(B_SIGNED
));
896 port(ID::A
, param(ID(A_WIDTH
)));
897 port(ID::B
, param(ID(B_WIDTH
)));
898 port(ID::Y
, param(ID(Y_WIDTH
)));
899 check_expected(/*check_matched_sign=*/false);
903 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
904 param_bool(ID(A_SIGNED
));
905 param_bool(ID(B_SIGNED
));
906 port(ID::A
, param(ID(A_WIDTH
)));
907 port(ID::B
, param(ID(B_WIDTH
)));
908 port(ID::Y
, param(ID(Y_WIDTH
)));
913 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($pow
))) {
914 param_bool(ID(A_SIGNED
));
915 param_bool(ID(B_SIGNED
));
916 port(ID::A
, param(ID(A_WIDTH
)));
917 port(ID::B
, param(ID(B_WIDTH
)));
918 port(ID::Y
, param(ID(Y_WIDTH
)));
919 check_expected(cell
->type
!= ID($pow
));
923 if (cell
->type
== ID($fa
)) {
924 port(ID::A
, param(ID(WIDTH
)));
925 port(ID::B
, param(ID(WIDTH
)));
926 port(ID(C
), param(ID(WIDTH
)));
927 port(ID(X
), param(ID(WIDTH
)));
928 port(ID::Y
, param(ID(WIDTH
)));
933 if (cell
->type
== ID($lcu
)) {
934 port(ID(P
), param(ID(WIDTH
)));
935 port(ID(G
), param(ID(WIDTH
)));
937 port(ID(CO
), param(ID(WIDTH
)));
942 if (cell
->type
== ID($alu
)) {
943 param_bool(ID(A_SIGNED
));
944 param_bool(ID(B_SIGNED
));
945 port(ID::A
, param(ID(A_WIDTH
)));
946 port(ID::B
, param(ID(B_WIDTH
)));
949 port(ID(X
), param(ID(Y_WIDTH
)));
950 port(ID::Y
, param(ID(Y_WIDTH
)));
951 port(ID(CO
), param(ID(Y_WIDTH
)));
956 if (cell
->type
== ID($macc
)) {
958 param(ID(CONFIG_WIDTH
));
959 port(ID::A
, param(ID(A_WIDTH
)));
960 port(ID::B
, param(ID(B_WIDTH
)));
961 port(ID::Y
, param(ID(Y_WIDTH
)));
963 Macc().from_cell(cell
);
967 if (cell
->type
== ID($logic_not
)) {
968 param_bool(ID(A_SIGNED
));
969 port(ID::A
, param(ID(A_WIDTH
)));
970 port(ID::Y
, param(ID(Y_WIDTH
)));
975 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
976 param_bool(ID(A_SIGNED
));
977 param_bool(ID(B_SIGNED
));
978 port(ID::A
, param(ID(A_WIDTH
)));
979 port(ID::B
, param(ID(B_WIDTH
)));
980 port(ID::Y
, param(ID(Y_WIDTH
)));
981 check_expected(/*check_matched_sign=*/false);
985 if (cell
->type
== ID($slice
)) {
987 port(ID::A
, param(ID(A_WIDTH
)));
988 port(ID::Y
, param(ID(Y_WIDTH
)));
989 if (param(ID(OFFSET
)) + param(ID(Y_WIDTH
)) > param(ID(A_WIDTH
)))
995 if (cell
->type
== ID($concat
)) {
996 port(ID::A
, param(ID(A_WIDTH
)));
997 port(ID::B
, param(ID(B_WIDTH
)));
998 port(ID::Y
, param(ID(A_WIDTH
)) + param(ID(B_WIDTH
)));
1003 if (cell
->type
== ID($mux
)) {
1004 port(ID::A
, param(ID(WIDTH
)));
1005 port(ID::B
, param(ID(WIDTH
)));
1007 port(ID::Y
, param(ID(WIDTH
)));
1012 if (cell
->type
== ID($pmux
)) {
1013 port(ID::A
, param(ID(WIDTH
)));
1014 port(ID::B
, param(ID(WIDTH
)) * param(ID(S_WIDTH
)));
1015 port(ID(S
), param(ID(S_WIDTH
)));
1016 port(ID::Y
, param(ID(WIDTH
)));
1021 if (cell
->type
== ID($lut
)) {
1023 port(ID::A
, param(ID(WIDTH
)));
1029 if (cell
->type
== ID($sop
)) {
1032 port(ID::A
, param(ID(WIDTH
)));
1038 if (cell
->type
== ID($sr
)) {
1039 param_bool(ID(SET_POLARITY
));
1040 param_bool(ID(CLR_POLARITY
));
1041 port(ID(SET
), param(ID(WIDTH
)));
1042 port(ID(CLR
), param(ID(WIDTH
)));
1043 port(ID(Q
), param(ID(WIDTH
)));
1048 if (cell
->type
== ID($ff
)) {
1049 port(ID(D
), param(ID(WIDTH
)));
1050 port(ID(Q
), param(ID(WIDTH
)));
1055 if (cell
->type
== ID($dff
)) {
1056 param_bool(ID(CLK_POLARITY
));
1058 port(ID(D
), param(ID(WIDTH
)));
1059 port(ID(Q
), param(ID(WIDTH
)));
1064 if (cell
->type
== ID($dffe
)) {
1065 param_bool(ID(CLK_POLARITY
));
1066 param_bool(ID(EN_POLARITY
));
1069 port(ID(D
), param(ID(WIDTH
)));
1070 port(ID(Q
), param(ID(WIDTH
)));
1075 if (cell
->type
== ID($dffsr
)) {
1076 param_bool(ID(CLK_POLARITY
));
1077 param_bool(ID(SET_POLARITY
));
1078 param_bool(ID(CLR_POLARITY
));
1080 port(ID(SET
), param(ID(WIDTH
)));
1081 port(ID(CLR
), param(ID(WIDTH
)));
1082 port(ID(D
), param(ID(WIDTH
)));
1083 port(ID(Q
), param(ID(WIDTH
)));
1088 if (cell
->type
== ID($adff
)) {
1089 param_bool(ID(CLK_POLARITY
));
1090 param_bool(ID(ARST_POLARITY
));
1091 param_bits(ID(ARST_VALUE
), param(ID(WIDTH
)));
1094 port(ID(D
), param(ID(WIDTH
)));
1095 port(ID(Q
), param(ID(WIDTH
)));
1100 if (cell
->type
== ID($dlatch
)) {
1101 param_bool(ID(EN_POLARITY
));
1103 port(ID(D
), param(ID(WIDTH
)));
1104 port(ID(Q
), param(ID(WIDTH
)));
1109 if (cell
->type
== ID($dlatchsr
)) {
1110 param_bool(ID(EN_POLARITY
));
1111 param_bool(ID(SET_POLARITY
));
1112 param_bool(ID(CLR_POLARITY
));
1114 port(ID(SET
), param(ID(WIDTH
)));
1115 port(ID(CLR
), param(ID(WIDTH
)));
1116 port(ID(D
), param(ID(WIDTH
)));
1117 port(ID(Q
), param(ID(WIDTH
)));
1122 if (cell
->type
== ID($fsm
)) {
1124 param_bool(ID(CLK_POLARITY
));
1125 param_bool(ID(ARST_POLARITY
));
1126 param(ID(STATE_BITS
));
1127 param(ID(STATE_NUM
));
1128 param(ID(STATE_NUM_LOG2
));
1129 param(ID(STATE_RST
));
1130 param_bits(ID(STATE_TABLE
), param(ID(STATE_BITS
)) * param(ID(STATE_NUM
)));
1131 param(ID(TRANS_NUM
));
1132 param_bits(ID(TRANS_TABLE
), param(ID(TRANS_NUM
)) * (2*param(ID(STATE_NUM_LOG2
)) + param(ID(CTRL_IN_WIDTH
)) + param(ID(CTRL_OUT_WIDTH
))));
1135 port(ID(CTRL_IN
), param(ID(CTRL_IN_WIDTH
)));
1136 port(ID(CTRL_OUT
), param(ID(CTRL_OUT_WIDTH
)));
1141 if (cell
->type
== ID($memrd
)) {
1143 param_bool(ID(CLK_ENABLE
));
1144 param_bool(ID(CLK_POLARITY
));
1145 param_bool(ID(TRANSPARENT
));
1148 port(ID(ADDR
), param(ID(ABITS
)));
1149 port(ID(DATA
), param(ID(WIDTH
)));
1154 if (cell
->type
== ID($memwr
)) {
1156 param_bool(ID(CLK_ENABLE
));
1157 param_bool(ID(CLK_POLARITY
));
1158 param(ID(PRIORITY
));
1160 port(ID(EN
), param(ID(WIDTH
)));
1161 port(ID(ADDR
), param(ID(ABITS
)));
1162 port(ID(DATA
), param(ID(WIDTH
)));
1167 if (cell
->type
== ID($meminit
)) {
1169 param(ID(PRIORITY
));
1170 port(ID(ADDR
), param(ID(ABITS
)));
1171 port(ID(DATA
), param(ID(WIDTH
)) * param(ID(WORDS
)));
1176 if (cell
->type
== ID($mem
)) {
1181 param_bits(ID(RD_CLK_ENABLE
), max(1, param(ID(RD_PORTS
))));
1182 param_bits(ID(RD_CLK_POLARITY
), max(1, param(ID(RD_PORTS
))));
1183 param_bits(ID(RD_TRANSPARENT
), max(1, param(ID(RD_PORTS
))));
1184 param_bits(ID(WR_CLK_ENABLE
), max(1, param(ID(WR_PORTS
))));
1185 param_bits(ID(WR_CLK_POLARITY
), max(1, param(ID(WR_PORTS
))));
1186 port(ID(RD_CLK
), param(ID(RD_PORTS
)));
1187 port(ID(RD_EN
), param(ID(RD_PORTS
)));
1188 port(ID(RD_ADDR
), param(ID(RD_PORTS
)) * param(ID(ABITS
)));
1189 port(ID(RD_DATA
), param(ID(RD_PORTS
)) * param(ID(WIDTH
)));
1190 port(ID(WR_CLK
), param(ID(WR_PORTS
)));
1191 port(ID(WR_EN
), param(ID(WR_PORTS
)) * param(ID(WIDTH
)));
1192 port(ID(WR_ADDR
), param(ID(WR_PORTS
)) * param(ID(ABITS
)));
1193 port(ID(WR_DATA
), param(ID(WR_PORTS
)) * param(ID(WIDTH
)));
1198 if (cell
->type
== ID($tribuf
)) {
1199 port(ID::A
, param(ID(WIDTH
)));
1200 port(ID::Y
, param(ID(WIDTH
)));
1206 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1213 if (cell
->type
== ID($initstate
)) {
1219 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1220 port(ID::Y
, param(ID(WIDTH
)));
1225 if (cell
->type
== ID($equiv
)) {
1233 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1234 param_bool(ID(FULL
));
1235 param_bool(ID(SRC_DST_PEN
));
1236 param_bool(ID(SRC_DST_POL
));
1237 param(ID(T_RISE_MIN
));
1238 param(ID(T_RISE_TYP
));
1239 param(ID(T_RISE_MAX
));
1240 param(ID(T_FALL_MIN
));
1241 param(ID(T_FALL_TYP
));
1242 param(ID(T_FALL_MAX
));
1244 port(ID(SRC
), param(ID(SRC_WIDTH
)));
1245 port(ID(DST
), param(ID(DST_WIDTH
)));
1246 if (cell
->type
== ID($specify3
)) {
1247 param_bool(ID(EDGE_EN
));
1248 param_bool(ID(EDGE_POL
));
1249 param_bool(ID(DAT_DST_PEN
));
1250 param_bool(ID(DAT_DST_POL
));
1251 port(ID(DAT
), param(ID(DST_WIDTH
)));
1257 if (cell
->type
== ID($specrule
)) {
1259 param_bool(ID(SRC_PEN
));
1260 param_bool(ID(SRC_POL
));
1261 param_bool(ID(DST_PEN
));
1262 param_bool(ID(DST_POL
));
1263 param(ID(T_LIMIT_MIN
));
1264 param(ID(T_LIMIT_TYP
));
1265 param(ID(T_LIMIT_MAX
));
1266 param(ID(T_LIMIT2_MIN
));
1267 param(ID(T_LIMIT2_TYP
));
1268 param(ID(T_LIMIT2_MAX
));
1269 port(ID(SRC_EN
), 1);
1270 port(ID(DST_EN
), 1);
1271 port(ID(SRC
), param(ID(SRC_WIDTH
)));
1272 port(ID(DST
), param(ID(DST_WIDTH
)));
1277 if (cell
->type
== ID($_BUF_
)) { check_gate("AY"); return; }
1278 if (cell
->type
== ID($_NOT_
)) { check_gate("AY"); return; }
1279 if (cell
->type
== ID($_AND_
)) { check_gate("ABY"); return; }
1280 if (cell
->type
== ID($_NAND_
)) { check_gate("ABY"); return; }
1281 if (cell
->type
== ID($_OR_
)) { check_gate("ABY"); return; }
1282 if (cell
->type
== ID($_NOR_
)) { check_gate("ABY"); return; }
1283 if (cell
->type
== ID($_XOR_
)) { check_gate("ABY"); return; }
1284 if (cell
->type
== ID($_XNOR_
)) { check_gate("ABY"); return; }
1285 if (cell
->type
== ID($_ANDNOT_
)) { check_gate("ABY"); return; }
1286 if (cell
->type
== ID($_ORNOT_
)) { check_gate("ABY"); return; }
1287 if (cell
->type
== ID($_MUX_
)) { check_gate("ABSY"); return; }
1288 if (cell
->type
== ID($_NMUX_
)) { check_gate("ABSY"); return; }
1289 if (cell
->type
== ID($_AOI3_
)) { check_gate("ABCY"); return; }
1290 if (cell
->type
== ID($_OAI3_
)) { check_gate("ABCY"); return; }
1291 if (cell
->type
== ID($_AOI4_
)) { check_gate("ABCDY"); return; }
1292 if (cell
->type
== ID($_OAI4_
)) { check_gate("ABCDY"); return; }
1294 if (cell
->type
== ID($_TBUF_
)) { check_gate("AYE"); return; }
1296 if (cell
->type
== ID($_MUX4_
)) { check_gate("ABCDSTY"); return; }
1297 if (cell
->type
== ID($_MUX8_
)) { check_gate("ABCDEFGHSTUY"); return; }
1298 if (cell
->type
== ID($_MUX16_
)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1300 if (cell
->type
== ID($_SR_NN_
)) { check_gate("SRQ"); return; }
1301 if (cell
->type
== ID($_SR_NP_
)) { check_gate("SRQ"); return; }
1302 if (cell
->type
== ID($_SR_PN_
)) { check_gate("SRQ"); return; }
1303 if (cell
->type
== ID($_SR_PP_
)) { check_gate("SRQ"); return; }
1305 if (cell
->type
== ID($_FF_
)) { check_gate("DQ"); return; }
1306 if (cell
->type
== ID($_DFF_N_
)) { check_gate("DQC"); return; }
1307 if (cell
->type
== ID($_DFF_P_
)) { check_gate("DQC"); return; }
1309 if (cell
->type
== ID($_DFFE_NN_
)) { check_gate("DQCE"); return; }
1310 if (cell
->type
== ID($_DFFE_NP_
)) { check_gate("DQCE"); return; }
1311 if (cell
->type
== ID($_DFFE_PN_
)) { check_gate("DQCE"); return; }
1312 if (cell
->type
== ID($_DFFE_PP_
)) { check_gate("DQCE"); return; }
1314 if (cell
->type
== ID($_DFF_NN0_
)) { check_gate("DQCR"); return; }
1315 if (cell
->type
== ID($_DFF_NN1_
)) { check_gate("DQCR"); return; }
1316 if (cell
->type
== ID($_DFF_NP0_
)) { check_gate("DQCR"); return; }
1317 if (cell
->type
== ID($_DFF_NP1_
)) { check_gate("DQCR"); return; }
1318 if (cell
->type
== ID($_DFF_PN0_
)) { check_gate("DQCR"); return; }
1319 if (cell
->type
== ID($_DFF_PN1_
)) { check_gate("DQCR"); return; }
1320 if (cell
->type
== ID($_DFF_PP0_
)) { check_gate("DQCR"); return; }
1321 if (cell
->type
== ID($_DFF_PP1_
)) { check_gate("DQCR"); return; }
1323 if (cell
->type
== ID($_DFFSR_NNN_
)) { check_gate("CSRDQ"); return; }
1324 if (cell
->type
== ID($_DFFSR_NNP_
)) { check_gate("CSRDQ"); return; }
1325 if (cell
->type
== ID($_DFFSR_NPN_
)) { check_gate("CSRDQ"); return; }
1326 if (cell
->type
== ID($_DFFSR_NPP_
)) { check_gate("CSRDQ"); return; }
1327 if (cell
->type
== ID($_DFFSR_PNN_
)) { check_gate("CSRDQ"); return; }
1328 if (cell
->type
== ID($_DFFSR_PNP_
)) { check_gate("CSRDQ"); return; }
1329 if (cell
->type
== ID($_DFFSR_PPN_
)) { check_gate("CSRDQ"); return; }
1330 if (cell
->type
== ID($_DFFSR_PPP_
)) { check_gate("CSRDQ"); return; }
1332 if (cell
->type
== ID($_DLATCH_N_
)) { check_gate("EDQ"); return; }
1333 if (cell
->type
== ID($_DLATCH_P_
)) { check_gate("EDQ"); return; }
1335 if (cell
->type
== ID($_DLATCHSR_NNN_
)) { check_gate("ESRDQ"); return; }
1336 if (cell
->type
== ID($_DLATCHSR_NNP_
)) { check_gate("ESRDQ"); return; }
1337 if (cell
->type
== ID($_DLATCHSR_NPN_
)) { check_gate("ESRDQ"); return; }
1338 if (cell
->type
== ID($_DLATCHSR_NPP_
)) { check_gate("ESRDQ"); return; }
1339 if (cell
->type
== ID($_DLATCHSR_PNN_
)) { check_gate("ESRDQ"); return; }
1340 if (cell
->type
== ID($_DLATCHSR_PNP_
)) { check_gate("ESRDQ"); return; }
1341 if (cell
->type
== ID($_DLATCHSR_PPN_
)) { check_gate("ESRDQ"); return; }
1342 if (cell
->type
== ID($_DLATCHSR_PPP_
)) { check_gate("ESRDQ"); return; }
1350 void RTLIL::Module::sort()
1352 wires_
.sort(sort_by_id_str());
1353 cells_
.sort(sort_by_id_str());
1354 avail_parameters
.sort(sort_by_id_str());
1355 memories
.sort(sort_by_id_str());
1356 processes
.sort(sort_by_id_str());
1357 for (auto &it
: cells_
)
1359 for (auto &it
: wires_
)
1360 it
.second
->attributes
.sort(sort_by_id_str());
1361 for (auto &it
: memories
)
1362 it
.second
->attributes
.sort(sort_by_id_str());
1365 void RTLIL::Module::check()
1368 std::vector
<bool> ports_declared
;
1369 for (auto &it
: wires_
) {
1370 log_assert(this == it
.second
->module
);
1371 log_assert(it
.first
== it
.second
->name
);
1372 log_assert(!it
.first
.empty());
1373 log_assert(it
.second
->width
>= 0);
1374 log_assert(it
.second
->port_id
>= 0);
1375 for (auto &it2
: it
.second
->attributes
)
1376 log_assert(!it2
.first
.empty());
1377 if (it
.second
->port_id
) {
1378 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1379 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1380 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1381 if (GetSize(ports_declared
) < it
.second
->port_id
)
1382 ports_declared
.resize(it
.second
->port_id
);
1383 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1384 ports_declared
[it
.second
->port_id
-1] = true;
1386 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1388 for (auto port_declared
: ports_declared
)
1389 log_assert(port_declared
== true);
1390 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1392 for (auto &it
: memories
) {
1393 log_assert(it
.first
== it
.second
->name
);
1394 log_assert(!it
.first
.empty());
1395 log_assert(it
.second
->width
>= 0);
1396 log_assert(it
.second
->size
>= 0);
1397 for (auto &it2
: it
.second
->attributes
)
1398 log_assert(!it2
.first
.empty());
1401 for (auto &it
: cells_
) {
1402 log_assert(this == it
.second
->module
);
1403 log_assert(it
.first
== it
.second
->name
);
1404 log_assert(!it
.first
.empty());
1405 log_assert(!it
.second
->type
.empty());
1406 for (auto &it2
: it
.second
->connections()) {
1407 log_assert(!it2
.first
.empty());
1410 for (auto &it2
: it
.second
->attributes
)
1411 log_assert(!it2
.first
.empty());
1412 for (auto &it2
: it
.second
->parameters
)
1413 log_assert(!it2
.first
.empty());
1414 InternalCellChecker
checker(this, it
.second
);
1418 for (auto &it
: processes
) {
1419 log_assert(it
.first
== it
.second
->name
);
1420 log_assert(!it
.first
.empty());
1421 log_assert(it
.second
->root_case
.compare
.empty());
1422 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1423 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1424 for (auto &switch_it
: all_cases
[i
]->switches
) {
1425 for (auto &case_it
: switch_it
->cases
) {
1426 for (auto &compare_it
: case_it
->compare
) {
1427 log_assert(switch_it
->signal
.size() == compare_it
.size());
1429 all_cases
.push_back(case_it
);
1433 for (auto &sync_it
: it
.second
->syncs
) {
1434 switch (sync_it
->type
) {
1440 log_assert(!sync_it
->signal
.empty());
1445 log_assert(sync_it
->signal
.empty());
1451 for (auto &it
: connections_
) {
1452 log_assert(it
.first
.size() == it
.second
.size());
1453 log_assert(!it
.first
.has_const());
1458 for (auto &it
: attributes
)
1459 log_assert(!it
.first
.empty());
1463 void RTLIL::Module::optimize()
1467 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1469 log_assert(new_mod
->refcount_wires_
== 0);
1470 log_assert(new_mod
->refcount_cells_
== 0);
1472 new_mod
->avail_parameters
= avail_parameters
;
1474 for (auto &conn
: connections_
)
1475 new_mod
->connect(conn
);
1477 for (auto &attr
: attributes
)
1478 new_mod
->attributes
[attr
.first
] = attr
.second
;
1480 for (auto &it
: wires_
)
1481 new_mod
->addWire(it
.first
, it
.second
);
1483 for (auto &it
: memories
)
1484 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1486 for (auto &it
: cells_
)
1487 new_mod
->addCell(it
.first
, it
.second
);
1489 for (auto &it
: processes
)
1490 new_mod
->processes
[it
.first
] = it
.second
->clone();
1492 struct RewriteSigSpecWorker
1495 void operator()(RTLIL::SigSpec
&sig
)
1497 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1498 for (auto &c
: chunks
)
1500 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1505 RewriteSigSpecWorker rewriteSigSpecWorker
;
1506 rewriteSigSpecWorker
.mod
= new_mod
;
1507 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1508 new_mod
->fixup_ports();
1511 RTLIL::Module
*RTLIL::Module::clone() const
1513 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1514 new_mod
->name
= name
;
1519 bool RTLIL::Module::has_memories() const
1521 return !memories
.empty();
1524 bool RTLIL::Module::has_processes() const
1526 return !processes
.empty();
1529 bool RTLIL::Module::has_memories_warn() const
1531 if (!memories
.empty())
1532 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1533 return !memories
.empty();
1536 bool RTLIL::Module::has_processes_warn() const
1538 if (!processes
.empty())
1539 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1540 return !processes
.empty();
1543 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1545 std::vector
<RTLIL::Wire
*> result
;
1546 result
.reserve(wires_
.size());
1547 for (auto &it
: wires_
)
1548 if (design
->selected(this, it
.second
))
1549 result
.push_back(it
.second
);
1553 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1555 std::vector
<RTLIL::Cell
*> result
;
1556 result
.reserve(cells_
.size());
1557 for (auto &it
: cells_
)
1558 if (design
->selected(this, it
.second
))
1559 result
.push_back(it
.second
);
1563 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1565 log_assert(!wire
->name
.empty());
1566 log_assert(count_id(wire
->name
) == 0);
1567 log_assert(refcount_wires_
== 0);
1568 wires_
[wire
->name
] = wire
;
1569 wire
->module
= this;
1572 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1574 log_assert(!cell
->name
.empty());
1575 log_assert(count_id(cell
->name
) == 0);
1576 log_assert(refcount_cells_
== 0);
1577 cells_
[cell
->name
] = cell
;
1578 cell
->module
= this;
1581 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1583 log_assert(refcount_wires_
== 0);
1585 struct DeleteWireWorker
1587 RTLIL::Module
*module
;
1588 const pool
<RTLIL::Wire
*> *wires_p
;
1590 void operator()(RTLIL::SigSpec
&sig
) {
1591 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1592 for (auto &c
: chunks
)
1593 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1594 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1600 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1601 log_assert(GetSize(lhs
) == GetSize(rhs
));
1602 RTLIL::SigSpec new_lhs
, new_rhs
;
1603 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1604 RTLIL::SigBit lhs_bit
= lhs
[i
];
1605 if (lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
))
1607 RTLIL::SigBit rhs_bit
= rhs
[i
];
1608 if (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))
1610 new_lhs
.append(lhs_bit
);
1611 new_rhs
.append(rhs_bit
);
1618 DeleteWireWorker delete_wire_worker
;
1619 delete_wire_worker
.module
= this;
1620 delete_wire_worker
.wires_p
= &wires
;
1621 rewrite_sigspecs2(delete_wire_worker
);
1623 for (auto &it
: wires
) {
1624 log_assert(wires_
.count(it
->name
) != 0);
1625 wires_
.erase(it
->name
);
1630 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1632 while (!cell
->connections_
.empty())
1633 cell
->unsetPort(cell
->connections_
.begin()->first
);
1635 log_assert(cells_
.count(cell
->name
) != 0);
1636 log_assert(refcount_cells_
== 0);
1637 cells_
.erase(cell
->name
);
1641 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1643 log_assert(wires_
[wire
->name
] == wire
);
1644 log_assert(refcount_wires_
== 0);
1645 wires_
.erase(wire
->name
);
1646 wire
->name
= new_name
;
1650 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1652 log_assert(cells_
[cell
->name
] == cell
);
1653 log_assert(refcount_wires_
== 0);
1654 cells_
.erase(cell
->name
);
1655 cell
->name
= new_name
;
1659 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1661 log_assert(count_id(old_name
) != 0);
1662 if (wires_
.count(old_name
))
1663 rename(wires_
.at(old_name
), new_name
);
1664 else if (cells_
.count(old_name
))
1665 rename(cells_
.at(old_name
), new_name
);
1670 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1672 log_assert(wires_
[w1
->name
] == w1
);
1673 log_assert(wires_
[w2
->name
] == w2
);
1674 log_assert(refcount_wires_
== 0);
1676 wires_
.erase(w1
->name
);
1677 wires_
.erase(w2
->name
);
1679 std::swap(w1
->name
, w2
->name
);
1681 wires_
[w1
->name
] = w1
;
1682 wires_
[w2
->name
] = w2
;
1685 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1687 log_assert(cells_
[c1
->name
] == c1
);
1688 log_assert(cells_
[c2
->name
] == c2
);
1689 log_assert(refcount_cells_
== 0);
1691 cells_
.erase(c1
->name
);
1692 cells_
.erase(c2
->name
);
1694 std::swap(c1
->name
, c2
->name
);
1696 cells_
[c1
->name
] = c1
;
1697 cells_
[c2
->name
] = c2
;
1700 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1703 return uniquify(name
, index
);
1706 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1709 if (count_id(name
) == 0)
1715 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1716 if (count_id(new_name
) == 0)
1722 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1724 if (a
->port_id
&& !b
->port_id
)
1726 if (!a
->port_id
&& b
->port_id
)
1729 if (a
->port_id
== b
->port_id
)
1730 return a
->name
< b
->name
;
1731 return a
->port_id
< b
->port_id
;
1734 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1736 for (auto mon
: monitors
)
1737 mon
->notify_connect(this, conn
);
1740 for (auto mon
: design
->monitors
)
1741 mon
->notify_connect(this, conn
);
1743 // ignore all attempts to assign constants to other constants
1744 if (conn
.first
.has_const()) {
1745 RTLIL::SigSig new_conn
;
1746 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1747 if (conn
.first
[i
].wire
) {
1748 new_conn
.first
.append(conn
.first
[i
]);
1749 new_conn
.second
.append(conn
.second
[i
]);
1751 if (GetSize(new_conn
.first
))
1757 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1758 log_backtrace("-X- ", yosys_xtrace
-1);
1761 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1762 connections_
.push_back(conn
);
1765 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1767 connect(RTLIL::SigSig(lhs
, rhs
));
1770 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1772 for (auto mon
: monitors
)
1773 mon
->notify_connect(this, new_conn
);
1776 for (auto mon
: design
->monitors
)
1777 mon
->notify_connect(this, new_conn
);
1780 log("#X# New connections vector in %s:\n", log_id(this));
1781 for (auto &conn
: new_conn
)
1782 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1783 log_backtrace("-X- ", yosys_xtrace
-1);
1786 connections_
= new_conn
;
1789 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1791 return connections_
;
1794 void RTLIL::Module::fixup_ports()
1796 std::vector
<RTLIL::Wire
*> all_ports
;
1798 for (auto &w
: wires_
)
1799 if (w
.second
->port_input
|| w
.second
->port_output
)
1800 all_ports
.push_back(w
.second
);
1802 w
.second
->port_id
= 0;
1804 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1807 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1808 ports
.push_back(all_ports
[i
]->name
);
1809 all_ports
[i
]->port_id
= i
+1;
1813 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1815 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1817 wire
->width
= width
;
1822 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1824 RTLIL::Wire
*wire
= addWire(name
);
1825 wire
->width
= other
->width
;
1826 wire
->start_offset
= other
->start_offset
;
1827 wire
->port_id
= other
->port_id
;
1828 wire
->port_input
= other
->port_input
;
1829 wire
->port_output
= other
->port_output
;
1830 wire
->upto
= other
->upto
;
1831 wire
->attributes
= other
->attributes
;
1835 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1837 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1844 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1846 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1847 cell
->connections_
= other
->connections_
;
1848 cell
->parameters
= other
->parameters
;
1849 cell
->attributes
= other
->attributes
;
1853 #define DEF_METHOD(_func, _y_size, _type) \
1854 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1855 RTLIL::Cell *cell = addCell(name, _type); \
1856 cell->parameters[ID(A_SIGNED)] = is_signed; \
1857 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1858 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1859 cell->setPort(ID::A, sig_a); \
1860 cell->setPort(ID::Y, sig_y); \
1861 cell->set_src_attribute(src); \
1864 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1865 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1866 add ## _func(name, sig_a, sig_y, is_signed, src); \
1869 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
1870 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
1871 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
1872 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
1873 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
1874 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
1875 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
1876 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
1877 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
1880 #define DEF_METHOD(_func, _y_size, _type) \
1881 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1882 RTLIL::Cell *cell = addCell(name, _type); \
1883 cell->parameters[ID(A_SIGNED)] = is_signed; \
1884 cell->parameters[ID(B_SIGNED)] = is_signed; \
1885 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1886 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1887 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1888 cell->setPort(ID::A, sig_a); \
1889 cell->setPort(ID::B, sig_b); \
1890 cell->setPort(ID::Y, sig_y); \
1891 cell->set_src_attribute(src); \
1894 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1895 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1896 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1899 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
1900 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
1901 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
1902 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
1903 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
1904 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
1905 DEF_METHOD(Lt
, 1, ID($lt
))
1906 DEF_METHOD(Le
, 1, ID($le
))
1907 DEF_METHOD(Eq
, 1, ID($eq
))
1908 DEF_METHOD(Ne
, 1, ID($ne
))
1909 DEF_METHOD(Eqx
, 1, ID($eqx
))
1910 DEF_METHOD(Nex
, 1, ID($nex
))
1911 DEF_METHOD(Ge
, 1, ID($ge
))
1912 DEF_METHOD(Gt
, 1, ID($gt
))
1913 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
1914 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
1915 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
1916 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
1917 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
1918 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
1919 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
1922 #define DEF_METHOD(_func, _y_size, _type) \
1923 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1924 RTLIL::Cell *cell = addCell(name, _type); \
1925 cell->parameters[ID(A_SIGNED)] = is_signed; \
1926 cell->parameters[ID(B_SIGNED)] = false; \
1927 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1928 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1929 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1930 cell->setPort(ID::A, sig_a); \
1931 cell->setPort(ID::B, sig_b); \
1932 cell->setPort(ID::Y, sig_y); \
1933 cell->set_src_attribute(src); \
1936 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1937 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1938 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1941 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
1942 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
1943 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
1944 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
1947 #define DEF_METHOD(_func, _type, _pmux) \
1948 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1949 RTLIL::Cell *cell = addCell(name, _type); \
1950 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1951 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1952 cell->setPort(ID::A, sig_a); \
1953 cell->setPort(ID::B, sig_b); \
1954 cell->setPort(ID(S), sig_s); \
1955 cell->setPort(ID::Y, sig_y); \
1956 cell->set_src_attribute(src); \
1959 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1960 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1961 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1964 DEF_METHOD(Mux
, ID($mux
), 0)
1965 DEF_METHOD(Pmux
, ID($pmux
), 1)
1968 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1969 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1970 RTLIL::Cell *cell = addCell(name, _type); \
1971 cell->setPort("\\" #_P1, sig1); \
1972 cell->setPort("\\" #_P2, sig2); \
1973 cell->set_src_attribute(src); \
1976 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1977 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1978 add ## _func(name, sig1, sig2, src); \
1981 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1982 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1983 RTLIL::Cell *cell = addCell(name, _type); \
1984 cell->setPort("\\" #_P1, sig1); \
1985 cell->setPort("\\" #_P2, sig2); \
1986 cell->setPort("\\" #_P3, sig3); \
1987 cell->set_src_attribute(src); \
1990 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1991 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1992 add ## _func(name, sig1, sig2, sig3, src); \
1995 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1996 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1997 RTLIL::Cell *cell = addCell(name, _type); \
1998 cell->setPort("\\" #_P1, sig1); \
1999 cell->setPort("\\" #_P2, sig2); \
2000 cell->setPort("\\" #_P3, sig3); \
2001 cell->setPort("\\" #_P4, sig4); \
2002 cell->set_src_attribute(src); \
2005 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
2006 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2007 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2010 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2011 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
2012 RTLIL::Cell *cell = addCell(name, _type); \
2013 cell->setPort("\\" #_P1, sig1); \
2014 cell->setPort("\\" #_P2, sig2); \
2015 cell->setPort("\\" #_P3, sig3); \
2016 cell->setPort("\\" #_P4, sig4); \
2017 cell->setPort("\\" #_P5, sig5); \
2018 cell->set_src_attribute(src); \
2021 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
2022 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2023 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2026 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
2027 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
2028 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
2029 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
2030 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
2031 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
2032 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
2033 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
2034 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
2035 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
2036 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
2037 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
2038 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
2039 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
2040 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
2041 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2047 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2049 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2050 cell
->parameters
[ID(A_SIGNED
)] = a_signed
;
2051 cell
->parameters
[ID(B_SIGNED
)] = b_signed
;
2052 cell
->parameters
[ID(A_WIDTH
)] = sig_a
.size();
2053 cell
->parameters
[ID(B_WIDTH
)] = sig_b
.size();
2054 cell
->parameters
[ID(Y_WIDTH
)] = sig_y
.size();
2055 cell
->setPort(ID::A
, sig_a
);
2056 cell
->setPort(ID::B
, sig_b
);
2057 cell
->setPort(ID::Y
, sig_y
);
2058 cell
->set_src_attribute(src
);
2062 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
, const std::string
&src
)
2064 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2065 cell
->parameters
[ID(A_WIDTH
)] = sig_a
.size();
2066 cell
->parameters
[ID(Y_WIDTH
)] = sig_y
.size();
2067 cell
->parameters
[ID(OFFSET
)] = offset
;
2068 cell
->setPort(ID::A
, sig_a
);
2069 cell
->setPort(ID::Y
, sig_y
);
2070 cell
->set_src_attribute(src
);
2074 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2076 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2077 cell
->parameters
[ID(A_WIDTH
)] = sig_a
.size();
2078 cell
->parameters
[ID(B_WIDTH
)] = sig_b
.size();
2079 cell
->setPort(ID::A
, sig_a
);
2080 cell
->setPort(ID::B
, sig_b
);
2081 cell
->setPort(ID::Y
, sig_y
);
2082 cell
->set_src_attribute(src
);
2086 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const lut
, const std::string
&src
)
2088 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2089 cell
->parameters
[ID(LUT
)] = lut
;
2090 cell
->parameters
[ID(WIDTH
)] = sig_a
.size();
2091 cell
->setPort(ID::A
, sig_a
);
2092 cell
->setPort(ID::Y
, sig_y
);
2093 cell
->set_src_attribute(src
);
2097 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2099 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2100 cell
->parameters
[ID(WIDTH
)] = sig_a
.size();
2101 cell
->setPort(ID::A
, sig_a
);
2102 cell
->setPort(ID(EN
), sig_en
);
2103 cell
->setPort(ID::Y
, sig_y
);
2104 cell
->set_src_attribute(src
);
2108 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2110 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2111 cell
->setPort(ID::A
, sig_a
);
2112 cell
->setPort(ID(EN
), sig_en
);
2113 cell
->set_src_attribute(src
);
2117 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2119 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2120 cell
->setPort(ID::A
, sig_a
);
2121 cell
->setPort(ID(EN
), sig_en
);
2122 cell
->set_src_attribute(src
);
2126 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2128 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2129 cell
->setPort(ID::A
, sig_a
);
2130 cell
->setPort(ID(EN
), sig_en
);
2131 cell
->set_src_attribute(src
);
2135 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2137 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2138 cell
->setPort(ID::A
, sig_a
);
2139 cell
->setPort(ID(EN
), sig_en
);
2140 cell
->set_src_attribute(src
);
2144 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2146 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2147 cell
->setPort(ID::A
, sig_a
);
2148 cell
->setPort(ID(EN
), sig_en
);
2149 cell
->set_src_attribute(src
);
2153 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2155 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2156 cell
->setPort(ID::A
, sig_a
);
2157 cell
->setPort(ID::B
, sig_b
);
2158 cell
->setPort(ID::Y
, sig_y
);
2159 cell
->set_src_attribute(src
);
2163 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2165 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2166 cell
->parameters
[ID(SET_POLARITY
)] = set_polarity
;
2167 cell
->parameters
[ID(CLR_POLARITY
)] = clr_polarity
;
2168 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2169 cell
->setPort(ID(SET
), sig_set
);
2170 cell
->setPort(ID(CLR
), sig_clr
);
2171 cell
->setPort(ID(Q
), sig_q
);
2172 cell
->set_src_attribute(src
);
2176 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2178 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2179 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2180 cell
->setPort(ID(D
), sig_d
);
2181 cell
->setPort(ID(Q
), sig_q
);
2182 cell
->set_src_attribute(src
);
2186 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2188 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2189 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2190 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2191 cell
->setPort(ID(CLK
), sig_clk
);
2192 cell
->setPort(ID(D
), sig_d
);
2193 cell
->setPort(ID(Q
), sig_q
);
2194 cell
->set_src_attribute(src
);
2198 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2200 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2201 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2202 cell
->parameters
[ID(EN_POLARITY
)] = en_polarity
;
2203 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2204 cell
->setPort(ID(CLK
), sig_clk
);
2205 cell
->setPort(ID(EN
), sig_en
);
2206 cell
->setPort(ID(D
), sig_d
);
2207 cell
->setPort(ID(Q
), sig_q
);
2208 cell
->set_src_attribute(src
);
2212 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2213 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2215 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2216 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2217 cell
->parameters
[ID(SET_POLARITY
)] = set_polarity
;
2218 cell
->parameters
[ID(CLR_POLARITY
)] = clr_polarity
;
2219 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2220 cell
->setPort(ID(CLK
), sig_clk
);
2221 cell
->setPort(ID(SET
), sig_set
);
2222 cell
->setPort(ID(CLR
), sig_clr
);
2223 cell
->setPort(ID(D
), sig_d
);
2224 cell
->setPort(ID(Q
), sig_q
);
2225 cell
->set_src_attribute(src
);
2229 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2230 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2232 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2233 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2234 cell
->parameters
[ID(ARST_POLARITY
)] = arst_polarity
;
2235 cell
->parameters
[ID(ARST_VALUE
)] = arst_value
;
2236 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2237 cell
->setPort(ID(CLK
), sig_clk
);
2238 cell
->setPort(ID(ARST
), sig_arst
);
2239 cell
->setPort(ID(D
), sig_d
);
2240 cell
->setPort(ID(Q
), sig_q
);
2241 cell
->set_src_attribute(src
);
2245 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2247 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2248 cell
->parameters
[ID(EN_POLARITY
)] = en_polarity
;
2249 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2250 cell
->setPort(ID(EN
), sig_en
);
2251 cell
->setPort(ID(D
), sig_d
);
2252 cell
->setPort(ID(Q
), sig_q
);
2253 cell
->set_src_attribute(src
);
2257 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2258 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2260 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2261 cell
->parameters
[ID(EN_POLARITY
)] = en_polarity
;
2262 cell
->parameters
[ID(SET_POLARITY
)] = set_polarity
;
2263 cell
->parameters
[ID(CLR_POLARITY
)] = clr_polarity
;
2264 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2265 cell
->setPort(ID(EN
), sig_en
);
2266 cell
->setPort(ID(SET
), sig_set
);
2267 cell
->setPort(ID(CLR
), sig_clr
);
2268 cell
->setPort(ID(D
), sig_d
);
2269 cell
->setPort(ID(Q
), sig_q
);
2270 cell
->set_src_attribute(src
);
2274 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2276 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2277 cell
->setPort(ID(D
), sig_d
);
2278 cell
->setPort(ID(Q
), sig_q
);
2279 cell
->set_src_attribute(src
);
2283 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2285 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2286 cell
->setPort(ID(C
), sig_clk
);
2287 cell
->setPort(ID(D
), sig_d
);
2288 cell
->setPort(ID(Q
), sig_q
);
2289 cell
->set_src_attribute(src
);
2293 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2295 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2296 cell
->setPort(ID(C
), sig_clk
);
2297 cell
->setPort(ID(E
), sig_en
);
2298 cell
->setPort(ID(D
), sig_d
);
2299 cell
->setPort(ID(Q
), sig_q
);
2300 cell
->set_src_attribute(src
);
2304 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2305 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2307 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2308 cell
->setPort(ID(C
), sig_clk
);
2309 cell
->setPort(ID(S
), sig_set
);
2310 cell
->setPort(ID(R
), sig_clr
);
2311 cell
->setPort(ID(D
), sig_d
);
2312 cell
->setPort(ID(Q
), sig_q
);
2313 cell
->set_src_attribute(src
);
2317 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2318 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2320 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2321 cell
->setPort(ID(C
), sig_clk
);
2322 cell
->setPort(ID(R
), sig_arst
);
2323 cell
->setPort(ID(D
), sig_d
);
2324 cell
->setPort(ID(Q
), sig_q
);
2325 cell
->set_src_attribute(src
);
2329 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2331 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2332 cell
->setPort(ID(E
), sig_en
);
2333 cell
->setPort(ID(D
), sig_d
);
2334 cell
->setPort(ID(Q
), sig_q
);
2335 cell
->set_src_attribute(src
);
2339 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2340 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2342 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2343 cell
->setPort(ID(E
), sig_en
);
2344 cell
->setPort(ID(S
), sig_set
);
2345 cell
->setPort(ID(R
), sig_clr
);
2346 cell
->setPort(ID(D
), sig_d
);
2347 cell
->setPort(ID(Q
), sig_q
);
2348 cell
->set_src_attribute(src
);
2352 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2354 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2355 Cell
*cell
= addCell(name
, ID($anyconst
));
2356 cell
->setParam(ID(WIDTH
), width
);
2357 cell
->setPort(ID::Y
, sig
);
2358 cell
->set_src_attribute(src
);
2362 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2364 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2365 Cell
*cell
= addCell(name
, ID($anyseq
));
2366 cell
->setParam(ID(WIDTH
), width
);
2367 cell
->setPort(ID::Y
, sig
);
2368 cell
->set_src_attribute(src
);
2372 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2374 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2375 Cell
*cell
= addCell(name
, ID($allconst
));
2376 cell
->setParam(ID(WIDTH
), width
);
2377 cell
->setPort(ID::Y
, sig
);
2378 cell
->set_src_attribute(src
);
2382 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2384 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2385 Cell
*cell
= addCell(name
, ID($allseq
));
2386 cell
->setParam(ID(WIDTH
), width
);
2387 cell
->setPort(ID::Y
, sig
);
2388 cell
->set_src_attribute(src
);
2392 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2394 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2395 Cell
*cell
= addCell(name
, ID($initstate
));
2396 cell
->setPort(ID::Y
, sig
);
2397 cell
->set_src_attribute(src
);
2403 static unsigned int hashidx_count
= 123456789;
2404 hashidx_count
= mkhash_xorshift(hashidx_count
);
2405 hashidx_
= hashidx_count
;
2412 port_output
= false;
2416 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2420 RTLIL::Wire::~Wire()
2423 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2428 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2429 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2435 RTLIL::Memory::Memory()
2437 static unsigned int hashidx_count
= 123456789;
2438 hashidx_count
= mkhash_xorshift(hashidx_count
);
2439 hashidx_
= hashidx_count
;
2445 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2449 RTLIL::Cell::Cell() : module(nullptr)
2451 static unsigned int hashidx_count
= 123456789;
2452 hashidx_count
= mkhash_xorshift(hashidx_count
);
2453 hashidx_
= hashidx_count
;
2455 // log("#memtrace# %p\n", this);
2459 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2463 RTLIL::Cell::~Cell()
2466 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2471 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2472 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2478 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2480 return connections_
.count(portname
) != 0;
2483 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2485 RTLIL::SigSpec signal
;
2486 auto conn_it
= connections_
.find(portname
);
2488 if (conn_it
!= connections_
.end())
2490 for (auto mon
: module
->monitors
)
2491 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2494 for (auto mon
: module
->design
->monitors
)
2495 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2498 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2499 log_backtrace("-X- ", yosys_xtrace
-1);
2502 connections_
.erase(conn_it
);
2506 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2508 auto conn_it
= connections_
.find(portname
);
2510 if (conn_it
== connections_
.end()) {
2511 connections_
[portname
] = RTLIL::SigSpec();
2512 conn_it
= connections_
.find(portname
);
2513 log_assert(conn_it
!= connections_
.end());
2515 if (conn_it
->second
== signal
)
2518 for (auto mon
: module
->monitors
)
2519 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2522 for (auto mon
: module
->design
->monitors
)
2523 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2526 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2527 log_backtrace("-X- ", yosys_xtrace
-1);
2530 conn_it
->second
= signal
;
2533 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2535 return connections_
.at(portname
);
2538 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2540 return connections_
;
2543 bool RTLIL::Cell::known() const
2545 if (yosys_celltypes
.cell_known(type
))
2547 if (module
&& module
->design
&& module
->design
->module(type
))
2552 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2554 if (yosys_celltypes
.cell_known(type
))
2555 return yosys_celltypes
.cell_input(type
, portname
);
2556 if (module
&& module
->design
) {
2557 RTLIL::Module
*m
= module
->design
->module(type
);
2558 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2559 return w
&& w
->port_input
;
2564 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2566 if (yosys_celltypes
.cell_known(type
))
2567 return yosys_celltypes
.cell_output(type
, portname
);
2568 if (module
&& module
->design
) {
2569 RTLIL::Module
*m
= module
->design
->module(type
);
2570 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2571 return w
&& w
->port_output
;
2576 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2578 return parameters
.count(paramname
) != 0;
2581 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2583 parameters
.erase(paramname
);
2586 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2588 parameters
[paramname
] = value
;
2591 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2593 return parameters
.at(paramname
);
2596 void RTLIL::Cell::sort()
2598 connections_
.sort(sort_by_id_str());
2599 parameters
.sort(sort_by_id_str());
2600 attributes
.sort(sort_by_id_str());
2603 void RTLIL::Cell::check()
2606 InternalCellChecker
checker(NULL
, this);
2611 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2613 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
2614 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
2617 if (type
== ID($mux
) || type
== ID($pmux
)) {
2618 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID::Y
]);
2619 if (type
== ID($pmux
))
2620 parameters
[ID(S_WIDTH
)] = GetSize(connections_
[ID(S
)]);
2625 if (type
== ID($lut
) || type
== ID($sop
)) {
2626 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID::A
]);
2630 if (type
== ID($fa
)) {
2631 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID::Y
]);
2635 if (type
== ID($lcu
)) {
2636 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID(CO
)]);
2640 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
2642 if (connections_
.count(ID::A
)) {
2643 if (signedness_ab
) {
2645 parameters
[ID(A_SIGNED
)] = true;
2646 else if (parameters
.count(ID(A_SIGNED
)) == 0)
2647 parameters
[ID(A_SIGNED
)] = false;
2649 parameters
[ID(A_WIDTH
)] = GetSize(connections_
[ID::A
]);
2652 if (connections_
.count(ID::B
)) {
2653 if (signedness_ab
) {
2655 parameters
[ID(B_SIGNED
)] = true;
2656 else if (parameters
.count(ID(B_SIGNED
)) == 0)
2657 parameters
[ID(B_SIGNED
)] = false;
2659 parameters
[ID(B_WIDTH
)] = GetSize(connections_
[ID::B
]);
2662 if (connections_
.count(ID::Y
))
2663 parameters
[ID(Y_WIDTH
)] = GetSize(connections_
[ID::Y
]);
2665 if (connections_
.count(ID(Q
)))
2666 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID(Q
)]);
2671 RTLIL::SigChunk::SigChunk()
2678 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2682 width
= GetSize(data
);
2686 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2688 log_assert(wire
!= nullptr);
2690 this->width
= wire
->width
;
2694 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2696 log_assert(wire
!= nullptr);
2698 this->width
= width
;
2699 this->offset
= offset
;
2702 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2705 data
= RTLIL::Const(str
).bits
;
2706 width
= GetSize(data
);
2710 RTLIL::SigChunk::SigChunk(int val
, int width
)
2713 data
= RTLIL::Const(val
, width
).bits
;
2714 this->width
= GetSize(data
);
2718 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2721 data
= RTLIL::Const(bit
, width
).bits
;
2722 this->width
= GetSize(data
);
2726 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
2731 data
= RTLIL::Const(bit
.data
).bits
;
2733 offset
= bit
.offset
;
2737 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
) : data(sigchunk
.data
)
2739 wire
= sigchunk
.wire
;
2740 data
= sigchunk
.data
;
2741 width
= sigchunk
.width
;
2742 offset
= sigchunk
.offset
;
2745 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2747 RTLIL::SigChunk ret
;
2750 ret
.offset
= this->offset
+ offset
;
2753 for (int i
= 0; i
< length
; i
++)
2754 ret
.data
.push_back(data
[offset
+i
]);
2760 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2762 if (wire
&& other
.wire
)
2763 if (wire
->name
!= other
.wire
->name
)
2764 return wire
->name
< other
.wire
->name
;
2766 if (wire
!= other
.wire
)
2767 return wire
< other
.wire
;
2769 if (offset
!= other
.offset
)
2770 return offset
< other
.offset
;
2772 if (width
!= other
.width
)
2773 return width
< other
.width
;
2775 return data
< other
.data
;
2778 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2780 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2783 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2790 RTLIL::SigSpec::SigSpec()
2796 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2801 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2803 cover("kernel.rtlil.sigspec.init.list");
2808 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2809 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2813 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2815 cover("kernel.rtlil.sigspec.assign");
2817 width_
= other
.width_
;
2818 hash_
= other
.hash_
;
2819 chunks_
= other
.chunks_
;
2822 if (!other
.bits_
.empty())
2824 RTLIL::SigChunk
*last
= NULL
;
2825 int last_end_offset
= 0;
2827 for (auto &bit
: other
.bits_
) {
2828 if (last
&& bit
.wire
== last
->wire
) {
2829 if (bit
.wire
== NULL
) {
2830 last
->data
.push_back(bit
.data
);
2833 } else if (last_end_offset
== bit
.offset
) {
2839 chunks_
.push_back(bit
);
2840 last
= &chunks_
.back();
2841 last_end_offset
= bit
.offset
+ 1;
2850 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2852 cover("kernel.rtlil.sigspec.init.const");
2854 chunks_
.push_back(RTLIL::SigChunk(value
));
2855 width_
= chunks_
.back().width
;
2860 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2862 cover("kernel.rtlil.sigspec.init.chunk");
2864 chunks_
.push_back(chunk
);
2865 width_
= chunks_
.back().width
;
2870 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2872 cover("kernel.rtlil.sigspec.init.wire");
2874 chunks_
.push_back(RTLIL::SigChunk(wire
));
2875 width_
= chunks_
.back().width
;
2880 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2882 cover("kernel.rtlil.sigspec.init.wire_part");
2884 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2885 width_
= chunks_
.back().width
;
2890 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2892 cover("kernel.rtlil.sigspec.init.str");
2894 chunks_
.push_back(RTLIL::SigChunk(str
));
2895 width_
= chunks_
.back().width
;
2900 RTLIL::SigSpec::SigSpec(int val
, int width
)
2902 cover("kernel.rtlil.sigspec.init.int");
2904 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2910 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2912 cover("kernel.rtlil.sigspec.init.state");
2914 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2920 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2922 cover("kernel.rtlil.sigspec.init.bit");
2924 if (bit
.wire
== NULL
)
2925 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2927 for (int i
= 0; i
< width
; i
++)
2928 chunks_
.push_back(bit
);
2934 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2936 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2940 for (auto &c
: chunks
)
2945 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2947 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2951 for (auto &bit
: bits
)
2956 RTLIL::SigSpec::SigSpec(pool
<RTLIL::SigBit
> bits
)
2958 cover("kernel.rtlil.sigspec.init.pool_bits");
2962 for (auto &bit
: bits
)
2967 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2969 cover("kernel.rtlil.sigspec.init.stdset_bits");
2973 for (auto &bit
: bits
)
2978 RTLIL::SigSpec::SigSpec(bool bit
)
2980 cover("kernel.rtlil.sigspec.init.bool");
2988 void RTLIL::SigSpec::pack() const
2990 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2992 if (that
->bits_
.empty())
2995 cover("kernel.rtlil.sigspec.convert.pack");
2996 log_assert(that
->chunks_
.empty());
2998 std::vector
<RTLIL::SigBit
> old_bits
;
2999 old_bits
.swap(that
->bits_
);
3001 RTLIL::SigChunk
*last
= NULL
;
3002 int last_end_offset
= 0;
3004 for (auto &bit
: old_bits
) {
3005 if (last
&& bit
.wire
== last
->wire
) {
3006 if (bit
.wire
== NULL
) {
3007 last
->data
.push_back(bit
.data
);
3010 } else if (last_end_offset
== bit
.offset
) {
3016 that
->chunks_
.push_back(bit
);
3017 last
= &that
->chunks_
.back();
3018 last_end_offset
= bit
.offset
+ 1;
3024 void RTLIL::SigSpec::unpack() const
3026 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3028 if (that
->chunks_
.empty())
3031 cover("kernel.rtlil.sigspec.convert.unpack");
3032 log_assert(that
->bits_
.empty());
3034 that
->bits_
.reserve(that
->width_
);
3035 for (auto &c
: that
->chunks_
)
3036 for (int i
= 0; i
< c
.width
; i
++)
3037 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
3039 that
->chunks_
.clear();
3043 void RTLIL::SigSpec::updhash() const
3045 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3047 if (that
->hash_
!= 0)
3050 cover("kernel.rtlil.sigspec.hash");
3053 that
->hash_
= mkhash_init
;
3054 for (auto &c
: that
->chunks_
)
3055 if (c
.wire
== NULL
) {
3056 for (auto &v
: c
.data
)
3057 that
->hash_
= mkhash(that
->hash_
, v
);
3059 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3060 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3061 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3064 if (that
->hash_
== 0)
3068 void RTLIL::SigSpec::sort()
3071 cover("kernel.rtlil.sigspec.sort");
3072 std::sort(bits_
.begin(), bits_
.end());
3075 void RTLIL::SigSpec::sort_and_unify()
3078 cover("kernel.rtlil.sigspec.sort_and_unify");
3080 // A copy of the bits vector is used to prevent duplicating the logic from
3081 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3082 // that isn't showing up as significant in profiles.
3083 std::vector
<SigBit
> unique_bits
= bits_
;
3084 std::sort(unique_bits
.begin(), unique_bits
.end());
3085 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3086 unique_bits
.erase(last
, unique_bits
.end());
3088 *this = unique_bits
;
3091 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3093 replace(pattern
, with
, this);
3096 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3098 log_assert(other
!= NULL
);
3099 log_assert(width_
== other
->width_
);
3100 log_assert(pattern
.width_
== with
.width_
);
3107 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3108 if (pattern
.bits_
[i
].wire
!= NULL
) {
3109 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3110 if (bits_
[j
] == pattern
.bits_
[i
]) {
3111 other
->bits_
[j
] = with
.bits_
[i
];
3120 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3122 replace(rules
, this);
3125 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3127 cover("kernel.rtlil.sigspec.replace_dict");
3129 log_assert(other
!= NULL
);
3130 log_assert(width_
== other
->width_
);
3132 if (rules
.empty()) return;
3136 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3137 auto it
= rules
.find(bits_
[i
]);
3138 if (it
!= rules
.end())
3139 other
->bits_
[i
] = it
->second
;
3145 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3147 replace(rules
, this);
3150 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3152 cover("kernel.rtlil.sigspec.replace_map");
3154 log_assert(other
!= NULL
);
3155 log_assert(width_
== other
->width_
);
3157 if (rules
.empty()) return;
3161 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3162 auto it
= rules
.find(bits_
[i
]);
3163 if (it
!= rules
.end())
3164 other
->bits_
[i
] = it
->second
;
3170 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3172 remove2(pattern
, NULL
);
3175 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3177 RTLIL::SigSpec tmp
= *this;
3178 tmp
.remove2(pattern
, other
);
3181 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3184 cover("kernel.rtlil.sigspec.remove_other");
3186 cover("kernel.rtlil.sigspec.remove");
3189 if (other
!= NULL
) {
3190 log_assert(width_
== other
->width_
);
3194 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3196 if (bits_
[i
].wire
== NULL
) continue;
3198 for (auto &pattern_chunk
: pattern
.chunks())
3199 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3200 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3201 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3202 bits_
.erase(bits_
.begin() + i
);
3204 if (other
!= NULL
) {
3205 other
->bits_
.erase(other
->bits_
.begin() + i
);
3215 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3217 remove2(pattern
, NULL
);
3220 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3222 RTLIL::SigSpec tmp
= *this;
3223 tmp
.remove2(pattern
, other
);
3226 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3229 cover("kernel.rtlil.sigspec.remove_other");
3231 cover("kernel.rtlil.sigspec.remove");
3235 if (other
!= NULL
) {
3236 log_assert(width_
== other
->width_
);
3240 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3241 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3242 bits_
.erase(bits_
.begin() + i
);
3244 if (other
!= NULL
) {
3245 other
->bits_
.erase(other
->bits_
.begin() + i
);
3254 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3257 cover("kernel.rtlil.sigspec.remove_other");
3259 cover("kernel.rtlil.sigspec.remove");
3263 if (other
!= NULL
) {
3264 log_assert(width_
== other
->width_
);
3268 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3269 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3270 bits_
.erase(bits_
.begin() + i
);
3272 if (other
!= NULL
) {
3273 other
->bits_
.erase(other
->bits_
.begin() + i
);
3282 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3285 cover("kernel.rtlil.sigspec.extract_other");
3287 cover("kernel.rtlil.sigspec.extract");
3289 log_assert(other
== NULL
|| width_
== other
->width_
);
3292 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3294 for (auto& pattern_chunk
: pattern
.chunks()) {
3296 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3297 for (int i
= 0; i
< width_
; i
++)
3298 if (bits_match
[i
].wire
&&
3299 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3300 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3301 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3302 ret
.append_bit(bits_other
[i
]);
3304 for (int i
= 0; i
< width_
; i
++)
3305 if (bits_match
[i
].wire
&&
3306 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3307 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3308 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3309 ret
.append_bit(bits_match
[i
]);
3317 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3320 cover("kernel.rtlil.sigspec.extract_other");
3322 cover("kernel.rtlil.sigspec.extract");
3324 log_assert(other
== NULL
|| width_
== other
->width_
);
3326 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3330 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3331 for (int i
= 0; i
< width_
; i
++)
3332 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3333 ret
.append_bit(bits_other
[i
]);
3335 for (int i
= 0; i
< width_
; i
++)
3336 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3337 ret
.append_bit(bits_match
[i
]);
3344 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3346 cover("kernel.rtlil.sigspec.replace_pos");
3351 log_assert(offset
>= 0);
3352 log_assert(with
.width_
>= 0);
3353 log_assert(offset
+with
.width_
<= width_
);
3355 for (int i
= 0; i
< with
.width_
; i
++)
3356 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3361 void RTLIL::SigSpec::remove_const()
3365 cover("kernel.rtlil.sigspec.remove_const.packed");
3367 std::vector
<RTLIL::SigChunk
> new_chunks
;
3368 new_chunks
.reserve(GetSize(chunks_
));
3371 for (auto &chunk
: chunks_
)
3372 if (chunk
.wire
!= NULL
) {
3373 new_chunks
.push_back(chunk
);
3374 width_
+= chunk
.width
;
3377 chunks_
.swap(new_chunks
);
3381 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3383 std::vector
<RTLIL::SigBit
> new_bits
;
3384 new_bits
.reserve(width_
);
3386 for (auto &bit
: bits_
)
3387 if (bit
.wire
!= NULL
)
3388 new_bits
.push_back(bit
);
3390 bits_
.swap(new_bits
);
3391 width_
= bits_
.size();
3397 void RTLIL::SigSpec::remove(int offset
, int length
)
3399 cover("kernel.rtlil.sigspec.remove_pos");
3403 log_assert(offset
>= 0);
3404 log_assert(length
>= 0);
3405 log_assert(offset
+ length
<= width_
);
3407 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3408 width_
= bits_
.size();
3413 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3416 cover("kernel.rtlil.sigspec.extract_pos");
3417 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3420 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3422 if (signal
.width_
== 0)
3430 cover("kernel.rtlil.sigspec.append");
3432 if (packed() != signal
.packed()) {
3438 for (auto &other_c
: signal
.chunks_
)
3440 auto &my_last_c
= chunks_
.back();
3441 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3442 auto &this_data
= my_last_c
.data
;
3443 auto &other_data
= other_c
.data
;
3444 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3445 my_last_c
.width
+= other_c
.width
;
3447 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3448 my_last_c
.width
+= other_c
.width
;
3450 chunks_
.push_back(other_c
);
3453 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3455 width_
+= signal
.width_
;
3459 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
3463 cover("kernel.rtlil.sigspec.append_bit.packed");
3465 if (chunks_
.size() == 0)
3466 chunks_
.push_back(bit
);
3468 if (bit
.wire
== NULL
)
3469 if (chunks_
.back().wire
== NULL
) {
3470 chunks_
.back().data
.push_back(bit
.data
);
3471 chunks_
.back().width
++;
3473 chunks_
.push_back(bit
);
3475 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3476 chunks_
.back().width
++;
3478 chunks_
.push_back(bit
);
3482 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3483 bits_
.push_back(bit
);
3490 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3492 cover("kernel.rtlil.sigspec.extend_u0");
3497 remove(width
, width_
- width
);
3499 if (width_
< width
) {
3500 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3502 padding
= RTLIL::State::S0
;
3503 while (width_
< width
)
3509 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3511 cover("kernel.rtlil.sigspec.repeat");
3514 for (int i
= 0; i
< num
; i
++)
3520 void RTLIL::SigSpec::check() const
3524 cover("kernel.rtlil.sigspec.check.skip");
3528 cover("kernel.rtlil.sigspec.check.packed");
3531 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3532 const RTLIL::SigChunk chunk
= chunks_
[i
];
3533 if (chunk
.wire
== NULL
) {
3535 log_assert(chunks_
[i
-1].wire
!= NULL
);
3536 log_assert(chunk
.offset
== 0);
3537 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3539 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3540 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3541 log_assert(chunk
.offset
>= 0);
3542 log_assert(chunk
.width
>= 0);
3543 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3544 log_assert(chunk
.data
.size() == 0);
3548 log_assert(w
== width_
);
3549 log_assert(bits_
.empty());
3553 cover("kernel.rtlil.sigspec.check.unpacked");
3555 log_assert(width_
== GetSize(bits_
));
3556 log_assert(chunks_
.empty());
3561 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3563 cover("kernel.rtlil.sigspec.comp_lt");
3568 if (width_
!= other
.width_
)
3569 return width_
< other
.width_
;
3574 if (chunks_
.size() != other
.chunks_
.size())
3575 return chunks_
.size() < other
.chunks_
.size();
3580 if (hash_
!= other
.hash_
)
3581 return hash_
< other
.hash_
;
3583 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3584 if (chunks_
[i
] != other
.chunks_
[i
]) {
3585 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3586 return chunks_
[i
] < other
.chunks_
[i
];
3589 cover("kernel.rtlil.sigspec.comp_lt.equal");
3593 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3595 cover("kernel.rtlil.sigspec.comp_eq");
3600 if (width_
!= other
.width_
)
3603 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3604 // since the RHS will contain one SigChunk of width 0 causing
3605 // the size check below to fail
3612 if (chunks_
.size() != other
.chunks_
.size())
3618 if (hash_
!= other
.hash_
)
3621 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3622 if (chunks_
[i
] != other
.chunks_
[i
]) {
3623 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3627 cover("kernel.rtlil.sigspec.comp_eq.equal");
3631 bool RTLIL::SigSpec::is_wire() const
3633 cover("kernel.rtlil.sigspec.is_wire");
3636 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3639 bool RTLIL::SigSpec::is_chunk() const
3641 cover("kernel.rtlil.sigspec.is_chunk");
3644 return GetSize(chunks_
) == 1;
3647 bool RTLIL::SigSpec::is_fully_const() const
3649 cover("kernel.rtlil.sigspec.is_fully_const");
3652 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3653 if (it
->width
> 0 && it
->wire
!= NULL
)
3658 bool RTLIL::SigSpec::is_fully_zero() const
3660 cover("kernel.rtlil.sigspec.is_fully_zero");
3663 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3664 if (it
->width
> 0 && it
->wire
!= NULL
)
3666 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3667 if (it
->data
[i
] != RTLIL::State::S0
)
3673 bool RTLIL::SigSpec::is_fully_ones() const
3675 cover("kernel.rtlil.sigspec.is_fully_ones");
3678 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3679 if (it
->width
> 0 && it
->wire
!= NULL
)
3681 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3682 if (it
->data
[i
] != RTLIL::State::S1
)
3688 bool RTLIL::SigSpec::is_fully_def() const
3690 cover("kernel.rtlil.sigspec.is_fully_def");
3693 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3694 if (it
->width
> 0 && it
->wire
!= NULL
)
3696 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3697 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3703 bool RTLIL::SigSpec::is_fully_undef() const
3705 cover("kernel.rtlil.sigspec.is_fully_undef");
3708 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3709 if (it
->width
> 0 && it
->wire
!= NULL
)
3711 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3712 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3718 bool RTLIL::SigSpec::has_const() const
3720 cover("kernel.rtlil.sigspec.has_const");
3723 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3724 if (it
->width
> 0 && it
->wire
== NULL
)
3729 bool RTLIL::SigSpec::has_marked_bits() const
3731 cover("kernel.rtlil.sigspec.has_marked_bits");
3734 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3735 if (it
->width
> 0 && it
->wire
== NULL
) {
3736 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3737 if (it
->data
[i
] == RTLIL::State::Sm
)
3743 bool RTLIL::SigSpec::as_bool() const
3745 cover("kernel.rtlil.sigspec.as_bool");
3748 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3750 return RTLIL::Const(chunks_
[0].data
).as_bool();
3754 int RTLIL::SigSpec::as_int(bool is_signed
) const
3756 cover("kernel.rtlil.sigspec.as_int");
3759 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3761 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3765 std::string
RTLIL::SigSpec::as_string() const
3767 cover("kernel.rtlil.sigspec.as_string");
3771 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3772 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3773 if (chunk
.wire
!= NULL
)
3774 for (int j
= 0; j
< chunk
.width
; j
++)
3777 str
+= RTLIL::Const(chunk
.data
).as_string();
3782 RTLIL::Const
RTLIL::SigSpec::as_const() const
3784 cover("kernel.rtlil.sigspec.as_const");
3787 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3789 return chunks_
[0].data
;
3790 return RTLIL::Const();
3793 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3795 cover("kernel.rtlil.sigspec.as_wire");
3798 log_assert(is_wire());
3799 return chunks_
[0].wire
;
3802 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3804 cover("kernel.rtlil.sigspec.as_chunk");
3807 log_assert(is_chunk());
3811 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3813 cover("kernel.rtlil.sigspec.as_bit");
3815 log_assert(width_
== 1);
3817 return RTLIL::SigBit(*chunks_
.begin());
3822 bool RTLIL::SigSpec::match(std::string pattern
) const
3824 cover("kernel.rtlil.sigspec.match");
3827 std::string str
= as_string();
3828 log_assert(pattern
.size() == str
.size());
3830 for (size_t i
= 0; i
< pattern
.size(); i
++) {
3831 if (pattern
[i
] == ' ')
3833 if (pattern
[i
] == '*') {
3834 if (str
[i
] != 'z' && str
[i
] != 'x')
3838 if (pattern
[i
] != str
[i
])
3845 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3847 cover("kernel.rtlil.sigspec.to_sigbit_set");
3850 std::set
<RTLIL::SigBit
> sigbits
;
3851 for (auto &c
: chunks_
)
3852 for (int i
= 0; i
< c
.width
; i
++)
3853 sigbits
.insert(RTLIL::SigBit(c
, i
));
3857 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3859 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3862 pool
<RTLIL::SigBit
> sigbits
;
3863 for (auto &c
: chunks_
)
3864 for (int i
= 0; i
< c
.width
; i
++)
3865 sigbits
.insert(RTLIL::SigBit(c
, i
));
3869 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3871 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3877 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3879 cover("kernel.rtlil.sigspec.to_sigbit_map");
3884 log_assert(width_
== other
.width_
);
3886 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3887 for (int i
= 0; i
< width_
; i
++)
3888 new_map
[bits_
[i
]] = other
.bits_
[i
];
3893 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3895 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3900 log_assert(width_
== other
.width_
);
3902 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3903 for (int i
= 0; i
< width_
; i
++)
3904 new_map
[bits_
[i
]] = other
.bits_
[i
];
3909 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3911 size_t start
= 0, end
= 0;
3912 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3913 tokens
.push_back(text
.substr(start
, end
- start
));
3916 tokens
.push_back(text
.substr(start
));
3919 static int sigspec_parse_get_dummy_line_num()
3924 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3926 cover("kernel.rtlil.sigspec.parse");
3928 AST::current_filename
= "input";
3930 std::vector
<std::string
> tokens
;
3931 sigspec_parse_split(tokens
, str
, ',');
3933 sig
= RTLIL::SigSpec();
3934 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3936 std::string netname
= tokens
[tokidx
];
3937 std::string indices
;
3939 if (netname
.size() == 0)
3942 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3943 cover("kernel.rtlil.sigspec.parse.const");
3944 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3945 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3948 sig
.append(RTLIL::Const(ast
->bits
));
3956 cover("kernel.rtlil.sigspec.parse.net");
3958 if (netname
[0] != '$' && netname
[0] != '\\')
3959 netname
= "\\" + netname
;
3961 if (module
->wires_
.count(netname
) == 0) {
3962 size_t indices_pos
= netname
.size()-1;
3963 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3966 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3967 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3969 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3971 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3972 indices
= netname
.substr(indices_pos
);
3973 netname
= netname
.substr(0, indices_pos
);
3978 if (module
->wires_
.count(netname
) == 0)
3981 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3982 if (!indices
.empty()) {
3983 std::vector
<std::string
> index_tokens
;
3984 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3985 if (index_tokens
.size() == 1) {
3986 cover("kernel.rtlil.sigspec.parse.bit_sel");
3987 int a
= atoi(index_tokens
.at(0).c_str());
3988 if (a
< 0 || a
>= wire
->width
)
3990 sig
.append(RTLIL::SigSpec(wire
, a
));
3992 cover("kernel.rtlil.sigspec.parse.part_sel");
3993 int a
= atoi(index_tokens
.at(0).c_str());
3994 int b
= atoi(index_tokens
.at(1).c_str());
3999 if (a
< 0 || a
>= wire
->width
)
4001 if (b
< 0 || b
>= wire
->width
)
4003 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
4012 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
4014 if (str
.empty() || str
[0] != '@')
4015 return parse(sig
, module
, str
);
4017 cover("kernel.rtlil.sigspec.parse.sel");
4019 str
= RTLIL::escape_id(str
.substr(1));
4020 if (design
->selection_vars
.count(str
) == 0)
4023 sig
= RTLIL::SigSpec();
4024 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
4025 for (auto &it
: module
->wires_
)
4026 if (sel
.selected_member(module
->name
, it
.first
))
4027 sig
.append(it
.second
);
4032 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4035 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4036 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
4041 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4042 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4046 if (lhs
.chunks_
.size() == 1) {
4047 char *p
= (char*)str
.c_str(), *endptr
;
4048 long int val
= strtol(p
, &endptr
, 10);
4049 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4050 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4051 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4056 return parse(sig
, module
, str
);
4059 RTLIL::CaseRule::~CaseRule()
4061 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4065 bool RTLIL::CaseRule::empty() const
4067 return actions
.empty() && switches
.empty();
4070 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4072 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4073 new_caserule
->compare
= compare
;
4074 new_caserule
->actions
= actions
;
4075 for (auto &it
: switches
)
4076 new_caserule
->switches
.push_back(it
->clone());
4077 return new_caserule
;
4080 RTLIL::SwitchRule::~SwitchRule()
4082 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4086 bool RTLIL::SwitchRule::empty() const
4088 return cases
.empty();
4091 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4093 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4094 new_switchrule
->signal
= signal
;
4095 new_switchrule
->attributes
= attributes
;
4096 for (auto &it
: cases
)
4097 new_switchrule
->cases
.push_back(it
->clone());
4098 return new_switchrule
;
4102 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4104 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4105 new_syncrule
->type
= type
;
4106 new_syncrule
->signal
= signal
;
4107 new_syncrule
->actions
= actions
;
4108 return new_syncrule
;
4111 RTLIL::Process::~Process()
4113 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4117 RTLIL::Process
*RTLIL::Process::clone() const
4119 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4121 new_proc
->name
= name
;
4122 new_proc
->attributes
= attributes
;
4124 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4125 new_proc
->root_case
= *rc_ptr
;
4126 rc_ptr
->switches
.clear();
4129 for (auto &it
: syncs
)
4130 new_proc
->syncs
.push_back(it
->clone());
4136 RTLIL::Memory::~Memory()
4138 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4140 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4141 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4143 return &all_memorys
;