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Added std::initializer_list<> constructor to SigSpec
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <assert.h>
27 #include <string.h>
28 #include <algorithm>
29
30 int RTLIL::autoidx = 1;
31
32 RTLIL::Const::Const()
33 {
34 flags = RTLIL::CONST_FLAG_NONE;
35 }
36
37 RTLIL::Const::Const(std::string str)
38 {
39 flags = RTLIL::CONST_FLAG_STRING;
40 for (int i = str.size()-1; i >= 0; i--) {
41 unsigned char ch = str[i];
42 for (int j = 0; j < 8; j++) {
43 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
44 ch = ch >> 1;
45 }
46 }
47 }
48
49 RTLIL::Const::Const(int val, int width)
50 {
51 flags = RTLIL::CONST_FLAG_NONE;
52 for (int i = 0; i < width; i++) {
53 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
54 val = val >> 1;
55 }
56 }
57
58 RTLIL::Const::Const(RTLIL::State bit, int width)
59 {
60 flags = RTLIL::CONST_FLAG_NONE;
61 for (int i = 0; i < width; i++)
62 bits.push_back(bit);
63 }
64
65 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
66 {
67 if (bits.size() != other.bits.size())
68 return bits.size() < other.bits.size();
69 for (size_t i = 0; i < bits.size(); i++)
70 if (bits[i] != other.bits[i])
71 return bits[i] < other.bits[i];
72 return false;
73 }
74
75 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
76 {
77 return bits == other.bits;
78 }
79
80 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
81 {
82 return bits != other.bits;
83 }
84
85 bool RTLIL::Const::as_bool() const
86 {
87 for (size_t i = 0; i < bits.size(); i++)
88 if (bits[i] == RTLIL::S1)
89 return true;
90 return false;
91 }
92
93 int RTLIL::Const::as_int() const
94 {
95 int ret = 0;
96 for (size_t i = 0; i < bits.size() && i < 32; i++)
97 if (bits[i] == RTLIL::S1)
98 ret |= 1 << i;
99 return ret;
100 }
101
102 std::string RTLIL::Const::as_string() const
103 {
104 std::string ret;
105 for (size_t i = bits.size(); i > 0; i--)
106 switch (bits[i-1]) {
107 case S0: ret += "0"; break;
108 case S1: ret += "1"; break;
109 case Sx: ret += "x"; break;
110 case Sz: ret += "z"; break;
111 case Sa: ret += "-"; break;
112 case Sm: ret += "m"; break;
113 }
114 return ret;
115 }
116
117 std::string RTLIL::Const::decode_string() const
118 {
119 std::string string;
120 std::vector <char> string_chars;
121 for (int i = 0; i < int (bits.size()); i += 8) {
122 char ch = 0;
123 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
124 if (bits[i + j] == RTLIL::State::S1)
125 ch |= 1 << j;
126 if (ch != 0)
127 string_chars.push_back(ch);
128 }
129 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
130 string += string_chars[i];
131 return string;
132 }
133
134 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
135 {
136 if (full_selection)
137 return true;
138 if (selected_modules.count(mod_name) > 0)
139 return true;
140 if (selected_members.count(mod_name) > 0)
141 return true;
142 return false;
143 }
144
145 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
146 {
147 if (full_selection)
148 return true;
149 if (selected_modules.count(mod_name) > 0)
150 return true;
151 return false;
152 }
153
154 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
155 {
156 if (full_selection)
157 return true;
158 if (selected_modules.count(mod_name) > 0)
159 return true;
160 if (selected_members.count(mod_name) > 0)
161 if (selected_members.at(mod_name).count(memb_name) > 0)
162 return true;
163 return false;
164 }
165
166 void RTLIL::Selection::optimize(RTLIL::Design *design)
167 {
168 if (full_selection) {
169 selected_modules.clear();
170 selected_members.clear();
171 return;
172 }
173
174 std::vector<RTLIL::IdString> del_list, add_list;
175
176 del_list.clear();
177 for (auto mod_name : selected_modules) {
178 if (design->modules_.count(mod_name) == 0)
179 del_list.push_back(mod_name);
180 selected_members.erase(mod_name);
181 }
182 for (auto mod_name : del_list)
183 selected_modules.erase(mod_name);
184
185 del_list.clear();
186 for (auto &it : selected_members)
187 if (design->modules_.count(it.first) == 0)
188 del_list.push_back(it.first);
189 for (auto mod_name : del_list)
190 selected_members.erase(mod_name);
191
192 for (auto &it : selected_members) {
193 del_list.clear();
194 for (auto memb_name : it.second)
195 if (design->modules_[it.first]->count_id(memb_name) == 0)
196 del_list.push_back(memb_name);
197 for (auto memb_name : del_list)
198 it.second.erase(memb_name);
199 }
200
201 del_list.clear();
202 add_list.clear();
203 for (auto &it : selected_members)
204 if (it.second.size() == 0)
205 del_list.push_back(it.first);
206 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
207 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
208 add_list.push_back(it.first);
209 for (auto mod_name : del_list)
210 selected_members.erase(mod_name);
211 for (auto mod_name : add_list) {
212 selected_members.erase(mod_name);
213 selected_modules.insert(mod_name);
214 }
215
216 if (selected_modules.size() == design->modules_.size()) {
217 full_selection = true;
218 selected_modules.clear();
219 selected_members.clear();
220 }
221 }
222
223 RTLIL::Design::~Design()
224 {
225 for (auto it = modules_.begin(); it != modules_.end(); it++)
226 delete it->second;
227 }
228
229 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
230 {
231 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
232 }
233
234 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
235 {
236 return modules_.count(name) ? modules_.at(name) : NULL;
237 }
238
239 void RTLIL::Design::add(RTLIL::Module *module)
240 {
241 assert(modules_.count(module->name) == 0);
242 assert(refcount_modules_ == 0);
243 modules_[module->name] = module;
244 }
245
246 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
247 {
248 assert(modules_.count(name) == 0);
249 assert(refcount_modules_ == 0);
250 modules_[name] = new RTLIL::Module;
251 modules_[name]->name = name;
252 return modules_[name];
253 }
254
255 void RTLIL::Design::remove(RTLIL::Module *module)
256 {
257 assert(modules_.at(module->name) == module);
258 modules_.erase(module->name);
259 delete module;
260 }
261
262 void RTLIL::Design::check()
263 {
264 #ifndef NDEBUG
265 for (auto &it : modules_) {
266 assert(it.first == it.second->name);
267 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
268 it.second->check();
269 }
270 #endif
271 }
272
273 void RTLIL::Design::optimize()
274 {
275 for (auto &it : modules_)
276 it.second->optimize();
277 for (auto &it : selection_stack)
278 it.optimize(this);
279 for (auto &it : selection_vars)
280 it.second.optimize(this);
281 }
282
283 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
284 {
285 if (!selected_active_module.empty() && mod_name != selected_active_module)
286 return false;
287 if (selection_stack.size() == 0)
288 return true;
289 return selection_stack.back().selected_module(mod_name);
290 }
291
292 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
293 {
294 if (!selected_active_module.empty() && mod_name != selected_active_module)
295 return false;
296 if (selection_stack.size() == 0)
297 return true;
298 return selection_stack.back().selected_whole_module(mod_name);
299 }
300
301 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
302 {
303 if (!selected_active_module.empty() && mod_name != selected_active_module)
304 return false;
305 if (selection_stack.size() == 0)
306 return true;
307 return selection_stack.back().selected_member(mod_name, memb_name);
308 }
309
310 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
311 {
312 return selected_module(mod->name);
313 }
314
315 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
316 {
317 return selected_whole_module(mod->name);
318 }
319
320 RTLIL::Module::Module()
321 {
322 refcount_wires_ = 0;
323 refcount_cells_ = 0;
324 }
325
326 RTLIL::Module::~Module()
327 {
328 for (auto it = wires_.begin(); it != wires_.end(); it++)
329 delete it->second;
330 for (auto it = memories.begin(); it != memories.end(); it++)
331 delete it->second;
332 for (auto it = cells_.begin(); it != cells_.end(); it++)
333 delete it->second;
334 for (auto it = processes.begin(); it != processes.end(); it++)
335 delete it->second;
336 }
337
338 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
339 {
340 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
341 }
342
343 size_t RTLIL::Module::count_id(RTLIL::IdString id)
344 {
345 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
346 }
347
348 #ifndef NDEBUG
349 namespace {
350 struct InternalCellChecker
351 {
352 RTLIL::Module *module;
353 RTLIL::Cell *cell;
354 std::set<RTLIL::IdString> expected_params, expected_ports;
355
356 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
357
358 void error(int linenr)
359 {
360 char *ptr;
361 size_t size;
362
363 FILE *f = open_memstream(&ptr, &size);
364 ILANG_BACKEND::dump_cell(f, " ", cell);
365 fputc(0, f);
366 fclose(f);
367
368 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
369 module ? module->name.c_str() : "", module ? "." : "",
370 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
371 }
372
373 int param(const char *name)
374 {
375 if (cell->parameters.count(name) == 0)
376 error(__LINE__);
377 expected_params.insert(name);
378 return cell->parameters.at(name).as_int();
379 }
380
381 int param_bool(const char *name)
382 {
383 int v = param(name);
384 if (cell->parameters.at(name).bits.size() > 32)
385 error(__LINE__);
386 if (v != 0 && v != 1)
387 error(__LINE__);
388 return v;
389 }
390
391 void param_bits(const char *name, int width)
392 {
393 param(name);
394 if (int(cell->parameters.at(name).bits.size()) != width)
395 error(__LINE__);
396 }
397
398 void port(const char *name, int width)
399 {
400 if (!cell->has(name))
401 error(__LINE__);
402 if (cell->get(name).size() != width)
403 error(__LINE__);
404 expected_ports.insert(name);
405 }
406
407 void check_expected(bool check_matched_sign = true)
408 {
409 for (auto &para : cell->parameters)
410 if (expected_params.count(para.first) == 0)
411 error(__LINE__);
412 for (auto &conn : cell->connections())
413 if (expected_ports.count(conn.first) == 0)
414 error(__LINE__);
415
416 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
417 bool a_is_signed = param("\\A_SIGNED") != 0;
418 bool b_is_signed = param("\\B_SIGNED") != 0;
419 if (a_is_signed != b_is_signed)
420 error(__LINE__);
421 }
422 }
423
424 void check_gate(const char *ports)
425 {
426 if (cell->parameters.size() != 0)
427 error(__LINE__);
428
429 for (const char *p = ports; *p; p++) {
430 char portname[3] = { '\\', *p, 0 };
431 if (!cell->has(portname))
432 error(__LINE__);
433 if (cell->get(portname).size() != 1)
434 error(__LINE__);
435 }
436
437 for (auto &conn : cell->connections()) {
438 if (conn.first.size() != 2 || conn.first.at(0) != '\\')
439 error(__LINE__);
440 if (strchr(ports, conn.first.at(1)) == NULL)
441 error(__LINE__);
442 }
443 }
444
445 void check()
446 {
447 if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
448 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
449 return;
450
451 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
452 param_bool("\\A_SIGNED");
453 port("\\A", param("\\A_WIDTH"));
454 port("\\Y", param("\\Y_WIDTH"));
455 check_expected();
456 return;
457 }
458
459 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
460 param_bool("\\A_SIGNED");
461 param_bool("\\B_SIGNED");
462 port("\\A", param("\\A_WIDTH"));
463 port("\\B", param("\\B_WIDTH"));
464 port("\\Y", param("\\Y_WIDTH"));
465 check_expected();
466 return;
467 }
468
469 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
470 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
471 param_bool("\\A_SIGNED");
472 port("\\A", param("\\A_WIDTH"));
473 port("\\Y", param("\\Y_WIDTH"));
474 check_expected();
475 return;
476 }
477
478 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
479 param_bool("\\A_SIGNED");
480 param_bool("\\B_SIGNED");
481 port("\\A", param("\\A_WIDTH"));
482 port("\\B", param("\\B_WIDTH"));
483 port("\\Y", param("\\Y_WIDTH"));
484 check_expected(false);
485 return;
486 }
487
488 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
489 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
490 param_bool("\\A_SIGNED");
491 param_bool("\\B_SIGNED");
492 port("\\A", param("\\A_WIDTH"));
493 port("\\B", param("\\B_WIDTH"));
494 port("\\Y", param("\\Y_WIDTH"));
495 check_expected();
496 return;
497 }
498
499 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
500 cell->type == "$mod" || cell->type == "$pow") {
501 param_bool("\\A_SIGNED");
502 param_bool("\\B_SIGNED");
503 port("\\A", param("\\A_WIDTH"));
504 port("\\B", param("\\B_WIDTH"));
505 port("\\Y", param("\\Y_WIDTH"));
506 check_expected(cell->type != "$pow");
507 return;
508 }
509
510 if (cell->type == "$logic_not") {
511 param_bool("\\A_SIGNED");
512 port("\\A", param("\\A_WIDTH"));
513 port("\\Y", param("\\Y_WIDTH"));
514 check_expected();
515 return;
516 }
517
518 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
519 param_bool("\\A_SIGNED");
520 param_bool("\\B_SIGNED");
521 port("\\A", param("\\A_WIDTH"));
522 port("\\B", param("\\B_WIDTH"));
523 port("\\Y", param("\\Y_WIDTH"));
524 check_expected(false);
525 return;
526 }
527
528 if (cell->type == "$slice") {
529 param("\\OFFSET");
530 port("\\A", param("\\A_WIDTH"));
531 port("\\Y", param("\\Y_WIDTH"));
532 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
533 error(__LINE__);
534 check_expected();
535 return;
536 }
537
538 if (cell->type == "$concat") {
539 port("\\A", param("\\A_WIDTH"));
540 port("\\B", param("\\B_WIDTH"));
541 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
542 check_expected();
543 return;
544 }
545
546 if (cell->type == "$mux") {
547 port("\\A", param("\\WIDTH"));
548 port("\\B", param("\\WIDTH"));
549 port("\\S", 1);
550 port("\\Y", param("\\WIDTH"));
551 check_expected();
552 return;
553 }
554
555 if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
556 port("\\A", param("\\WIDTH"));
557 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
558 port("\\S", param("\\S_WIDTH"));
559 port("\\Y", param("\\WIDTH"));
560 check_expected();
561 return;
562 }
563
564 if (cell->type == "$lut") {
565 param("\\LUT");
566 port("\\I", param("\\WIDTH"));
567 port("\\O", 1);
568 check_expected();
569 return;
570 }
571
572 if (cell->type == "$sr") {
573 param_bool("\\SET_POLARITY");
574 param_bool("\\CLR_POLARITY");
575 port("\\SET", param("\\WIDTH"));
576 port("\\CLR", param("\\WIDTH"));
577 port("\\Q", param("\\WIDTH"));
578 check_expected();
579 return;
580 }
581
582 if (cell->type == "$dff") {
583 param_bool("\\CLK_POLARITY");
584 port("\\CLK", 1);
585 port("\\D", param("\\WIDTH"));
586 port("\\Q", param("\\WIDTH"));
587 check_expected();
588 return;
589 }
590
591 if (cell->type == "$dffsr") {
592 param_bool("\\CLK_POLARITY");
593 param_bool("\\SET_POLARITY");
594 param_bool("\\CLR_POLARITY");
595 port("\\CLK", 1);
596 port("\\SET", param("\\WIDTH"));
597 port("\\CLR", param("\\WIDTH"));
598 port("\\D", param("\\WIDTH"));
599 port("\\Q", param("\\WIDTH"));
600 check_expected();
601 return;
602 }
603
604 if (cell->type == "$adff") {
605 param_bool("\\CLK_POLARITY");
606 param_bool("\\ARST_POLARITY");
607 param_bits("\\ARST_VALUE", param("\\WIDTH"));
608 port("\\CLK", 1);
609 port("\\ARST", 1);
610 port("\\D", param("\\WIDTH"));
611 port("\\Q", param("\\WIDTH"));
612 check_expected();
613 return;
614 }
615
616 if (cell->type == "$dlatch") {
617 param_bool("\\EN_POLARITY");
618 port("\\EN", 1);
619 port("\\D", param("\\WIDTH"));
620 port("\\Q", param("\\WIDTH"));
621 check_expected();
622 return;
623 }
624
625 if (cell->type == "$dlatchsr") {
626 param_bool("\\EN_POLARITY");
627 param_bool("\\SET_POLARITY");
628 param_bool("\\CLR_POLARITY");
629 port("\\EN", 1);
630 port("\\SET", param("\\WIDTH"));
631 port("\\CLR", param("\\WIDTH"));
632 port("\\D", param("\\WIDTH"));
633 port("\\Q", param("\\WIDTH"));
634 check_expected();
635 return;
636 }
637
638 if (cell->type == "$fsm") {
639 param("\\NAME");
640 param_bool("\\CLK_POLARITY");
641 param_bool("\\ARST_POLARITY");
642 param("\\STATE_BITS");
643 param("\\STATE_NUM");
644 param("\\STATE_NUM_LOG2");
645 param("\\STATE_RST");
646 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
647 param("\\TRANS_NUM");
648 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
649 port("\\CLK", 1);
650 port("\\ARST", 1);
651 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
652 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
653 check_expected();
654 return;
655 }
656
657 if (cell->type == "$memrd") {
658 param("\\MEMID");
659 param_bool("\\CLK_ENABLE");
660 param_bool("\\CLK_POLARITY");
661 param_bool("\\TRANSPARENT");
662 port("\\CLK", 1);
663 port("\\ADDR", param("\\ABITS"));
664 port("\\DATA", param("\\WIDTH"));
665 check_expected();
666 return;
667 }
668
669 if (cell->type == "$memwr") {
670 param("\\MEMID");
671 param_bool("\\CLK_ENABLE");
672 param_bool("\\CLK_POLARITY");
673 param("\\PRIORITY");
674 port("\\CLK", 1);
675 port("\\EN", param("\\WIDTH"));
676 port("\\ADDR", param("\\ABITS"));
677 port("\\DATA", param("\\WIDTH"));
678 check_expected();
679 return;
680 }
681
682 if (cell->type == "$mem") {
683 param("\\MEMID");
684 param("\\SIZE");
685 param("\\OFFSET");
686 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
687 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
688 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
689 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
690 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
691 port("\\RD_CLK", param("\\RD_PORTS"));
692 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
693 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
694 port("\\WR_CLK", param("\\WR_PORTS"));
695 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
696 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
697 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
698 check_expected();
699 return;
700 }
701
702 if (cell->type == "$assert") {
703 port("\\A", 1);
704 port("\\EN", 1);
705 check_expected();
706 return;
707 }
708
709 if (cell->type == "$_INV_") { check_gate("AY"); return; }
710 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
711 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
712 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
713 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
714
715 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
716 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
717 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
718 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
719
720 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
721 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
722
723 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
724 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
725 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
726 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
727 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
728 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
729 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
730 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
731
732 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
733 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
734 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
735 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
736 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
737 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
738 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
739 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
740
741 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
742 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
743
744 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
745 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
746 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
747 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
748 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
749 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
750 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
751 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
752
753 error(__LINE__);
754 }
755 };
756 }
757 #endif
758
759 void RTLIL::Module::check()
760 {
761 #ifndef NDEBUG
762 for (auto &it : wires_) {
763 assert(it.first == it.second->name);
764 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
765 assert(it.second->width >= 0);
766 assert(it.second->port_id >= 0);
767 for (auto &it2 : it.second->attributes) {
768 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
769 }
770 }
771
772 for (auto &it : memories) {
773 assert(it.first == it.second->name);
774 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
775 assert(it.second->width >= 0);
776 assert(it.second->size >= 0);
777 for (auto &it2 : it.second->attributes) {
778 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
779 }
780 }
781
782 for (auto &it : cells_) {
783 assert(it.first == it.second->name);
784 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
785 assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
786 for (auto &it2 : it.second->connections()) {
787 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
788 it2.second.check();
789 }
790 for (auto &it2 : it.second->attributes) {
791 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
792 }
793 for (auto &it2 : it.second->parameters) {
794 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
795 }
796 InternalCellChecker checker(this, it.second);
797 checker.check();
798 }
799
800 for (auto &it : processes) {
801 assert(it.first == it.second->name);
802 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
803 // FIXME: More checks here..
804 }
805
806 for (auto &it : connections_) {
807 assert(it.first.size() == it.second.size());
808 it.first.check();
809 it.second.check();
810 }
811
812 for (auto &it : attributes) {
813 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
814 }
815 #endif
816 }
817
818 void RTLIL::Module::optimize()
819 {
820 }
821
822 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
823 {
824 log_assert(new_mod->refcount_wires_ == 0);
825 log_assert(new_mod->refcount_cells_ == 0);
826
827 new_mod->connections_ = connections_;
828 new_mod->attributes = attributes;
829
830 for (auto &it : wires_)
831 new_mod->addWire(it.first, it.second);
832
833 for (auto &it : memories)
834 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
835
836 for (auto &it : cells_)
837 new_mod->addCell(it.first, it.second);
838
839 for (auto &it : processes)
840 new_mod->processes[it.first] = it.second->clone();
841
842 struct RewriteSigSpecWorker
843 {
844 RTLIL::Module *mod;
845 void operator()(RTLIL::SigSpec &sig)
846 {
847 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
848 for (auto &c : chunks)
849 if (c.wire != NULL)
850 c.wire = mod->wires_.at(c.wire->name);
851 sig = chunks;
852 }
853 };
854
855 RewriteSigSpecWorker rewriteSigSpecWorker;
856 rewriteSigSpecWorker.mod = new_mod;
857 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
858 }
859
860 RTLIL::Module *RTLIL::Module::clone() const
861 {
862 RTLIL::Module *new_mod = new RTLIL::Module;
863 new_mod->name = name;
864 cloneInto(new_mod);
865 return new_mod;
866 }
867
868 void RTLIL::Module::add(RTLIL::Wire *wire)
869 {
870 log_assert(!wire->name.empty());
871 log_assert(count_id(wire->name) == 0);
872 log_assert(refcount_wires_ == 0);
873 wires_[wire->name] = wire;
874 }
875
876 void RTLIL::Module::add(RTLIL::Cell *cell)
877 {
878 log_assert(!cell->name.empty());
879 log_assert(count_id(cell->name) == 0);
880 log_assert(refcount_cells_ == 0);
881 cells_[cell->name] = cell;
882 }
883
884 namespace {
885 struct DeleteWireWorker
886 {
887 RTLIL::Module *module;
888 const std::set<RTLIL::Wire*> *wires_p;
889
890 void operator()(RTLIL::SigSpec &sig) {
891 std::vector<RTLIL::SigChunk> chunks = sig;
892 for (auto &c : chunks)
893 if (c.wire != NULL && wires_p->count(c.wire)) {
894 c.wire = module->addWire(NEW_ID, c.width);
895 c.offset = 0;
896 }
897 sig = chunks;
898 }
899 };
900 }
901
902 #if 0
903 void RTLIL::Module::remove(RTLIL::Wire *wire)
904 {
905 std::set<RTLIL::Wire*> wires_;
906 wires_.insert(wire);
907 remove(wires_);
908 }
909 #endif
910
911 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
912 {
913 log_assert(refcount_wires_ == 0);
914
915 DeleteWireWorker delete_wire_worker;
916 delete_wire_worker.module = this;
917 delete_wire_worker.wires_p = &wires;
918 rewrite_sigspecs(delete_wire_worker);
919
920 for (auto &it : wires) {
921 log_assert(wires_.count(it->name) != 0);
922 wires_.erase(it->name);
923 delete it;
924 }
925 }
926
927 void RTLIL::Module::remove(RTLIL::Cell *cell)
928 {
929 log_assert(cells_.count(cell->name) != 0);
930 log_assert(refcount_cells_ == 0);
931 cells_.erase(cell->name);
932 delete cell;
933 }
934
935 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
936 {
937 assert(wires_[wire->name] == wire);
938 log_assert(refcount_wires_ == 0);
939 wires_.erase(wire->name);
940 wire->name = new_name;
941 add(wire);
942 }
943
944 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
945 {
946 assert(cells_[cell->name] == cell);
947 log_assert(refcount_wires_ == 0);
948 cells_.erase(cell->name);
949 cell->name = new_name;
950 add(cell);
951 }
952
953 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
954 {
955 assert(count_id(old_name) != 0);
956 if (wires_.count(old_name))
957 rename(wires_.at(old_name), new_name);
958 else if (cells_.count(old_name))
959 rename(cells_.at(old_name), new_name);
960 else
961 log_abort();
962 }
963
964 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
965 {
966 if (a->port_id && !b->port_id)
967 return true;
968 if (!a->port_id && b->port_id)
969 return false;
970
971 if (a->port_id == b->port_id)
972 return a->name < b->name;
973 return a->port_id < b->port_id;
974 }
975
976 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
977 {
978 connections_.push_back(conn);
979 }
980
981 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
982 {
983 connections_.push_back(RTLIL::SigSig(lhs, rhs));
984 }
985
986 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
987 {
988 return connections_;
989 }
990
991 void RTLIL::Module::fixup_ports()
992 {
993 std::vector<RTLIL::Wire*> all_ports;
994
995 for (auto &w : wires_)
996 if (w.second->port_input || w.second->port_output)
997 all_ports.push_back(w.second);
998 else
999 w.second->port_id = 0;
1000
1001 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1002 for (size_t i = 0; i < all_ports.size(); i++)
1003 all_ports[i]->port_id = i+1;
1004 }
1005
1006 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1007 {
1008 RTLIL::Wire *wire = new RTLIL::Wire;
1009 wire->name = name;
1010 wire->width = width;
1011 add(wire);
1012 return wire;
1013 }
1014
1015 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1016 {
1017 RTLIL::Wire *wire = addWire(name);
1018 wire->width = other->width;
1019 wire->start_offset = other->start_offset;
1020 wire->port_id = other->port_id;
1021 wire->port_input = other->port_input;
1022 wire->port_output = other->port_output;
1023 wire->attributes = other->attributes;
1024 return wire;
1025 }
1026
1027 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1028 {
1029 RTLIL::Cell *cell = new RTLIL::Cell;
1030 cell->name = name;
1031 cell->type = type;
1032 add(cell);
1033 return cell;
1034 }
1035
1036 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1037 {
1038 RTLIL::Cell *cell = addCell(name, other->type);
1039 cell->connections_ = other->connections_;
1040 cell->parameters = other->parameters;
1041 cell->attributes = other->attributes;
1042 return cell;
1043 }
1044
1045 #define DEF_METHOD(_func, _y_size, _type) \
1046 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1047 RTLIL::Cell *cell = new RTLIL::Cell; \
1048 cell->name = name; \
1049 cell->type = _type; \
1050 cell->parameters["\\A_SIGNED"] = is_signed; \
1051 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1052 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1053 cell->set("\\A", sig_a); \
1054 cell->set("\\Y", sig_y); \
1055 add(cell); \
1056 return cell; \
1057 } \
1058 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1059 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1060 add ## _func(name, sig_a, sig_y, is_signed); \
1061 return sig_y; \
1062 }
1063 DEF_METHOD(Not, sig_a.size(), "$not")
1064 DEF_METHOD(Pos, sig_a.size(), "$pos")
1065 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1066 DEF_METHOD(Neg, sig_a.size(), "$neg")
1067 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1068 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1069 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1070 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1071 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1072 DEF_METHOD(LogicNot, 1, "$logic_not")
1073 #undef DEF_METHOD
1074
1075 #define DEF_METHOD(_func, _y_size, _type) \
1076 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1077 RTLIL::Cell *cell = new RTLIL::Cell; \
1078 cell->name = name; \
1079 cell->type = _type; \
1080 cell->parameters["\\A_SIGNED"] = is_signed; \
1081 cell->parameters["\\B_SIGNED"] = is_signed; \
1082 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1083 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1084 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1085 cell->set("\\A", sig_a); \
1086 cell->set("\\B", sig_b); \
1087 cell->set("\\Y", sig_y); \
1088 add(cell); \
1089 return cell; \
1090 } \
1091 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1092 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1093 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1094 return sig_y; \
1095 }
1096 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1097 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1098 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1099 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1100 DEF_METHOD(Shl, sig_a.size(), "$shl")
1101 DEF_METHOD(Shr, sig_a.size(), "$shr")
1102 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1103 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1104 DEF_METHOD(Lt, 1, "$lt")
1105 DEF_METHOD(Le, 1, "$le")
1106 DEF_METHOD(Eq, 1, "$eq")
1107 DEF_METHOD(Ne, 1, "$ne")
1108 DEF_METHOD(Eqx, 1, "$eqx")
1109 DEF_METHOD(Nex, 1, "$nex")
1110 DEF_METHOD(Ge, 1, "$ge")
1111 DEF_METHOD(Gt, 1, "$gt")
1112 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1113 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1114 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1115 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1116 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1117 DEF_METHOD(LogicAnd, 1, "$logic_and")
1118 DEF_METHOD(LogicOr, 1, "$logic_or")
1119 #undef DEF_METHOD
1120
1121 #define DEF_METHOD(_func, _type, _pmux) \
1122 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1123 RTLIL::Cell *cell = new RTLIL::Cell; \
1124 cell->name = name; \
1125 cell->type = _type; \
1126 cell->parameters["\\WIDTH"] = sig_a.size(); \
1127 cell->parameters["\\WIDTH"] = sig_b.size(); \
1128 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1129 cell->set("\\A", sig_a); \
1130 cell->set("\\B", sig_b); \
1131 cell->set("\\S", sig_s); \
1132 cell->set("\\Y", sig_y); \
1133 add(cell); \
1134 return cell; \
1135 } \
1136 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1137 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1138 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1139 return sig_y; \
1140 }
1141 DEF_METHOD(Mux, "$mux", 0)
1142 DEF_METHOD(Pmux, "$pmux", 1)
1143 DEF_METHOD(SafePmux, "$safe_pmux", 1)
1144 #undef DEF_METHOD
1145
1146 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1147 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1148 RTLIL::Cell *cell = new RTLIL::Cell; \
1149 cell->name = name; \
1150 cell->type = _type; \
1151 cell->set("\\" #_P1, sig1); \
1152 cell->set("\\" #_P2, sig2); \
1153 add(cell); \
1154 return cell; \
1155 } \
1156 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1157 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1158 add ## _func(name, sig1, sig2); \
1159 return sig2; \
1160 }
1161 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1162 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1163 RTLIL::Cell *cell = new RTLIL::Cell; \
1164 cell->name = name; \
1165 cell->type = _type; \
1166 cell->set("\\" #_P1, sig1); \
1167 cell->set("\\" #_P2, sig2); \
1168 cell->set("\\" #_P3, sig3); \
1169 add(cell); \
1170 return cell; \
1171 } \
1172 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1173 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1174 add ## _func(name, sig1, sig2, sig3); \
1175 return sig3; \
1176 }
1177 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1178 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1179 RTLIL::Cell *cell = new RTLIL::Cell; \
1180 cell->name = name; \
1181 cell->type = _type; \
1182 cell->set("\\" #_P1, sig1); \
1183 cell->set("\\" #_P2, sig2); \
1184 cell->set("\\" #_P3, sig3); \
1185 cell->set("\\" #_P4, sig4); \
1186 add(cell); \
1187 return cell; \
1188 } \
1189 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1190 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1191 add ## _func(name, sig1, sig2, sig3, sig4); \
1192 return sig4; \
1193 }
1194 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1195 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1196 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1197 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1198 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1199 #undef DEF_METHOD_2
1200 #undef DEF_METHOD_3
1201 #undef DEF_METHOD_4
1202
1203 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1204 {
1205 RTLIL::Cell *cell = new RTLIL::Cell;
1206 cell->name = name;
1207 cell->type = "$pow";
1208 cell->parameters["\\A_SIGNED"] = a_signed;
1209 cell->parameters["\\B_SIGNED"] = b_signed;
1210 cell->parameters["\\A_WIDTH"] = sig_a.size();
1211 cell->parameters["\\B_WIDTH"] = sig_b.size();
1212 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1213 cell->set("\\A", sig_a);
1214 cell->set("\\B", sig_b);
1215 cell->set("\\Y", sig_y);
1216 add(cell);
1217 return cell;
1218 }
1219
1220 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1221 {
1222 RTLIL::Cell *cell = new RTLIL::Cell;
1223 cell->name = name;
1224 cell->type = "$slice";
1225 cell->parameters["\\A_WIDTH"] = sig_a.size();
1226 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1227 cell->parameters["\\OFFSET"] = offset;
1228 cell->set("\\A", sig_a);
1229 cell->set("\\Y", sig_y);
1230 add(cell);
1231 return cell;
1232 }
1233
1234 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1235 {
1236 RTLIL::Cell *cell = new RTLIL::Cell;
1237 cell->name = name;
1238 cell->type = "$concat";
1239 cell->parameters["\\A_WIDTH"] = sig_a.size();
1240 cell->parameters["\\B_WIDTH"] = sig_b.size();
1241 cell->set("\\A", sig_a);
1242 cell->set("\\B", sig_b);
1243 cell->set("\\Y", sig_y);
1244 add(cell);
1245 return cell;
1246 }
1247
1248 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1249 {
1250 RTLIL::Cell *cell = new RTLIL::Cell;
1251 cell->name = name;
1252 cell->type = "$lut";
1253 cell->parameters["\\LUT"] = lut;
1254 cell->parameters["\\WIDTH"] = sig_i.size();
1255 cell->set("\\I", sig_i);
1256 cell->set("\\O", sig_o);
1257 add(cell);
1258 return cell;
1259 }
1260
1261 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1262 {
1263 RTLIL::Cell *cell = new RTLIL::Cell;
1264 cell->name = name;
1265 cell->type = "$assert";
1266 cell->set("\\A", sig_a);
1267 cell->set("\\EN", sig_en);
1268 add(cell);
1269 return cell;
1270 }
1271
1272 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1273 {
1274 RTLIL::Cell *cell = new RTLIL::Cell;
1275 cell->name = name;
1276 cell->type = "$sr";
1277 cell->parameters["\\SET_POLARITY"] = set_polarity;
1278 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1279 cell->parameters["\\WIDTH"] = sig_q.size();
1280 cell->set("\\SET", sig_set);
1281 cell->set("\\CLR", sig_clr);
1282 cell->set("\\Q", sig_q);
1283 add(cell);
1284 return cell;
1285 }
1286
1287 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1288 {
1289 RTLIL::Cell *cell = new RTLIL::Cell;
1290 cell->name = name;
1291 cell->type = "$dff";
1292 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1293 cell->parameters["\\WIDTH"] = sig_q.size();
1294 cell->set("\\CLK", sig_clk);
1295 cell->set("\\D", sig_d);
1296 cell->set("\\Q", sig_q);
1297 add(cell);
1298 return cell;
1299 }
1300
1301 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1302 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1303 {
1304 RTLIL::Cell *cell = new RTLIL::Cell;
1305 cell->name = name;
1306 cell->type = "$dffsr";
1307 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1308 cell->parameters["\\SET_POLARITY"] = set_polarity;
1309 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1310 cell->parameters["\\WIDTH"] = sig_q.size();
1311 cell->set("\\CLK", sig_clk);
1312 cell->set("\\SET", sig_set);
1313 cell->set("\\CLR", sig_clr);
1314 cell->set("\\D", sig_d);
1315 cell->set("\\Q", sig_q);
1316 add(cell);
1317 return cell;
1318 }
1319
1320 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1321 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1322 {
1323 RTLIL::Cell *cell = new RTLIL::Cell;
1324 cell->name = name;
1325 cell->type = "$adff";
1326 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1327 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1328 cell->parameters["\\ARST_VALUE"] = arst_value;
1329 cell->parameters["\\WIDTH"] = sig_q.size();
1330 cell->set("\\CLK", sig_clk);
1331 cell->set("\\ARST", sig_arst);
1332 cell->set("\\D", sig_d);
1333 cell->set("\\Q", sig_q);
1334 add(cell);
1335 return cell;
1336 }
1337
1338 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1339 {
1340 RTLIL::Cell *cell = new RTLIL::Cell;
1341 cell->name = name;
1342 cell->type = "$dlatch";
1343 cell->parameters["\\EN_POLARITY"] = en_polarity;
1344 cell->parameters["\\WIDTH"] = sig_q.size();
1345 cell->set("\\EN", sig_en);
1346 cell->set("\\D", sig_d);
1347 cell->set("\\Q", sig_q);
1348 add(cell);
1349 return cell;
1350 }
1351
1352 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1353 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1354 {
1355 RTLIL::Cell *cell = new RTLIL::Cell;
1356 cell->name = name;
1357 cell->type = "$dlatchsr";
1358 cell->parameters["\\EN_POLARITY"] = en_polarity;
1359 cell->parameters["\\SET_POLARITY"] = set_polarity;
1360 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1361 cell->parameters["\\WIDTH"] = sig_q.size();
1362 cell->set("\\EN", sig_en);
1363 cell->set("\\SET", sig_set);
1364 cell->set("\\CLR", sig_clr);
1365 cell->set("\\D", sig_d);
1366 cell->set("\\Q", sig_q);
1367 add(cell);
1368 return cell;
1369 }
1370
1371 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1372 {
1373 RTLIL::Cell *cell = new RTLIL::Cell;
1374 cell->name = name;
1375 cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
1376 cell->set("\\C", sig_clk);
1377 cell->set("\\D", sig_d);
1378 cell->set("\\Q", sig_q);
1379 add(cell);
1380 return cell;
1381 }
1382
1383 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1384 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1385 {
1386 RTLIL::Cell *cell = new RTLIL::Cell;
1387 cell->name = name;
1388 cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1389 cell->set("\\C", sig_clk);
1390 cell->set("\\S", sig_set);
1391 cell->set("\\R", sig_clr);
1392 cell->set("\\D", sig_d);
1393 cell->set("\\Q", sig_q);
1394 add(cell);
1395 return cell;
1396 }
1397
1398 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1399 bool arst_value, bool clk_polarity, bool arst_polarity)
1400 {
1401 RTLIL::Cell *cell = new RTLIL::Cell;
1402 cell->name = name;
1403 cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
1404 cell->set("\\C", sig_clk);
1405 cell->set("\\R", sig_arst);
1406 cell->set("\\D", sig_d);
1407 cell->set("\\Q", sig_q);
1408 add(cell);
1409 return cell;
1410 }
1411
1412 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1413 {
1414 RTLIL::Cell *cell = new RTLIL::Cell;
1415 cell->name = name;
1416 cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
1417 cell->set("\\E", sig_en);
1418 cell->set("\\D", sig_d);
1419 cell->set("\\Q", sig_q);
1420 add(cell);
1421 return cell;
1422 }
1423
1424 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1425 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1426 {
1427 RTLIL::Cell *cell = new RTLIL::Cell;
1428 cell->name = name;
1429 cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1430 cell->set("\\E", sig_en);
1431 cell->set("\\S", sig_set);
1432 cell->set("\\R", sig_clr);
1433 cell->set("\\D", sig_d);
1434 cell->set("\\Q", sig_q);
1435 add(cell);
1436 return cell;
1437 }
1438
1439
1440 RTLIL::Wire::Wire()
1441 {
1442 width = 1;
1443 start_offset = 0;
1444 port_id = 0;
1445 port_input = false;
1446 port_output = false;
1447 }
1448
1449 RTLIL::Memory::Memory()
1450 {
1451 width = 1;
1452 size = 0;
1453 }
1454
1455 bool RTLIL::Cell::has(RTLIL::IdString portname)
1456 {
1457 return connections_.count(portname) != 0;
1458 }
1459
1460 void RTLIL::Cell::unset(RTLIL::IdString portname)
1461 {
1462 connections_.erase(portname);
1463 }
1464
1465 void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
1466 {
1467 connections_[portname] = signal;
1468 }
1469
1470 const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
1471 {
1472 return connections_.at(portname);
1473 }
1474
1475 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1476 {
1477 return connections_;
1478 }
1479
1480 void RTLIL::Cell::check()
1481 {
1482 #ifndef NDEBUG
1483 InternalCellChecker checker(NULL, this);
1484 checker.check();
1485 #endif
1486 }
1487
1488 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1489 {
1490 if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1491 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1492 return;
1493
1494 if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
1495 {
1496 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1497 if (type == "$pmux" || type == "$safe_pmux")
1498 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1499 check();
1500 return;
1501 }
1502
1503 bool signedness_ab = type != "$slice" && type != "$concat";
1504
1505 if (connections_.count("\\A")) {
1506 if (signedness_ab) {
1507 if (set_a_signed)
1508 parameters["\\A_SIGNED"] = true;
1509 else if (parameters.count("\\A_SIGNED") == 0)
1510 parameters["\\A_SIGNED"] = false;
1511 }
1512 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1513 }
1514
1515 if (connections_.count("\\B")) {
1516 if (signedness_ab) {
1517 if (set_b_signed)
1518 parameters["\\B_SIGNED"] = true;
1519 else if (parameters.count("\\B_SIGNED") == 0)
1520 parameters["\\B_SIGNED"] = false;
1521 }
1522 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1523 }
1524
1525 if (connections_.count("\\Y"))
1526 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1527
1528 check();
1529 }
1530
1531 RTLIL::SigChunk::SigChunk()
1532 {
1533 wire = NULL;
1534 width = 0;
1535 offset = 0;
1536 }
1537
1538 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1539 {
1540 wire = NULL;
1541 data = value;
1542 width = data.bits.size();
1543 offset = 0;
1544 }
1545
1546 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1547 {
1548 log_assert(wire != nullptr);
1549 this->wire = wire;
1550 this->width = wire->width;
1551 this->offset = 0;
1552 }
1553
1554 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1555 {
1556 log_assert(wire != nullptr);
1557 this->wire = wire;
1558 this->width = width;
1559 this->offset = offset;
1560 }
1561
1562 RTLIL::SigChunk::SigChunk(const std::string &str)
1563 {
1564 wire = NULL;
1565 data = RTLIL::Const(str);
1566 width = data.bits.size();
1567 offset = 0;
1568 }
1569
1570 RTLIL::SigChunk::SigChunk(int val, int width)
1571 {
1572 wire = NULL;
1573 data = RTLIL::Const(val, width);
1574 this->width = data.bits.size();
1575 offset = 0;
1576 }
1577
1578 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1579 {
1580 wire = NULL;
1581 data = RTLIL::Const(bit, width);
1582 this->width = data.bits.size();
1583 offset = 0;
1584 }
1585
1586 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1587 {
1588 wire = bit.wire;
1589 if (wire == NULL)
1590 data = RTLIL::Const(bit.data);
1591 offset = bit.offset;
1592 width = 1;
1593 }
1594
1595 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1596 {
1597 RTLIL::SigChunk ret;
1598 if (wire) {
1599 ret.wire = wire;
1600 ret.offset = this->offset + offset;
1601 ret.width = length;
1602 } else {
1603 for (int i = 0; i < length; i++)
1604 ret.data.bits.push_back(data.bits[offset+i]);
1605 ret.width = length;
1606 }
1607 return ret;
1608 }
1609
1610 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1611 {
1612 if (wire && other.wire)
1613 if (wire->name != other.wire->name)
1614 return wire->name < other.wire->name;
1615
1616 if (wire != other.wire)
1617 return wire < other.wire;
1618
1619 if (offset != other.offset)
1620 return offset < other.offset;
1621
1622 if (width != other.width)
1623 return width < other.width;
1624
1625 return data.bits < other.data.bits;
1626 }
1627
1628 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1629 {
1630 if (wire != other.wire || width != other.width || offset != other.offset)
1631 return false;
1632 if (data.bits != other.data.bits)
1633 return false;
1634 return true;
1635 }
1636
1637 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1638 {
1639 if (*this == other)
1640 return false;
1641 return true;
1642 }
1643
1644 RTLIL::SigSpec::SigSpec()
1645 {
1646 width_ = 0;
1647 hash_ = 0;
1648 }
1649
1650 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1651 {
1652 *this = other;
1653 }
1654
1655 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1656 {
1657 cover("kernel.rtlil.sigspec.init.list");
1658
1659 width_ = 0;
1660 hash_ = 0;
1661
1662 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1663 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1664 append(*it);
1665 }
1666
1667 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1668 {
1669 cover("kernel.rtlil.sigspec.assign");
1670
1671 width_ = other.width_;
1672 hash_ = other.hash_;
1673 chunks_ = other.chunks_;
1674 bits_.clear();
1675
1676 if (!other.bits_.empty())
1677 {
1678 RTLIL::SigChunk *last = NULL;
1679 int last_end_offset = 0;
1680
1681 for (auto &bit : other.bits_) {
1682 if (last && bit.wire == last->wire) {
1683 if (bit.wire == NULL) {
1684 last->data.bits.push_back(bit.data);
1685 last->width++;
1686 continue;
1687 } else if (last_end_offset == bit.offset) {
1688 last_end_offset++;
1689 last->width++;
1690 continue;
1691 }
1692 }
1693 chunks_.push_back(bit);
1694 last = &chunks_.back();
1695 last_end_offset = bit.offset + 1;
1696 }
1697
1698 check();
1699 }
1700
1701 return *this;
1702 }
1703
1704 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1705 {
1706 cover("kernel.rtlil.sigspec.init.const");
1707
1708 chunks_.push_back(RTLIL::SigChunk(value));
1709 width_ = chunks_.back().width;
1710 hash_ = 0;
1711 check();
1712 }
1713
1714 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1715 {
1716 cover("kernel.rtlil.sigspec.init.chunk");
1717
1718 chunks_.push_back(chunk);
1719 width_ = chunks_.back().width;
1720 hash_ = 0;
1721 check();
1722 }
1723
1724 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1725 {
1726 cover("kernel.rtlil.sigspec.init.wire");
1727
1728 chunks_.push_back(RTLIL::SigChunk(wire));
1729 width_ = chunks_.back().width;
1730 hash_ = 0;
1731 check();
1732 }
1733
1734 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1735 {
1736 cover("kernel.rtlil.sigspec.init.wire_part");
1737
1738 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1739 width_ = chunks_.back().width;
1740 hash_ = 0;
1741 check();
1742 }
1743
1744 RTLIL::SigSpec::SigSpec(const std::string &str)
1745 {
1746 cover("kernel.rtlil.sigspec.init.str");
1747
1748 chunks_.push_back(RTLIL::SigChunk(str));
1749 width_ = chunks_.back().width;
1750 hash_ = 0;
1751 check();
1752 }
1753
1754 RTLIL::SigSpec::SigSpec(int val, int width)
1755 {
1756 cover("kernel.rtlil.sigspec.init.int");
1757
1758 chunks_.push_back(RTLIL::SigChunk(val, width));
1759 width_ = width;
1760 hash_ = 0;
1761 check();
1762 }
1763
1764 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1765 {
1766 cover("kernel.rtlil.sigspec.init.state");
1767
1768 chunks_.push_back(RTLIL::SigChunk(bit, width));
1769 width_ = width;
1770 hash_ = 0;
1771 check();
1772 }
1773
1774 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1775 {
1776 cover("kernel.rtlil.sigspec.init.bit");
1777
1778 if (bit.wire == NULL)
1779 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1780 else
1781 for (int i = 0; i < width; i++)
1782 chunks_.push_back(bit);
1783 width_ = width;
1784 hash_ = 0;
1785 check();
1786 }
1787
1788 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1789 {
1790 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1791
1792 width_ = 0;
1793 hash_ = 0;
1794 for (auto &c : chunks)
1795 append(c);
1796 check();
1797 }
1798
1799 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1800 {
1801 cover("kernel.rtlil.sigspec.init.stdvec_bits");
1802
1803 width_ = 0;
1804 hash_ = 0;
1805 for (auto &bit : bits)
1806 append_bit(bit);
1807 check();
1808 }
1809
1810 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1811 {
1812 cover("kernel.rtlil.sigspec.init.stdset_bits");
1813
1814 width_ = 0;
1815 hash_ = 0;
1816 for (auto &bit : bits)
1817 append_bit(bit);
1818 check();
1819 }
1820
1821 void RTLIL::SigSpec::pack() const
1822 {
1823 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1824
1825 if (that->bits_.empty())
1826 return;
1827
1828 cover("kernel.rtlil.sigspec.convert.pack");
1829 log_assert(that->chunks_.empty());
1830
1831 std::vector<RTLIL::SigBit> old_bits;
1832 old_bits.swap(that->bits_);
1833
1834 RTLIL::SigChunk *last = NULL;
1835 int last_end_offset = 0;
1836
1837 for (auto &bit : old_bits) {
1838 if (last && bit.wire == last->wire) {
1839 if (bit.wire == NULL) {
1840 last->data.bits.push_back(bit.data);
1841 last->width++;
1842 continue;
1843 } else if (last_end_offset == bit.offset) {
1844 last_end_offset++;
1845 last->width++;
1846 continue;
1847 }
1848 }
1849 that->chunks_.push_back(bit);
1850 last = &that->chunks_.back();
1851 last_end_offset = bit.offset + 1;
1852 }
1853
1854 check();
1855 }
1856
1857 void RTLIL::SigSpec::unpack() const
1858 {
1859 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1860
1861 if (that->chunks_.empty())
1862 return;
1863
1864 cover("kernel.rtlil.sigspec.convert.unpack");
1865 log_assert(that->bits_.empty());
1866
1867 that->bits_.reserve(that->width_);
1868 for (auto &c : that->chunks_)
1869 for (int i = 0; i < c.width; i++)
1870 that->bits_.push_back(RTLIL::SigBit(c, i));
1871
1872 that->chunks_.clear();
1873 that->hash_ = 0;
1874 }
1875
1876 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
1877
1878 void RTLIL::SigSpec::hash() const
1879 {
1880 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1881
1882 if (that->hash_ != 0)
1883 return;
1884
1885 cover("kernel.rtlil.sigspec.hash");
1886 that->pack();
1887
1888 that->hash_ = 5381;
1889 for (auto &c : that->chunks_)
1890 if (c.wire == NULL) {
1891 for (auto &v : c.data.bits)
1892 DJB2(that->hash_, v);
1893 } else {
1894 for (auto &v : c.wire->name)
1895 DJB2(that->hash_, v);
1896 DJB2(that->hash_, c.offset);
1897 DJB2(that->hash_, c.width);
1898 }
1899
1900 if (that->hash_ == 0)
1901 that->hash_ = 1;
1902 }
1903
1904 void RTLIL::SigSpec::sort()
1905 {
1906 unpack();
1907 cover("kernel.rtlil.sigspec.sort");
1908 std::sort(bits_.begin(), bits_.end());
1909 }
1910
1911 void RTLIL::SigSpec::sort_and_unify()
1912 {
1913 cover("kernel.rtlil.sigspec.sort_and_unify");
1914 *this = this->to_sigbit_set();
1915 }
1916
1917 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
1918 {
1919 replace(pattern, with, this);
1920 }
1921
1922 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
1923 {
1924 cover("kernel.rtlil.sigspec.replace");
1925
1926 unpack();
1927 pattern.unpack();
1928 with.unpack();
1929
1930 assert(other != NULL);
1931 assert(width_ == other->width_);
1932 other->unpack();
1933
1934 assert(pattern.width_ == with.width_);
1935
1936 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
1937 for (int i = 0; i < SIZE(pattern.bits_); i++)
1938 if (pattern.bits_[i].wire != NULL)
1939 pattern_map[pattern.bits_[i]] = with.bits_[i];
1940
1941 for (int i = 0; i < SIZE(bits_); i++)
1942 if (pattern_map.count(bits_[i]))
1943 other->bits_[i] = pattern_map.at(bits_[i]);
1944
1945 other->check();
1946 }
1947
1948 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
1949 {
1950 remove2(pattern, NULL);
1951 }
1952
1953 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
1954 {
1955 RTLIL::SigSpec tmp = *this;
1956 tmp.remove2(pattern, other);
1957 }
1958
1959 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
1960 {
1961 if (other)
1962 cover("kernel.rtlil.sigspec.remove_other");
1963 else
1964 cover("kernel.rtlil.sigspec.remove");
1965
1966 unpack();
1967
1968 if (other != NULL) {
1969 assert(width_ == other->width_);
1970 other->unpack();
1971 }
1972
1973 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
1974 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
1975
1976 for (int i = 0; i < SIZE(bits_); i++) {
1977 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
1978 continue;
1979 if (other != NULL)
1980 new_other_bits.push_back(other->bits_[i]);
1981 new_bits.push_back(bits_[i]);
1982 }
1983
1984 bits_.swap(new_bits);
1985 width_ = SIZE(bits_);
1986
1987 if (other != NULL) {
1988 other->bits_.swap(new_other_bits);
1989 other->width_ = SIZE(other->bits_);
1990 }
1991
1992 check();
1993 }
1994
1995 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
1996 {
1997 if (other)
1998 cover("kernel.rtlil.sigspec.extract_other");
1999 else
2000 cover("kernel.rtlil.sigspec.extract");
2001
2002 pack();
2003 pattern.pack();
2004
2005 if (other != NULL)
2006 other->pack();
2007
2008 assert(other == NULL || width_ == other->width_);
2009
2010 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
2011 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2012 RTLIL::SigSpec ret;
2013
2014 if (other) {
2015 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2016 for (int i = 0; i < width_; i++)
2017 if (bits_match[i].wire && pat.count(bits_match[i]))
2018 ret.append_bit(bits_other[i]);
2019 } else {
2020 for (int i = 0; i < width_; i++)
2021 if (bits_match[i].wire && pat.count(bits_match[i]))
2022 ret.append_bit(bits_match[i]);
2023 }
2024
2025 ret.check();
2026 return ret;
2027 }
2028
2029 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2030 {
2031 cover("kernel.rtlil.sigspec.replace_pos");
2032
2033 unpack();
2034 with.unpack();
2035
2036 assert(offset >= 0);
2037 assert(with.width_ >= 0);
2038 assert(offset+with.width_ <= width_);
2039
2040 for (int i = 0; i < with.width_; i++)
2041 bits_.at(offset + i) = with.bits_.at(i);
2042
2043 check();
2044 }
2045
2046 void RTLIL::SigSpec::remove_const()
2047 {
2048 if (packed())
2049 {
2050 cover("kernel.rtlil.sigspec.remove_const.packed");
2051
2052 std::vector<RTLIL::SigChunk> new_chunks;
2053 new_chunks.reserve(SIZE(chunks_));
2054
2055 width_ = 0;
2056 for (auto &chunk : chunks_)
2057 if (chunk.wire != NULL) {
2058 new_chunks.push_back(chunk);
2059 width_ += chunk.width;
2060 }
2061
2062 chunks_.swap(new_chunks);
2063 }
2064 else
2065 {
2066 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2067
2068 std::vector<RTLIL::SigBit> new_bits;
2069 new_bits.reserve(width_);
2070
2071 for (auto &bit : bits_)
2072 if (bit.wire != NULL)
2073 new_bits.push_back(bit);
2074
2075 bits_.swap(new_bits);
2076 width_ = bits_.size();
2077 }
2078
2079 check();
2080 }
2081
2082 void RTLIL::SigSpec::remove(int offset, int length)
2083 {
2084 cover("kernel.rtlil.sigspec.remove_pos");
2085
2086 unpack();
2087
2088 assert(offset >= 0);
2089 assert(length >= 0);
2090 assert(offset + length <= width_);
2091
2092 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2093 width_ = bits_.size();
2094
2095 check();
2096 }
2097
2098 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2099 {
2100 unpack();
2101 cover("kernel.rtlil.sigspec.extract_pos");
2102 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2103 }
2104
2105 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2106 {
2107 if (signal.width_ == 0)
2108 return;
2109
2110 if (width_ == 0) {
2111 *this = signal;
2112 return;
2113 }
2114
2115 cover("kernel.rtlil.sigspec.append");
2116
2117 if (packed() != signal.packed()) {
2118 pack();
2119 signal.pack();
2120 }
2121
2122 if (packed())
2123 for (auto &other_c : signal.chunks_)
2124 {
2125 auto &my_last_c = chunks_.back();
2126 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2127 auto &this_data = my_last_c.data.bits;
2128 auto &other_data = other_c.data.bits;
2129 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2130 my_last_c.width += other_c.width;
2131 } else
2132 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2133 my_last_c.width += other_c.width;
2134 } else
2135 chunks_.push_back(other_c);
2136 }
2137 else
2138 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2139
2140 width_ += signal.width_;
2141 check();
2142 }
2143
2144 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2145 {
2146 if (packed())
2147 {
2148 cover("kernel.rtlil.sigspec.append_bit.packed");
2149
2150 if (chunks_.size() == 0)
2151 chunks_.push_back(bit);
2152 else
2153 if (bit.wire == NULL)
2154 if (chunks_.back().wire == NULL) {
2155 chunks_.back().data.bits.push_back(bit.data);
2156 chunks_.back().width++;
2157 } else
2158 chunks_.push_back(bit);
2159 else
2160 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2161 chunks_.back().width++;
2162 else
2163 chunks_.push_back(bit);
2164 }
2165 else
2166 {
2167 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2168 bits_.push_back(bit);
2169 }
2170
2171 width_++;
2172 check();
2173 }
2174
2175 void RTLIL::SigSpec::extend(int width, bool is_signed)
2176 {
2177 cover("kernel.rtlil.sigspec.extend");
2178
2179 pack();
2180
2181 if (width_ > width)
2182 remove(width, width_ - width);
2183
2184 if (width_ < width) {
2185 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2186 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2187 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2188 padding = RTLIL::SigSpec(RTLIL::State::S0);
2189 while (width_ < width)
2190 append(padding);
2191 }
2192 }
2193
2194 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2195 {
2196 cover("kernel.rtlil.sigspec.extend_u0");
2197
2198 pack();
2199
2200 if (width_ > width)
2201 remove(width, width_ - width);
2202
2203 if (width_ < width) {
2204 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2205 if (!is_signed)
2206 padding = RTLIL::SigSpec(RTLIL::State::S0);
2207 while (width_ < width)
2208 append(padding);
2209 }
2210
2211 }
2212
2213 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2214 {
2215 cover("kernel.rtlil.sigspec.repeat");
2216
2217 RTLIL::SigSpec sig;
2218 for (int i = 0; i < num; i++)
2219 sig.append(*this);
2220 return sig;
2221 }
2222
2223 #ifndef NDEBUG
2224 void RTLIL::SigSpec::check() const
2225 {
2226 if (width_ > 64)
2227 {
2228 cover("kernel.rtlil.sigspec.check.skip");
2229 }
2230 else if (packed())
2231 {
2232 cover("kernel.rtlil.sigspec.check.packed");
2233
2234 int w = 0;
2235 for (size_t i = 0; i < chunks_.size(); i++) {
2236 const RTLIL::SigChunk chunk = chunks_[i];
2237 if (chunk.wire == NULL) {
2238 if (i > 0)
2239 assert(chunks_[i-1].wire != NULL);
2240 assert(chunk.offset == 0);
2241 assert(chunk.data.bits.size() == (size_t)chunk.width);
2242 } else {
2243 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2244 assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2245 assert(chunk.offset >= 0);
2246 assert(chunk.width >= 0);
2247 assert(chunk.offset + chunk.width <= chunk.wire->width);
2248 assert(chunk.data.bits.size() == 0);
2249 }
2250 w += chunk.width;
2251 }
2252 assert(w == width_);
2253 assert(bits_.empty());
2254 }
2255 else
2256 {
2257 cover("kernel.rtlil.sigspec.check.unpacked");
2258
2259 assert(width_ == SIZE(bits_));
2260 assert(chunks_.empty());
2261 }
2262 }
2263 #endif
2264
2265 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2266 {
2267 cover("kernel.rtlil.sigspec.comp_lt");
2268
2269 if (this == &other)
2270 return false;
2271
2272 if (width_ != other.width_)
2273 return width_ < other.width_;
2274
2275 pack();
2276 other.pack();
2277
2278 if (chunks_.size() != other.chunks_.size())
2279 return chunks_.size() < other.chunks_.size();
2280
2281 hash();
2282 other.hash();
2283
2284 if (hash_ != other.hash_)
2285 return hash_ < other.hash_;
2286
2287 for (size_t i = 0; i < chunks_.size(); i++)
2288 if (chunks_[i] != other.chunks_[i]) {
2289 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2290 return chunks_[i] < other.chunks_[i];
2291 }
2292
2293 cover("kernel.rtlil.sigspec.comp_lt.equal");
2294 return false;
2295 }
2296
2297 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2298 {
2299 cover("kernel.rtlil.sigspec.comp_eq");
2300
2301 if (this == &other)
2302 return true;
2303
2304 if (width_ != other.width_)
2305 return false;
2306
2307 pack();
2308 other.pack();
2309
2310 if (chunks_.size() != chunks_.size())
2311 return false;
2312
2313 hash();
2314 other.hash();
2315
2316 if (hash_ != other.hash_)
2317 return false;
2318
2319 for (size_t i = 0; i < chunks_.size(); i++)
2320 if (chunks_[i] != other.chunks_[i]) {
2321 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2322 return false;
2323 }
2324
2325 cover("kernel.rtlil.sigspec.comp_eq.equal");
2326 return true;
2327 }
2328
2329 bool RTLIL::SigSpec::is_wire() const
2330 {
2331 cover("kernel.rtlil.sigspec.is_wire");
2332
2333 pack();
2334 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2335 }
2336
2337 bool RTLIL::SigSpec::is_chunk() const
2338 {
2339 cover("kernel.rtlil.sigspec.is_chunk");
2340
2341 pack();
2342 return SIZE(chunks_) == 1;
2343 }
2344
2345 bool RTLIL::SigSpec::is_fully_const() const
2346 {
2347 cover("kernel.rtlil.sigspec.is_fully_const");
2348
2349 pack();
2350 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2351 if (it->width > 0 && it->wire != NULL)
2352 return false;
2353 return true;
2354 }
2355
2356 bool RTLIL::SigSpec::is_fully_def() const
2357 {
2358 cover("kernel.rtlil.sigspec.is_fully_def");
2359
2360 pack();
2361 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2362 if (it->width > 0 && it->wire != NULL)
2363 return false;
2364 for (size_t i = 0; i < it->data.bits.size(); i++)
2365 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2366 return false;
2367 }
2368 return true;
2369 }
2370
2371 bool RTLIL::SigSpec::is_fully_undef() const
2372 {
2373 cover("kernel.rtlil.sigspec.is_fully_undef");
2374
2375 pack();
2376 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2377 if (it->width > 0 && it->wire != NULL)
2378 return false;
2379 for (size_t i = 0; i < it->data.bits.size(); i++)
2380 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2381 return false;
2382 }
2383 return true;
2384 }
2385
2386 bool RTLIL::SigSpec::has_marked_bits() const
2387 {
2388 cover("kernel.rtlil.sigspec.has_marked_bits");
2389
2390 pack();
2391 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2392 if (it->width > 0 && it->wire == NULL) {
2393 for (size_t i = 0; i < it->data.bits.size(); i++)
2394 if (it->data.bits[i] == RTLIL::State::Sm)
2395 return true;
2396 }
2397 return false;
2398 }
2399
2400 bool RTLIL::SigSpec::as_bool() const
2401 {
2402 cover("kernel.rtlil.sigspec.as_bool");
2403
2404 pack();
2405 assert(is_fully_const() && SIZE(chunks_) <= 1);
2406 if (width_)
2407 return chunks_[0].data.as_bool();
2408 return false;
2409 }
2410
2411 int RTLIL::SigSpec::as_int() const
2412 {
2413 cover("kernel.rtlil.sigspec.as_int");
2414
2415 pack();
2416 assert(is_fully_const() && SIZE(chunks_) <= 1);
2417 if (width_)
2418 return chunks_[0].data.as_int();
2419 return 0;
2420 }
2421
2422 std::string RTLIL::SigSpec::as_string() const
2423 {
2424 cover("kernel.rtlil.sigspec.as_string");
2425
2426 pack();
2427 std::string str;
2428 for (size_t i = chunks_.size(); i > 0; i--) {
2429 const RTLIL::SigChunk &chunk = chunks_[i-1];
2430 if (chunk.wire != NULL)
2431 for (int j = 0; j < chunk.width; j++)
2432 str += "?";
2433 else
2434 str += chunk.data.as_string();
2435 }
2436 return str;
2437 }
2438
2439 RTLIL::Const RTLIL::SigSpec::as_const() const
2440 {
2441 cover("kernel.rtlil.sigspec.as_const");
2442
2443 pack();
2444 assert(is_fully_const() && SIZE(chunks_) <= 1);
2445 if (width_)
2446 return chunks_[0].data;
2447 return RTLIL::Const();
2448 }
2449
2450 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2451 {
2452 cover("kernel.rtlil.sigspec.as_wire");
2453
2454 pack();
2455 assert(is_wire());
2456 return chunks_[0].wire;
2457 }
2458
2459 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2460 {
2461 cover("kernel.rtlil.sigspec.as_chunk");
2462
2463 pack();
2464 assert(is_chunk());
2465 return chunks_[0];
2466 }
2467
2468 bool RTLIL::SigSpec::match(std::string pattern) const
2469 {
2470 cover("kernel.rtlil.sigspec.match");
2471
2472 pack();
2473 std::string str = as_string();
2474 assert(pattern.size() == str.size());
2475
2476 for (size_t i = 0; i < pattern.size(); i++) {
2477 if (pattern[i] == ' ')
2478 continue;
2479 if (pattern[i] == '*') {
2480 if (str[i] != 'z' && str[i] != 'x')
2481 return false;
2482 continue;
2483 }
2484 if (pattern[i] != str[i])
2485 return false;
2486 }
2487
2488 return true;
2489 }
2490
2491 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2492 {
2493 cover("kernel.rtlil.sigspec.to_sigbit_set");
2494
2495 pack();
2496 std::set<RTLIL::SigBit> sigbits;
2497 for (auto &c : chunks_)
2498 for (int i = 0; i < c.width; i++)
2499 sigbits.insert(RTLIL::SigBit(c, i));
2500 return sigbits;
2501 }
2502
2503 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2504 {
2505 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2506
2507 unpack();
2508 return bits_;
2509 }
2510
2511 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2512 {
2513 cover("kernel.rtlil.sigspec.to_single_sigbit");
2514
2515 pack();
2516 log_assert(width_ == 1);
2517 for (auto &c : chunks_)
2518 if (c.width)
2519 return RTLIL::SigBit(c);
2520 log_abort();
2521 }
2522
2523 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2524 {
2525 size_t start = 0, end = 0;
2526 while ((end = text.find(sep, start)) != std::string::npos) {
2527 tokens.push_back(text.substr(start, end - start));
2528 start = end + 1;
2529 }
2530 tokens.push_back(text.substr(start));
2531 }
2532
2533 static int sigspec_parse_get_dummy_line_num()
2534 {
2535 return 0;
2536 }
2537
2538 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2539 {
2540 cover("kernel.rtlil.sigspec.parse");
2541
2542 std::vector<std::string> tokens;
2543 sigspec_parse_split(tokens, str, ',');
2544
2545 sig = RTLIL::SigSpec();
2546 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2547 {
2548 std::string netname = tokens[tokidx];
2549 std::string indices;
2550
2551 if (netname.size() == 0)
2552 continue;
2553
2554 if ('0' <= netname[0] && netname[0] <= '9') {
2555 cover("kernel.rtlil.sigspec.parse.const");
2556 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2557 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2558 if (ast == NULL)
2559 return false;
2560 sig.append(RTLIL::Const(ast->bits));
2561 delete ast;
2562 continue;
2563 }
2564
2565 if (module == NULL)
2566 return false;
2567
2568 cover("kernel.rtlil.sigspec.parse.net");
2569
2570 if (netname[0] != '$' && netname[0] != '\\')
2571 netname = "\\" + netname;
2572
2573 if (module->wires_.count(netname) == 0) {
2574 size_t indices_pos = netname.size()-1;
2575 if (indices_pos > 2 && netname[indices_pos] == ']')
2576 {
2577 indices_pos--;
2578 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2579 if (indices_pos > 0 && netname[indices_pos] == ':') {
2580 indices_pos--;
2581 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2582 }
2583 if (indices_pos > 0 && netname[indices_pos] == '[') {
2584 indices = netname.substr(indices_pos);
2585 netname = netname.substr(0, indices_pos);
2586 }
2587 }
2588 }
2589
2590 if (module->wires_.count(netname) == 0)
2591 return false;
2592
2593 RTLIL::Wire *wire = module->wires_.at(netname);
2594 if (!indices.empty()) {
2595 std::vector<std::string> index_tokens;
2596 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2597 if (index_tokens.size() == 1) {
2598 cover("kernel.rtlil.sigspec.parse.bit_sel");
2599 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2600 } else {
2601 cover("kernel.rtlil.sigspec.parse.part_sel");
2602 int a = atoi(index_tokens.at(0).c_str());
2603 int b = atoi(index_tokens.at(1).c_str());
2604 if (a > b) {
2605 int tmp = a;
2606 a = b, b = tmp;
2607 }
2608 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2609 }
2610 } else
2611 sig.append(wire);
2612 }
2613
2614 return true;
2615 }
2616
2617 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2618 {
2619 if (str.empty() || str[0] != '@')
2620 return parse(sig, module, str);
2621
2622 cover("kernel.rtlil.sigspec.parse.sel");
2623
2624 str = RTLIL::escape_id(str.substr(1));
2625 if (design->selection_vars.count(str) == 0)
2626 return false;
2627
2628 sig = RTLIL::SigSpec();
2629 RTLIL::Selection &sel = design->selection_vars.at(str);
2630 for (auto &it : module->wires_)
2631 if (sel.selected_member(module->name, it.first))
2632 sig.append(it.second);
2633
2634 return true;
2635 }
2636
2637 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2638 {
2639 if (str == "0") {
2640 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2641 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2642 return true;
2643 }
2644
2645 if (str == "~0") {
2646 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2647 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2648 return true;
2649 }
2650
2651 if (lhs.chunks_.size() == 1) {
2652 char *p = (char*)str.c_str(), *endptr;
2653 long long int val = strtoll(p, &endptr, 10);
2654 if (endptr && endptr != p && *endptr == 0) {
2655 sig = RTLIL::SigSpec(val, lhs.width_);
2656 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2657 return true;
2658 }
2659 }
2660
2661 return parse(sig, module, str);
2662 }
2663
2664 RTLIL::CaseRule::~CaseRule()
2665 {
2666 for (auto it = switches.begin(); it != switches.end(); it++)
2667 delete *it;
2668 }
2669
2670 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2671 {
2672 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2673 new_caserule->compare = compare;
2674 new_caserule->actions = actions;
2675 for (auto &it : switches)
2676 new_caserule->switches.push_back(it->clone());
2677 return new_caserule;
2678 }
2679
2680 RTLIL::SwitchRule::~SwitchRule()
2681 {
2682 for (auto it = cases.begin(); it != cases.end(); it++)
2683 delete *it;
2684 }
2685
2686 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2687 {
2688 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2689 new_switchrule->signal = signal;
2690 new_switchrule->attributes = attributes;
2691 for (auto &it : cases)
2692 new_switchrule->cases.push_back(it->clone());
2693 return new_switchrule;
2694
2695 }
2696
2697 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2698 {
2699 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2700 new_syncrule->type = type;
2701 new_syncrule->signal = signal;
2702 new_syncrule->actions = actions;
2703 return new_syncrule;
2704 }
2705
2706 RTLIL::Process::~Process()
2707 {
2708 for (auto it = syncs.begin(); it != syncs.end(); it++)
2709 delete *it;
2710 }
2711
2712 RTLIL::Process *RTLIL::Process::clone() const
2713 {
2714 RTLIL::Process *new_proc = new RTLIL::Process;
2715
2716 new_proc->name = name;
2717 new_proc->attributes = attributes;
2718
2719 RTLIL::CaseRule *rc_ptr = root_case.clone();
2720 new_proc->root_case = *rc_ptr;
2721 rc_ptr->switches.clear();
2722 delete rc_ptr;
2723
2724 for (auto &it : syncs)
2725 new_proc->syncs.push_back(it->clone());
2726
2727 return new_proc;
2728 }
2729