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blackbox: Include whiteboxed modules
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/rtlil/rtlil_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($dffsre),
58 ID($adff),
59 ID($adffe),
60 ID($sdff),
61 ID($sdffe),
62 ID($sdffce),
63 ID($dlatch),
64 ID($adlatch),
65 ID($dlatchsr),
66 ID($_DFFE_NN_),
67 ID($_DFFE_NP_),
68 ID($_DFFE_PN_),
69 ID($_DFFE_PP_),
70 ID($_DFFSR_NNN_),
71 ID($_DFFSR_NNP_),
72 ID($_DFFSR_NPN_),
73 ID($_DFFSR_NPP_),
74 ID($_DFFSR_PNN_),
75 ID($_DFFSR_PNP_),
76 ID($_DFFSR_PPN_),
77 ID($_DFFSR_PPP_),
78 ID($_DFFSRE_NNNN_),
79 ID($_DFFSRE_NNNP_),
80 ID($_DFFSRE_NNPN_),
81 ID($_DFFSRE_NNPP_),
82 ID($_DFFSRE_NPNN_),
83 ID($_DFFSRE_NPNP_),
84 ID($_DFFSRE_NPPN_),
85 ID($_DFFSRE_NPPP_),
86 ID($_DFFSRE_PNNN_),
87 ID($_DFFSRE_PNNP_),
88 ID($_DFFSRE_PNPN_),
89 ID($_DFFSRE_PNPP_),
90 ID($_DFFSRE_PPNN_),
91 ID($_DFFSRE_PPNP_),
92 ID($_DFFSRE_PPPN_),
93 ID($_DFFSRE_PPPP_),
94 ID($_DFF_N_),
95 ID($_DFF_P_),
96 ID($_DFF_NN0_),
97 ID($_DFF_NN1_),
98 ID($_DFF_NP0_),
99 ID($_DFF_NP1_),
100 ID($_DFF_PN0_),
101 ID($_DFF_PN1_),
102 ID($_DFF_PP0_),
103 ID($_DFF_PP1_),
104 ID($_DFFE_NN0N_),
105 ID($_DFFE_NN0P_),
106 ID($_DFFE_NN1N_),
107 ID($_DFFE_NN1P_),
108 ID($_DFFE_NP0N_),
109 ID($_DFFE_NP0P_),
110 ID($_DFFE_NP1N_),
111 ID($_DFFE_NP1P_),
112 ID($_DFFE_PN0N_),
113 ID($_DFFE_PN0P_),
114 ID($_DFFE_PN1N_),
115 ID($_DFFE_PN1P_),
116 ID($_DFFE_PP0N_),
117 ID($_DFFE_PP0P_),
118 ID($_DFFE_PP1N_),
119 ID($_DFFE_PP1P_),
120 ID($_SDFF_NN0_),
121 ID($_SDFF_NN1_),
122 ID($_SDFF_NP0_),
123 ID($_SDFF_NP1_),
124 ID($_SDFF_PN0_),
125 ID($_SDFF_PN1_),
126 ID($_SDFF_PP0_),
127 ID($_SDFF_PP1_),
128 ID($_SDFFE_NN0N_),
129 ID($_SDFFE_NN0P_),
130 ID($_SDFFE_NN1N_),
131 ID($_SDFFE_NN1P_),
132 ID($_SDFFE_NP0N_),
133 ID($_SDFFE_NP0P_),
134 ID($_SDFFE_NP1N_),
135 ID($_SDFFE_NP1P_),
136 ID($_SDFFE_PN0N_),
137 ID($_SDFFE_PN0P_),
138 ID($_SDFFE_PN1N_),
139 ID($_SDFFE_PN1P_),
140 ID($_SDFFE_PP0N_),
141 ID($_SDFFE_PP0P_),
142 ID($_SDFFE_PP1N_),
143 ID($_SDFFE_PP1P_),
144 ID($_SDFFCE_NN0N_),
145 ID($_SDFFCE_NN0P_),
146 ID($_SDFFCE_NN1N_),
147 ID($_SDFFCE_NN1P_),
148 ID($_SDFFCE_NP0N_),
149 ID($_SDFFCE_NP0P_),
150 ID($_SDFFCE_NP1N_),
151 ID($_SDFFCE_NP1P_),
152 ID($_SDFFCE_PN0N_),
153 ID($_SDFFCE_PN0P_),
154 ID($_SDFFCE_PN1N_),
155 ID($_SDFFCE_PN1P_),
156 ID($_SDFFCE_PP0N_),
157 ID($_SDFFCE_PP0P_),
158 ID($_SDFFCE_PP1N_),
159 ID($_SDFFCE_PP1P_),
160 ID($_SR_NN_),
161 ID($_SR_NP_),
162 ID($_SR_PN_),
163 ID($_SR_PP_),
164 ID($_DLATCH_N_),
165 ID($_DLATCH_P_),
166 ID($_DLATCH_NN0_),
167 ID($_DLATCH_NN1_),
168 ID($_DLATCH_NP0_),
169 ID($_DLATCH_NP1_),
170 ID($_DLATCH_PN0_),
171 ID($_DLATCH_PN1_),
172 ID($_DLATCH_PP0_),
173 ID($_DLATCH_PP1_),
174 ID($_DLATCHSR_NNN_),
175 ID($_DLATCHSR_NNP_),
176 ID($_DLATCHSR_NPN_),
177 ID($_DLATCHSR_NPP_),
178 ID($_DLATCHSR_PNN_),
179 ID($_DLATCHSR_PNP_),
180 ID($_DLATCHSR_PPN_),
181 ID($_DLATCHSR_PPP_),
182 ID($_FF_),
183 };
184 return res;
185 }
186
187 RTLIL::Const::Const()
188 {
189 flags = RTLIL::CONST_FLAG_NONE;
190 }
191
192 RTLIL::Const::Const(std::string str)
193 {
194 flags = RTLIL::CONST_FLAG_STRING;
195 for (int i = str.size()-1; i >= 0; i--) {
196 unsigned char ch = str[i];
197 for (int j = 0; j < 8; j++) {
198 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
199 ch = ch >> 1;
200 }
201 }
202 }
203
204 RTLIL::Const::Const(int val, int width)
205 {
206 flags = RTLIL::CONST_FLAG_NONE;
207 for (int i = 0; i < width; i++) {
208 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
209 val = val >> 1;
210 }
211 }
212
213 RTLIL::Const::Const(RTLIL::State bit, int width)
214 {
215 flags = RTLIL::CONST_FLAG_NONE;
216 for (int i = 0; i < width; i++)
217 bits.push_back(bit);
218 }
219
220 RTLIL::Const::Const(const std::vector<bool> &bits)
221 {
222 flags = RTLIL::CONST_FLAG_NONE;
223 for (const auto &b : bits)
224 this->bits.emplace_back(b ? State::S1 : State::S0);
225 }
226
227 RTLIL::Const::Const(const RTLIL::Const &c)
228 {
229 flags = c.flags;
230 for (const auto &b : c.bits)
231 this->bits.push_back(b);
232 }
233
234 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
235 {
236 if (bits.size() != other.bits.size())
237 return bits.size() < other.bits.size();
238 for (size_t i = 0; i < bits.size(); i++)
239 if (bits[i] != other.bits[i])
240 return bits[i] < other.bits[i];
241 return false;
242 }
243
244 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
245 {
246 return bits == other.bits;
247 }
248
249 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
250 {
251 return bits != other.bits;
252 }
253
254 bool RTLIL::Const::as_bool() const
255 {
256 for (size_t i = 0; i < bits.size(); i++)
257 if (bits[i] == State::S1)
258 return true;
259 return false;
260 }
261
262 int RTLIL::Const::as_int(bool is_signed) const
263 {
264 int32_t ret = 0;
265 for (size_t i = 0; i < bits.size() && i < 32; i++)
266 if (bits[i] == State::S1)
267 ret |= 1 << i;
268 if (is_signed && bits.back() == State::S1)
269 for (size_t i = bits.size(); i < 32; i++)
270 ret |= 1 << i;
271 return ret;
272 }
273
274 std::string RTLIL::Const::as_string() const
275 {
276 std::string ret;
277 ret.reserve(bits.size());
278 for (size_t i = bits.size(); i > 0; i--)
279 switch (bits[i-1]) {
280 case S0: ret += "0"; break;
281 case S1: ret += "1"; break;
282 case Sx: ret += "x"; break;
283 case Sz: ret += "z"; break;
284 case Sa: ret += "-"; break;
285 case Sm: ret += "m"; break;
286 }
287 return ret;
288 }
289
290 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
291 {
292 Const c;
293 c.bits.reserve(str.size());
294 for (auto it = str.rbegin(); it != str.rend(); it++)
295 switch (*it) {
296 case '0': c.bits.push_back(State::S0); break;
297 case '1': c.bits.push_back(State::S1); break;
298 case 'x': c.bits.push_back(State::Sx); break;
299 case 'z': c.bits.push_back(State::Sz); break;
300 case 'm': c.bits.push_back(State::Sm); break;
301 default: c.bits.push_back(State::Sa);
302 }
303 return c;
304 }
305
306 std::string RTLIL::Const::decode_string() const
307 {
308 std::string string;
309 string.reserve(GetSize(bits)/8);
310 for (int i = 0; i < GetSize(bits); i += 8) {
311 char ch = 0;
312 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
313 if (bits[i + j] == RTLIL::State::S1)
314 ch |= 1 << j;
315 if (ch != 0)
316 string.append({ch});
317 }
318 std::reverse(string.begin(), string.end());
319 return string;
320 }
321
322 bool RTLIL::Const::is_fully_zero() const
323 {
324 cover("kernel.rtlil.const.is_fully_zero");
325
326 for (const auto &bit : bits)
327 if (bit != RTLIL::State::S0)
328 return false;
329
330 return true;
331 }
332
333 bool RTLIL::Const::is_fully_ones() const
334 {
335 cover("kernel.rtlil.const.is_fully_ones");
336
337 for (const auto &bit : bits)
338 if (bit != RTLIL::State::S1)
339 return false;
340
341 return true;
342 }
343
344 bool RTLIL::Const::is_fully_def() const
345 {
346 cover("kernel.rtlil.const.is_fully_def");
347
348 for (const auto &bit : bits)
349 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
350 return false;
351
352 return true;
353 }
354
355 bool RTLIL::Const::is_fully_undef() const
356 {
357 cover("kernel.rtlil.const.is_fully_undef");
358
359 for (const auto &bit : bits)
360 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
361 return false;
362
363 return true;
364 }
365
366 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
367 {
368 return attributes.count(id);
369 }
370
371 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
372 {
373 if (value)
374 attributes[id] = RTLIL::Const(1);
375 else
376 attributes.erase(id);
377 }
378
379 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
380 {
381 const auto it = attributes.find(id);
382 if (it == attributes.end())
383 return false;
384 return it->second.as_bool();
385 }
386
387 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
388 {
389 if (value.empty())
390 attributes.erase(id);
391 else
392 attributes[id] = value;
393 }
394
395 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
396 {
397 std::string value;
398 const auto it = attributes.find(id);
399 if (it != attributes.end())
400 value = it->second.decode_string();
401 return value;
402 }
403
404 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
405 {
406 string attrval;
407 for (const auto &s : data) {
408 if (!attrval.empty())
409 attrval += "|";
410 attrval += s;
411 }
412 set_string_attribute(id, attrval);
413 }
414
415 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
416 {
417 pool<string> union_data = get_strpool_attribute(id);
418 union_data.insert(data.begin(), data.end());
419 if (!union_data.empty())
420 set_strpool_attribute(id, union_data);
421 }
422
423 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
424 {
425 pool<string> data;
426 if (attributes.count(id) != 0)
427 for (auto s : split_tokens(get_string_attribute(id), "|"))
428 data.insert(s);
429 return data;
430 }
431
432 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
433 {
434 string attrval;
435 for (const auto &ident : hierarchy) {
436 if (!attrval.empty())
437 attrval += " ";
438 attrval += ident;
439 }
440 set_string_attribute(ID::hdlname, attrval);
441 }
442
443 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
444 {
445 return split_tokens(get_string_attribute(ID::hdlname), " ");
446 }
447
448 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
449 {
450 if (full_selection)
451 return true;
452 if (selected_modules.count(mod_name) > 0)
453 return true;
454 if (selected_members.count(mod_name) > 0)
455 return true;
456 return false;
457 }
458
459 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
460 {
461 if (full_selection)
462 return true;
463 if (selected_modules.count(mod_name) > 0)
464 return true;
465 return false;
466 }
467
468 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
469 {
470 if (full_selection)
471 return true;
472 if (selected_modules.count(mod_name) > 0)
473 return true;
474 if (selected_members.count(mod_name) > 0)
475 if (selected_members.at(mod_name).count(memb_name) > 0)
476 return true;
477 return false;
478 }
479
480 void RTLIL::Selection::optimize(RTLIL::Design *design)
481 {
482 if (full_selection) {
483 selected_modules.clear();
484 selected_members.clear();
485 return;
486 }
487
488 std::vector<RTLIL::IdString> del_list, add_list;
489
490 del_list.clear();
491 for (auto mod_name : selected_modules) {
492 if (design->modules_.count(mod_name) == 0)
493 del_list.push_back(mod_name);
494 selected_members.erase(mod_name);
495 }
496 for (auto mod_name : del_list)
497 selected_modules.erase(mod_name);
498
499 del_list.clear();
500 for (auto &it : selected_members)
501 if (design->modules_.count(it.first) == 0)
502 del_list.push_back(it.first);
503 for (auto mod_name : del_list)
504 selected_members.erase(mod_name);
505
506 for (auto &it : selected_members) {
507 del_list.clear();
508 for (auto memb_name : it.second)
509 if (design->modules_[it.first]->count_id(memb_name) == 0)
510 del_list.push_back(memb_name);
511 for (auto memb_name : del_list)
512 it.second.erase(memb_name);
513 }
514
515 del_list.clear();
516 add_list.clear();
517 for (auto &it : selected_members)
518 if (it.second.size() == 0)
519 del_list.push_back(it.first);
520 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
521 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
522 add_list.push_back(it.first);
523 for (auto mod_name : del_list)
524 selected_members.erase(mod_name);
525 for (auto mod_name : add_list) {
526 selected_members.erase(mod_name);
527 selected_modules.insert(mod_name);
528 }
529
530 if (selected_modules.size() == design->modules_.size()) {
531 full_selection = true;
532 selected_modules.clear();
533 selected_members.clear();
534 }
535 }
536
537 RTLIL::Design::Design()
538 : verilog_defines (new define_map_t)
539 {
540 static unsigned int hashidx_count = 123456789;
541 hashidx_count = mkhash_xorshift(hashidx_count);
542 hashidx_ = hashidx_count;
543
544 refcount_modules_ = 0;
545 selection_stack.push_back(RTLIL::Selection());
546
547 #ifdef WITH_PYTHON
548 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
549 #endif
550 }
551
552 RTLIL::Design::~Design()
553 {
554 for (auto it = modules_.begin(); it != modules_.end(); ++it)
555 delete it->second;
556 for (auto n : verilog_packages)
557 delete n;
558 for (auto n : verilog_globals)
559 delete n;
560 #ifdef WITH_PYTHON
561 RTLIL::Design::get_all_designs()->erase(hashidx_);
562 #endif
563 }
564
565 #ifdef WITH_PYTHON
566 static std::map<unsigned int, RTLIL::Design*> all_designs;
567 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
568 {
569 return &all_designs;
570 }
571 #endif
572
573 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
574 {
575 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
576 }
577
578 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
579 {
580 return modules_.count(name) ? modules_.at(name) : NULL;
581 }
582
583 RTLIL::Module *RTLIL::Design::top_module()
584 {
585 RTLIL::Module *module = nullptr;
586 int module_count = 0;
587
588 for (auto mod : selected_modules()) {
589 if (mod->get_bool_attribute(ID::top))
590 return mod;
591 module_count++;
592 module = mod;
593 }
594
595 return module_count == 1 ? module : nullptr;
596 }
597
598 void RTLIL::Design::add(RTLIL::Module *module)
599 {
600 log_assert(modules_.count(module->name) == 0);
601 log_assert(refcount_modules_ == 0);
602 modules_[module->name] = module;
603 module->design = this;
604
605 for (auto mon : monitors)
606 mon->notify_module_add(module);
607
608 if (yosys_xtrace) {
609 log("#X# New Module: %s\n", log_id(module));
610 log_backtrace("-X- ", yosys_xtrace-1);
611 }
612 }
613
614 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
615 {
616 if (modules_.count(name) != 0)
617 log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str());
618 log_assert(refcount_modules_ == 0);
619
620 RTLIL::Module *module = new RTLIL::Module;
621 modules_[name] = module;
622 module->design = this;
623 module->name = name;
624
625 for (auto mon : monitors)
626 mon->notify_module_add(module);
627
628 if (yosys_xtrace) {
629 log("#X# New Module: %s\n", log_id(module));
630 log_backtrace("-X- ", yosys_xtrace-1);
631 }
632
633 return module;
634 }
635
636 void RTLIL::Design::scratchpad_unset(const std::string &varname)
637 {
638 scratchpad.erase(varname);
639 }
640
641 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
642 {
643 scratchpad[varname] = stringf("%d", value);
644 }
645
646 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
647 {
648 scratchpad[varname] = value ? "true" : "false";
649 }
650
651 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
652 {
653 scratchpad[varname] = std::move(value);
654 }
655
656 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
657 {
658 auto it = scratchpad.find(varname);
659 if (it == scratchpad.end())
660 return default_value;
661
662 const std::string &str = it->second;
663
664 if (str == "0" || str == "false")
665 return 0;
666
667 if (str == "1" || str == "true")
668 return 1;
669
670 char *endptr = nullptr;
671 long int parsed_value = strtol(str.c_str(), &endptr, 10);
672 return *endptr ? default_value : parsed_value;
673 }
674
675 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
676 {
677 auto it = scratchpad.find(varname);
678 if (it == scratchpad.end())
679 return default_value;
680
681 const std::string &str = it->second;
682
683 if (str == "0" || str == "false")
684 return false;
685
686 if (str == "1" || str == "true")
687 return true;
688
689 return default_value;
690 }
691
692 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
693 {
694 auto it = scratchpad.find(varname);
695 if (it == scratchpad.end())
696 return default_value;
697
698 return it->second;
699 }
700
701 void RTLIL::Design::remove(RTLIL::Module *module)
702 {
703 for (auto mon : monitors)
704 mon->notify_module_del(module);
705
706 if (yosys_xtrace) {
707 log("#X# Remove Module: %s\n", log_id(module));
708 log_backtrace("-X- ", yosys_xtrace-1);
709 }
710
711 log_assert(modules_.at(module->name) == module);
712 log_assert(refcount_modules_ == 0);
713 modules_.erase(module->name);
714 delete module;
715 }
716
717 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
718 {
719 modules_.erase(module->name);
720 module->name = new_name;
721 add(module);
722 }
723
724 void RTLIL::Design::sort()
725 {
726 scratchpad.sort();
727 modules_.sort(sort_by_id_str());
728 for (auto &it : modules_)
729 it.second->sort();
730 }
731
732 void RTLIL::Design::check()
733 {
734 #ifndef NDEBUG
735 for (auto &it : modules_) {
736 log_assert(this == it.second->design);
737 log_assert(it.first == it.second->name);
738 log_assert(!it.first.empty());
739 it.second->check();
740 }
741 #endif
742 }
743
744 void RTLIL::Design::optimize()
745 {
746 for (auto &it : modules_)
747 it.second->optimize();
748 for (auto &it : selection_stack)
749 it.optimize(this);
750 for (auto &it : selection_vars)
751 it.second.optimize(this);
752 }
753
754 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
755 {
756 if (!selected_active_module.empty() && mod_name != selected_active_module)
757 return false;
758 if (selection_stack.size() == 0)
759 return true;
760 return selection_stack.back().selected_module(mod_name);
761 }
762
763 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
764 {
765 if (!selected_active_module.empty() && mod_name != selected_active_module)
766 return false;
767 if (selection_stack.size() == 0)
768 return true;
769 return selection_stack.back().selected_whole_module(mod_name);
770 }
771
772 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
773 {
774 if (!selected_active_module.empty() && mod_name != selected_active_module)
775 return false;
776 if (selection_stack.size() == 0)
777 return true;
778 return selection_stack.back().selected_member(mod_name, memb_name);
779 }
780
781 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
782 {
783 return selected_module(mod->name);
784 }
785
786 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
787 {
788 return selected_whole_module(mod->name);
789 }
790
791 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
792 {
793 std::vector<RTLIL::Module*> result;
794 result.reserve(modules_.size());
795 for (auto &it : modules_)
796 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
797 result.push_back(it.second);
798 return result;
799 }
800
801 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
802 {
803 std::vector<RTLIL::Module*> result;
804 result.reserve(modules_.size());
805 for (auto &it : modules_)
806 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
807 result.push_back(it.second);
808 return result;
809 }
810
811 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
812 {
813 std::vector<RTLIL::Module*> result;
814 result.reserve(modules_.size());
815 for (auto &it : modules_)
816 if (it.second->get_blackbox_attribute(include_wb))
817 continue;
818 else if (selected_whole_module(it.first))
819 result.push_back(it.second);
820 else if (selected_module(it.first))
821 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
822 return result;
823 }
824
825 RTLIL::Module::Module()
826 {
827 static unsigned int hashidx_count = 123456789;
828 hashidx_count = mkhash_xorshift(hashidx_count);
829 hashidx_ = hashidx_count;
830
831 design = nullptr;
832 refcount_wires_ = 0;
833 refcount_cells_ = 0;
834
835 #ifdef WITH_PYTHON
836 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
837 #endif
838 }
839
840 RTLIL::Module::~Module()
841 {
842 for (auto it = wires_.begin(); it != wires_.end(); ++it)
843 delete it->second;
844 for (auto it = memories.begin(); it != memories.end(); ++it)
845 delete it->second;
846 for (auto it = cells_.begin(); it != cells_.end(); ++it)
847 delete it->second;
848 for (auto it = processes.begin(); it != processes.end(); ++it)
849 delete it->second;
850 #ifdef WITH_PYTHON
851 RTLIL::Module::get_all_modules()->erase(hashidx_);
852 #endif
853 }
854
855 #ifdef WITH_PYTHON
856 static std::map<unsigned int, RTLIL::Module*> all_modules;
857 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
858 {
859 return &all_modules;
860 }
861 #endif
862
863 void RTLIL::Module::makeblackbox()
864 {
865 pool<RTLIL::Wire*> delwires;
866
867 for (auto it = wires_.begin(); it != wires_.end(); ++it)
868 if (!it->second->port_input && !it->second->port_output)
869 delwires.insert(it->second);
870
871 for (auto it = memories.begin(); it != memories.end(); ++it)
872 delete it->second;
873 memories.clear();
874
875 for (auto it = cells_.begin(); it != cells_.end(); ++it)
876 delete it->second;
877 cells_.clear();
878
879 for (auto it = processes.begin(); it != processes.end(); ++it)
880 delete it->second;
881 processes.clear();
882
883 connections_.clear();
884
885 remove(delwires);
886 set_bool_attribute(ID::blackbox);
887 }
888
889 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
890 {
891 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
892 }
893
894 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
895 {
896 if (mayfail)
897 return RTLIL::IdString();
898 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
899 }
900
901
902 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
903 {
904 if (mayfail)
905 return RTLIL::IdString();
906 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
907 }
908
909 size_t RTLIL::Module::count_id(RTLIL::IdString id)
910 {
911 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
912 }
913
914 #ifndef NDEBUG
915 namespace {
916 struct InternalCellChecker
917 {
918 RTLIL::Module *module;
919 RTLIL::Cell *cell;
920 pool<RTLIL::IdString> expected_params, expected_ports;
921
922 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
923
924 void error(int linenr)
925 {
926 std::stringstream buf;
927 RTLIL_BACKEND::dump_cell(buf, " ", cell);
928
929 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
930 module ? module->name.c_str() : "", module ? "." : "",
931 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
932 }
933
934 int param(RTLIL::IdString name)
935 {
936 auto it = cell->parameters.find(name);
937 if (it == cell->parameters.end())
938 error(__LINE__);
939 expected_params.insert(name);
940 return it->second.as_int();
941 }
942
943 int param_bool(RTLIL::IdString name)
944 {
945 int v = param(name);
946 if (GetSize(cell->parameters.at(name)) > 32)
947 error(__LINE__);
948 if (v != 0 && v != 1)
949 error(__LINE__);
950 return v;
951 }
952
953 int param_bool(RTLIL::IdString name, bool expected)
954 {
955 int v = param_bool(name);
956 if (v != expected)
957 error(__LINE__);
958 return v;
959 }
960
961 void param_bits(RTLIL::IdString name, int width)
962 {
963 param(name);
964 if (GetSize(cell->parameters.at(name).bits) != width)
965 error(__LINE__);
966 }
967
968 void port(RTLIL::IdString name, int width)
969 {
970 auto it = cell->connections_.find(name);
971 if (it == cell->connections_.end())
972 error(__LINE__);
973 if (GetSize(it->second) != width)
974 error(__LINE__);
975 expected_ports.insert(name);
976 }
977
978 void check_expected(bool check_matched_sign = false)
979 {
980 for (auto &para : cell->parameters)
981 if (expected_params.count(para.first) == 0)
982 error(__LINE__);
983 for (auto &conn : cell->connections())
984 if (expected_ports.count(conn.first) == 0)
985 error(__LINE__);
986
987 if (check_matched_sign) {
988 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
989 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
990 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
991 if (a_is_signed != b_is_signed)
992 error(__LINE__);
993 }
994 }
995
996 void check()
997 {
998 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
999 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
1000 return;
1001
1002 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
1003 param_bool(ID::A_SIGNED);
1004 port(ID::A, param(ID::A_WIDTH));
1005 port(ID::Y, param(ID::Y_WIDTH));
1006 check_expected();
1007 return;
1008 }
1009
1010 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
1011 param_bool(ID::A_SIGNED);
1012 param_bool(ID::B_SIGNED);
1013 port(ID::A, param(ID::A_WIDTH));
1014 port(ID::B, param(ID::B_WIDTH));
1015 port(ID::Y, param(ID::Y_WIDTH));
1016 check_expected(true);
1017 return;
1018 }
1019
1020 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
1021 param_bool(ID::A_SIGNED);
1022 port(ID::A, param(ID::A_WIDTH));
1023 port(ID::Y, param(ID::Y_WIDTH));
1024 check_expected();
1025 return;
1026 }
1027
1028 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
1029 param_bool(ID::A_SIGNED);
1030 param_bool(ID::B_SIGNED, /*expected=*/false);
1031 port(ID::A, param(ID::A_WIDTH));
1032 port(ID::B, param(ID::B_WIDTH));
1033 port(ID::Y, param(ID::Y_WIDTH));
1034 check_expected(/*check_matched_sign=*/false);
1035 return;
1036 }
1037
1038 if (cell->type.in(ID($shift), ID($shiftx))) {
1039 if (cell->type == ID($shiftx)) {
1040 param_bool(ID::A_SIGNED, /*expected=*/false);
1041 } else {
1042 param_bool(ID::A_SIGNED);
1043 }
1044 param_bool(ID::B_SIGNED);
1045 port(ID::A, param(ID::A_WIDTH));
1046 port(ID::B, param(ID::B_WIDTH));
1047 port(ID::Y, param(ID::Y_WIDTH));
1048 check_expected(/*check_matched_sign=*/false);
1049 return;
1050 }
1051
1052 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
1053 param_bool(ID::A_SIGNED);
1054 param_bool(ID::B_SIGNED);
1055 port(ID::A, param(ID::A_WIDTH));
1056 port(ID::B, param(ID::B_WIDTH));
1057 port(ID::Y, param(ID::Y_WIDTH));
1058 check_expected(true);
1059 return;
1060 }
1061
1062 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
1063 param_bool(ID::A_SIGNED);
1064 param_bool(ID::B_SIGNED);
1065 port(ID::A, param(ID::A_WIDTH));
1066 port(ID::B, param(ID::B_WIDTH));
1067 port(ID::Y, param(ID::Y_WIDTH));
1068 check_expected(cell->type != ID($pow));
1069 return;
1070 }
1071
1072 if (cell->type == ID($fa)) {
1073 port(ID::A, param(ID::WIDTH));
1074 port(ID::B, param(ID::WIDTH));
1075 port(ID::C, param(ID::WIDTH));
1076 port(ID::X, param(ID::WIDTH));
1077 port(ID::Y, param(ID::WIDTH));
1078 check_expected();
1079 return;
1080 }
1081
1082 if (cell->type == ID($lcu)) {
1083 port(ID::P, param(ID::WIDTH));
1084 port(ID::G, param(ID::WIDTH));
1085 port(ID::CI, 1);
1086 port(ID::CO, param(ID::WIDTH));
1087 check_expected();
1088 return;
1089 }
1090
1091 if (cell->type == ID($alu)) {
1092 param_bool(ID::A_SIGNED);
1093 param_bool(ID::B_SIGNED);
1094 port(ID::A, param(ID::A_WIDTH));
1095 port(ID::B, param(ID::B_WIDTH));
1096 port(ID::CI, 1);
1097 port(ID::BI, 1);
1098 port(ID::X, param(ID::Y_WIDTH));
1099 port(ID::Y, param(ID::Y_WIDTH));
1100 port(ID::CO, param(ID::Y_WIDTH));
1101 check_expected(true);
1102 return;
1103 }
1104
1105 if (cell->type == ID($macc)) {
1106 param(ID::CONFIG);
1107 param(ID::CONFIG_WIDTH);
1108 port(ID::A, param(ID::A_WIDTH));
1109 port(ID::B, param(ID::B_WIDTH));
1110 port(ID::Y, param(ID::Y_WIDTH));
1111 check_expected();
1112 Macc().from_cell(cell);
1113 return;
1114 }
1115
1116 if (cell->type == ID($logic_not)) {
1117 param_bool(ID::A_SIGNED);
1118 port(ID::A, param(ID::A_WIDTH));
1119 port(ID::Y, param(ID::Y_WIDTH));
1120 check_expected();
1121 return;
1122 }
1123
1124 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1125 param_bool(ID::A_SIGNED);
1126 param_bool(ID::B_SIGNED);
1127 port(ID::A, param(ID::A_WIDTH));
1128 port(ID::B, param(ID::B_WIDTH));
1129 port(ID::Y, param(ID::Y_WIDTH));
1130 check_expected(/*check_matched_sign=*/false);
1131 return;
1132 }
1133
1134 if (cell->type == ID($slice)) {
1135 param(ID::OFFSET);
1136 port(ID::A, param(ID::A_WIDTH));
1137 port(ID::Y, param(ID::Y_WIDTH));
1138 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1139 error(__LINE__);
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == ID($concat)) {
1145 port(ID::A, param(ID::A_WIDTH));
1146 port(ID::B, param(ID::B_WIDTH));
1147 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1148 check_expected();
1149 return;
1150 }
1151
1152 if (cell->type == ID($mux)) {
1153 port(ID::A, param(ID::WIDTH));
1154 port(ID::B, param(ID::WIDTH));
1155 port(ID::S, 1);
1156 port(ID::Y, param(ID::WIDTH));
1157 check_expected();
1158 return;
1159 }
1160
1161 if (cell->type == ID($pmux)) {
1162 port(ID::A, param(ID::WIDTH));
1163 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1164 port(ID::S, param(ID::S_WIDTH));
1165 port(ID::Y, param(ID::WIDTH));
1166 check_expected();
1167 return;
1168 }
1169
1170 if (cell->type == ID($lut)) {
1171 param(ID::LUT);
1172 port(ID::A, param(ID::WIDTH));
1173 port(ID::Y, 1);
1174 check_expected();
1175 return;
1176 }
1177
1178 if (cell->type == ID($sop)) {
1179 param(ID::DEPTH);
1180 param(ID::TABLE);
1181 port(ID::A, param(ID::WIDTH));
1182 port(ID::Y, 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type == ID($sr)) {
1188 param_bool(ID::SET_POLARITY);
1189 param_bool(ID::CLR_POLARITY);
1190 port(ID::SET, param(ID::WIDTH));
1191 port(ID::CLR, param(ID::WIDTH));
1192 port(ID::Q, param(ID::WIDTH));
1193 check_expected();
1194 return;
1195 }
1196
1197 if (cell->type == ID($ff)) {
1198 port(ID::D, param(ID::WIDTH));
1199 port(ID::Q, param(ID::WIDTH));
1200 check_expected();
1201 return;
1202 }
1203
1204 if (cell->type == ID($dff)) {
1205 param_bool(ID::CLK_POLARITY);
1206 port(ID::CLK, 1);
1207 port(ID::D, param(ID::WIDTH));
1208 port(ID::Q, param(ID::WIDTH));
1209 check_expected();
1210 return;
1211 }
1212
1213 if (cell->type == ID($dffe)) {
1214 param_bool(ID::CLK_POLARITY);
1215 param_bool(ID::EN_POLARITY);
1216 port(ID::CLK, 1);
1217 port(ID::EN, 1);
1218 port(ID::D, param(ID::WIDTH));
1219 port(ID::Q, param(ID::WIDTH));
1220 check_expected();
1221 return;
1222 }
1223
1224 if (cell->type == ID($dffsr)) {
1225 param_bool(ID::CLK_POLARITY);
1226 param_bool(ID::SET_POLARITY);
1227 param_bool(ID::CLR_POLARITY);
1228 port(ID::CLK, 1);
1229 port(ID::SET, param(ID::WIDTH));
1230 port(ID::CLR, param(ID::WIDTH));
1231 port(ID::D, param(ID::WIDTH));
1232 port(ID::Q, param(ID::WIDTH));
1233 check_expected();
1234 return;
1235 }
1236
1237 if (cell->type == ID($dffsre)) {
1238 param_bool(ID::CLK_POLARITY);
1239 param_bool(ID::SET_POLARITY);
1240 param_bool(ID::CLR_POLARITY);
1241 param_bool(ID::EN_POLARITY);
1242 port(ID::CLK, 1);
1243 port(ID::EN, 1);
1244 port(ID::SET, param(ID::WIDTH));
1245 port(ID::CLR, param(ID::WIDTH));
1246 port(ID::D, param(ID::WIDTH));
1247 port(ID::Q, param(ID::WIDTH));
1248 check_expected();
1249 return;
1250 }
1251
1252 if (cell->type == ID($adff)) {
1253 param_bool(ID::CLK_POLARITY);
1254 param_bool(ID::ARST_POLARITY);
1255 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1256 port(ID::CLK, 1);
1257 port(ID::ARST, 1);
1258 port(ID::D, param(ID::WIDTH));
1259 port(ID::Q, param(ID::WIDTH));
1260 check_expected();
1261 return;
1262 }
1263
1264 if (cell->type == ID($sdff)) {
1265 param_bool(ID::CLK_POLARITY);
1266 param_bool(ID::SRST_POLARITY);
1267 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1268 port(ID::CLK, 1);
1269 port(ID::SRST, 1);
1270 port(ID::D, param(ID::WIDTH));
1271 port(ID::Q, param(ID::WIDTH));
1272 check_expected();
1273 return;
1274 }
1275
1276 if (cell->type.in(ID($sdffe), ID($sdffce))) {
1277 param_bool(ID::CLK_POLARITY);
1278 param_bool(ID::EN_POLARITY);
1279 param_bool(ID::SRST_POLARITY);
1280 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1281 port(ID::CLK, 1);
1282 port(ID::EN, 1);
1283 port(ID::SRST, 1);
1284 port(ID::D, param(ID::WIDTH));
1285 port(ID::Q, param(ID::WIDTH));
1286 check_expected();
1287 return;
1288 }
1289
1290 if (cell->type == ID($adffe)) {
1291 param_bool(ID::CLK_POLARITY);
1292 param_bool(ID::EN_POLARITY);
1293 param_bool(ID::ARST_POLARITY);
1294 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1295 port(ID::CLK, 1);
1296 port(ID::EN, 1);
1297 port(ID::ARST, 1);
1298 port(ID::D, param(ID::WIDTH));
1299 port(ID::Q, param(ID::WIDTH));
1300 check_expected();
1301 return;
1302 }
1303
1304 if (cell->type == ID($dlatch)) {
1305 param_bool(ID::EN_POLARITY);
1306 port(ID::EN, 1);
1307 port(ID::D, param(ID::WIDTH));
1308 port(ID::Q, param(ID::WIDTH));
1309 check_expected();
1310 return;
1311 }
1312
1313 if (cell->type == ID($adlatch)) {
1314 param_bool(ID::EN_POLARITY);
1315 param_bool(ID::ARST_POLARITY);
1316 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1317 port(ID::EN, 1);
1318 port(ID::ARST, 1);
1319 port(ID::D, param(ID::WIDTH));
1320 port(ID::Q, param(ID::WIDTH));
1321 check_expected();
1322 return;
1323 }
1324
1325 if (cell->type == ID($dlatchsr)) {
1326 param_bool(ID::EN_POLARITY);
1327 param_bool(ID::SET_POLARITY);
1328 param_bool(ID::CLR_POLARITY);
1329 port(ID::EN, 1);
1330 port(ID::SET, param(ID::WIDTH));
1331 port(ID::CLR, param(ID::WIDTH));
1332 port(ID::D, param(ID::WIDTH));
1333 port(ID::Q, param(ID::WIDTH));
1334 check_expected();
1335 return;
1336 }
1337
1338 if (cell->type == ID($fsm)) {
1339 param(ID::NAME);
1340 param_bool(ID::CLK_POLARITY);
1341 param_bool(ID::ARST_POLARITY);
1342 param(ID::STATE_BITS);
1343 param(ID::STATE_NUM);
1344 param(ID::STATE_NUM_LOG2);
1345 param(ID::STATE_RST);
1346 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1347 param(ID::TRANS_NUM);
1348 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1349 port(ID::CLK, 1);
1350 port(ID::ARST, 1);
1351 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1352 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1353 check_expected();
1354 return;
1355 }
1356
1357 if (cell->type == ID($memrd)) {
1358 param(ID::MEMID);
1359 param_bool(ID::CLK_ENABLE);
1360 param_bool(ID::CLK_POLARITY);
1361 param_bool(ID::TRANSPARENT);
1362 port(ID::CLK, 1);
1363 port(ID::EN, 1);
1364 port(ID::ADDR, param(ID::ABITS));
1365 port(ID::DATA, param(ID::WIDTH));
1366 check_expected();
1367 return;
1368 }
1369
1370 if (cell->type == ID($memwr)) {
1371 param(ID::MEMID);
1372 param_bool(ID::CLK_ENABLE);
1373 param_bool(ID::CLK_POLARITY);
1374 param(ID::PRIORITY);
1375 port(ID::CLK, 1);
1376 port(ID::EN, param(ID::WIDTH));
1377 port(ID::ADDR, param(ID::ABITS));
1378 port(ID::DATA, param(ID::WIDTH));
1379 check_expected();
1380 return;
1381 }
1382
1383 if (cell->type == ID($meminit)) {
1384 param(ID::MEMID);
1385 param(ID::PRIORITY);
1386 port(ID::ADDR, param(ID::ABITS));
1387 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1388 check_expected();
1389 return;
1390 }
1391
1392 if (cell->type == ID($mem)) {
1393 param(ID::MEMID);
1394 param(ID::SIZE);
1395 param(ID::OFFSET);
1396 param(ID::INIT);
1397 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1398 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1399 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1400 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1401 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1402 port(ID::RD_CLK, param(ID::RD_PORTS));
1403 port(ID::RD_EN, param(ID::RD_PORTS));
1404 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1405 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1406 port(ID::WR_CLK, param(ID::WR_PORTS));
1407 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1408 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1409 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1410 check_expected();
1411 return;
1412 }
1413
1414 if (cell->type == ID($tribuf)) {
1415 port(ID::A, param(ID::WIDTH));
1416 port(ID::Y, param(ID::WIDTH));
1417 port(ID::EN, 1);
1418 check_expected();
1419 return;
1420 }
1421
1422 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1423 port(ID::A, 1);
1424 port(ID::EN, 1);
1425 check_expected();
1426 return;
1427 }
1428
1429 if (cell->type == ID($initstate)) {
1430 port(ID::Y, 1);
1431 check_expected();
1432 return;
1433 }
1434
1435 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1436 port(ID::Y, param(ID::WIDTH));
1437 check_expected();
1438 return;
1439 }
1440
1441 if (cell->type == ID($equiv)) {
1442 port(ID::A, 1);
1443 port(ID::B, 1);
1444 port(ID::Y, 1);
1445 check_expected();
1446 return;
1447 }
1448
1449 if (cell->type.in(ID($specify2), ID($specify3))) {
1450 param_bool(ID::FULL);
1451 param_bool(ID::SRC_DST_PEN);
1452 param_bool(ID::SRC_DST_POL);
1453 param(ID::T_RISE_MIN);
1454 param(ID::T_RISE_TYP);
1455 param(ID::T_RISE_MAX);
1456 param(ID::T_FALL_MIN);
1457 param(ID::T_FALL_TYP);
1458 param(ID::T_FALL_MAX);
1459 port(ID::EN, 1);
1460 port(ID::SRC, param(ID::SRC_WIDTH));
1461 port(ID::DST, param(ID::DST_WIDTH));
1462 if (cell->type == ID($specify3)) {
1463 param_bool(ID::EDGE_EN);
1464 param_bool(ID::EDGE_POL);
1465 param_bool(ID::DAT_DST_PEN);
1466 param_bool(ID::DAT_DST_POL);
1467 port(ID::DAT, param(ID::DST_WIDTH));
1468 }
1469 check_expected();
1470 return;
1471 }
1472
1473 if (cell->type == ID($specrule)) {
1474 param(ID::TYPE);
1475 param_bool(ID::SRC_PEN);
1476 param_bool(ID::SRC_POL);
1477 param_bool(ID::DST_PEN);
1478 param_bool(ID::DST_POL);
1479 param(ID::T_LIMIT_MIN);
1480 param(ID::T_LIMIT_TYP);
1481 param(ID::T_LIMIT_MAX);
1482 param(ID::T_LIMIT2_MIN);
1483 param(ID::T_LIMIT2_TYP);
1484 param(ID::T_LIMIT2_MAX);
1485 port(ID::SRC_EN, 1);
1486 port(ID::DST_EN, 1);
1487 port(ID::SRC, param(ID::SRC_WIDTH));
1488 port(ID::DST, param(ID::DST_WIDTH));
1489 check_expected();
1490 return;
1491 }
1492
1493 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1494 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1495 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1496 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1497 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1498 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1499 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1500 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1501 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1502 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1503 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1504 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1505 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1506 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1507 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1508 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1509
1510 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1511
1512 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1513 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1514 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1515
1516 if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
1517 { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1518
1519 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1520
1521 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1522 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1523
1524 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1525 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1526
1527 if (cell->type.in(
1528 ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
1529 ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
1530 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1531
1532 if (cell->type.in(
1533 ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
1534 ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
1535 ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
1536 ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
1537 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1538
1539 if (cell->type.in(
1540 ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
1541 ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
1542 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1543
1544 if (cell->type.in(
1545 ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
1546 ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
1547 ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
1548 ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
1549 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
1550
1551 if (cell->type.in(
1552 ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
1553 ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
1554 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1555
1556 if (cell->type.in(
1557 ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
1558 ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
1559 ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
1560 ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
1561 ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
1562 ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
1563 ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
1564 ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
1565 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1566
1567 if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
1568 { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1569
1570 if (cell->type.in(
1571 ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
1572 ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
1573 { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1574
1575 if (cell->type.in(
1576 ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
1577 ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
1578 { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1579
1580 error(__LINE__);
1581 }
1582 };
1583 }
1584 #endif
1585
1586 void RTLIL::Module::sort()
1587 {
1588 wires_.sort(sort_by_id_str());
1589 cells_.sort(sort_by_id_str());
1590 parameter_default_values.sort(sort_by_id_str());
1591 memories.sort(sort_by_id_str());
1592 processes.sort(sort_by_id_str());
1593 for (auto &it : cells_)
1594 it.second->sort();
1595 for (auto &it : wires_)
1596 it.second->attributes.sort(sort_by_id_str());
1597 for (auto &it : memories)
1598 it.second->attributes.sort(sort_by_id_str());
1599 }
1600
1601 void RTLIL::Module::check()
1602 {
1603 #ifndef NDEBUG
1604 std::vector<bool> ports_declared;
1605 for (auto &it : wires_) {
1606 log_assert(this == it.second->module);
1607 log_assert(it.first == it.second->name);
1608 log_assert(!it.first.empty());
1609 log_assert(it.second->width >= 0);
1610 log_assert(it.second->port_id >= 0);
1611 for (auto &it2 : it.second->attributes)
1612 log_assert(!it2.first.empty());
1613 if (it.second->port_id) {
1614 log_assert(GetSize(ports) >= it.second->port_id);
1615 log_assert(ports.at(it.second->port_id-1) == it.first);
1616 log_assert(it.second->port_input || it.second->port_output);
1617 if (GetSize(ports_declared) < it.second->port_id)
1618 ports_declared.resize(it.second->port_id);
1619 log_assert(ports_declared[it.second->port_id-1] == false);
1620 ports_declared[it.second->port_id-1] = true;
1621 } else
1622 log_assert(!it.second->port_input && !it.second->port_output);
1623 }
1624 for (auto port_declared : ports_declared)
1625 log_assert(port_declared == true);
1626 log_assert(GetSize(ports) == GetSize(ports_declared));
1627
1628 for (auto &it : memories) {
1629 log_assert(it.first == it.second->name);
1630 log_assert(!it.first.empty());
1631 log_assert(it.second->width >= 0);
1632 log_assert(it.second->size >= 0);
1633 for (auto &it2 : it.second->attributes)
1634 log_assert(!it2.first.empty());
1635 }
1636
1637 for (auto &it : cells_) {
1638 log_assert(this == it.second->module);
1639 log_assert(it.first == it.second->name);
1640 log_assert(!it.first.empty());
1641 log_assert(!it.second->type.empty());
1642 for (auto &it2 : it.second->connections()) {
1643 log_assert(!it2.first.empty());
1644 it2.second.check();
1645 }
1646 for (auto &it2 : it.second->attributes)
1647 log_assert(!it2.first.empty());
1648 for (auto &it2 : it.second->parameters)
1649 log_assert(!it2.first.empty());
1650 InternalCellChecker checker(this, it.second);
1651 checker.check();
1652 }
1653
1654 for (auto &it : processes) {
1655 log_assert(it.first == it.second->name);
1656 log_assert(!it.first.empty());
1657 log_assert(it.second->root_case.compare.empty());
1658 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1659 for (size_t i = 0; i < all_cases.size(); i++) {
1660 for (auto &switch_it : all_cases[i]->switches) {
1661 for (auto &case_it : switch_it->cases) {
1662 for (auto &compare_it : case_it->compare) {
1663 log_assert(switch_it->signal.size() == compare_it.size());
1664 }
1665 all_cases.push_back(case_it);
1666 }
1667 }
1668 }
1669 for (auto &sync_it : it.second->syncs) {
1670 switch (sync_it->type) {
1671 case SyncType::ST0:
1672 case SyncType::ST1:
1673 case SyncType::STp:
1674 case SyncType::STn:
1675 case SyncType::STe:
1676 log_assert(!sync_it->signal.empty());
1677 break;
1678 case SyncType::STa:
1679 case SyncType::STg:
1680 case SyncType::STi:
1681 log_assert(sync_it->signal.empty());
1682 break;
1683 }
1684 }
1685 }
1686
1687 for (auto &it : connections_) {
1688 log_assert(it.first.size() == it.second.size());
1689 log_assert(!it.first.has_const());
1690 it.first.check();
1691 it.second.check();
1692 }
1693
1694 for (auto &it : attributes)
1695 log_assert(!it.first.empty());
1696 #endif
1697 }
1698
1699 void RTLIL::Module::optimize()
1700 {
1701 }
1702
1703 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1704 {
1705 log_assert(new_mod->refcount_wires_ == 0);
1706 log_assert(new_mod->refcount_cells_ == 0);
1707
1708 new_mod->avail_parameters = avail_parameters;
1709 new_mod->parameter_default_values = parameter_default_values;
1710
1711 for (auto &conn : connections_)
1712 new_mod->connect(conn);
1713
1714 for (auto &attr : attributes)
1715 new_mod->attributes[attr.first] = attr.second;
1716
1717 for (auto &it : wires_)
1718 new_mod->addWire(it.first, it.second);
1719
1720 for (auto &it : memories)
1721 new_mod->addMemory(it.first, it.second);
1722
1723 for (auto &it : cells_)
1724 new_mod->addCell(it.first, it.second);
1725
1726 for (auto &it : processes)
1727 new_mod->addProcess(it.first, it.second);
1728
1729 struct RewriteSigSpecWorker
1730 {
1731 RTLIL::Module *mod;
1732 void operator()(RTLIL::SigSpec &sig)
1733 {
1734 sig.pack();
1735 for (auto &c : sig.chunks_)
1736 if (c.wire != NULL)
1737 c.wire = mod->wires_.at(c.wire->name);
1738 }
1739 };
1740
1741 RewriteSigSpecWorker rewriteSigSpecWorker;
1742 rewriteSigSpecWorker.mod = new_mod;
1743 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1744 new_mod->fixup_ports();
1745 }
1746
1747 RTLIL::Module *RTLIL::Module::clone() const
1748 {
1749 RTLIL::Module *new_mod = new RTLIL::Module;
1750 new_mod->name = name;
1751 cloneInto(new_mod);
1752 return new_mod;
1753 }
1754
1755 bool RTLIL::Module::has_memories() const
1756 {
1757 return !memories.empty();
1758 }
1759
1760 bool RTLIL::Module::has_processes() const
1761 {
1762 return !processes.empty();
1763 }
1764
1765 bool RTLIL::Module::has_memories_warn() const
1766 {
1767 if (!memories.empty())
1768 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1769 return !memories.empty();
1770 }
1771
1772 bool RTLIL::Module::has_processes_warn() const
1773 {
1774 if (!processes.empty())
1775 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1776 return !processes.empty();
1777 }
1778
1779 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1780 {
1781 std::vector<RTLIL::Wire*> result;
1782 result.reserve(wires_.size());
1783 for (auto &it : wires_)
1784 if (design->selected(this, it.second))
1785 result.push_back(it.second);
1786 return result;
1787 }
1788
1789 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1790 {
1791 std::vector<RTLIL::Cell*> result;
1792 result.reserve(cells_.size());
1793 for (auto &it : cells_)
1794 if (design->selected(this, it.second))
1795 result.push_back(it.second);
1796 return result;
1797 }
1798
1799 void RTLIL::Module::add(RTLIL::Wire *wire)
1800 {
1801 log_assert(!wire->name.empty());
1802 log_assert(count_id(wire->name) == 0);
1803 log_assert(refcount_wires_ == 0);
1804 wires_[wire->name] = wire;
1805 wire->module = this;
1806 }
1807
1808 void RTLIL::Module::add(RTLIL::Cell *cell)
1809 {
1810 log_assert(!cell->name.empty());
1811 log_assert(count_id(cell->name) == 0);
1812 log_assert(refcount_cells_ == 0);
1813 cells_[cell->name] = cell;
1814 cell->module = this;
1815 }
1816
1817 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1818 {
1819 log_assert(refcount_wires_ == 0);
1820
1821 struct DeleteWireWorker
1822 {
1823 RTLIL::Module *module;
1824 const pool<RTLIL::Wire*> *wires_p;
1825
1826 void operator()(RTLIL::SigSpec &sig) {
1827 sig.pack();
1828 for (auto &c : sig.chunks_)
1829 if (c.wire != NULL && wires_p->count(c.wire)) {
1830 c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
1831 c.offset = 0;
1832 }
1833 }
1834
1835 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1836 log_assert(GetSize(lhs) == GetSize(rhs));
1837 lhs.unpack();
1838 rhs.unpack();
1839 for (int i = 0; i < GetSize(lhs); i++) {
1840 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1841 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1842 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1843 lhs_bit = State::Sx;
1844 rhs_bit = State::Sx;
1845 }
1846 }
1847 }
1848 };
1849
1850 DeleteWireWorker delete_wire_worker;
1851 delete_wire_worker.module = this;
1852 delete_wire_worker.wires_p = &wires;
1853 rewrite_sigspecs2(delete_wire_worker);
1854
1855 for (auto &it : wires) {
1856 log_assert(wires_.count(it->name) != 0);
1857 wires_.erase(it->name);
1858 delete it;
1859 }
1860 }
1861
1862 void RTLIL::Module::remove(RTLIL::Cell *cell)
1863 {
1864 while (!cell->connections_.empty())
1865 cell->unsetPort(cell->connections_.begin()->first);
1866
1867 log_assert(cells_.count(cell->name) != 0);
1868 log_assert(refcount_cells_ == 0);
1869 cells_.erase(cell->name);
1870 delete cell;
1871 }
1872
1873 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1874 {
1875 log_assert(wires_[wire->name] == wire);
1876 log_assert(refcount_wires_ == 0);
1877 wires_.erase(wire->name);
1878 wire->name = new_name;
1879 add(wire);
1880 }
1881
1882 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1883 {
1884 log_assert(cells_[cell->name] == cell);
1885 log_assert(refcount_wires_ == 0);
1886 cells_.erase(cell->name);
1887 cell->name = new_name;
1888 add(cell);
1889 }
1890
1891 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1892 {
1893 log_assert(count_id(old_name) != 0);
1894 if (wires_.count(old_name))
1895 rename(wires_.at(old_name), new_name);
1896 else if (cells_.count(old_name))
1897 rename(cells_.at(old_name), new_name);
1898 else
1899 log_abort();
1900 }
1901
1902 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1903 {
1904 log_assert(wires_[w1->name] == w1);
1905 log_assert(wires_[w2->name] == w2);
1906 log_assert(refcount_wires_ == 0);
1907
1908 wires_.erase(w1->name);
1909 wires_.erase(w2->name);
1910
1911 std::swap(w1->name, w2->name);
1912
1913 wires_[w1->name] = w1;
1914 wires_[w2->name] = w2;
1915 }
1916
1917 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1918 {
1919 log_assert(cells_[c1->name] == c1);
1920 log_assert(cells_[c2->name] == c2);
1921 log_assert(refcount_cells_ == 0);
1922
1923 cells_.erase(c1->name);
1924 cells_.erase(c2->name);
1925
1926 std::swap(c1->name, c2->name);
1927
1928 cells_[c1->name] = c1;
1929 cells_[c2->name] = c2;
1930 }
1931
1932 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1933 {
1934 int index = 0;
1935 return uniquify(name, index);
1936 }
1937
1938 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1939 {
1940 if (index == 0) {
1941 if (count_id(name) == 0)
1942 return name;
1943 index++;
1944 }
1945
1946 while (1) {
1947 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1948 if (count_id(new_name) == 0)
1949 return new_name;
1950 index++;
1951 }
1952 }
1953
1954 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1955 {
1956 if (a->port_id && !b->port_id)
1957 return true;
1958 if (!a->port_id && b->port_id)
1959 return false;
1960
1961 if (a->port_id == b->port_id)
1962 return a->name < b->name;
1963 return a->port_id < b->port_id;
1964 }
1965
1966 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1967 {
1968 for (auto mon : monitors)
1969 mon->notify_connect(this, conn);
1970
1971 if (design)
1972 for (auto mon : design->monitors)
1973 mon->notify_connect(this, conn);
1974
1975 // ignore all attempts to assign constants to other constants
1976 if (conn.first.has_const()) {
1977 RTLIL::SigSig new_conn;
1978 for (int i = 0; i < GetSize(conn.first); i++)
1979 if (conn.first[i].wire) {
1980 new_conn.first.append(conn.first[i]);
1981 new_conn.second.append(conn.second[i]);
1982 }
1983 if (GetSize(new_conn.first))
1984 connect(new_conn);
1985 return;
1986 }
1987
1988 if (yosys_xtrace) {
1989 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1990 log_backtrace("-X- ", yosys_xtrace-1);
1991 }
1992
1993 log_assert(GetSize(conn.first) == GetSize(conn.second));
1994 connections_.push_back(conn);
1995 }
1996
1997 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1998 {
1999 connect(RTLIL::SigSig(lhs, rhs));
2000 }
2001
2002 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
2003 {
2004 for (auto mon : monitors)
2005 mon->notify_connect(this, new_conn);
2006
2007 if (design)
2008 for (auto mon : design->monitors)
2009 mon->notify_connect(this, new_conn);
2010
2011 if (yosys_xtrace) {
2012 log("#X# New connections vector in %s:\n", log_id(this));
2013 for (auto &conn: new_conn)
2014 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2015 log_backtrace("-X- ", yosys_xtrace-1);
2016 }
2017
2018 connections_ = new_conn;
2019 }
2020
2021 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
2022 {
2023 return connections_;
2024 }
2025
2026 void RTLIL::Module::fixup_ports()
2027 {
2028 std::vector<RTLIL::Wire*> all_ports;
2029
2030 for (auto &w : wires_)
2031 if (w.second->port_input || w.second->port_output)
2032 all_ports.push_back(w.second);
2033 else
2034 w.second->port_id = 0;
2035
2036 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
2037
2038 ports.clear();
2039 for (size_t i = 0; i < all_ports.size(); i++) {
2040 ports.push_back(all_ports[i]->name);
2041 all_ports[i]->port_id = i+1;
2042 }
2043 }
2044
2045 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
2046 {
2047 RTLIL::Wire *wire = new RTLIL::Wire;
2048 wire->name = name;
2049 wire->width = width;
2050 add(wire);
2051 return wire;
2052 }
2053
2054 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
2055 {
2056 RTLIL::Wire *wire = addWire(name);
2057 wire->width = other->width;
2058 wire->start_offset = other->start_offset;
2059 wire->port_id = other->port_id;
2060 wire->port_input = other->port_input;
2061 wire->port_output = other->port_output;
2062 wire->upto = other->upto;
2063 wire->is_signed = other->is_signed;
2064 wire->attributes = other->attributes;
2065 return wire;
2066 }
2067
2068 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
2069 {
2070 RTLIL::Cell *cell = new RTLIL::Cell;
2071 cell->name = name;
2072 cell->type = type;
2073 add(cell);
2074 return cell;
2075 }
2076
2077 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
2078 {
2079 RTLIL::Cell *cell = addCell(name, other->type);
2080 cell->connections_ = other->connections_;
2081 cell->parameters = other->parameters;
2082 cell->attributes = other->attributes;
2083 return cell;
2084 }
2085
2086 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
2087 {
2088 RTLIL::Memory *mem = new RTLIL::Memory;
2089 mem->name = name;
2090 mem->width = other->width;
2091 mem->start_offset = other->start_offset;
2092 mem->size = other->size;
2093 mem->attributes = other->attributes;
2094 memories[mem->name] = mem;
2095 return mem;
2096 }
2097
2098 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
2099 {
2100 RTLIL::Process *proc = other->clone();
2101 proc->name = name;
2102 processes[name] = proc;
2103 return proc;
2104 }
2105
2106 #define DEF_METHOD(_func, _y_size, _type) \
2107 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2108 RTLIL::Cell *cell = addCell(name, _type); \
2109 cell->parameters[ID::A_SIGNED] = is_signed; \
2110 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2111 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2112 cell->setPort(ID::A, sig_a); \
2113 cell->setPort(ID::Y, sig_y); \
2114 cell->set_src_attribute(src); \
2115 return cell; \
2116 } \
2117 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2118 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2119 add ## _func(name, sig_a, sig_y, is_signed, src); \
2120 return sig_y; \
2121 }
2122 DEF_METHOD(Not, sig_a.size(), ID($not))
2123 DEF_METHOD(Pos, sig_a.size(), ID($pos))
2124 DEF_METHOD(Neg, sig_a.size(), ID($neg))
2125 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
2126 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
2127 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
2128 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
2129 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
2130 DEF_METHOD(LogicNot, 1, ID($logic_not))
2131 #undef DEF_METHOD
2132
2133 #define DEF_METHOD(_func, _y_size, _type) \
2134 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2135 RTLIL::Cell *cell = addCell(name, _type); \
2136 cell->parameters[ID::A_SIGNED] = is_signed; \
2137 cell->parameters[ID::B_SIGNED] = is_signed; \
2138 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2139 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2140 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2141 cell->setPort(ID::A, sig_a); \
2142 cell->setPort(ID::B, sig_b); \
2143 cell->setPort(ID::Y, sig_y); \
2144 cell->set_src_attribute(src); \
2145 return cell; \
2146 } \
2147 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2148 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2149 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2150 return sig_y; \
2151 }
2152 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
2153 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
2154 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
2155 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
2156 DEF_METHOD(Shift, sig_a.size(), ID($shift))
2157 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
2158 DEF_METHOD(Lt, 1, ID($lt))
2159 DEF_METHOD(Le, 1, ID($le))
2160 DEF_METHOD(Eq, 1, ID($eq))
2161 DEF_METHOD(Ne, 1, ID($ne))
2162 DEF_METHOD(Eqx, 1, ID($eqx))
2163 DEF_METHOD(Nex, 1, ID($nex))
2164 DEF_METHOD(Ge, 1, ID($ge))
2165 DEF_METHOD(Gt, 1, ID($gt))
2166 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
2167 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
2168 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
2169 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
2170 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
2171 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
2172 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
2173 DEF_METHOD(LogicAnd, 1, ID($logic_and))
2174 DEF_METHOD(LogicOr, 1, ID($logic_or))
2175 #undef DEF_METHOD
2176
2177 #define DEF_METHOD(_func, _y_size, _type) \
2178 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2179 RTLIL::Cell *cell = addCell(name, _type); \
2180 cell->parameters[ID::A_SIGNED] = is_signed; \
2181 cell->parameters[ID::B_SIGNED] = false; \
2182 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2183 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2184 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2185 cell->setPort(ID::A, sig_a); \
2186 cell->setPort(ID::B, sig_b); \
2187 cell->setPort(ID::Y, sig_y); \
2188 cell->set_src_attribute(src); \
2189 return cell; \
2190 } \
2191 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2192 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2193 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2194 return sig_y; \
2195 }
2196 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2197 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2198 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2199 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2200 #undef DEF_METHOD
2201
2202 #define DEF_METHOD(_func, _type, _pmux) \
2203 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2204 RTLIL::Cell *cell = addCell(name, _type); \
2205 cell->parameters[ID::WIDTH] = sig_a.size(); \
2206 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2207 cell->setPort(ID::A, sig_a); \
2208 cell->setPort(ID::B, sig_b); \
2209 cell->setPort(ID::S, sig_s); \
2210 cell->setPort(ID::Y, sig_y); \
2211 cell->set_src_attribute(src); \
2212 return cell; \
2213 } \
2214 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2215 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2216 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2217 return sig_y; \
2218 }
2219 DEF_METHOD(Mux, ID($mux), 0)
2220 DEF_METHOD(Pmux, ID($pmux), 1)
2221 #undef DEF_METHOD
2222
2223 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2224 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2225 RTLIL::Cell *cell = addCell(name, _type); \
2226 cell->setPort("\\" #_P1, sig1); \
2227 cell->setPort("\\" #_P2, sig2); \
2228 cell->set_src_attribute(src); \
2229 return cell; \
2230 } \
2231 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2232 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2233 add ## _func(name, sig1, sig2, src); \
2234 return sig2; \
2235 }
2236 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2237 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2238 RTLIL::Cell *cell = addCell(name, _type); \
2239 cell->setPort("\\" #_P1, sig1); \
2240 cell->setPort("\\" #_P2, sig2); \
2241 cell->setPort("\\" #_P3, sig3); \
2242 cell->set_src_attribute(src); \
2243 return cell; \
2244 } \
2245 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2246 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2247 add ## _func(name, sig1, sig2, sig3, src); \
2248 return sig3; \
2249 }
2250 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2251 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2252 RTLIL::Cell *cell = addCell(name, _type); \
2253 cell->setPort("\\" #_P1, sig1); \
2254 cell->setPort("\\" #_P2, sig2); \
2255 cell->setPort("\\" #_P3, sig3); \
2256 cell->setPort("\\" #_P4, sig4); \
2257 cell->set_src_attribute(src); \
2258 return cell; \
2259 } \
2260 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2261 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2262 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2263 return sig4; \
2264 }
2265 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2266 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2267 RTLIL::Cell *cell = addCell(name, _type); \
2268 cell->setPort("\\" #_P1, sig1); \
2269 cell->setPort("\\" #_P2, sig2); \
2270 cell->setPort("\\" #_P3, sig3); \
2271 cell->setPort("\\" #_P4, sig4); \
2272 cell->setPort("\\" #_P5, sig5); \
2273 cell->set_src_attribute(src); \
2274 return cell; \
2275 } \
2276 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2277 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2278 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2279 return sig5; \
2280 }
2281 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2282 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2283 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2284 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2285 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2286 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2287 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2288 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2289 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2290 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2291 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2292 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2293 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2294 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2295 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2296 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2297 #undef DEF_METHOD_2
2298 #undef DEF_METHOD_3
2299 #undef DEF_METHOD_4
2300 #undef DEF_METHOD_5
2301
2302 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2303 {
2304 RTLIL::Cell *cell = addCell(name, ID($pow));
2305 cell->parameters[ID::A_SIGNED] = a_signed;
2306 cell->parameters[ID::B_SIGNED] = b_signed;
2307 cell->parameters[ID::A_WIDTH] = sig_a.size();
2308 cell->parameters[ID::B_WIDTH] = sig_b.size();
2309 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2310 cell->setPort(ID::A, sig_a);
2311 cell->setPort(ID::B, sig_b);
2312 cell->setPort(ID::Y, sig_y);
2313 cell->set_src_attribute(src);
2314 return cell;
2315 }
2316
2317 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2318 {
2319 RTLIL::Cell *cell = addCell(name, ID($slice));
2320 cell->parameters[ID::A_WIDTH] = sig_a.size();
2321 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2322 cell->parameters[ID::OFFSET] = offset;
2323 cell->setPort(ID::A, sig_a);
2324 cell->setPort(ID::Y, sig_y);
2325 cell->set_src_attribute(src);
2326 return cell;
2327 }
2328
2329 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2330 {
2331 RTLIL::Cell *cell = addCell(name, ID($concat));
2332 cell->parameters[ID::A_WIDTH] = sig_a.size();
2333 cell->parameters[ID::B_WIDTH] = sig_b.size();
2334 cell->setPort(ID::A, sig_a);
2335 cell->setPort(ID::B, sig_b);
2336 cell->setPort(ID::Y, sig_y);
2337 cell->set_src_attribute(src);
2338 return cell;
2339 }
2340
2341 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2342 {
2343 RTLIL::Cell *cell = addCell(name, ID($lut));
2344 cell->parameters[ID::LUT] = lut;
2345 cell->parameters[ID::WIDTH] = sig_a.size();
2346 cell->setPort(ID::A, sig_a);
2347 cell->setPort(ID::Y, sig_y);
2348 cell->set_src_attribute(src);
2349 return cell;
2350 }
2351
2352 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2353 {
2354 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2355 cell->parameters[ID::WIDTH] = sig_a.size();
2356 cell->setPort(ID::A, sig_a);
2357 cell->setPort(ID::EN, sig_en);
2358 cell->setPort(ID::Y, sig_y);
2359 cell->set_src_attribute(src);
2360 return cell;
2361 }
2362
2363 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2364 {
2365 RTLIL::Cell *cell = addCell(name, ID($assert));
2366 cell->setPort(ID::A, sig_a);
2367 cell->setPort(ID::EN, sig_en);
2368 cell->set_src_attribute(src);
2369 return cell;
2370 }
2371
2372 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2373 {
2374 RTLIL::Cell *cell = addCell(name, ID($assume));
2375 cell->setPort(ID::A, sig_a);
2376 cell->setPort(ID::EN, sig_en);
2377 cell->set_src_attribute(src);
2378 return cell;
2379 }
2380
2381 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2382 {
2383 RTLIL::Cell *cell = addCell(name, ID($live));
2384 cell->setPort(ID::A, sig_a);
2385 cell->setPort(ID::EN, sig_en);
2386 cell->set_src_attribute(src);
2387 return cell;
2388 }
2389
2390 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2391 {
2392 RTLIL::Cell *cell = addCell(name, ID($fair));
2393 cell->setPort(ID::A, sig_a);
2394 cell->setPort(ID::EN, sig_en);
2395 cell->set_src_attribute(src);
2396 return cell;
2397 }
2398
2399 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2400 {
2401 RTLIL::Cell *cell = addCell(name, ID($cover));
2402 cell->setPort(ID::A, sig_a);
2403 cell->setPort(ID::EN, sig_en);
2404 cell->set_src_attribute(src);
2405 return cell;
2406 }
2407
2408 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2409 {
2410 RTLIL::Cell *cell = addCell(name, ID($equiv));
2411 cell->setPort(ID::A, sig_a);
2412 cell->setPort(ID::B, sig_b);
2413 cell->setPort(ID::Y, sig_y);
2414 cell->set_src_attribute(src);
2415 return cell;
2416 }
2417
2418 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2419 {
2420 RTLIL::Cell *cell = addCell(name, ID($sr));
2421 cell->parameters[ID::SET_POLARITY] = set_polarity;
2422 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2423 cell->parameters[ID::WIDTH] = sig_q.size();
2424 cell->setPort(ID::SET, sig_set);
2425 cell->setPort(ID::CLR, sig_clr);
2426 cell->setPort(ID::Q, sig_q);
2427 cell->set_src_attribute(src);
2428 return cell;
2429 }
2430
2431 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2432 {
2433 RTLIL::Cell *cell = addCell(name, ID($ff));
2434 cell->parameters[ID::WIDTH] = sig_q.size();
2435 cell->setPort(ID::D, sig_d);
2436 cell->setPort(ID::Q, sig_q);
2437 cell->set_src_attribute(src);
2438 return cell;
2439 }
2440
2441 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2442 {
2443 RTLIL::Cell *cell = addCell(name, ID($dff));
2444 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2445 cell->parameters[ID::WIDTH] = sig_q.size();
2446 cell->setPort(ID::CLK, sig_clk);
2447 cell->setPort(ID::D, sig_d);
2448 cell->setPort(ID::Q, sig_q);
2449 cell->set_src_attribute(src);
2450 return cell;
2451 }
2452
2453 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2454 {
2455 RTLIL::Cell *cell = addCell(name, ID($dffe));
2456 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2457 cell->parameters[ID::EN_POLARITY] = en_polarity;
2458 cell->parameters[ID::WIDTH] = sig_q.size();
2459 cell->setPort(ID::CLK, sig_clk);
2460 cell->setPort(ID::EN, sig_en);
2461 cell->setPort(ID::D, sig_d);
2462 cell->setPort(ID::Q, sig_q);
2463 cell->set_src_attribute(src);
2464 return cell;
2465 }
2466
2467 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2468 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2469 {
2470 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2471 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2472 cell->parameters[ID::SET_POLARITY] = set_polarity;
2473 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2474 cell->parameters[ID::WIDTH] = sig_q.size();
2475 cell->setPort(ID::CLK, sig_clk);
2476 cell->setPort(ID::SET, sig_set);
2477 cell->setPort(ID::CLR, sig_clr);
2478 cell->setPort(ID::D, sig_d);
2479 cell->setPort(ID::Q, sig_q);
2480 cell->set_src_attribute(src);
2481 return cell;
2482 }
2483
2484 RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2485 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2486 {
2487 RTLIL::Cell *cell = addCell(name, ID($dffsre));
2488 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2489 cell->parameters[ID::EN_POLARITY] = en_polarity;
2490 cell->parameters[ID::SET_POLARITY] = set_polarity;
2491 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2492 cell->parameters[ID::WIDTH] = sig_q.size();
2493 cell->setPort(ID::CLK, sig_clk);
2494 cell->setPort(ID::EN, sig_en);
2495 cell->setPort(ID::SET, sig_set);
2496 cell->setPort(ID::CLR, sig_clr);
2497 cell->setPort(ID::D, sig_d);
2498 cell->setPort(ID::Q, sig_q);
2499 cell->set_src_attribute(src);
2500 return cell;
2501 }
2502
2503 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2504 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2505 {
2506 RTLIL::Cell *cell = addCell(name, ID($adff));
2507 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2508 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2509 cell->parameters[ID::ARST_VALUE] = arst_value;
2510 cell->parameters[ID::WIDTH] = sig_q.size();
2511 cell->setPort(ID::CLK, sig_clk);
2512 cell->setPort(ID::ARST, sig_arst);
2513 cell->setPort(ID::D, sig_d);
2514 cell->setPort(ID::Q, sig_q);
2515 cell->set_src_attribute(src);
2516 return cell;
2517 }
2518
2519 RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2520 RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2521 {
2522 RTLIL::Cell *cell = addCell(name, ID($adffe));
2523 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2524 cell->parameters[ID::EN_POLARITY] = en_polarity;
2525 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2526 cell->parameters[ID::ARST_VALUE] = arst_value;
2527 cell->parameters[ID::WIDTH] = sig_q.size();
2528 cell->setPort(ID::CLK, sig_clk);
2529 cell->setPort(ID::EN, sig_en);
2530 cell->setPort(ID::ARST, sig_arst);
2531 cell->setPort(ID::D, sig_d);
2532 cell->setPort(ID::Q, sig_q);
2533 cell->set_src_attribute(src);
2534 return cell;
2535 }
2536
2537 RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2538 RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2539 {
2540 RTLIL::Cell *cell = addCell(name, ID($sdff));
2541 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2542 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2543 cell->parameters[ID::SRST_VALUE] = srst_value;
2544 cell->parameters[ID::WIDTH] = sig_q.size();
2545 cell->setPort(ID::CLK, sig_clk);
2546 cell->setPort(ID::SRST, sig_srst);
2547 cell->setPort(ID::D, sig_d);
2548 cell->setPort(ID::Q, sig_q);
2549 cell->set_src_attribute(src);
2550 return cell;
2551 }
2552
2553 RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2554 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2555 {
2556 RTLIL::Cell *cell = addCell(name, ID($sdffe));
2557 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2558 cell->parameters[ID::EN_POLARITY] = en_polarity;
2559 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2560 cell->parameters[ID::SRST_VALUE] = srst_value;
2561 cell->parameters[ID::WIDTH] = sig_q.size();
2562 cell->setPort(ID::CLK, sig_clk);
2563 cell->setPort(ID::EN, sig_en);
2564 cell->setPort(ID::SRST, sig_srst);
2565 cell->setPort(ID::D, sig_d);
2566 cell->setPort(ID::Q, sig_q);
2567 cell->set_src_attribute(src);
2568 return cell;
2569 }
2570
2571 RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2572 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2573 {
2574 RTLIL::Cell *cell = addCell(name, ID($sdffce));
2575 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2576 cell->parameters[ID::EN_POLARITY] = en_polarity;
2577 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2578 cell->parameters[ID::SRST_VALUE] = srst_value;
2579 cell->parameters[ID::WIDTH] = sig_q.size();
2580 cell->setPort(ID::CLK, sig_clk);
2581 cell->setPort(ID::EN, sig_en);
2582 cell->setPort(ID::SRST, sig_srst);
2583 cell->setPort(ID::D, sig_d);
2584 cell->setPort(ID::Q, sig_q);
2585 cell->set_src_attribute(src);
2586 return cell;
2587 }
2588
2589 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2590 {
2591 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2592 cell->parameters[ID::EN_POLARITY] = en_polarity;
2593 cell->parameters[ID::WIDTH] = sig_q.size();
2594 cell->setPort(ID::EN, sig_en);
2595 cell->setPort(ID::D, sig_d);
2596 cell->setPort(ID::Q, sig_q);
2597 cell->set_src_attribute(src);
2598 return cell;
2599 }
2600
2601 RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2602 RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2603 {
2604 RTLIL::Cell *cell = addCell(name, ID($adlatch));
2605 cell->parameters[ID::EN_POLARITY] = en_polarity;
2606 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2607 cell->parameters[ID::ARST_VALUE] = arst_value;
2608 cell->parameters[ID::WIDTH] = sig_q.size();
2609 cell->setPort(ID::EN, sig_en);
2610 cell->setPort(ID::ARST, sig_arst);
2611 cell->setPort(ID::D, sig_d);
2612 cell->setPort(ID::Q, sig_q);
2613 cell->set_src_attribute(src);
2614 return cell;
2615 }
2616
2617 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2618 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2619 {
2620 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2621 cell->parameters[ID::EN_POLARITY] = en_polarity;
2622 cell->parameters[ID::SET_POLARITY] = set_polarity;
2623 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2624 cell->parameters[ID::WIDTH] = sig_q.size();
2625 cell->setPort(ID::EN, sig_en);
2626 cell->setPort(ID::SET, sig_set);
2627 cell->setPort(ID::CLR, sig_clr);
2628 cell->setPort(ID::D, sig_d);
2629 cell->setPort(ID::Q, sig_q);
2630 cell->set_src_attribute(src);
2631 return cell;
2632 }
2633
2634 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2635 const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2636 {
2637 RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2638 cell->setPort(ID::S, sig_set);
2639 cell->setPort(ID::R, sig_clr);
2640 cell->setPort(ID::Q, sig_q);
2641 cell->set_src_attribute(src);
2642 return cell;
2643 }
2644
2645 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2646 {
2647 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2648 cell->setPort(ID::D, sig_d);
2649 cell->setPort(ID::Q, sig_q);
2650 cell->set_src_attribute(src);
2651 return cell;
2652 }
2653
2654 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2655 {
2656 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2657 cell->setPort(ID::C, sig_clk);
2658 cell->setPort(ID::D, sig_d);
2659 cell->setPort(ID::Q, sig_q);
2660 cell->set_src_attribute(src);
2661 return cell;
2662 }
2663
2664 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2665 {
2666 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2667 cell->setPort(ID::C, sig_clk);
2668 cell->setPort(ID::E, sig_en);
2669 cell->setPort(ID::D, sig_d);
2670 cell->setPort(ID::Q, sig_q);
2671 cell->set_src_attribute(src);
2672 return cell;
2673 }
2674
2675 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2676 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2677 {
2678 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2679 cell->setPort(ID::C, sig_clk);
2680 cell->setPort(ID::S, sig_set);
2681 cell->setPort(ID::R, sig_clr);
2682 cell->setPort(ID::D, sig_d);
2683 cell->setPort(ID::Q, sig_q);
2684 cell->set_src_attribute(src);
2685 return cell;
2686 }
2687
2688 RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2689 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2690 {
2691 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2692 cell->setPort(ID::C, sig_clk);
2693 cell->setPort(ID::S, sig_set);
2694 cell->setPort(ID::R, sig_clr);
2695 cell->setPort(ID::E, sig_en);
2696 cell->setPort(ID::D, sig_d);
2697 cell->setPort(ID::Q, sig_q);
2698 cell->set_src_attribute(src);
2699 return cell;
2700 }
2701
2702 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2703 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2704 {
2705 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2706 cell->setPort(ID::C, sig_clk);
2707 cell->setPort(ID::R, sig_arst);
2708 cell->setPort(ID::D, sig_d);
2709 cell->setPort(ID::Q, sig_q);
2710 cell->set_src_attribute(src);
2711 return cell;
2712 }
2713
2714 RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2715 bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2716 {
2717 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2718 cell->setPort(ID::C, sig_clk);
2719 cell->setPort(ID::R, sig_arst);
2720 cell->setPort(ID::E, sig_en);
2721 cell->setPort(ID::D, sig_d);
2722 cell->setPort(ID::Q, sig_q);
2723 cell->set_src_attribute(src);
2724 return cell;
2725 }
2726
2727 RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2728 bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2729 {
2730 RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
2731 cell->setPort(ID::C, sig_clk);
2732 cell->setPort(ID::R, sig_srst);
2733 cell->setPort(ID::D, sig_d);
2734 cell->setPort(ID::Q, sig_q);
2735 cell->set_src_attribute(src);
2736 return cell;
2737 }
2738
2739 RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2740 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2741 {
2742 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2743 cell->setPort(ID::C, sig_clk);
2744 cell->setPort(ID::R, sig_srst);
2745 cell->setPort(ID::E, sig_en);
2746 cell->setPort(ID::D, sig_d);
2747 cell->setPort(ID::Q, sig_q);
2748 cell->set_src_attribute(src);
2749 return cell;
2750 }
2751
2752 RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2753 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2754 {
2755 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2756 cell->setPort(ID::C, sig_clk);
2757 cell->setPort(ID::R, sig_srst);
2758 cell->setPort(ID::E, sig_en);
2759 cell->setPort(ID::D, sig_d);
2760 cell->setPort(ID::Q, sig_q);
2761 cell->set_src_attribute(src);
2762 return cell;
2763 }
2764
2765 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2766 {
2767 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2768 cell->setPort(ID::E, sig_en);
2769 cell->setPort(ID::D, sig_d);
2770 cell->setPort(ID::Q, sig_q);
2771 cell->set_src_attribute(src);
2772 return cell;
2773 }
2774
2775 RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2776 bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2777 {
2778 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2779 cell->setPort(ID::E, sig_en);
2780 cell->setPort(ID::R, sig_arst);
2781 cell->setPort(ID::D, sig_d);
2782 cell->setPort(ID::Q, sig_q);
2783 cell->set_src_attribute(src);
2784 return cell;
2785 }
2786
2787 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2788 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2789 {
2790 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2791 cell->setPort(ID::E, sig_en);
2792 cell->setPort(ID::S, sig_set);
2793 cell->setPort(ID::R, sig_clr);
2794 cell->setPort(ID::D, sig_d);
2795 cell->setPort(ID::Q, sig_q);
2796 cell->set_src_attribute(src);
2797 return cell;
2798 }
2799
2800 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2801 {
2802 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2803 Cell *cell = addCell(name, ID($anyconst));
2804 cell->setParam(ID::WIDTH, width);
2805 cell->setPort(ID::Y, sig);
2806 cell->set_src_attribute(src);
2807 return sig;
2808 }
2809
2810 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2811 {
2812 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2813 Cell *cell = addCell(name, ID($anyseq));
2814 cell->setParam(ID::WIDTH, width);
2815 cell->setPort(ID::Y, sig);
2816 cell->set_src_attribute(src);
2817 return sig;
2818 }
2819
2820 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2821 {
2822 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2823 Cell *cell = addCell(name, ID($allconst));
2824 cell->setParam(ID::WIDTH, width);
2825 cell->setPort(ID::Y, sig);
2826 cell->set_src_attribute(src);
2827 return sig;
2828 }
2829
2830 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2831 {
2832 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2833 Cell *cell = addCell(name, ID($allseq));
2834 cell->setParam(ID::WIDTH, width);
2835 cell->setPort(ID::Y, sig);
2836 cell->set_src_attribute(src);
2837 return sig;
2838 }
2839
2840 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2841 {
2842 RTLIL::SigSpec sig = addWire(NEW_ID);
2843 Cell *cell = addCell(name, ID($initstate));
2844 cell->setPort(ID::Y, sig);
2845 cell->set_src_attribute(src);
2846 return sig;
2847 }
2848
2849 RTLIL::Wire::Wire()
2850 {
2851 static unsigned int hashidx_count = 123456789;
2852 hashidx_count = mkhash_xorshift(hashidx_count);
2853 hashidx_ = hashidx_count;
2854
2855 module = nullptr;
2856 width = 1;
2857 start_offset = 0;
2858 port_id = 0;
2859 port_input = false;
2860 port_output = false;
2861 upto = false;
2862 is_signed = false;
2863
2864 #ifdef WITH_PYTHON
2865 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2866 #endif
2867 }
2868
2869 RTLIL::Wire::~Wire()
2870 {
2871 #ifdef WITH_PYTHON
2872 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2873 #endif
2874 }
2875
2876 #ifdef WITH_PYTHON
2877 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2878 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2879 {
2880 return &all_wires;
2881 }
2882 #endif
2883
2884 RTLIL::Memory::Memory()
2885 {
2886 static unsigned int hashidx_count = 123456789;
2887 hashidx_count = mkhash_xorshift(hashidx_count);
2888 hashidx_ = hashidx_count;
2889
2890 width = 1;
2891 start_offset = 0;
2892 size = 0;
2893 #ifdef WITH_PYTHON
2894 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2895 #endif
2896 }
2897
2898 RTLIL::Cell::Cell() : module(nullptr)
2899 {
2900 static unsigned int hashidx_count = 123456789;
2901 hashidx_count = mkhash_xorshift(hashidx_count);
2902 hashidx_ = hashidx_count;
2903
2904 // log("#memtrace# %p\n", this);
2905 memhasher();
2906
2907 #ifdef WITH_PYTHON
2908 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2909 #endif
2910 }
2911
2912 RTLIL::Cell::~Cell()
2913 {
2914 #ifdef WITH_PYTHON
2915 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2916 #endif
2917 }
2918
2919 #ifdef WITH_PYTHON
2920 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2921 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2922 {
2923 return &all_cells;
2924 }
2925 #endif
2926
2927 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2928 {
2929 return connections_.count(portname) != 0;
2930 }
2931
2932 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2933 {
2934 RTLIL::SigSpec signal;
2935 auto conn_it = connections_.find(portname);
2936
2937 if (conn_it != connections_.end())
2938 {
2939 for (auto mon : module->monitors)
2940 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2941
2942 if (module->design)
2943 for (auto mon : module->design->monitors)
2944 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2945
2946 if (yosys_xtrace) {
2947 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2948 log_backtrace("-X- ", yosys_xtrace-1);
2949 }
2950
2951 connections_.erase(conn_it);
2952 }
2953 }
2954
2955 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2956 {
2957 auto r = connections_.insert(portname);
2958 auto conn_it = r.first;
2959 if (!r.second && conn_it->second == signal)
2960 return;
2961
2962 for (auto mon : module->monitors)
2963 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2964
2965 if (module->design)
2966 for (auto mon : module->design->monitors)
2967 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2968
2969 if (yosys_xtrace) {
2970 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2971 log_backtrace("-X- ", yosys_xtrace-1);
2972 }
2973
2974 conn_it->second = std::move(signal);
2975 }
2976
2977 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2978 {
2979 return connections_.at(portname);
2980 }
2981
2982 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2983 {
2984 return connections_;
2985 }
2986
2987 bool RTLIL::Cell::known() const
2988 {
2989 if (yosys_celltypes.cell_known(type))
2990 return true;
2991 if (module && module->design && module->design->module(type))
2992 return true;
2993 return false;
2994 }
2995
2996 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2997 {
2998 if (yosys_celltypes.cell_known(type))
2999 return yosys_celltypes.cell_input(type, portname);
3000 if (module && module->design) {
3001 RTLIL::Module *m = module->design->module(type);
3002 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3003 return w && w->port_input;
3004 }
3005 return false;
3006 }
3007
3008 bool RTLIL::Cell::output(RTLIL::IdString portname) const
3009 {
3010 if (yosys_celltypes.cell_known(type))
3011 return yosys_celltypes.cell_output(type, portname);
3012 if (module && module->design) {
3013 RTLIL::Module *m = module->design->module(type);
3014 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3015 return w && w->port_output;
3016 }
3017 return false;
3018 }
3019
3020 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
3021 {
3022 return parameters.count(paramname) != 0;
3023 }
3024
3025 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
3026 {
3027 parameters.erase(paramname);
3028 }
3029
3030 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
3031 {
3032 parameters[paramname] = std::move(value);
3033 }
3034
3035 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
3036 {
3037 const auto &it = parameters.find(paramname);
3038 if (it != parameters.end())
3039 return it->second;
3040 if (module && module->design) {
3041 RTLIL::Module *m = module->design->module(type);
3042 if (m)
3043 return m->parameter_default_values.at(paramname);
3044 }
3045 throw std::out_of_range("Cell::getParam()");
3046 }
3047
3048 void RTLIL::Cell::sort()
3049 {
3050 connections_.sort(sort_by_id_str());
3051 parameters.sort(sort_by_id_str());
3052 attributes.sort(sort_by_id_str());
3053 }
3054
3055 void RTLIL::Cell::check()
3056 {
3057 #ifndef NDEBUG
3058 InternalCellChecker checker(NULL, this);
3059 checker.check();
3060 #endif
3061 }
3062
3063 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
3064 {
3065 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
3066 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
3067 return;
3068
3069 if (type == ID($mux) || type == ID($pmux)) {
3070 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3071 if (type == ID($pmux))
3072 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3073 check();
3074 return;
3075 }
3076
3077 if (type == ID($lut) || type == ID($sop)) {
3078 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3079 return;
3080 }
3081
3082 if (type == ID($fa)) {
3083 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3084 return;
3085 }
3086
3087 if (type == ID($lcu)) {
3088 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
3089 return;
3090 }
3091
3092 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
3093
3094 if (connections_.count(ID::A)) {
3095 if (signedness_ab) {
3096 if (set_a_signed)
3097 parameters[ID::A_SIGNED] = true;
3098 else if (parameters.count(ID::A_SIGNED) == 0)
3099 parameters[ID::A_SIGNED] = false;
3100 }
3101 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
3102 }
3103
3104 if (connections_.count(ID::B)) {
3105 if (signedness_ab) {
3106 if (set_b_signed)
3107 parameters[ID::B_SIGNED] = true;
3108 else if (parameters.count(ID::B_SIGNED) == 0)
3109 parameters[ID::B_SIGNED] = false;
3110 }
3111 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
3112 }
3113
3114 if (connections_.count(ID::Y))
3115 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
3116
3117 if (connections_.count(ID::Q))
3118 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
3119
3120 check();
3121 }
3122
3123 RTLIL::SigChunk::SigChunk()
3124 {
3125 wire = NULL;
3126 width = 0;
3127 offset = 0;
3128 }
3129
3130 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
3131 {
3132 wire = NULL;
3133 data = value.bits;
3134 width = GetSize(data);
3135 offset = 0;
3136 }
3137
3138 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
3139 {
3140 log_assert(wire != nullptr);
3141 this->wire = wire;
3142 this->width = wire->width;
3143 this->offset = 0;
3144 }
3145
3146 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
3147 {
3148 log_assert(wire != nullptr);
3149 this->wire = wire;
3150 this->width = width;
3151 this->offset = offset;
3152 }
3153
3154 RTLIL::SigChunk::SigChunk(const std::string &str)
3155 {
3156 wire = NULL;
3157 data = RTLIL::Const(str).bits;
3158 width = GetSize(data);
3159 offset = 0;
3160 }
3161
3162 RTLIL::SigChunk::SigChunk(int val, int width)
3163 {
3164 wire = NULL;
3165 data = RTLIL::Const(val, width).bits;
3166 this->width = GetSize(data);
3167 offset = 0;
3168 }
3169
3170 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
3171 {
3172 wire = NULL;
3173 data = RTLIL::Const(bit, width).bits;
3174 this->width = GetSize(data);
3175 offset = 0;
3176 }
3177
3178 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
3179 {
3180 wire = bit.wire;
3181 offset = 0;
3182 if (wire == NULL)
3183 data = RTLIL::Const(bit.data).bits;
3184 else
3185 offset = bit.offset;
3186 width = 1;
3187 }
3188
3189 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
3190 {
3191 *this = sigchunk;
3192 }
3193
3194 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
3195 {
3196 RTLIL::SigChunk ret;
3197 if (wire) {
3198 ret.wire = wire;
3199 ret.offset = this->offset + offset;
3200 ret.width = length;
3201 } else {
3202 for (int i = 0; i < length; i++)
3203 ret.data.push_back(data[offset+i]);
3204 ret.width = length;
3205 }
3206 return ret;
3207 }
3208
3209 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
3210 {
3211 if (wire && other.wire)
3212 if (wire->name != other.wire->name)
3213 return wire->name < other.wire->name;
3214
3215 if (wire != other.wire)
3216 return wire < other.wire;
3217
3218 if (offset != other.offset)
3219 return offset < other.offset;
3220
3221 if (width != other.width)
3222 return width < other.width;
3223
3224 return data < other.data;
3225 }
3226
3227 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
3228 {
3229 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
3230 }
3231
3232 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
3233 {
3234 if (*this == other)
3235 return false;
3236 return true;
3237 }
3238
3239 RTLIL::SigSpec::SigSpec()
3240 {
3241 width_ = 0;
3242 hash_ = 0;
3243 }
3244
3245 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
3246 {
3247 *this = other;
3248 }
3249
3250 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
3251 {
3252 cover("kernel.rtlil.sigspec.init.list");
3253
3254 width_ = 0;
3255 hash_ = 0;
3256
3257 log_assert(parts.size() > 0);
3258 auto ie = parts.begin();
3259 auto it = ie + parts.size() - 1;
3260 while (it >= ie)
3261 append(*it--);
3262 }
3263
3264 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
3265 {
3266 cover("kernel.rtlil.sigspec.assign");
3267
3268 width_ = other.width_;
3269 hash_ = other.hash_;
3270 chunks_ = other.chunks_;
3271 bits_ = other.bits_;
3272 return *this;
3273 }
3274
3275 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
3276 {
3277 cover("kernel.rtlil.sigspec.init.const");
3278
3279 if (GetSize(value) != 0) {
3280 chunks_.emplace_back(value);
3281 width_ = chunks_.back().width;
3282 } else {
3283 width_ = 0;
3284 }
3285 hash_ = 0;
3286 check();
3287 }
3288
3289 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
3290 {
3291 cover("kernel.rtlil.sigspec.init.chunk");
3292
3293 if (chunk.width != 0) {
3294 chunks_.emplace_back(chunk);
3295 width_ = chunks_.back().width;
3296 } else {
3297 width_ = 0;
3298 }
3299 hash_ = 0;
3300 check();
3301 }
3302
3303 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
3304 {
3305 cover("kernel.rtlil.sigspec.init.wire");
3306
3307 if (wire->width != 0) {
3308 chunks_.emplace_back(wire);
3309 width_ = chunks_.back().width;
3310 } else {
3311 width_ = 0;
3312 }
3313 hash_ = 0;
3314 check();
3315 }
3316
3317 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
3318 {
3319 cover("kernel.rtlil.sigspec.init.wire_part");
3320
3321 if (width != 0) {
3322 chunks_.emplace_back(wire, offset, width);
3323 width_ = chunks_.back().width;
3324 } else {
3325 width_ = 0;
3326 }
3327 hash_ = 0;
3328 check();
3329 }
3330
3331 RTLIL::SigSpec::SigSpec(const std::string &str)
3332 {
3333 cover("kernel.rtlil.sigspec.init.str");
3334
3335 if (str.size() != 0) {
3336 chunks_.emplace_back(str);
3337 width_ = chunks_.back().width;
3338 } else {
3339 width_ = 0;
3340 }
3341 hash_ = 0;
3342 check();
3343 }
3344
3345 RTLIL::SigSpec::SigSpec(int val, int width)
3346 {
3347 cover("kernel.rtlil.sigspec.init.int");
3348
3349 if (width != 0)
3350 chunks_.emplace_back(val, width);
3351 width_ = width;
3352 hash_ = 0;
3353 check();
3354 }
3355
3356 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
3357 {
3358 cover("kernel.rtlil.sigspec.init.state");
3359
3360 if (width != 0)
3361 chunks_.emplace_back(bit, width);
3362 width_ = width;
3363 hash_ = 0;
3364 check();
3365 }
3366
3367 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
3368 {
3369 cover("kernel.rtlil.sigspec.init.bit");
3370
3371 if (width != 0) {
3372 if (bit.wire == NULL)
3373 chunks_.emplace_back(bit.data, width);
3374 else
3375 for (int i = 0; i < width; i++)
3376 chunks_.push_back(bit);
3377 }
3378 width_ = width;
3379 hash_ = 0;
3380 check();
3381 }
3382
3383 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
3384 {
3385 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3386
3387 width_ = 0;
3388 hash_ = 0;
3389 for (const auto &c : chunks)
3390 append(c);
3391 check();
3392 }
3393
3394 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
3395 {
3396 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3397
3398 width_ = 0;
3399 hash_ = 0;
3400 for (const auto &bit : bits)
3401 append(bit);
3402 check();
3403 }
3404
3405 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3406 {
3407 cover("kernel.rtlil.sigspec.init.pool_bits");
3408
3409 width_ = 0;
3410 hash_ = 0;
3411 for (const auto &bit : bits)
3412 append(bit);
3413 check();
3414 }
3415
3416 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3417 {
3418 cover("kernel.rtlil.sigspec.init.stdset_bits");
3419
3420 width_ = 0;
3421 hash_ = 0;
3422 for (const auto &bit : bits)
3423 append(bit);
3424 check();
3425 }
3426
3427 RTLIL::SigSpec::SigSpec(bool bit)
3428 {
3429 cover("kernel.rtlil.sigspec.init.bool");
3430
3431 width_ = 0;
3432 hash_ = 0;
3433 append(SigBit(bit));
3434 check();
3435 }
3436
3437 void RTLIL::SigSpec::pack() const
3438 {
3439 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3440
3441 if (that->bits_.empty())
3442 return;
3443
3444 cover("kernel.rtlil.sigspec.convert.pack");
3445 log_assert(that->chunks_.empty());
3446
3447 std::vector<RTLIL::SigBit> old_bits;
3448 old_bits.swap(that->bits_);
3449
3450 RTLIL::SigChunk *last = NULL;
3451 int last_end_offset = 0;
3452
3453 for (auto &bit : old_bits) {
3454 if (last && bit.wire == last->wire) {
3455 if (bit.wire == NULL) {
3456 last->data.push_back(bit.data);
3457 last->width++;
3458 continue;
3459 } else if (last_end_offset == bit.offset) {
3460 last_end_offset++;
3461 last->width++;
3462 continue;
3463 }
3464 }
3465 that->chunks_.push_back(bit);
3466 last = &that->chunks_.back();
3467 last_end_offset = bit.offset + 1;
3468 }
3469
3470 check();
3471 }
3472
3473 void RTLIL::SigSpec::unpack() const
3474 {
3475 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3476
3477 if (that->chunks_.empty())
3478 return;
3479
3480 cover("kernel.rtlil.sigspec.convert.unpack");
3481 log_assert(that->bits_.empty());
3482
3483 that->bits_.reserve(that->width_);
3484 for (auto &c : that->chunks_)
3485 for (int i = 0; i < c.width; i++)
3486 that->bits_.emplace_back(c, i);
3487
3488 that->chunks_.clear();
3489 that->hash_ = 0;
3490 }
3491
3492 void RTLIL::SigSpec::updhash() const
3493 {
3494 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3495
3496 if (that->hash_ != 0)
3497 return;
3498
3499 cover("kernel.rtlil.sigspec.hash");
3500 that->pack();
3501
3502 that->hash_ = mkhash_init;
3503 for (auto &c : that->chunks_)
3504 if (c.wire == NULL) {
3505 for (auto &v : c.data)
3506 that->hash_ = mkhash(that->hash_, v);
3507 } else {
3508 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3509 that->hash_ = mkhash(that->hash_, c.offset);
3510 that->hash_ = mkhash(that->hash_, c.width);
3511 }
3512
3513 if (that->hash_ == 0)
3514 that->hash_ = 1;
3515 }
3516
3517 void RTLIL::SigSpec::sort()
3518 {
3519 unpack();
3520 cover("kernel.rtlil.sigspec.sort");
3521 std::sort(bits_.begin(), bits_.end());
3522 }
3523
3524 void RTLIL::SigSpec::sort_and_unify()
3525 {
3526 unpack();
3527 cover("kernel.rtlil.sigspec.sort_and_unify");
3528
3529 // A copy of the bits vector is used to prevent duplicating the logic from
3530 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3531 // that isn't showing up as significant in profiles.
3532 std::vector<SigBit> unique_bits = bits_;
3533 std::sort(unique_bits.begin(), unique_bits.end());
3534 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3535 unique_bits.erase(last, unique_bits.end());
3536
3537 *this = unique_bits;
3538 }
3539
3540 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3541 {
3542 replace(pattern, with, this);
3543 }
3544
3545 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3546 {
3547 log_assert(other != NULL);
3548 log_assert(width_ == other->width_);
3549 log_assert(pattern.width_ == with.width_);
3550
3551 pattern.unpack();
3552 with.unpack();
3553 unpack();
3554 other->unpack();
3555
3556 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3557 if (pattern.bits_[i].wire != NULL) {
3558 for (int j = 0; j < GetSize(bits_); j++) {
3559 if (bits_[j] == pattern.bits_[i]) {
3560 other->bits_[j] = with.bits_[i];
3561 }
3562 }
3563 }
3564 }
3565
3566 other->check();
3567 }
3568
3569 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3570 {
3571 replace(rules, this);
3572 }
3573
3574 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3575 {
3576 cover("kernel.rtlil.sigspec.replace_dict");
3577
3578 log_assert(other != NULL);
3579 log_assert(width_ == other->width_);
3580
3581 if (rules.empty()) return;
3582 unpack();
3583 other->unpack();
3584
3585 for (int i = 0; i < GetSize(bits_); i++) {
3586 auto it = rules.find(bits_[i]);
3587 if (it != rules.end())
3588 other->bits_[i] = it->second;
3589 }
3590
3591 other->check();
3592 }
3593
3594 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3595 {
3596 replace(rules, this);
3597 }
3598
3599 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3600 {
3601 cover("kernel.rtlil.sigspec.replace_map");
3602
3603 log_assert(other != NULL);
3604 log_assert(width_ == other->width_);
3605
3606 if (rules.empty()) return;
3607 unpack();
3608 other->unpack();
3609
3610 for (int i = 0; i < GetSize(bits_); i++) {
3611 auto it = rules.find(bits_[i]);
3612 if (it != rules.end())
3613 other->bits_[i] = it->second;
3614 }
3615
3616 other->check();
3617 }
3618
3619 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3620 {
3621 remove2(pattern, NULL);
3622 }
3623
3624 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3625 {
3626 RTLIL::SigSpec tmp = *this;
3627 tmp.remove2(pattern, other);
3628 }
3629
3630 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3631 {
3632 if (other)
3633 cover("kernel.rtlil.sigspec.remove_other");
3634 else
3635 cover("kernel.rtlil.sigspec.remove");
3636
3637 unpack();
3638 if (other != NULL) {
3639 log_assert(width_ == other->width_);
3640 other->unpack();
3641 }
3642
3643 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3644 {
3645 if (bits_[i].wire == NULL) continue;
3646
3647 for (auto &pattern_chunk : pattern.chunks())
3648 if (bits_[i].wire == pattern_chunk.wire &&
3649 bits_[i].offset >= pattern_chunk.offset &&
3650 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3651 bits_.erase(bits_.begin() + i);
3652 width_--;
3653 if (other != NULL) {
3654 other->bits_.erase(other->bits_.begin() + i);
3655 other->width_--;
3656 }
3657 break;
3658 }
3659 }
3660
3661 check();
3662 }
3663
3664 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3665 {
3666 remove2(pattern, NULL);
3667 }
3668
3669 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3670 {
3671 RTLIL::SigSpec tmp = *this;
3672 tmp.remove2(pattern, other);
3673 }
3674
3675 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3676 {
3677 if (other)
3678 cover("kernel.rtlil.sigspec.remove_other");
3679 else
3680 cover("kernel.rtlil.sigspec.remove");
3681
3682 unpack();
3683
3684 if (other != NULL) {
3685 log_assert(width_ == other->width_);
3686 other->unpack();
3687 }
3688
3689 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3690 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3691 bits_.erase(bits_.begin() + i);
3692 width_--;
3693 if (other != NULL) {
3694 other->bits_.erase(other->bits_.begin() + i);
3695 other->width_--;
3696 }
3697 }
3698 }
3699
3700 check();
3701 }
3702
3703 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3704 {
3705 if (other)
3706 cover("kernel.rtlil.sigspec.remove_other");
3707 else
3708 cover("kernel.rtlil.sigspec.remove");
3709
3710 unpack();
3711
3712 if (other != NULL) {
3713 log_assert(width_ == other->width_);
3714 other->unpack();
3715 }
3716
3717 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3718 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3719 bits_.erase(bits_.begin() + i);
3720 width_--;
3721 if (other != NULL) {
3722 other->bits_.erase(other->bits_.begin() + i);
3723 other->width_--;
3724 }
3725 }
3726 }
3727
3728 check();
3729 }
3730
3731 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3732 {
3733 if (other)
3734 cover("kernel.rtlil.sigspec.extract_other");
3735 else
3736 cover("kernel.rtlil.sigspec.extract");
3737
3738 log_assert(other == NULL || width_ == other->width_);
3739
3740 RTLIL::SigSpec ret;
3741 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3742
3743 for (auto& pattern_chunk : pattern.chunks()) {
3744 if (other) {
3745 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3746 for (int i = 0; i < width_; i++)
3747 if (bits_match[i].wire &&
3748 bits_match[i].wire == pattern_chunk.wire &&
3749 bits_match[i].offset >= pattern_chunk.offset &&
3750 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3751 ret.append(bits_other[i]);
3752 } else {
3753 for (int i = 0; i < width_; i++)
3754 if (bits_match[i].wire &&
3755 bits_match[i].wire == pattern_chunk.wire &&
3756 bits_match[i].offset >= pattern_chunk.offset &&
3757 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3758 ret.append(bits_match[i]);
3759 }
3760 }
3761
3762 ret.check();
3763 return ret;
3764 }
3765
3766 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3767 {
3768 if (other)
3769 cover("kernel.rtlil.sigspec.extract_other");
3770 else
3771 cover("kernel.rtlil.sigspec.extract");
3772
3773 log_assert(other == NULL || width_ == other->width_);
3774
3775 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3776 RTLIL::SigSpec ret;
3777
3778 if (other) {
3779 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3780 for (int i = 0; i < width_; i++)
3781 if (bits_match[i].wire && pattern.count(bits_match[i]))
3782 ret.append(bits_other[i]);
3783 } else {
3784 for (int i = 0; i < width_; i++)
3785 if (bits_match[i].wire && pattern.count(bits_match[i]))
3786 ret.append(bits_match[i]);
3787 }
3788
3789 ret.check();
3790 return ret;
3791 }
3792
3793 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3794 {
3795 cover("kernel.rtlil.sigspec.replace_pos");
3796
3797 unpack();
3798 with.unpack();
3799
3800 log_assert(offset >= 0);
3801 log_assert(with.width_ >= 0);
3802 log_assert(offset+with.width_ <= width_);
3803
3804 for (int i = 0; i < with.width_; i++)
3805 bits_.at(offset + i) = with.bits_.at(i);
3806
3807 check();
3808 }
3809
3810 void RTLIL::SigSpec::remove_const()
3811 {
3812 if (packed())
3813 {
3814 cover("kernel.rtlil.sigspec.remove_const.packed");
3815
3816 std::vector<RTLIL::SigChunk> new_chunks;
3817 new_chunks.reserve(GetSize(chunks_));
3818
3819 width_ = 0;
3820 for (auto &chunk : chunks_)
3821 if (chunk.wire != NULL) {
3822 if (!new_chunks.empty() &&
3823 new_chunks.back().wire == chunk.wire &&
3824 new_chunks.back().offset + new_chunks.back().width == chunk.offset) {
3825 new_chunks.back().width += chunk.width;
3826 } else {
3827 new_chunks.push_back(chunk);
3828 }
3829 width_ += chunk.width;
3830 }
3831
3832 chunks_.swap(new_chunks);
3833 }
3834 else
3835 {
3836 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3837
3838 std::vector<RTLIL::SigBit> new_bits;
3839 new_bits.reserve(width_);
3840
3841 for (auto &bit : bits_)
3842 if (bit.wire != NULL)
3843 new_bits.push_back(bit);
3844
3845 bits_.swap(new_bits);
3846 width_ = bits_.size();
3847 }
3848
3849 check();
3850 }
3851
3852 void RTLIL::SigSpec::remove(int offset, int length)
3853 {
3854 cover("kernel.rtlil.sigspec.remove_pos");
3855
3856 unpack();
3857
3858 log_assert(offset >= 0);
3859 log_assert(length >= 0);
3860 log_assert(offset + length <= width_);
3861
3862 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3863 width_ = bits_.size();
3864
3865 check();
3866 }
3867
3868 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3869 {
3870 unpack();
3871 cover("kernel.rtlil.sigspec.extract_pos");
3872 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3873 }
3874
3875 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3876 {
3877 if (signal.width_ == 0)
3878 return;
3879
3880 if (width_ == 0) {
3881 *this = signal;
3882 return;
3883 }
3884
3885 cover("kernel.rtlil.sigspec.append");
3886
3887 if (packed() != signal.packed()) {
3888 pack();
3889 signal.pack();
3890 }
3891
3892 if (packed())
3893 for (auto &other_c : signal.chunks_)
3894 {
3895 auto &my_last_c = chunks_.back();
3896 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3897 auto &this_data = my_last_c.data;
3898 auto &other_data = other_c.data;
3899 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3900 my_last_c.width += other_c.width;
3901 } else
3902 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3903 my_last_c.width += other_c.width;
3904 } else
3905 chunks_.push_back(other_c);
3906 }
3907 else
3908 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3909
3910 width_ += signal.width_;
3911 check();
3912 }
3913
3914 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3915 {
3916 if (packed())
3917 {
3918 cover("kernel.rtlil.sigspec.append_bit.packed");
3919
3920 if (chunks_.size() == 0)
3921 chunks_.push_back(bit);
3922 else
3923 if (bit.wire == NULL)
3924 if (chunks_.back().wire == NULL) {
3925 chunks_.back().data.push_back(bit.data);
3926 chunks_.back().width++;
3927 } else
3928 chunks_.push_back(bit);
3929 else
3930 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3931 chunks_.back().width++;
3932 else
3933 chunks_.push_back(bit);
3934 }
3935 else
3936 {
3937 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3938 bits_.push_back(bit);
3939 }
3940
3941 width_++;
3942 check();
3943 }
3944
3945 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3946 {
3947 cover("kernel.rtlil.sigspec.extend_u0");
3948
3949 pack();
3950
3951 if (width_ > width)
3952 remove(width, width_ - width);
3953
3954 if (width_ < width) {
3955 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3956 if (!is_signed)
3957 padding = RTLIL::State::S0;
3958 while (width_ < width)
3959 append(padding);
3960 }
3961
3962 }
3963
3964 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3965 {
3966 cover("kernel.rtlil.sigspec.repeat");
3967
3968 RTLIL::SigSpec sig;
3969 for (int i = 0; i < num; i++)
3970 sig.append(*this);
3971 return sig;
3972 }
3973
3974 #ifndef NDEBUG
3975 void RTLIL::SigSpec::check() const
3976 {
3977 if (width_ > 64)
3978 {
3979 cover("kernel.rtlil.sigspec.check.skip");
3980 }
3981 else if (packed())
3982 {
3983 cover("kernel.rtlil.sigspec.check.packed");
3984
3985 int w = 0;
3986 for (size_t i = 0; i < chunks_.size(); i++) {
3987 const RTLIL::SigChunk &chunk = chunks_[i];
3988 log_assert(chunk.width != 0);
3989 if (chunk.wire == NULL) {
3990 if (i > 0)
3991 log_assert(chunks_[i-1].wire != NULL);
3992 log_assert(chunk.offset == 0);
3993 log_assert(chunk.data.size() == (size_t)chunk.width);
3994 } else {
3995 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3996 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3997 log_assert(chunk.offset >= 0);
3998 log_assert(chunk.width >= 0);
3999 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
4000 log_assert(chunk.data.size() == 0);
4001 }
4002 w += chunk.width;
4003 }
4004 log_assert(w == width_);
4005 log_assert(bits_.empty());
4006 }
4007 else
4008 {
4009 cover("kernel.rtlil.sigspec.check.unpacked");
4010
4011 log_assert(width_ == GetSize(bits_));
4012 log_assert(chunks_.empty());
4013 }
4014 }
4015 #endif
4016
4017 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
4018 {
4019 cover("kernel.rtlil.sigspec.comp_lt");
4020
4021 if (this == &other)
4022 return false;
4023
4024 if (width_ != other.width_)
4025 return width_ < other.width_;
4026
4027 pack();
4028 other.pack();
4029
4030 if (chunks_.size() != other.chunks_.size())
4031 return chunks_.size() < other.chunks_.size();
4032
4033 updhash();
4034 other.updhash();
4035
4036 if (hash_ != other.hash_)
4037 return hash_ < other.hash_;
4038
4039 for (size_t i = 0; i < chunks_.size(); i++)
4040 if (chunks_[i] != other.chunks_[i]) {
4041 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4042 return chunks_[i] < other.chunks_[i];
4043 }
4044
4045 cover("kernel.rtlil.sigspec.comp_lt.equal");
4046 return false;
4047 }
4048
4049 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
4050 {
4051 cover("kernel.rtlil.sigspec.comp_eq");
4052
4053 if (this == &other)
4054 return true;
4055
4056 if (width_ != other.width_)
4057 return false;
4058
4059 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4060 // since the RHS will contain one SigChunk of width 0 causing
4061 // the size check below to fail
4062 if (width_ == 0)
4063 return true;
4064
4065 pack();
4066 other.pack();
4067
4068 if (chunks_.size() != other.chunks_.size())
4069 return false;
4070
4071 updhash();
4072 other.updhash();
4073
4074 if (hash_ != other.hash_)
4075 return false;
4076
4077 for (size_t i = 0; i < chunks_.size(); i++)
4078 if (chunks_[i] != other.chunks_[i]) {
4079 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4080 return false;
4081 }
4082
4083 cover("kernel.rtlil.sigspec.comp_eq.equal");
4084 return true;
4085 }
4086
4087 bool RTLIL::SigSpec::is_wire() const
4088 {
4089 cover("kernel.rtlil.sigspec.is_wire");
4090
4091 pack();
4092 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
4093 }
4094
4095 bool RTLIL::SigSpec::is_chunk() const
4096 {
4097 cover("kernel.rtlil.sigspec.is_chunk");
4098
4099 pack();
4100 return GetSize(chunks_) == 1;
4101 }
4102
4103 bool RTLIL::SigSpec::is_fully_const() const
4104 {
4105 cover("kernel.rtlil.sigspec.is_fully_const");
4106
4107 pack();
4108 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4109 if (it->width > 0 && it->wire != NULL)
4110 return false;
4111 return true;
4112 }
4113
4114 bool RTLIL::SigSpec::is_fully_zero() const
4115 {
4116 cover("kernel.rtlil.sigspec.is_fully_zero");
4117
4118 pack();
4119 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4120 if (it->width > 0 && it->wire != NULL)
4121 return false;
4122 for (size_t i = 0; i < it->data.size(); i++)
4123 if (it->data[i] != RTLIL::State::S0)
4124 return false;
4125 }
4126 return true;
4127 }
4128
4129 bool RTLIL::SigSpec::is_fully_ones() const
4130 {
4131 cover("kernel.rtlil.sigspec.is_fully_ones");
4132
4133 pack();
4134 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4135 if (it->width > 0 && it->wire != NULL)
4136 return false;
4137 for (size_t i = 0; i < it->data.size(); i++)
4138 if (it->data[i] != RTLIL::State::S1)
4139 return false;
4140 }
4141 return true;
4142 }
4143
4144 bool RTLIL::SigSpec::is_fully_def() const
4145 {
4146 cover("kernel.rtlil.sigspec.is_fully_def");
4147
4148 pack();
4149 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4150 if (it->width > 0 && it->wire != NULL)
4151 return false;
4152 for (size_t i = 0; i < it->data.size(); i++)
4153 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
4154 return false;
4155 }
4156 return true;
4157 }
4158
4159 bool RTLIL::SigSpec::is_fully_undef() const
4160 {
4161 cover("kernel.rtlil.sigspec.is_fully_undef");
4162
4163 pack();
4164 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4165 if (it->width > 0 && it->wire != NULL)
4166 return false;
4167 for (size_t i = 0; i < it->data.size(); i++)
4168 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
4169 return false;
4170 }
4171 return true;
4172 }
4173
4174 bool RTLIL::SigSpec::has_const() const
4175 {
4176 cover("kernel.rtlil.sigspec.has_const");
4177
4178 pack();
4179 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4180 if (it->width > 0 && it->wire == NULL)
4181 return true;
4182 return false;
4183 }
4184
4185 bool RTLIL::SigSpec::has_marked_bits() const
4186 {
4187 cover("kernel.rtlil.sigspec.has_marked_bits");
4188
4189 pack();
4190 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4191 if (it->width > 0 && it->wire == NULL) {
4192 for (size_t i = 0; i < it->data.size(); i++)
4193 if (it->data[i] == RTLIL::State::Sm)
4194 return true;
4195 }
4196 return false;
4197 }
4198
4199 bool RTLIL::SigSpec::as_bool() const
4200 {
4201 cover("kernel.rtlil.sigspec.as_bool");
4202
4203 pack();
4204 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4205 if (width_)
4206 return RTLIL::Const(chunks_[0].data).as_bool();
4207 return false;
4208 }
4209
4210 int RTLIL::SigSpec::as_int(bool is_signed) const
4211 {
4212 cover("kernel.rtlil.sigspec.as_int");
4213
4214 pack();
4215 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4216 if (width_)
4217 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
4218 return 0;
4219 }
4220
4221 std::string RTLIL::SigSpec::as_string() const
4222 {
4223 cover("kernel.rtlil.sigspec.as_string");
4224
4225 pack();
4226 std::string str;
4227 str.reserve(size());
4228 for (size_t i = chunks_.size(); i > 0; i--) {
4229 const RTLIL::SigChunk &chunk = chunks_[i-1];
4230 if (chunk.wire != NULL)
4231 str.append(chunk.width, '?');
4232 else
4233 str += RTLIL::Const(chunk.data).as_string();
4234 }
4235 return str;
4236 }
4237
4238 RTLIL::Const RTLIL::SigSpec::as_const() const
4239 {
4240 cover("kernel.rtlil.sigspec.as_const");
4241
4242 pack();
4243 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4244 if (width_)
4245 return chunks_[0].data;
4246 return RTLIL::Const();
4247 }
4248
4249 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
4250 {
4251 cover("kernel.rtlil.sigspec.as_wire");
4252
4253 pack();
4254 log_assert(is_wire());
4255 return chunks_[0].wire;
4256 }
4257
4258 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
4259 {
4260 cover("kernel.rtlil.sigspec.as_chunk");
4261
4262 pack();
4263 log_assert(is_chunk());
4264 return chunks_[0];
4265 }
4266
4267 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
4268 {
4269 cover("kernel.rtlil.sigspec.as_bit");
4270
4271 log_assert(width_ == 1);
4272 if (packed())
4273 return RTLIL::SigBit(*chunks_.begin());
4274 else
4275 return bits_[0];
4276 }
4277
4278 bool RTLIL::SigSpec::match(const char* pattern) const
4279 {
4280 cover("kernel.rtlil.sigspec.match");
4281
4282 unpack();
4283 log_assert(int(strlen(pattern)) == GetSize(bits_));
4284
4285 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
4286 if (*pattern == ' ')
4287 continue;
4288 if (*pattern == '*') {
4289 if (*it != State::Sz && *it != State::Sx)
4290 return false;
4291 continue;
4292 }
4293 if (*pattern == '0') {
4294 if (*it != State::S0)
4295 return false;
4296 } else
4297 if (*pattern == '1') {
4298 if (*it != State::S1)
4299 return false;
4300 } else
4301 log_abort();
4302 }
4303
4304 return true;
4305 }
4306
4307 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
4308 {
4309 cover("kernel.rtlil.sigspec.to_sigbit_set");
4310
4311 pack();
4312 std::set<RTLIL::SigBit> sigbits;
4313 for (auto &c : chunks_)
4314 for (int i = 0; i < c.width; i++)
4315 sigbits.insert(RTLIL::SigBit(c, i));
4316 return sigbits;
4317 }
4318
4319 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
4320 {
4321 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4322
4323 pack();
4324 pool<RTLIL::SigBit> sigbits;
4325 sigbits.reserve(size());
4326 for (auto &c : chunks_)
4327 for (int i = 0; i < c.width; i++)
4328 sigbits.insert(RTLIL::SigBit(c, i));
4329 return sigbits;
4330 }
4331
4332 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
4333 {
4334 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4335
4336 unpack();
4337 return bits_;
4338 }
4339
4340 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
4341 {
4342 cover("kernel.rtlil.sigspec.to_sigbit_map");
4343
4344 unpack();
4345 other.unpack();
4346
4347 log_assert(width_ == other.width_);
4348
4349 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
4350 for (int i = 0; i < width_; i++)
4351 new_map[bits_[i]] = other.bits_[i];
4352
4353 return new_map;
4354 }
4355
4356 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
4357 {
4358 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4359
4360 unpack();
4361 other.unpack();
4362
4363 log_assert(width_ == other.width_);
4364
4365 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
4366 new_map.reserve(size());
4367 for (int i = 0; i < width_; i++)
4368 new_map[bits_[i]] = other.bits_[i];
4369
4370 return new_map;
4371 }
4372
4373 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
4374 {
4375 size_t start = 0, end = 0;
4376 while ((end = text.find(sep, start)) != std::string::npos) {
4377 tokens.push_back(text.substr(start, end - start));
4378 start = end + 1;
4379 }
4380 tokens.push_back(text.substr(start));
4381 }
4382
4383 static int sigspec_parse_get_dummy_line_num()
4384 {
4385 return 0;
4386 }
4387
4388 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4389 {
4390 cover("kernel.rtlil.sigspec.parse");
4391
4392 AST::current_filename = "input";
4393
4394 std::vector<std::string> tokens;
4395 sigspec_parse_split(tokens, str, ',');
4396
4397 sig = RTLIL::SigSpec();
4398 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
4399 {
4400 std::string netname = tokens[tokidx];
4401 std::string indices;
4402
4403 if (netname.size() == 0)
4404 continue;
4405
4406 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4407 cover("kernel.rtlil.sigspec.parse.const");
4408 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4409 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4410 if (ast == NULL)
4411 return false;
4412 sig.append(RTLIL::Const(ast->bits));
4413 delete ast;
4414 continue;
4415 }
4416
4417 if (module == NULL)
4418 return false;
4419
4420 cover("kernel.rtlil.sigspec.parse.net");
4421
4422 if (netname[0] != '$' && netname[0] != '\\')
4423 netname = "\\" + netname;
4424
4425 if (module->wires_.count(netname) == 0) {
4426 size_t indices_pos = netname.size()-1;
4427 if (indices_pos > 2 && netname[indices_pos] == ']')
4428 {
4429 indices_pos--;
4430 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4431 if (indices_pos > 0 && netname[indices_pos] == ':') {
4432 indices_pos--;
4433 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4434 }
4435 if (indices_pos > 0 && netname[indices_pos] == '[') {
4436 indices = netname.substr(indices_pos);
4437 netname = netname.substr(0, indices_pos);
4438 }
4439 }
4440 }
4441
4442 if (module->wires_.count(netname) == 0)
4443 return false;
4444
4445 RTLIL::Wire *wire = module->wires_.at(netname);
4446 if (!indices.empty()) {
4447 std::vector<std::string> index_tokens;
4448 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4449 if (index_tokens.size() == 1) {
4450 cover("kernel.rtlil.sigspec.parse.bit_sel");
4451 int a = atoi(index_tokens.at(0).c_str());
4452 if (a < 0 || a >= wire->width)
4453 return false;
4454 sig.append(RTLIL::SigSpec(wire, a));
4455 } else {
4456 cover("kernel.rtlil.sigspec.parse.part_sel");
4457 int a = atoi(index_tokens.at(0).c_str());
4458 int b = atoi(index_tokens.at(1).c_str());
4459 if (a > b) {
4460 int tmp = a;
4461 a = b, b = tmp;
4462 }
4463 if (a < 0 || a >= wire->width)
4464 return false;
4465 if (b < 0 || b >= wire->width)
4466 return false;
4467 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4468 }
4469 } else
4470 sig.append(wire);
4471 }
4472
4473 return true;
4474 }
4475
4476 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4477 {
4478 if (str.empty() || str[0] != '@')
4479 return parse(sig, module, str);
4480
4481 cover("kernel.rtlil.sigspec.parse.sel");
4482
4483 str = RTLIL::escape_id(str.substr(1));
4484 if (design->selection_vars.count(str) == 0)
4485 return false;
4486
4487 sig = RTLIL::SigSpec();
4488 RTLIL::Selection &sel = design->selection_vars.at(str);
4489 for (auto &it : module->wires_)
4490 if (sel.selected_member(module->name, it.first))
4491 sig.append(it.second);
4492
4493 return true;
4494 }
4495
4496 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4497 {
4498 if (str == "0") {
4499 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4500 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4501 return true;
4502 }
4503
4504 if (str == "~0") {
4505 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4506 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4507 return true;
4508 }
4509
4510 if (lhs.chunks_.size() == 1) {
4511 char *p = (char*)str.c_str(), *endptr;
4512 long int val = strtol(p, &endptr, 10);
4513 if (endptr && endptr != p && *endptr == 0) {
4514 sig = RTLIL::SigSpec(val, lhs.width_);
4515 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4516 return true;
4517 }
4518 }
4519
4520 return parse(sig, module, str);
4521 }
4522
4523 RTLIL::CaseRule::~CaseRule()
4524 {
4525 for (auto it = switches.begin(); it != switches.end(); it++)
4526 delete *it;
4527 }
4528
4529 bool RTLIL::CaseRule::empty() const
4530 {
4531 return actions.empty() && switches.empty();
4532 }
4533
4534 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4535 {
4536 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4537 new_caserule->compare = compare;
4538 new_caserule->actions = actions;
4539 for (auto &it : switches)
4540 new_caserule->switches.push_back(it->clone());
4541 return new_caserule;
4542 }
4543
4544 RTLIL::SwitchRule::~SwitchRule()
4545 {
4546 for (auto it = cases.begin(); it != cases.end(); it++)
4547 delete *it;
4548 }
4549
4550 bool RTLIL::SwitchRule::empty() const
4551 {
4552 return cases.empty();
4553 }
4554
4555 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4556 {
4557 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4558 new_switchrule->signal = signal;
4559 new_switchrule->attributes = attributes;
4560 for (auto &it : cases)
4561 new_switchrule->cases.push_back(it->clone());
4562 return new_switchrule;
4563
4564 }
4565
4566 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4567 {
4568 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4569 new_syncrule->type = type;
4570 new_syncrule->signal = signal;
4571 new_syncrule->actions = actions;
4572 new_syncrule->mem_write_actions = mem_write_actions;
4573 return new_syncrule;
4574 }
4575
4576 RTLIL::Process::~Process()
4577 {
4578 for (auto it = syncs.begin(); it != syncs.end(); it++)
4579 delete *it;
4580 }
4581
4582 RTLIL::Process *RTLIL::Process::clone() const
4583 {
4584 RTLIL::Process *new_proc = new RTLIL::Process;
4585
4586 new_proc->name = name;
4587 new_proc->attributes = attributes;
4588
4589 RTLIL::CaseRule *rc_ptr = root_case.clone();
4590 new_proc->root_case = *rc_ptr;
4591 rc_ptr->switches.clear();
4592 delete rc_ptr;
4593
4594 for (auto &it : syncs)
4595 new_proc->syncs.push_back(it->clone());
4596
4597 return new_proc;
4598 }
4599
4600 #ifdef WITH_PYTHON
4601 RTLIL::Memory::~Memory()
4602 {
4603 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4604 }
4605 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4606 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4607 {
4608 return &all_memorys;
4609 }
4610 #endif
4611 YOSYS_NAMESPACE_END