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Merge pull request #1937 from hzeller/consexpr-opportunity
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($adff),
58 ID($dlatch),
59 ID($dlatchsr),
60 ID($_DFFE_NN_),
61 ID($_DFFE_NP_),
62 ID($_DFFE_PN_),
63 ID($_DFFE_PP_),
64 ID($_DFFSR_NNN_),
65 ID($_DFFSR_NNP_),
66 ID($_DFFSR_NPN_),
67 ID($_DFFSR_NPP_),
68 ID($_DFFSR_PNN_),
69 ID($_DFFSR_PNP_),
70 ID($_DFFSR_PPN_),
71 ID($_DFFSR_PPP_),
72 ID($_DFF_NN0_),
73 ID($_DFF_NN1_),
74 ID($_DFF_NP0_),
75 ID($_DFF_NP1_),
76 ID($_DFF_N_),
77 ID($_DFF_PN0_),
78 ID($_DFF_PN1_),
79 ID($_DFF_PP0_),
80 ID($_DFF_PP1_),
81 ID($_DFF_P_),
82 ID($_DLATCHSR_NNN_),
83 ID($_DLATCHSR_NNP_),
84 ID($_DLATCHSR_NPN_),
85 ID($_DLATCHSR_NPP_),
86 ID($_DLATCHSR_PNN_),
87 ID($_DLATCHSR_PNP_),
88 ID($_DLATCHSR_PPN_),
89 ID($_DLATCHSR_PPP_),
90 ID($_DLATCH_N_),
91 ID($_DLATCH_P_),
92 ID($_FF_),
93 };
94 return res;
95 }
96
97 RTLIL::Const::Const()
98 {
99 flags = RTLIL::CONST_FLAG_NONE;
100 }
101
102 RTLIL::Const::Const(std::string str)
103 {
104 flags = RTLIL::CONST_FLAG_STRING;
105 for (int i = str.size()-1; i >= 0; i--) {
106 unsigned char ch = str[i];
107 for (int j = 0; j < 8; j++) {
108 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
109 ch = ch >> 1;
110 }
111 }
112 }
113
114 RTLIL::Const::Const(int val, int width)
115 {
116 flags = RTLIL::CONST_FLAG_NONE;
117 for (int i = 0; i < width; i++) {
118 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
119 val = val >> 1;
120 }
121 }
122
123 RTLIL::Const::Const(RTLIL::State bit, int width)
124 {
125 flags = RTLIL::CONST_FLAG_NONE;
126 for (int i = 0; i < width; i++)
127 bits.push_back(bit);
128 }
129
130 RTLIL::Const::Const(const std::vector<bool> &bits)
131 {
132 flags = RTLIL::CONST_FLAG_NONE;
133 for (const auto &b : bits)
134 this->bits.emplace_back(b ? State::S1 : State::S0);
135 }
136
137 RTLIL::Const::Const(const RTLIL::Const &c)
138 {
139 flags = c.flags;
140 for (const auto &b : c.bits)
141 this->bits.push_back(b);
142 }
143
144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
145 {
146 if (bits.size() != other.bits.size())
147 return bits.size() < other.bits.size();
148 for (size_t i = 0; i < bits.size(); i++)
149 if (bits[i] != other.bits[i])
150 return bits[i] < other.bits[i];
151 return false;
152 }
153
154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
155 {
156 return bits == other.bits;
157 }
158
159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
160 {
161 return bits != other.bits;
162 }
163
164 bool RTLIL::Const::as_bool() const
165 {
166 for (size_t i = 0; i < bits.size(); i++)
167 if (bits[i] == State::S1)
168 return true;
169 return false;
170 }
171
172 int RTLIL::Const::as_int(bool is_signed) const
173 {
174 int32_t ret = 0;
175 for (size_t i = 0; i < bits.size() && i < 32; i++)
176 if (bits[i] == State::S1)
177 ret |= 1 << i;
178 if (is_signed && bits.back() == State::S1)
179 for (size_t i = bits.size(); i < 32; i++)
180 ret |= 1 << i;
181 return ret;
182 }
183
184 std::string RTLIL::Const::as_string() const
185 {
186 std::string ret;
187 ret.reserve(bits.size());
188 for (size_t i = bits.size(); i > 0; i--)
189 switch (bits[i-1]) {
190 case S0: ret += "0"; break;
191 case S1: ret += "1"; break;
192 case Sx: ret += "x"; break;
193 case Sz: ret += "z"; break;
194 case Sa: ret += "-"; break;
195 case Sm: ret += "m"; break;
196 }
197 return ret;
198 }
199
200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
201 {
202 Const c;
203 c.bits.reserve(str.size());
204 for (auto it = str.rbegin(); it != str.rend(); it++)
205 switch (*it) {
206 case '0': c.bits.push_back(State::S0); break;
207 case '1': c.bits.push_back(State::S1); break;
208 case 'x': c.bits.push_back(State::Sx); break;
209 case 'z': c.bits.push_back(State::Sz); break;
210 case 'm': c.bits.push_back(State::Sm); break;
211 default: c.bits.push_back(State::Sa);
212 }
213 return c;
214 }
215
216 std::string RTLIL::Const::decode_string() const
217 {
218 std::string string;
219 string.reserve(GetSize(bits)/8);
220 for (int i = 0; i < GetSize(bits); i += 8) {
221 char ch = 0;
222 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
223 if (bits[i + j] == RTLIL::State::S1)
224 ch |= 1 << j;
225 if (ch != 0)
226 string.append({ch});
227 }
228 std::reverse(string.begin(), string.end());
229 return string;
230 }
231
232 bool RTLIL::Const::is_fully_zero() const
233 {
234 cover("kernel.rtlil.const.is_fully_zero");
235
236 for (const auto &bit : bits)
237 if (bit != RTLIL::State::S0)
238 return false;
239
240 return true;
241 }
242
243 bool RTLIL::Const::is_fully_ones() const
244 {
245 cover("kernel.rtlil.const.is_fully_ones");
246
247 for (const auto &bit : bits)
248 if (bit != RTLIL::State::S1)
249 return false;
250
251 return true;
252 }
253
254 bool RTLIL::Const::is_fully_def() const
255 {
256 cover("kernel.rtlil.const.is_fully_def");
257
258 for (const auto &bit : bits)
259 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
260 return false;
261
262 return true;
263 }
264
265 bool RTLIL::Const::is_fully_undef() const
266 {
267 cover("kernel.rtlil.const.is_fully_undef");
268
269 for (const auto &bit : bits)
270 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
271 return false;
272
273 return true;
274 }
275
276 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
277 {
278 if (value)
279 attributes[id] = RTLIL::Const(1);
280 else
281 attributes.erase(id);
282 }
283
284 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
285 {
286 const auto it = attributes.find(id);
287 if (it == attributes.end())
288 return false;
289 return it->second.as_bool();
290 }
291
292 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
293 {
294 string attrval;
295 for (const auto &s : data) {
296 if (!attrval.empty())
297 attrval += "|";
298 attrval += s;
299 }
300 attributes[id] = RTLIL::Const(attrval);
301 }
302
303 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
304 {
305 pool<string> union_data = get_strpool_attribute(id);
306 union_data.insert(data.begin(), data.end());
307 if (!union_data.empty())
308 set_strpool_attribute(id, union_data);
309 }
310
311 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
312 {
313 pool<string> data;
314 if (attributes.count(id) != 0)
315 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
316 data.insert(s);
317 return data;
318 }
319
320 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
321 {
322 if (src.empty())
323 attributes.erase(ID::src);
324 else
325 attributes[ID::src] = src;
326 }
327
328 std::string RTLIL::AttrObject::get_src_attribute() const
329 {
330 std::string src;
331 const auto it = attributes.find(ID::src);
332 if (it != attributes.end())
333 src = it->second.decode_string();
334 return src;
335 }
336
337 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
338 {
339 if (full_selection)
340 return true;
341 if (selected_modules.count(mod_name) > 0)
342 return true;
343 if (selected_members.count(mod_name) > 0)
344 return true;
345 return false;
346 }
347
348 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
349 {
350 if (full_selection)
351 return true;
352 if (selected_modules.count(mod_name) > 0)
353 return true;
354 return false;
355 }
356
357 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
358 {
359 if (full_selection)
360 return true;
361 if (selected_modules.count(mod_name) > 0)
362 return true;
363 if (selected_members.count(mod_name) > 0)
364 if (selected_members.at(mod_name).count(memb_name) > 0)
365 return true;
366 return false;
367 }
368
369 void RTLIL::Selection::optimize(RTLIL::Design *design)
370 {
371 if (full_selection) {
372 selected_modules.clear();
373 selected_members.clear();
374 return;
375 }
376
377 std::vector<RTLIL::IdString> del_list, add_list;
378
379 del_list.clear();
380 for (auto mod_name : selected_modules) {
381 if (design->modules_.count(mod_name) == 0)
382 del_list.push_back(mod_name);
383 selected_members.erase(mod_name);
384 }
385 for (auto mod_name : del_list)
386 selected_modules.erase(mod_name);
387
388 del_list.clear();
389 for (auto &it : selected_members)
390 if (design->modules_.count(it.first) == 0)
391 del_list.push_back(it.first);
392 for (auto mod_name : del_list)
393 selected_members.erase(mod_name);
394
395 for (auto &it : selected_members) {
396 del_list.clear();
397 for (auto memb_name : it.second)
398 if (design->modules_[it.first]->count_id(memb_name) == 0)
399 del_list.push_back(memb_name);
400 for (auto memb_name : del_list)
401 it.second.erase(memb_name);
402 }
403
404 del_list.clear();
405 add_list.clear();
406 for (auto &it : selected_members)
407 if (it.second.size() == 0)
408 del_list.push_back(it.first);
409 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
410 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
411 add_list.push_back(it.first);
412 for (auto mod_name : del_list)
413 selected_members.erase(mod_name);
414 for (auto mod_name : add_list) {
415 selected_members.erase(mod_name);
416 selected_modules.insert(mod_name);
417 }
418
419 if (selected_modules.size() == design->modules_.size()) {
420 full_selection = true;
421 selected_modules.clear();
422 selected_members.clear();
423 }
424 }
425
426 RTLIL::Design::Design()
427 : verilog_defines (new define_map_t)
428 {
429 static unsigned int hashidx_count = 123456789;
430 hashidx_count = mkhash_xorshift(hashidx_count);
431 hashidx_ = hashidx_count;
432
433 refcount_modules_ = 0;
434 selection_stack.push_back(RTLIL::Selection());
435
436 #ifdef WITH_PYTHON
437 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
438 #endif
439 }
440
441 RTLIL::Design::~Design()
442 {
443 for (auto it = modules_.begin(); it != modules_.end(); ++it)
444 delete it->second;
445 for (auto n : verilog_packages)
446 delete n;
447 for (auto n : verilog_globals)
448 delete n;
449 #ifdef WITH_PYTHON
450 RTLIL::Design::get_all_designs()->erase(hashidx_);
451 #endif
452 }
453
454 #ifdef WITH_PYTHON
455 static std::map<unsigned int, RTLIL::Design*> all_designs;
456 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
457 {
458 return &all_designs;
459 }
460 #endif
461
462 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
463 {
464 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
465 }
466
467 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
468 {
469 return modules_.count(name) ? modules_.at(name) : NULL;
470 }
471
472 RTLIL::Module *RTLIL::Design::top_module()
473 {
474 RTLIL::Module *module = nullptr;
475 int module_count = 0;
476
477 for (auto mod : selected_modules()) {
478 if (mod->get_bool_attribute(ID::top))
479 return mod;
480 module_count++;
481 module = mod;
482 }
483
484 return module_count == 1 ? module : nullptr;
485 }
486
487 void RTLIL::Design::add(RTLIL::Module *module)
488 {
489 log_assert(modules_.count(module->name) == 0);
490 log_assert(refcount_modules_ == 0);
491 modules_[module->name] = module;
492 module->design = this;
493
494 for (auto mon : monitors)
495 mon->notify_module_add(module);
496
497 if (yosys_xtrace) {
498 log("#X# New Module: %s\n", log_id(module));
499 log_backtrace("-X- ", yosys_xtrace-1);
500 }
501 }
502
503 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
504 {
505 log_assert(modules_.count(name) == 0);
506 log_assert(refcount_modules_ == 0);
507
508 RTLIL::Module *module = new RTLIL::Module;
509 modules_[name] = module;
510 module->design = this;
511 module->name = name;
512
513 for (auto mon : monitors)
514 mon->notify_module_add(module);
515
516 if (yosys_xtrace) {
517 log("#X# New Module: %s\n", log_id(module));
518 log_backtrace("-X- ", yosys_xtrace-1);
519 }
520
521 return module;
522 }
523
524 void RTLIL::Design::scratchpad_unset(const std::string &varname)
525 {
526 scratchpad.erase(varname);
527 }
528
529 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
530 {
531 scratchpad[varname] = stringf("%d", value);
532 }
533
534 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
535 {
536 scratchpad[varname] = value ? "true" : "false";
537 }
538
539 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
540 {
541 scratchpad[varname] = std::move(value);
542 }
543
544 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
545 {
546 auto it = scratchpad.find(varname);
547 if (it == scratchpad.end())
548 return default_value;
549
550 const std::string &str = it->second;
551
552 if (str == "0" || str == "false")
553 return 0;
554
555 if (str == "1" || str == "true")
556 return 1;
557
558 char *endptr = nullptr;
559 long int parsed_value = strtol(str.c_str(), &endptr, 10);
560 return *endptr ? default_value : parsed_value;
561 }
562
563 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
564 {
565 auto it = scratchpad.find(varname);
566 if (it == scratchpad.end())
567 return default_value;
568
569 const std::string &str = it->second;
570
571 if (str == "0" || str == "false")
572 return false;
573
574 if (str == "1" || str == "true")
575 return true;
576
577 return default_value;
578 }
579
580 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
581 {
582 auto it = scratchpad.find(varname);
583 if (it == scratchpad.end())
584 return default_value;
585
586 return it->second;
587 }
588
589 void RTLIL::Design::remove(RTLIL::Module *module)
590 {
591 for (auto mon : monitors)
592 mon->notify_module_del(module);
593
594 if (yosys_xtrace) {
595 log("#X# Remove Module: %s\n", log_id(module));
596 log_backtrace("-X- ", yosys_xtrace-1);
597 }
598
599 log_assert(modules_.at(module->name) == module);
600 modules_.erase(module->name);
601 delete module;
602 }
603
604 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
605 {
606 modules_.erase(module->name);
607 module->name = new_name;
608 add(module);
609 }
610
611 void RTLIL::Design::sort()
612 {
613 scratchpad.sort();
614 modules_.sort(sort_by_id_str());
615 for (auto &it : modules_)
616 it.second->sort();
617 }
618
619 void RTLIL::Design::check()
620 {
621 #ifndef NDEBUG
622 for (auto &it : modules_) {
623 log_assert(this == it.second->design);
624 log_assert(it.first == it.second->name);
625 log_assert(!it.first.empty());
626 it.second->check();
627 }
628 #endif
629 }
630
631 void RTLIL::Design::optimize()
632 {
633 for (auto &it : modules_)
634 it.second->optimize();
635 for (auto &it : selection_stack)
636 it.optimize(this);
637 for (auto &it : selection_vars)
638 it.second.optimize(this);
639 }
640
641 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
642 {
643 if (!selected_active_module.empty() && mod_name != selected_active_module)
644 return false;
645 if (selection_stack.size() == 0)
646 return true;
647 return selection_stack.back().selected_module(mod_name);
648 }
649
650 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
651 {
652 if (!selected_active_module.empty() && mod_name != selected_active_module)
653 return false;
654 if (selection_stack.size() == 0)
655 return true;
656 return selection_stack.back().selected_whole_module(mod_name);
657 }
658
659 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
660 {
661 if (!selected_active_module.empty() && mod_name != selected_active_module)
662 return false;
663 if (selection_stack.size() == 0)
664 return true;
665 return selection_stack.back().selected_member(mod_name, memb_name);
666 }
667
668 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
669 {
670 return selected_module(mod->name);
671 }
672
673 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
674 {
675 return selected_whole_module(mod->name);
676 }
677
678 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
679 {
680 std::vector<RTLIL::Module*> result;
681 result.reserve(modules_.size());
682 for (auto &it : modules_)
683 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
684 result.push_back(it.second);
685 return result;
686 }
687
688 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
689 {
690 std::vector<RTLIL::Module*> result;
691 result.reserve(modules_.size());
692 for (auto &it : modules_)
693 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
694 result.push_back(it.second);
695 return result;
696 }
697
698 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
699 {
700 std::vector<RTLIL::Module*> result;
701 result.reserve(modules_.size());
702 for (auto &it : modules_)
703 if (it.second->get_blackbox_attribute())
704 continue;
705 else if (selected_whole_module(it.first))
706 result.push_back(it.second);
707 else if (selected_module(it.first))
708 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
709 return result;
710 }
711
712 RTLIL::Module::Module()
713 {
714 static unsigned int hashidx_count = 123456789;
715 hashidx_count = mkhash_xorshift(hashidx_count);
716 hashidx_ = hashidx_count;
717
718 design = nullptr;
719 refcount_wires_ = 0;
720 refcount_cells_ = 0;
721
722 #ifdef WITH_PYTHON
723 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
724 #endif
725 }
726
727 RTLIL::Module::~Module()
728 {
729 for (auto it = wires_.begin(); it != wires_.end(); ++it)
730 delete it->second;
731 for (auto it = memories.begin(); it != memories.end(); ++it)
732 delete it->second;
733 for (auto it = cells_.begin(); it != cells_.end(); ++it)
734 delete it->second;
735 for (auto it = processes.begin(); it != processes.end(); ++it)
736 delete it->second;
737 #ifdef WITH_PYTHON
738 RTLIL::Module::get_all_modules()->erase(hashidx_);
739 #endif
740 }
741
742 #ifdef WITH_PYTHON
743 static std::map<unsigned int, RTLIL::Module*> all_modules;
744 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
745 {
746 return &all_modules;
747 }
748 #endif
749
750 void RTLIL::Module::makeblackbox()
751 {
752 pool<RTLIL::Wire*> delwires;
753
754 for (auto it = wires_.begin(); it != wires_.end(); ++it)
755 if (!it->second->port_input && !it->second->port_output)
756 delwires.insert(it->second);
757
758 for (auto it = memories.begin(); it != memories.end(); ++it)
759 delete it->second;
760 memories.clear();
761
762 for (auto it = cells_.begin(); it != cells_.end(); ++it)
763 delete it->second;
764 cells_.clear();
765
766 for (auto it = processes.begin(); it != processes.end(); ++it)
767 delete it->second;
768 processes.clear();
769
770 connections_.clear();
771
772 remove(delwires);
773 set_bool_attribute(ID::blackbox);
774 }
775
776 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
777 {
778 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
779 }
780
781 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
782 {
783 if (mayfail)
784 return RTLIL::IdString();
785 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
786 }
787
788
789 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
790 {
791 if (mayfail)
792 return RTLIL::IdString();
793 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
794 }
795
796 size_t RTLIL::Module::count_id(RTLIL::IdString id)
797 {
798 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
799 }
800
801 #ifndef NDEBUG
802 namespace {
803 struct InternalCellChecker
804 {
805 RTLIL::Module *module;
806 RTLIL::Cell *cell;
807 pool<RTLIL::IdString> expected_params, expected_ports;
808
809 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
810
811 void error(int linenr)
812 {
813 std::stringstream buf;
814 ILANG_BACKEND::dump_cell(buf, " ", cell);
815
816 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
817 module ? module->name.c_str() : "", module ? "." : "",
818 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
819 }
820
821 int param(RTLIL::IdString name)
822 {
823 auto it = cell->parameters.find(name);
824 if (it == cell->parameters.end())
825 error(__LINE__);
826 expected_params.insert(name);
827 return it->second.as_int();
828 }
829
830 int param_bool(RTLIL::IdString name)
831 {
832 int v = param(name);
833 if (GetSize(cell->parameters.at(name)) > 32)
834 error(__LINE__);
835 if (v != 0 && v != 1)
836 error(__LINE__);
837 return v;
838 }
839
840 int param_bool(RTLIL::IdString name, bool expected)
841 {
842 int v = param_bool(name);
843 if (v != expected)
844 error(__LINE__);
845 return v;
846 }
847
848 void param_bits(RTLIL::IdString name, int width)
849 {
850 param(name);
851 if (GetSize(cell->parameters.at(name).bits) != width)
852 error(__LINE__);
853 }
854
855 void port(RTLIL::IdString name, int width)
856 {
857 auto it = cell->connections_.find(name);
858 if (it == cell->connections_.end())
859 error(__LINE__);
860 if (GetSize(it->second) != width)
861 error(__LINE__);
862 expected_ports.insert(name);
863 }
864
865 void check_expected(bool check_matched_sign = false)
866 {
867 for (auto &para : cell->parameters)
868 if (expected_params.count(para.first) == 0)
869 error(__LINE__);
870 for (auto &conn : cell->connections())
871 if (expected_ports.count(conn.first) == 0)
872 error(__LINE__);
873
874 if (check_matched_sign) {
875 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
876 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
877 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
878 if (a_is_signed != b_is_signed)
879 error(__LINE__);
880 }
881 }
882
883 void check()
884 {
885 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
886 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
887 return;
888
889 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
890 param_bool(ID::A_SIGNED);
891 port(ID::A, param(ID::A_WIDTH));
892 port(ID::Y, param(ID::Y_WIDTH));
893 check_expected();
894 return;
895 }
896
897 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
898 param_bool(ID::A_SIGNED);
899 param_bool(ID::B_SIGNED);
900 port(ID::A, param(ID::A_WIDTH));
901 port(ID::B, param(ID::B_WIDTH));
902 port(ID::Y, param(ID::Y_WIDTH));
903 check_expected(true);
904 return;
905 }
906
907 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
908 param_bool(ID::A_SIGNED);
909 port(ID::A, param(ID::A_WIDTH));
910 port(ID::Y, param(ID::Y_WIDTH));
911 check_expected();
912 return;
913 }
914
915 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
916 param_bool(ID::A_SIGNED);
917 param_bool(ID::B_SIGNED, /*expected=*/false);
918 port(ID::A, param(ID::A_WIDTH));
919 port(ID::B, param(ID::B_WIDTH));
920 port(ID::Y, param(ID::Y_WIDTH));
921 check_expected(/*check_matched_sign=*/false);
922 return;
923 }
924
925 if (cell->type.in(ID($shift), ID($shiftx))) {
926 param_bool(ID::A_SIGNED);
927 param_bool(ID::B_SIGNED);
928 port(ID::A, param(ID::A_WIDTH));
929 port(ID::B, param(ID::B_WIDTH));
930 port(ID::Y, param(ID::Y_WIDTH));
931 check_expected(/*check_matched_sign=*/false);
932 return;
933 }
934
935 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
936 param_bool(ID::A_SIGNED);
937 param_bool(ID::B_SIGNED);
938 port(ID::A, param(ID::A_WIDTH));
939 port(ID::B, param(ID::B_WIDTH));
940 port(ID::Y, param(ID::Y_WIDTH));
941 check_expected(true);
942 return;
943 }
944
945 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
946 param_bool(ID::A_SIGNED);
947 param_bool(ID::B_SIGNED);
948 port(ID::A, param(ID::A_WIDTH));
949 port(ID::B, param(ID::B_WIDTH));
950 port(ID::Y, param(ID::Y_WIDTH));
951 check_expected(cell->type != ID($pow));
952 return;
953 }
954
955 if (cell->type == ID($fa)) {
956 port(ID::A, param(ID::WIDTH));
957 port(ID::B, param(ID::WIDTH));
958 port(ID::C, param(ID::WIDTH));
959 port(ID::X, param(ID::WIDTH));
960 port(ID::Y, param(ID::WIDTH));
961 check_expected();
962 return;
963 }
964
965 if (cell->type == ID($lcu)) {
966 port(ID::P, param(ID::WIDTH));
967 port(ID::G, param(ID::WIDTH));
968 port(ID::CI, 1);
969 port(ID::CO, param(ID::WIDTH));
970 check_expected();
971 return;
972 }
973
974 if (cell->type == ID($alu)) {
975 param_bool(ID::A_SIGNED);
976 param_bool(ID::B_SIGNED);
977 port(ID::A, param(ID::A_WIDTH));
978 port(ID::B, param(ID::B_WIDTH));
979 port(ID::CI, 1);
980 port(ID::BI, 1);
981 port(ID::X, param(ID::Y_WIDTH));
982 port(ID::Y, param(ID::Y_WIDTH));
983 port(ID::CO, param(ID::Y_WIDTH));
984 check_expected(true);
985 return;
986 }
987
988 if (cell->type == ID($macc)) {
989 param(ID::CONFIG);
990 param(ID::CONFIG_WIDTH);
991 port(ID::A, param(ID::A_WIDTH));
992 port(ID::B, param(ID::B_WIDTH));
993 port(ID::Y, param(ID::Y_WIDTH));
994 check_expected();
995 Macc().from_cell(cell);
996 return;
997 }
998
999 if (cell->type == ID($logic_not)) {
1000 param_bool(ID::A_SIGNED);
1001 port(ID::A, param(ID::A_WIDTH));
1002 port(ID::Y, param(ID::Y_WIDTH));
1003 check_expected();
1004 return;
1005 }
1006
1007 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1008 param_bool(ID::A_SIGNED);
1009 param_bool(ID::B_SIGNED);
1010 port(ID::A, param(ID::A_WIDTH));
1011 port(ID::B, param(ID::B_WIDTH));
1012 port(ID::Y, param(ID::Y_WIDTH));
1013 check_expected(/*check_matched_sign=*/false);
1014 return;
1015 }
1016
1017 if (cell->type == ID($slice)) {
1018 param(ID::OFFSET);
1019 port(ID::A, param(ID::A_WIDTH));
1020 port(ID::Y, param(ID::Y_WIDTH));
1021 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1022 error(__LINE__);
1023 check_expected();
1024 return;
1025 }
1026
1027 if (cell->type == ID($concat)) {
1028 port(ID::A, param(ID::A_WIDTH));
1029 port(ID::B, param(ID::B_WIDTH));
1030 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1031 check_expected();
1032 return;
1033 }
1034
1035 if (cell->type == ID($mux)) {
1036 port(ID::A, param(ID::WIDTH));
1037 port(ID::B, param(ID::WIDTH));
1038 port(ID::S, 1);
1039 port(ID::Y, param(ID::WIDTH));
1040 check_expected();
1041 return;
1042 }
1043
1044 if (cell->type == ID($pmux)) {
1045 port(ID::A, param(ID::WIDTH));
1046 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1047 port(ID::S, param(ID::S_WIDTH));
1048 port(ID::Y, param(ID::WIDTH));
1049 check_expected();
1050 return;
1051 }
1052
1053 if (cell->type == ID($lut)) {
1054 param(ID::LUT);
1055 port(ID::A, param(ID::WIDTH));
1056 port(ID::Y, 1);
1057 check_expected();
1058 return;
1059 }
1060
1061 if (cell->type == ID($sop)) {
1062 param(ID::DEPTH);
1063 param(ID::TABLE);
1064 port(ID::A, param(ID::WIDTH));
1065 port(ID::Y, 1);
1066 check_expected();
1067 return;
1068 }
1069
1070 if (cell->type == ID($sr)) {
1071 param_bool(ID::SET_POLARITY);
1072 param_bool(ID::CLR_POLARITY);
1073 port(ID::SET, param(ID::WIDTH));
1074 port(ID::CLR, param(ID::WIDTH));
1075 port(ID::Q, param(ID::WIDTH));
1076 check_expected();
1077 return;
1078 }
1079
1080 if (cell->type == ID($ff)) {
1081 port(ID::D, param(ID::WIDTH));
1082 port(ID::Q, param(ID::WIDTH));
1083 check_expected();
1084 return;
1085 }
1086
1087 if (cell->type == ID($dff)) {
1088 param_bool(ID::CLK_POLARITY);
1089 port(ID::CLK, 1);
1090 port(ID::D, param(ID::WIDTH));
1091 port(ID::Q, param(ID::WIDTH));
1092 check_expected();
1093 return;
1094 }
1095
1096 if (cell->type == ID($dffe)) {
1097 param_bool(ID::CLK_POLARITY);
1098 param_bool(ID::EN_POLARITY);
1099 port(ID::CLK, 1);
1100 port(ID::EN, 1);
1101 port(ID::D, param(ID::WIDTH));
1102 port(ID::Q, param(ID::WIDTH));
1103 check_expected();
1104 return;
1105 }
1106
1107 if (cell->type == ID($dffsr)) {
1108 param_bool(ID::CLK_POLARITY);
1109 param_bool(ID::SET_POLARITY);
1110 param_bool(ID::CLR_POLARITY);
1111 port(ID::CLK, 1);
1112 port(ID::SET, param(ID::WIDTH));
1113 port(ID::CLR, param(ID::WIDTH));
1114 port(ID::D, param(ID::WIDTH));
1115 port(ID::Q, param(ID::WIDTH));
1116 check_expected();
1117 return;
1118 }
1119
1120 if (cell->type == ID($adff)) {
1121 param_bool(ID::CLK_POLARITY);
1122 param_bool(ID::ARST_POLARITY);
1123 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1124 port(ID::CLK, 1);
1125 port(ID::ARST, 1);
1126 port(ID::D, param(ID::WIDTH));
1127 port(ID::Q, param(ID::WIDTH));
1128 check_expected();
1129 return;
1130 }
1131
1132 if (cell->type == ID($dlatch)) {
1133 param_bool(ID::EN_POLARITY);
1134 port(ID::EN, 1);
1135 port(ID::D, param(ID::WIDTH));
1136 port(ID::Q, param(ID::WIDTH));
1137 check_expected();
1138 return;
1139 }
1140
1141 if (cell->type == ID($dlatchsr)) {
1142 param_bool(ID::EN_POLARITY);
1143 param_bool(ID::SET_POLARITY);
1144 param_bool(ID::CLR_POLARITY);
1145 port(ID::EN, 1);
1146 port(ID::SET, param(ID::WIDTH));
1147 port(ID::CLR, param(ID::WIDTH));
1148 port(ID::D, param(ID::WIDTH));
1149 port(ID::Q, param(ID::WIDTH));
1150 check_expected();
1151 return;
1152 }
1153
1154 if (cell->type == ID($fsm)) {
1155 param(ID::NAME);
1156 param_bool(ID::CLK_POLARITY);
1157 param_bool(ID::ARST_POLARITY);
1158 param(ID::STATE_BITS);
1159 param(ID::STATE_NUM);
1160 param(ID::STATE_NUM_LOG2);
1161 param(ID::STATE_RST);
1162 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1163 param(ID::TRANS_NUM);
1164 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1165 port(ID::CLK, 1);
1166 port(ID::ARST, 1);
1167 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1168 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1169 check_expected();
1170 return;
1171 }
1172
1173 if (cell->type == ID($memrd)) {
1174 param(ID::MEMID);
1175 param_bool(ID::CLK_ENABLE);
1176 param_bool(ID::CLK_POLARITY);
1177 param_bool(ID::TRANSPARENT);
1178 port(ID::CLK, 1);
1179 port(ID::EN, 1);
1180 port(ID::ADDR, param(ID::ABITS));
1181 port(ID::DATA, param(ID::WIDTH));
1182 check_expected();
1183 return;
1184 }
1185
1186 if (cell->type == ID($memwr)) {
1187 param(ID::MEMID);
1188 param_bool(ID::CLK_ENABLE);
1189 param_bool(ID::CLK_POLARITY);
1190 param(ID::PRIORITY);
1191 port(ID::CLK, 1);
1192 port(ID::EN, param(ID::WIDTH));
1193 port(ID::ADDR, param(ID::ABITS));
1194 port(ID::DATA, param(ID::WIDTH));
1195 check_expected();
1196 return;
1197 }
1198
1199 if (cell->type == ID($meminit)) {
1200 param(ID::MEMID);
1201 param(ID::PRIORITY);
1202 port(ID::ADDR, param(ID::ABITS));
1203 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1204 check_expected();
1205 return;
1206 }
1207
1208 if (cell->type == ID($mem)) {
1209 param(ID::MEMID);
1210 param(ID::SIZE);
1211 param(ID::OFFSET);
1212 param(ID::INIT);
1213 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1214 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1215 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1216 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1217 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1218 port(ID::RD_CLK, param(ID::RD_PORTS));
1219 port(ID::RD_EN, param(ID::RD_PORTS));
1220 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1221 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1222 port(ID::WR_CLK, param(ID::WR_PORTS));
1223 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1224 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1225 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1226 check_expected();
1227 return;
1228 }
1229
1230 if (cell->type == ID($tribuf)) {
1231 port(ID::A, param(ID::WIDTH));
1232 port(ID::Y, param(ID::WIDTH));
1233 port(ID::EN, 1);
1234 check_expected();
1235 return;
1236 }
1237
1238 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1239 port(ID::A, 1);
1240 port(ID::EN, 1);
1241 check_expected();
1242 return;
1243 }
1244
1245 if (cell->type == ID($initstate)) {
1246 port(ID::Y, 1);
1247 check_expected();
1248 return;
1249 }
1250
1251 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1252 port(ID::Y, param(ID::WIDTH));
1253 check_expected();
1254 return;
1255 }
1256
1257 if (cell->type == ID($equiv)) {
1258 port(ID::A, 1);
1259 port(ID::B, 1);
1260 port(ID::Y, 1);
1261 check_expected();
1262 return;
1263 }
1264
1265 if (cell->type.in(ID($specify2), ID($specify3))) {
1266 param_bool(ID::FULL);
1267 param_bool(ID::SRC_DST_PEN);
1268 param_bool(ID::SRC_DST_POL);
1269 param(ID::T_RISE_MIN);
1270 param(ID::T_RISE_TYP);
1271 param(ID::T_RISE_MAX);
1272 param(ID::T_FALL_MIN);
1273 param(ID::T_FALL_TYP);
1274 param(ID::T_FALL_MAX);
1275 port(ID::EN, 1);
1276 port(ID::SRC, param(ID::SRC_WIDTH));
1277 port(ID::DST, param(ID::DST_WIDTH));
1278 if (cell->type == ID($specify3)) {
1279 param_bool(ID::EDGE_EN);
1280 param_bool(ID::EDGE_POL);
1281 param_bool(ID::DAT_DST_PEN);
1282 param_bool(ID::DAT_DST_POL);
1283 port(ID::DAT, param(ID::DST_WIDTH));
1284 }
1285 check_expected();
1286 return;
1287 }
1288
1289 if (cell->type == ID($specrule)) {
1290 param(ID::TYPE);
1291 param_bool(ID::SRC_PEN);
1292 param_bool(ID::SRC_POL);
1293 param_bool(ID::DST_PEN);
1294 param_bool(ID::DST_POL);
1295 param(ID::T_LIMIT_MIN);
1296 param(ID::T_LIMIT_TYP);
1297 param(ID::T_LIMIT_MAX);
1298 param(ID::T_LIMIT2_MIN);
1299 param(ID::T_LIMIT2_TYP);
1300 param(ID::T_LIMIT2_MAX);
1301 port(ID::SRC_EN, 1);
1302 port(ID::DST_EN, 1);
1303 port(ID::SRC, param(ID::SRC_WIDTH));
1304 port(ID::DST, param(ID::DST_WIDTH));
1305 check_expected();
1306 return;
1307 }
1308
1309 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1310 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1311 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1312 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1313 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1314 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1315 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1316 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1317 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1318 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1319 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1320 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1321 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1322 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1323 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1324 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1325
1326 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1327
1328 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1329 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1330 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1331
1332 if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1333 if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1334 if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1335 if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1336
1337 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1338 if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1339 if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1340
1341 if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1342 if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1343 if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1344 if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1345
1346 if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1347 if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1348 if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1349 if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1350 if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1351 if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1352 if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1353 if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1354
1355 if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1356 if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1357 if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1358 if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1359 if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1360 if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1361 if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1362 if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1363
1364 if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1365 if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1366
1367 if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1368 if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1369 if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1370 if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1371 if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1372 if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1373 if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1374 if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1375
1376 error(__LINE__);
1377 }
1378 };
1379 }
1380 #endif
1381
1382 void RTLIL::Module::sort()
1383 {
1384 wires_.sort(sort_by_id_str());
1385 cells_.sort(sort_by_id_str());
1386 avail_parameters.sort(sort_by_id_str());
1387 memories.sort(sort_by_id_str());
1388 processes.sort(sort_by_id_str());
1389 for (auto &it : cells_)
1390 it.second->sort();
1391 for (auto &it : wires_)
1392 it.second->attributes.sort(sort_by_id_str());
1393 for (auto &it : memories)
1394 it.second->attributes.sort(sort_by_id_str());
1395 }
1396
1397 void RTLIL::Module::check()
1398 {
1399 #ifndef NDEBUG
1400 std::vector<bool> ports_declared;
1401 for (auto &it : wires_) {
1402 log_assert(this == it.second->module);
1403 log_assert(it.first == it.second->name);
1404 log_assert(!it.first.empty());
1405 log_assert(it.second->width >= 0);
1406 log_assert(it.second->port_id >= 0);
1407 for (auto &it2 : it.second->attributes)
1408 log_assert(!it2.first.empty());
1409 if (it.second->port_id) {
1410 log_assert(GetSize(ports) >= it.second->port_id);
1411 log_assert(ports.at(it.second->port_id-1) == it.first);
1412 log_assert(it.second->port_input || it.second->port_output);
1413 if (GetSize(ports_declared) < it.second->port_id)
1414 ports_declared.resize(it.second->port_id);
1415 log_assert(ports_declared[it.second->port_id-1] == false);
1416 ports_declared[it.second->port_id-1] = true;
1417 } else
1418 log_assert(!it.second->port_input && !it.second->port_output);
1419 }
1420 for (auto port_declared : ports_declared)
1421 log_assert(port_declared == true);
1422 log_assert(GetSize(ports) == GetSize(ports_declared));
1423
1424 for (auto &it : memories) {
1425 log_assert(it.first == it.second->name);
1426 log_assert(!it.first.empty());
1427 log_assert(it.second->width >= 0);
1428 log_assert(it.second->size >= 0);
1429 for (auto &it2 : it.second->attributes)
1430 log_assert(!it2.first.empty());
1431 }
1432
1433 for (auto &it : cells_) {
1434 log_assert(this == it.second->module);
1435 log_assert(it.first == it.second->name);
1436 log_assert(!it.first.empty());
1437 log_assert(!it.second->type.empty());
1438 for (auto &it2 : it.second->connections()) {
1439 log_assert(!it2.first.empty());
1440 it2.second.check();
1441 }
1442 for (auto &it2 : it.second->attributes)
1443 log_assert(!it2.first.empty());
1444 for (auto &it2 : it.second->parameters)
1445 log_assert(!it2.first.empty());
1446 InternalCellChecker checker(this, it.second);
1447 checker.check();
1448 }
1449
1450 for (auto &it : processes) {
1451 log_assert(it.first == it.second->name);
1452 log_assert(!it.first.empty());
1453 log_assert(it.second->root_case.compare.empty());
1454 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1455 for (size_t i = 0; i < all_cases.size(); i++) {
1456 for (auto &switch_it : all_cases[i]->switches) {
1457 for (auto &case_it : switch_it->cases) {
1458 for (auto &compare_it : case_it->compare) {
1459 log_assert(switch_it->signal.size() == compare_it.size());
1460 }
1461 all_cases.push_back(case_it);
1462 }
1463 }
1464 }
1465 for (auto &sync_it : it.second->syncs) {
1466 switch (sync_it->type) {
1467 case SyncType::ST0:
1468 case SyncType::ST1:
1469 case SyncType::STp:
1470 case SyncType::STn:
1471 case SyncType::STe:
1472 log_assert(!sync_it->signal.empty());
1473 break;
1474 case SyncType::STa:
1475 case SyncType::STg:
1476 case SyncType::STi:
1477 log_assert(sync_it->signal.empty());
1478 break;
1479 }
1480 }
1481 }
1482
1483 for (auto &it : connections_) {
1484 log_assert(it.first.size() == it.second.size());
1485 log_assert(!it.first.has_const());
1486 it.first.check();
1487 it.second.check();
1488 }
1489
1490 for (auto &it : attributes)
1491 log_assert(!it.first.empty());
1492 #endif
1493 }
1494
1495 void RTLIL::Module::optimize()
1496 {
1497 }
1498
1499 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1500 {
1501 log_assert(new_mod->refcount_wires_ == 0);
1502 log_assert(new_mod->refcount_cells_ == 0);
1503
1504 new_mod->avail_parameters = avail_parameters;
1505
1506 for (auto &conn : connections_)
1507 new_mod->connect(conn);
1508
1509 for (auto &attr : attributes)
1510 new_mod->attributes[attr.first] = attr.second;
1511
1512 for (auto &it : wires_)
1513 new_mod->addWire(it.first, it.second);
1514
1515 for (auto &it : memories)
1516 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1517
1518 for (auto &it : cells_)
1519 new_mod->addCell(it.first, it.second);
1520
1521 for (auto &it : processes)
1522 new_mod->processes[it.first] = it.second->clone();
1523
1524 struct RewriteSigSpecWorker
1525 {
1526 RTLIL::Module *mod;
1527 void operator()(RTLIL::SigSpec &sig)
1528 {
1529 sig.pack();
1530 for (auto &c : sig.chunks_)
1531 if (c.wire != NULL)
1532 c.wire = mod->wires_.at(c.wire->name);
1533 }
1534 };
1535
1536 RewriteSigSpecWorker rewriteSigSpecWorker;
1537 rewriteSigSpecWorker.mod = new_mod;
1538 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1539 new_mod->fixup_ports();
1540 }
1541
1542 RTLIL::Module *RTLIL::Module::clone() const
1543 {
1544 RTLIL::Module *new_mod = new RTLIL::Module;
1545 new_mod->name = name;
1546 cloneInto(new_mod);
1547 return new_mod;
1548 }
1549
1550 bool RTLIL::Module::has_memories() const
1551 {
1552 return !memories.empty();
1553 }
1554
1555 bool RTLIL::Module::has_processes() const
1556 {
1557 return !processes.empty();
1558 }
1559
1560 bool RTLIL::Module::has_memories_warn() const
1561 {
1562 if (!memories.empty())
1563 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1564 return !memories.empty();
1565 }
1566
1567 bool RTLIL::Module::has_processes_warn() const
1568 {
1569 if (!processes.empty())
1570 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1571 return !processes.empty();
1572 }
1573
1574 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1575 {
1576 std::vector<RTLIL::Wire*> result;
1577 result.reserve(wires_.size());
1578 for (auto &it : wires_)
1579 if (design->selected(this, it.second))
1580 result.push_back(it.second);
1581 return result;
1582 }
1583
1584 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1585 {
1586 std::vector<RTLIL::Cell*> result;
1587 result.reserve(cells_.size());
1588 for (auto &it : cells_)
1589 if (design->selected(this, it.second))
1590 result.push_back(it.second);
1591 return result;
1592 }
1593
1594 void RTLIL::Module::add(RTLIL::Wire *wire)
1595 {
1596 log_assert(!wire->name.empty());
1597 log_assert(count_id(wire->name) == 0);
1598 log_assert(refcount_wires_ == 0);
1599 wires_[wire->name] = wire;
1600 wire->module = this;
1601 }
1602
1603 void RTLIL::Module::add(RTLIL::Cell *cell)
1604 {
1605 log_assert(!cell->name.empty());
1606 log_assert(count_id(cell->name) == 0);
1607 log_assert(refcount_cells_ == 0);
1608 cells_[cell->name] = cell;
1609 cell->module = this;
1610 }
1611
1612 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1613 {
1614 log_assert(refcount_wires_ == 0);
1615
1616 struct DeleteWireWorker
1617 {
1618 RTLIL::Module *module;
1619 const pool<RTLIL::Wire*> *wires_p;
1620
1621 void operator()(RTLIL::SigSpec &sig) {
1622 sig.pack();
1623 for (auto &c : sig.chunks_)
1624 if (c.wire != NULL && wires_p->count(c.wire)) {
1625 c.wire = module->addWire(NEW_ID, c.width);
1626 c.offset = 0;
1627 }
1628 }
1629
1630 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1631 log_assert(GetSize(lhs) == GetSize(rhs));
1632 lhs.unpack();
1633 rhs.unpack();
1634 for (int i = 0; i < GetSize(lhs); i++) {
1635 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1636 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1637 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1638 lhs_bit = State::Sx;
1639 rhs_bit = State::Sx;
1640 }
1641 }
1642 }
1643 };
1644
1645 DeleteWireWorker delete_wire_worker;
1646 delete_wire_worker.module = this;
1647 delete_wire_worker.wires_p = &wires;
1648 rewrite_sigspecs2(delete_wire_worker);
1649
1650 for (auto &it : wires) {
1651 log_assert(wires_.count(it->name) != 0);
1652 wires_.erase(it->name);
1653 delete it;
1654 }
1655 }
1656
1657 void RTLIL::Module::remove(RTLIL::Cell *cell)
1658 {
1659 while (!cell->connections_.empty())
1660 cell->unsetPort(cell->connections_.begin()->first);
1661
1662 log_assert(cells_.count(cell->name) != 0);
1663 log_assert(refcount_cells_ == 0);
1664 cells_.erase(cell->name);
1665 delete cell;
1666 }
1667
1668 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1669 {
1670 log_assert(wires_[wire->name] == wire);
1671 log_assert(refcount_wires_ == 0);
1672 wires_.erase(wire->name);
1673 wire->name = new_name;
1674 add(wire);
1675 }
1676
1677 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1678 {
1679 log_assert(cells_[cell->name] == cell);
1680 log_assert(refcount_wires_ == 0);
1681 cells_.erase(cell->name);
1682 cell->name = new_name;
1683 add(cell);
1684 }
1685
1686 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1687 {
1688 log_assert(count_id(old_name) != 0);
1689 if (wires_.count(old_name))
1690 rename(wires_.at(old_name), new_name);
1691 else if (cells_.count(old_name))
1692 rename(cells_.at(old_name), new_name);
1693 else
1694 log_abort();
1695 }
1696
1697 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1698 {
1699 log_assert(wires_[w1->name] == w1);
1700 log_assert(wires_[w2->name] == w2);
1701 log_assert(refcount_wires_ == 0);
1702
1703 wires_.erase(w1->name);
1704 wires_.erase(w2->name);
1705
1706 std::swap(w1->name, w2->name);
1707
1708 wires_[w1->name] = w1;
1709 wires_[w2->name] = w2;
1710 }
1711
1712 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1713 {
1714 log_assert(cells_[c1->name] == c1);
1715 log_assert(cells_[c2->name] == c2);
1716 log_assert(refcount_cells_ == 0);
1717
1718 cells_.erase(c1->name);
1719 cells_.erase(c2->name);
1720
1721 std::swap(c1->name, c2->name);
1722
1723 cells_[c1->name] = c1;
1724 cells_[c2->name] = c2;
1725 }
1726
1727 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1728 {
1729 int index = 0;
1730 return uniquify(name, index);
1731 }
1732
1733 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1734 {
1735 if (index == 0) {
1736 if (count_id(name) == 0)
1737 return name;
1738 index++;
1739 }
1740
1741 while (1) {
1742 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1743 if (count_id(new_name) == 0)
1744 return new_name;
1745 index++;
1746 }
1747 }
1748
1749 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1750 {
1751 if (a->port_id && !b->port_id)
1752 return true;
1753 if (!a->port_id && b->port_id)
1754 return false;
1755
1756 if (a->port_id == b->port_id)
1757 return a->name < b->name;
1758 return a->port_id < b->port_id;
1759 }
1760
1761 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1762 {
1763 for (auto mon : monitors)
1764 mon->notify_connect(this, conn);
1765
1766 if (design)
1767 for (auto mon : design->monitors)
1768 mon->notify_connect(this, conn);
1769
1770 // ignore all attempts to assign constants to other constants
1771 if (conn.first.has_const()) {
1772 RTLIL::SigSig new_conn;
1773 for (int i = 0; i < GetSize(conn.first); i++)
1774 if (conn.first[i].wire) {
1775 new_conn.first.append(conn.first[i]);
1776 new_conn.second.append(conn.second[i]);
1777 }
1778 if (GetSize(new_conn.first))
1779 connect(new_conn);
1780 return;
1781 }
1782
1783 if (yosys_xtrace) {
1784 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1785 log_backtrace("-X- ", yosys_xtrace-1);
1786 }
1787
1788 log_assert(GetSize(conn.first) == GetSize(conn.second));
1789 connections_.push_back(conn);
1790 }
1791
1792 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1793 {
1794 connect(RTLIL::SigSig(lhs, rhs));
1795 }
1796
1797 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1798 {
1799 for (auto mon : monitors)
1800 mon->notify_connect(this, new_conn);
1801
1802 if (design)
1803 for (auto mon : design->monitors)
1804 mon->notify_connect(this, new_conn);
1805
1806 if (yosys_xtrace) {
1807 log("#X# New connections vector in %s:\n", log_id(this));
1808 for (auto &conn: new_conn)
1809 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1810 log_backtrace("-X- ", yosys_xtrace-1);
1811 }
1812
1813 connections_ = new_conn;
1814 }
1815
1816 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1817 {
1818 return connections_;
1819 }
1820
1821 void RTLIL::Module::fixup_ports()
1822 {
1823 std::vector<RTLIL::Wire*> all_ports;
1824
1825 for (auto &w : wires_)
1826 if (w.second->port_input || w.second->port_output)
1827 all_ports.push_back(w.second);
1828 else
1829 w.second->port_id = 0;
1830
1831 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1832
1833 ports.clear();
1834 for (size_t i = 0; i < all_ports.size(); i++) {
1835 ports.push_back(all_ports[i]->name);
1836 all_ports[i]->port_id = i+1;
1837 }
1838 }
1839
1840 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1841 {
1842 RTLIL::Wire *wire = new RTLIL::Wire;
1843 wire->name = name;
1844 wire->width = width;
1845 add(wire);
1846 return wire;
1847 }
1848
1849 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1850 {
1851 RTLIL::Wire *wire = addWire(name);
1852 wire->width = other->width;
1853 wire->start_offset = other->start_offset;
1854 wire->port_id = other->port_id;
1855 wire->port_input = other->port_input;
1856 wire->port_output = other->port_output;
1857 wire->upto = other->upto;
1858 wire->attributes = other->attributes;
1859 return wire;
1860 }
1861
1862 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1863 {
1864 RTLIL::Cell *cell = new RTLIL::Cell;
1865 cell->name = name;
1866 cell->type = type;
1867 add(cell);
1868 return cell;
1869 }
1870
1871 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1872 {
1873 RTLIL::Cell *cell = addCell(name, other->type);
1874 cell->connections_ = other->connections_;
1875 cell->parameters = other->parameters;
1876 cell->attributes = other->attributes;
1877 return cell;
1878 }
1879
1880 #define DEF_METHOD(_func, _y_size, _type) \
1881 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1882 RTLIL::Cell *cell = addCell(name, _type); \
1883 cell->parameters[ID::A_SIGNED] = is_signed; \
1884 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1885 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1886 cell->setPort(ID::A, sig_a); \
1887 cell->setPort(ID::Y, sig_y); \
1888 cell->set_src_attribute(src); \
1889 return cell; \
1890 } \
1891 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1892 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1893 add ## _func(name, sig_a, sig_y, is_signed, src); \
1894 return sig_y; \
1895 }
1896 DEF_METHOD(Not, sig_a.size(), ID($not))
1897 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1898 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1899 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1900 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1901 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1902 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1903 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1904 DEF_METHOD(LogicNot, 1, ID($logic_not))
1905 #undef DEF_METHOD
1906
1907 #define DEF_METHOD(_func, _y_size, _type) \
1908 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1909 RTLIL::Cell *cell = addCell(name, _type); \
1910 cell->parameters[ID::A_SIGNED] = is_signed; \
1911 cell->parameters[ID::B_SIGNED] = is_signed; \
1912 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1913 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1914 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1915 cell->setPort(ID::A, sig_a); \
1916 cell->setPort(ID::B, sig_b); \
1917 cell->setPort(ID::Y, sig_y); \
1918 cell->set_src_attribute(src); \
1919 return cell; \
1920 } \
1921 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1922 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1923 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1924 return sig_y; \
1925 }
1926 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1927 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1928 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1929 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1930 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1931 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1932 DEF_METHOD(Lt, 1, ID($lt))
1933 DEF_METHOD(Le, 1, ID($le))
1934 DEF_METHOD(Eq, 1, ID($eq))
1935 DEF_METHOD(Ne, 1, ID($ne))
1936 DEF_METHOD(Eqx, 1, ID($eqx))
1937 DEF_METHOD(Nex, 1, ID($nex))
1938 DEF_METHOD(Ge, 1, ID($ge))
1939 DEF_METHOD(Gt, 1, ID($gt))
1940 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1941 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1942 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1943 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1944 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1945 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1946 DEF_METHOD(LogicOr, 1, ID($logic_or))
1947 #undef DEF_METHOD
1948
1949 #define DEF_METHOD(_func, _y_size, _type) \
1950 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1951 RTLIL::Cell *cell = addCell(name, _type); \
1952 cell->parameters[ID::A_SIGNED] = is_signed; \
1953 cell->parameters[ID::B_SIGNED] = false; \
1954 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1955 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1956 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1957 cell->setPort(ID::A, sig_a); \
1958 cell->setPort(ID::B, sig_b); \
1959 cell->setPort(ID::Y, sig_y); \
1960 cell->set_src_attribute(src); \
1961 return cell; \
1962 } \
1963 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1964 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1965 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1966 return sig_y; \
1967 }
1968 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1969 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1970 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1971 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1972 #undef DEF_METHOD
1973
1974 #define DEF_METHOD(_func, _type, _pmux) \
1975 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1976 RTLIL::Cell *cell = addCell(name, _type); \
1977 cell->parameters[ID::WIDTH] = sig_a.size(); \
1978 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1979 cell->setPort(ID::A, sig_a); \
1980 cell->setPort(ID::B, sig_b); \
1981 cell->setPort(ID::S, sig_s); \
1982 cell->setPort(ID::Y, sig_y); \
1983 cell->set_src_attribute(src); \
1984 return cell; \
1985 } \
1986 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1987 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1988 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1989 return sig_y; \
1990 }
1991 DEF_METHOD(Mux, ID($mux), 0)
1992 DEF_METHOD(Pmux, ID($pmux), 1)
1993 #undef DEF_METHOD
1994
1995 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1996 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1997 RTLIL::Cell *cell = addCell(name, _type); \
1998 cell->setPort("\\" #_P1, sig1); \
1999 cell->setPort("\\" #_P2, sig2); \
2000 cell->set_src_attribute(src); \
2001 return cell; \
2002 } \
2003 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2004 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2005 add ## _func(name, sig1, sig2, src); \
2006 return sig2; \
2007 }
2008 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2009 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2010 RTLIL::Cell *cell = addCell(name, _type); \
2011 cell->setPort("\\" #_P1, sig1); \
2012 cell->setPort("\\" #_P2, sig2); \
2013 cell->setPort("\\" #_P3, sig3); \
2014 cell->set_src_attribute(src); \
2015 return cell; \
2016 } \
2017 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2018 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2019 add ## _func(name, sig1, sig2, sig3, src); \
2020 return sig3; \
2021 }
2022 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2023 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2024 RTLIL::Cell *cell = addCell(name, _type); \
2025 cell->setPort("\\" #_P1, sig1); \
2026 cell->setPort("\\" #_P2, sig2); \
2027 cell->setPort("\\" #_P3, sig3); \
2028 cell->setPort("\\" #_P4, sig4); \
2029 cell->set_src_attribute(src); \
2030 return cell; \
2031 } \
2032 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2033 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2034 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2035 return sig4; \
2036 }
2037 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2038 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2039 RTLIL::Cell *cell = addCell(name, _type); \
2040 cell->setPort("\\" #_P1, sig1); \
2041 cell->setPort("\\" #_P2, sig2); \
2042 cell->setPort("\\" #_P3, sig3); \
2043 cell->setPort("\\" #_P4, sig4); \
2044 cell->setPort("\\" #_P5, sig5); \
2045 cell->set_src_attribute(src); \
2046 return cell; \
2047 } \
2048 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2049 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2050 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2051 return sig5; \
2052 }
2053 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2054 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2055 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2056 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2057 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2058 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2059 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2060 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2061 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2062 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2063 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2064 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2065 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2066 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2067 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2068 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2069 #undef DEF_METHOD_2
2070 #undef DEF_METHOD_3
2071 #undef DEF_METHOD_4
2072 #undef DEF_METHOD_5
2073
2074 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2075 {
2076 RTLIL::Cell *cell = addCell(name, ID($pow));
2077 cell->parameters[ID::A_SIGNED] = a_signed;
2078 cell->parameters[ID::B_SIGNED] = b_signed;
2079 cell->parameters[ID::A_WIDTH] = sig_a.size();
2080 cell->parameters[ID::B_WIDTH] = sig_b.size();
2081 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2082 cell->setPort(ID::A, sig_a);
2083 cell->setPort(ID::B, sig_b);
2084 cell->setPort(ID::Y, sig_y);
2085 cell->set_src_attribute(src);
2086 return cell;
2087 }
2088
2089 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2090 {
2091 RTLIL::Cell *cell = addCell(name, ID($slice));
2092 cell->parameters[ID::A_WIDTH] = sig_a.size();
2093 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2094 cell->parameters[ID::OFFSET] = offset;
2095 cell->setPort(ID::A, sig_a);
2096 cell->setPort(ID::Y, sig_y);
2097 cell->set_src_attribute(src);
2098 return cell;
2099 }
2100
2101 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2102 {
2103 RTLIL::Cell *cell = addCell(name, ID($concat));
2104 cell->parameters[ID::A_WIDTH] = sig_a.size();
2105 cell->parameters[ID::B_WIDTH] = sig_b.size();
2106 cell->setPort(ID::A, sig_a);
2107 cell->setPort(ID::B, sig_b);
2108 cell->setPort(ID::Y, sig_y);
2109 cell->set_src_attribute(src);
2110 return cell;
2111 }
2112
2113 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2114 {
2115 RTLIL::Cell *cell = addCell(name, ID($lut));
2116 cell->parameters[ID::LUT] = lut;
2117 cell->parameters[ID::WIDTH] = sig_a.size();
2118 cell->setPort(ID::A, sig_a);
2119 cell->setPort(ID::Y, sig_y);
2120 cell->set_src_attribute(src);
2121 return cell;
2122 }
2123
2124 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2125 {
2126 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2127 cell->parameters[ID::WIDTH] = sig_a.size();
2128 cell->setPort(ID::A, sig_a);
2129 cell->setPort(ID::EN, sig_en);
2130 cell->setPort(ID::Y, sig_y);
2131 cell->set_src_attribute(src);
2132 return cell;
2133 }
2134
2135 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2136 {
2137 RTLIL::Cell *cell = addCell(name, ID($assert));
2138 cell->setPort(ID::A, sig_a);
2139 cell->setPort(ID::EN, sig_en);
2140 cell->set_src_attribute(src);
2141 return cell;
2142 }
2143
2144 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2145 {
2146 RTLIL::Cell *cell = addCell(name, ID($assume));
2147 cell->setPort(ID::A, sig_a);
2148 cell->setPort(ID::EN, sig_en);
2149 cell->set_src_attribute(src);
2150 return cell;
2151 }
2152
2153 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2154 {
2155 RTLIL::Cell *cell = addCell(name, ID($live));
2156 cell->setPort(ID::A, sig_a);
2157 cell->setPort(ID::EN, sig_en);
2158 cell->set_src_attribute(src);
2159 return cell;
2160 }
2161
2162 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2163 {
2164 RTLIL::Cell *cell = addCell(name, ID($fair));
2165 cell->setPort(ID::A, sig_a);
2166 cell->setPort(ID::EN, sig_en);
2167 cell->set_src_attribute(src);
2168 return cell;
2169 }
2170
2171 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2172 {
2173 RTLIL::Cell *cell = addCell(name, ID($cover));
2174 cell->setPort(ID::A, sig_a);
2175 cell->setPort(ID::EN, sig_en);
2176 cell->set_src_attribute(src);
2177 return cell;
2178 }
2179
2180 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2181 {
2182 RTLIL::Cell *cell = addCell(name, ID($equiv));
2183 cell->setPort(ID::A, sig_a);
2184 cell->setPort(ID::B, sig_b);
2185 cell->setPort(ID::Y, sig_y);
2186 cell->set_src_attribute(src);
2187 return cell;
2188 }
2189
2190 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2191 {
2192 RTLIL::Cell *cell = addCell(name, ID($sr));
2193 cell->parameters[ID::SET_POLARITY] = set_polarity;
2194 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2195 cell->parameters[ID::WIDTH] = sig_q.size();
2196 cell->setPort(ID::SET, sig_set);
2197 cell->setPort(ID::CLR, sig_clr);
2198 cell->setPort(ID::Q, sig_q);
2199 cell->set_src_attribute(src);
2200 return cell;
2201 }
2202
2203 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2204 {
2205 RTLIL::Cell *cell = addCell(name, ID($ff));
2206 cell->parameters[ID::WIDTH] = sig_q.size();
2207 cell->setPort(ID::D, sig_d);
2208 cell->setPort(ID::Q, sig_q);
2209 cell->set_src_attribute(src);
2210 return cell;
2211 }
2212
2213 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2214 {
2215 RTLIL::Cell *cell = addCell(name, ID($dff));
2216 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2217 cell->parameters[ID::WIDTH] = sig_q.size();
2218 cell->setPort(ID::CLK, sig_clk);
2219 cell->setPort(ID::D, sig_d);
2220 cell->setPort(ID::Q, sig_q);
2221 cell->set_src_attribute(src);
2222 return cell;
2223 }
2224
2225 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2226 {
2227 RTLIL::Cell *cell = addCell(name, ID($dffe));
2228 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2229 cell->parameters[ID::EN_POLARITY] = en_polarity;
2230 cell->parameters[ID::WIDTH] = sig_q.size();
2231 cell->setPort(ID::CLK, sig_clk);
2232 cell->setPort(ID::EN, sig_en);
2233 cell->setPort(ID::D, sig_d);
2234 cell->setPort(ID::Q, sig_q);
2235 cell->set_src_attribute(src);
2236 return cell;
2237 }
2238
2239 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2240 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2241 {
2242 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2243 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2244 cell->parameters[ID::SET_POLARITY] = set_polarity;
2245 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2246 cell->parameters[ID::WIDTH] = sig_q.size();
2247 cell->setPort(ID::CLK, sig_clk);
2248 cell->setPort(ID::SET, sig_set);
2249 cell->setPort(ID::CLR, sig_clr);
2250 cell->setPort(ID::D, sig_d);
2251 cell->setPort(ID::Q, sig_q);
2252 cell->set_src_attribute(src);
2253 return cell;
2254 }
2255
2256 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2257 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2258 {
2259 RTLIL::Cell *cell = addCell(name, ID($adff));
2260 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2261 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2262 cell->parameters[ID::ARST_VALUE] = arst_value;
2263 cell->parameters[ID::WIDTH] = sig_q.size();
2264 cell->setPort(ID::CLK, sig_clk);
2265 cell->setPort(ID::ARST, sig_arst);
2266 cell->setPort(ID::D, sig_d);
2267 cell->setPort(ID::Q, sig_q);
2268 cell->set_src_attribute(src);
2269 return cell;
2270 }
2271
2272 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2273 {
2274 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2275 cell->parameters[ID::EN_POLARITY] = en_polarity;
2276 cell->parameters[ID::WIDTH] = sig_q.size();
2277 cell->setPort(ID::EN, sig_en);
2278 cell->setPort(ID::D, sig_d);
2279 cell->setPort(ID::Q, sig_q);
2280 cell->set_src_attribute(src);
2281 return cell;
2282 }
2283
2284 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2285 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2286 {
2287 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2288 cell->parameters[ID::EN_POLARITY] = en_polarity;
2289 cell->parameters[ID::SET_POLARITY] = set_polarity;
2290 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2291 cell->parameters[ID::WIDTH] = sig_q.size();
2292 cell->setPort(ID::EN, sig_en);
2293 cell->setPort(ID::SET, sig_set);
2294 cell->setPort(ID::CLR, sig_clr);
2295 cell->setPort(ID::D, sig_d);
2296 cell->setPort(ID::Q, sig_q);
2297 cell->set_src_attribute(src);
2298 return cell;
2299 }
2300
2301 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2302 {
2303 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2304 cell->setPort(ID::D, sig_d);
2305 cell->setPort(ID::Q, sig_q);
2306 cell->set_src_attribute(src);
2307 return cell;
2308 }
2309
2310 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2311 {
2312 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2313 cell->setPort(ID::C, sig_clk);
2314 cell->setPort(ID::D, sig_d);
2315 cell->setPort(ID::Q, sig_q);
2316 cell->set_src_attribute(src);
2317 return cell;
2318 }
2319
2320 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2321 {
2322 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2323 cell->setPort(ID::C, sig_clk);
2324 cell->setPort(ID::E, sig_en);
2325 cell->setPort(ID::D, sig_d);
2326 cell->setPort(ID::Q, sig_q);
2327 cell->set_src_attribute(src);
2328 return cell;
2329 }
2330
2331 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2332 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2333 {
2334 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2335 cell->setPort(ID::C, sig_clk);
2336 cell->setPort(ID::S, sig_set);
2337 cell->setPort(ID::R, sig_clr);
2338 cell->setPort(ID::D, sig_d);
2339 cell->setPort(ID::Q, sig_q);
2340 cell->set_src_attribute(src);
2341 return cell;
2342 }
2343
2344 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2345 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2346 {
2347 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2348 cell->setPort(ID::C, sig_clk);
2349 cell->setPort(ID::R, sig_arst);
2350 cell->setPort(ID::D, sig_d);
2351 cell->setPort(ID::Q, sig_q);
2352 cell->set_src_attribute(src);
2353 return cell;
2354 }
2355
2356 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2357 {
2358 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2359 cell->setPort(ID::E, sig_en);
2360 cell->setPort(ID::D, sig_d);
2361 cell->setPort(ID::Q, sig_q);
2362 cell->set_src_attribute(src);
2363 return cell;
2364 }
2365
2366 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2367 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2368 {
2369 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2370 cell->setPort(ID::E, sig_en);
2371 cell->setPort(ID::S, sig_set);
2372 cell->setPort(ID::R, sig_clr);
2373 cell->setPort(ID::D, sig_d);
2374 cell->setPort(ID::Q, sig_q);
2375 cell->set_src_attribute(src);
2376 return cell;
2377 }
2378
2379 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2380 {
2381 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2382 Cell *cell = addCell(name, ID($anyconst));
2383 cell->setParam(ID::WIDTH, width);
2384 cell->setPort(ID::Y, sig);
2385 cell->set_src_attribute(src);
2386 return sig;
2387 }
2388
2389 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2390 {
2391 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2392 Cell *cell = addCell(name, ID($anyseq));
2393 cell->setParam(ID::WIDTH, width);
2394 cell->setPort(ID::Y, sig);
2395 cell->set_src_attribute(src);
2396 return sig;
2397 }
2398
2399 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2400 {
2401 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2402 Cell *cell = addCell(name, ID($allconst));
2403 cell->setParam(ID::WIDTH, width);
2404 cell->setPort(ID::Y, sig);
2405 cell->set_src_attribute(src);
2406 return sig;
2407 }
2408
2409 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2410 {
2411 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2412 Cell *cell = addCell(name, ID($allseq));
2413 cell->setParam(ID::WIDTH, width);
2414 cell->setPort(ID::Y, sig);
2415 cell->set_src_attribute(src);
2416 return sig;
2417 }
2418
2419 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2420 {
2421 RTLIL::SigSpec sig = addWire(NEW_ID);
2422 Cell *cell = addCell(name, ID($initstate));
2423 cell->setPort(ID::Y, sig);
2424 cell->set_src_attribute(src);
2425 return sig;
2426 }
2427
2428 RTLIL::Wire::Wire()
2429 {
2430 static unsigned int hashidx_count = 123456789;
2431 hashidx_count = mkhash_xorshift(hashidx_count);
2432 hashidx_ = hashidx_count;
2433
2434 module = nullptr;
2435 width = 1;
2436 start_offset = 0;
2437 port_id = 0;
2438 port_input = false;
2439 port_output = false;
2440 upto = false;
2441
2442 #ifdef WITH_PYTHON
2443 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2444 #endif
2445 }
2446
2447 RTLIL::Wire::~Wire()
2448 {
2449 #ifdef WITH_PYTHON
2450 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2451 #endif
2452 }
2453
2454 #ifdef WITH_PYTHON
2455 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2456 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2457 {
2458 return &all_wires;
2459 }
2460 #endif
2461
2462 RTLIL::Memory::Memory()
2463 {
2464 static unsigned int hashidx_count = 123456789;
2465 hashidx_count = mkhash_xorshift(hashidx_count);
2466 hashidx_ = hashidx_count;
2467
2468 width = 1;
2469 start_offset = 0;
2470 size = 0;
2471 #ifdef WITH_PYTHON
2472 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2473 #endif
2474 }
2475
2476 RTLIL::Cell::Cell() : module(nullptr)
2477 {
2478 static unsigned int hashidx_count = 123456789;
2479 hashidx_count = mkhash_xorshift(hashidx_count);
2480 hashidx_ = hashidx_count;
2481
2482 // log("#memtrace# %p\n", this);
2483 memhasher();
2484
2485 #ifdef WITH_PYTHON
2486 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2487 #endif
2488 }
2489
2490 RTLIL::Cell::~Cell()
2491 {
2492 #ifdef WITH_PYTHON
2493 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2494 #endif
2495 }
2496
2497 #ifdef WITH_PYTHON
2498 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2499 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2500 {
2501 return &all_cells;
2502 }
2503 #endif
2504
2505 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2506 {
2507 return connections_.count(portname) != 0;
2508 }
2509
2510 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2511 {
2512 RTLIL::SigSpec signal;
2513 auto conn_it = connections_.find(portname);
2514
2515 if (conn_it != connections_.end())
2516 {
2517 for (auto mon : module->monitors)
2518 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2519
2520 if (module->design)
2521 for (auto mon : module->design->monitors)
2522 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2523
2524 if (yosys_xtrace) {
2525 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2526 log_backtrace("-X- ", yosys_xtrace-1);
2527 }
2528
2529 connections_.erase(conn_it);
2530 }
2531 }
2532
2533 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2534 {
2535 auto r = connections_.insert(portname);
2536 auto conn_it = r.first;
2537 if (!r.second && conn_it->second == signal)
2538 return;
2539
2540 for (auto mon : module->monitors)
2541 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2542
2543 if (module->design)
2544 for (auto mon : module->design->monitors)
2545 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2546
2547 if (yosys_xtrace) {
2548 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2549 log_backtrace("-X- ", yosys_xtrace-1);
2550 }
2551
2552 conn_it->second = std::move(signal);
2553 }
2554
2555 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2556 {
2557 return connections_.at(portname);
2558 }
2559
2560 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2561 {
2562 return connections_;
2563 }
2564
2565 bool RTLIL::Cell::known() const
2566 {
2567 if (yosys_celltypes.cell_known(type))
2568 return true;
2569 if (module && module->design && module->design->module(type))
2570 return true;
2571 return false;
2572 }
2573
2574 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2575 {
2576 if (yosys_celltypes.cell_known(type))
2577 return yosys_celltypes.cell_input(type, portname);
2578 if (module && module->design) {
2579 RTLIL::Module *m = module->design->module(type);
2580 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2581 return w && w->port_input;
2582 }
2583 return false;
2584 }
2585
2586 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2587 {
2588 if (yosys_celltypes.cell_known(type))
2589 return yosys_celltypes.cell_output(type, portname);
2590 if (module && module->design) {
2591 RTLIL::Module *m = module->design->module(type);
2592 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2593 return w && w->port_output;
2594 }
2595 return false;
2596 }
2597
2598 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2599 {
2600 return parameters.count(paramname) != 0;
2601 }
2602
2603 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2604 {
2605 parameters.erase(paramname);
2606 }
2607
2608 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2609 {
2610 parameters[paramname] = std::move(value);
2611 }
2612
2613 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2614 {
2615 return parameters.at(paramname);
2616 }
2617
2618 void RTLIL::Cell::sort()
2619 {
2620 connections_.sort(sort_by_id_str());
2621 parameters.sort(sort_by_id_str());
2622 attributes.sort(sort_by_id_str());
2623 }
2624
2625 void RTLIL::Cell::check()
2626 {
2627 #ifndef NDEBUG
2628 InternalCellChecker checker(NULL, this);
2629 checker.check();
2630 #endif
2631 }
2632
2633 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2634 {
2635 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2636 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2637 return;
2638
2639 if (type == ID($mux) || type == ID($pmux)) {
2640 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2641 if (type == ID($pmux))
2642 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2643 check();
2644 return;
2645 }
2646
2647 if (type == ID($lut) || type == ID($sop)) {
2648 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2649 return;
2650 }
2651
2652 if (type == ID($fa)) {
2653 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2654 return;
2655 }
2656
2657 if (type == ID($lcu)) {
2658 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2659 return;
2660 }
2661
2662 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2663
2664 if (connections_.count(ID::A)) {
2665 if (signedness_ab) {
2666 if (set_a_signed)
2667 parameters[ID::A_SIGNED] = true;
2668 else if (parameters.count(ID::A_SIGNED) == 0)
2669 parameters[ID::A_SIGNED] = false;
2670 }
2671 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2672 }
2673
2674 if (connections_.count(ID::B)) {
2675 if (signedness_ab) {
2676 if (set_b_signed)
2677 parameters[ID::B_SIGNED] = true;
2678 else if (parameters.count(ID::B_SIGNED) == 0)
2679 parameters[ID::B_SIGNED] = false;
2680 }
2681 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2682 }
2683
2684 if (connections_.count(ID::Y))
2685 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2686
2687 if (connections_.count(ID::Q))
2688 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2689
2690 check();
2691 }
2692
2693 RTLIL::SigChunk::SigChunk()
2694 {
2695 wire = NULL;
2696 width = 0;
2697 offset = 0;
2698 }
2699
2700 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2701 {
2702 wire = NULL;
2703 data = value.bits;
2704 width = GetSize(data);
2705 offset = 0;
2706 }
2707
2708 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2709 {
2710 log_assert(wire != nullptr);
2711 this->wire = wire;
2712 this->width = wire->width;
2713 this->offset = 0;
2714 }
2715
2716 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2717 {
2718 log_assert(wire != nullptr);
2719 this->wire = wire;
2720 this->width = width;
2721 this->offset = offset;
2722 }
2723
2724 RTLIL::SigChunk::SigChunk(const std::string &str)
2725 {
2726 wire = NULL;
2727 data = RTLIL::Const(str).bits;
2728 width = GetSize(data);
2729 offset = 0;
2730 }
2731
2732 RTLIL::SigChunk::SigChunk(int val, int width)
2733 {
2734 wire = NULL;
2735 data = RTLIL::Const(val, width).bits;
2736 this->width = GetSize(data);
2737 offset = 0;
2738 }
2739
2740 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2741 {
2742 wire = NULL;
2743 data = RTLIL::Const(bit, width).bits;
2744 this->width = GetSize(data);
2745 offset = 0;
2746 }
2747
2748 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2749 {
2750 wire = bit.wire;
2751 offset = 0;
2752 if (wire == NULL)
2753 data = RTLIL::Const(bit.data).bits;
2754 else
2755 offset = bit.offset;
2756 width = 1;
2757 }
2758
2759 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2760 {
2761 *this = sigchunk;
2762 }
2763
2764 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2765 {
2766 RTLIL::SigChunk ret;
2767 if (wire) {
2768 ret.wire = wire;
2769 ret.offset = this->offset + offset;
2770 ret.width = length;
2771 } else {
2772 for (int i = 0; i < length; i++)
2773 ret.data.push_back(data[offset+i]);
2774 ret.width = length;
2775 }
2776 return ret;
2777 }
2778
2779 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2780 {
2781 if (wire && other.wire)
2782 if (wire->name != other.wire->name)
2783 return wire->name < other.wire->name;
2784
2785 if (wire != other.wire)
2786 return wire < other.wire;
2787
2788 if (offset != other.offset)
2789 return offset < other.offset;
2790
2791 if (width != other.width)
2792 return width < other.width;
2793
2794 return data < other.data;
2795 }
2796
2797 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2798 {
2799 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2800 }
2801
2802 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2803 {
2804 if (*this == other)
2805 return false;
2806 return true;
2807 }
2808
2809 RTLIL::SigSpec::SigSpec()
2810 {
2811 width_ = 0;
2812 hash_ = 0;
2813 }
2814
2815 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2816 {
2817 *this = other;
2818 }
2819
2820 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2821 {
2822 cover("kernel.rtlil.sigspec.init.list");
2823
2824 width_ = 0;
2825 hash_ = 0;
2826
2827 log_assert(parts.size() > 0);
2828 auto ie = parts.begin();
2829 auto it = ie + parts.size() - 1;
2830 while (it >= ie)
2831 append(*it--);
2832 }
2833
2834 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2835 {
2836 cover("kernel.rtlil.sigspec.assign");
2837
2838 width_ = other.width_;
2839 hash_ = other.hash_;
2840 chunks_ = other.chunks_;
2841 bits_ = other.bits_;
2842 return *this;
2843 }
2844
2845 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2846 {
2847 cover("kernel.rtlil.sigspec.init.const");
2848
2849 chunks_.emplace_back(value);
2850 width_ = chunks_.back().width;
2851 hash_ = 0;
2852 check();
2853 }
2854
2855 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2856 {
2857 cover("kernel.rtlil.sigspec.init.chunk");
2858
2859 chunks_.emplace_back(chunk);
2860 width_ = chunks_.back().width;
2861 hash_ = 0;
2862 check();
2863 }
2864
2865 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2866 {
2867 cover("kernel.rtlil.sigspec.init.wire");
2868
2869 chunks_.emplace_back(wire);
2870 width_ = chunks_.back().width;
2871 hash_ = 0;
2872 check();
2873 }
2874
2875 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2876 {
2877 cover("kernel.rtlil.sigspec.init.wire_part");
2878
2879 chunks_.emplace_back(wire, offset, width);
2880 width_ = chunks_.back().width;
2881 hash_ = 0;
2882 check();
2883 }
2884
2885 RTLIL::SigSpec::SigSpec(const std::string &str)
2886 {
2887 cover("kernel.rtlil.sigspec.init.str");
2888
2889 chunks_.emplace_back(str);
2890 width_ = chunks_.back().width;
2891 hash_ = 0;
2892 check();
2893 }
2894
2895 RTLIL::SigSpec::SigSpec(int val, int width)
2896 {
2897 cover("kernel.rtlil.sigspec.init.int");
2898
2899 chunks_.emplace_back(val, width);
2900 width_ = width;
2901 hash_ = 0;
2902 check();
2903 }
2904
2905 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2906 {
2907 cover("kernel.rtlil.sigspec.init.state");
2908
2909 chunks_.emplace_back(bit, width);
2910 width_ = width;
2911 hash_ = 0;
2912 check();
2913 }
2914
2915 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2916 {
2917 cover("kernel.rtlil.sigspec.init.bit");
2918
2919 if (bit.wire == NULL)
2920 chunks_.emplace_back(bit.data, width);
2921 else
2922 for (int i = 0; i < width; i++)
2923 chunks_.push_back(bit);
2924 width_ = width;
2925 hash_ = 0;
2926 check();
2927 }
2928
2929 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2930 {
2931 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2932
2933 width_ = 0;
2934 hash_ = 0;
2935 for (const auto &c : chunks)
2936 append(c);
2937 check();
2938 }
2939
2940 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2941 {
2942 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2943
2944 width_ = 0;
2945 hash_ = 0;
2946 for (const auto &bit : bits)
2947 append(bit);
2948 check();
2949 }
2950
2951 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2952 {
2953 cover("kernel.rtlil.sigspec.init.pool_bits");
2954
2955 width_ = 0;
2956 hash_ = 0;
2957 for (const auto &bit : bits)
2958 append(bit);
2959 check();
2960 }
2961
2962 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2963 {
2964 cover("kernel.rtlil.sigspec.init.stdset_bits");
2965
2966 width_ = 0;
2967 hash_ = 0;
2968 for (const auto &bit : bits)
2969 append(bit);
2970 check();
2971 }
2972
2973 RTLIL::SigSpec::SigSpec(bool bit)
2974 {
2975 cover("kernel.rtlil.sigspec.init.bool");
2976
2977 width_ = 0;
2978 hash_ = 0;
2979 append(SigBit(bit));
2980 check();
2981 }
2982
2983 void RTLIL::SigSpec::pack() const
2984 {
2985 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2986
2987 if (that->bits_.empty())
2988 return;
2989
2990 cover("kernel.rtlil.sigspec.convert.pack");
2991 log_assert(that->chunks_.empty());
2992
2993 std::vector<RTLIL::SigBit> old_bits;
2994 old_bits.swap(that->bits_);
2995
2996 RTLIL::SigChunk *last = NULL;
2997 int last_end_offset = 0;
2998
2999 for (auto &bit : old_bits) {
3000 if (last && bit.wire == last->wire) {
3001 if (bit.wire == NULL) {
3002 last->data.push_back(bit.data);
3003 last->width++;
3004 continue;
3005 } else if (last_end_offset == bit.offset) {
3006 last_end_offset++;
3007 last->width++;
3008 continue;
3009 }
3010 }
3011 that->chunks_.push_back(bit);
3012 last = &that->chunks_.back();
3013 last_end_offset = bit.offset + 1;
3014 }
3015
3016 check();
3017 }
3018
3019 void RTLIL::SigSpec::unpack() const
3020 {
3021 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3022
3023 if (that->chunks_.empty())
3024 return;
3025
3026 cover("kernel.rtlil.sigspec.convert.unpack");
3027 log_assert(that->bits_.empty());
3028
3029 that->bits_.reserve(that->width_);
3030 for (auto &c : that->chunks_)
3031 for (int i = 0; i < c.width; i++)
3032 that->bits_.emplace_back(c, i);
3033
3034 that->chunks_.clear();
3035 that->hash_ = 0;
3036 }
3037
3038 void RTLIL::SigSpec::updhash() const
3039 {
3040 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3041
3042 if (that->hash_ != 0)
3043 return;
3044
3045 cover("kernel.rtlil.sigspec.hash");
3046 that->pack();
3047
3048 that->hash_ = mkhash_init;
3049 for (auto &c : that->chunks_)
3050 if (c.wire == NULL) {
3051 for (auto &v : c.data)
3052 that->hash_ = mkhash(that->hash_, v);
3053 } else {
3054 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3055 that->hash_ = mkhash(that->hash_, c.offset);
3056 that->hash_ = mkhash(that->hash_, c.width);
3057 }
3058
3059 if (that->hash_ == 0)
3060 that->hash_ = 1;
3061 }
3062
3063 void RTLIL::SigSpec::sort()
3064 {
3065 unpack();
3066 cover("kernel.rtlil.sigspec.sort");
3067 std::sort(bits_.begin(), bits_.end());
3068 }
3069
3070 void RTLIL::SigSpec::sort_and_unify()
3071 {
3072 unpack();
3073 cover("kernel.rtlil.sigspec.sort_and_unify");
3074
3075 // A copy of the bits vector is used to prevent duplicating the logic from
3076 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3077 // that isn't showing up as significant in profiles.
3078 std::vector<SigBit> unique_bits = bits_;
3079 std::sort(unique_bits.begin(), unique_bits.end());
3080 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3081 unique_bits.erase(last, unique_bits.end());
3082
3083 *this = unique_bits;
3084 }
3085
3086 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3087 {
3088 replace(pattern, with, this);
3089 }
3090
3091 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3092 {
3093 log_assert(other != NULL);
3094 log_assert(width_ == other->width_);
3095 log_assert(pattern.width_ == with.width_);
3096
3097 pattern.unpack();
3098 with.unpack();
3099 unpack();
3100 other->unpack();
3101
3102 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3103 if (pattern.bits_[i].wire != NULL) {
3104 for (int j = 0; j < GetSize(bits_); j++) {
3105 if (bits_[j] == pattern.bits_[i]) {
3106 other->bits_[j] = with.bits_[i];
3107 }
3108 }
3109 }
3110 }
3111
3112 other->check();
3113 }
3114
3115 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3116 {
3117 replace(rules, this);
3118 }
3119
3120 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3121 {
3122 cover("kernel.rtlil.sigspec.replace_dict");
3123
3124 log_assert(other != NULL);
3125 log_assert(width_ == other->width_);
3126
3127 if (rules.empty()) return;
3128 unpack();
3129 other->unpack();
3130
3131 for (int i = 0; i < GetSize(bits_); i++) {
3132 auto it = rules.find(bits_[i]);
3133 if (it != rules.end())
3134 other->bits_[i] = it->second;
3135 }
3136
3137 other->check();
3138 }
3139
3140 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3141 {
3142 replace(rules, this);
3143 }
3144
3145 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3146 {
3147 cover("kernel.rtlil.sigspec.replace_map");
3148
3149 log_assert(other != NULL);
3150 log_assert(width_ == other->width_);
3151
3152 if (rules.empty()) return;
3153 unpack();
3154 other->unpack();
3155
3156 for (int i = 0; i < GetSize(bits_); i++) {
3157 auto it = rules.find(bits_[i]);
3158 if (it != rules.end())
3159 other->bits_[i] = it->second;
3160 }
3161
3162 other->check();
3163 }
3164
3165 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3166 {
3167 remove2(pattern, NULL);
3168 }
3169
3170 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3171 {
3172 RTLIL::SigSpec tmp = *this;
3173 tmp.remove2(pattern, other);
3174 }
3175
3176 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3177 {
3178 if (other)
3179 cover("kernel.rtlil.sigspec.remove_other");
3180 else
3181 cover("kernel.rtlil.sigspec.remove");
3182
3183 unpack();
3184 if (other != NULL) {
3185 log_assert(width_ == other->width_);
3186 other->unpack();
3187 }
3188
3189 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3190 {
3191 if (bits_[i].wire == NULL) continue;
3192
3193 for (auto &pattern_chunk : pattern.chunks())
3194 if (bits_[i].wire == pattern_chunk.wire &&
3195 bits_[i].offset >= pattern_chunk.offset &&
3196 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3197 bits_.erase(bits_.begin() + i);
3198 width_--;
3199 if (other != NULL) {
3200 other->bits_.erase(other->bits_.begin() + i);
3201 other->width_--;
3202 }
3203 break;
3204 }
3205 }
3206
3207 check();
3208 }
3209
3210 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3211 {
3212 remove2(pattern, NULL);
3213 }
3214
3215 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3216 {
3217 RTLIL::SigSpec tmp = *this;
3218 tmp.remove2(pattern, other);
3219 }
3220
3221 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3222 {
3223 if (other)
3224 cover("kernel.rtlil.sigspec.remove_other");
3225 else
3226 cover("kernel.rtlil.sigspec.remove");
3227
3228 unpack();
3229
3230 if (other != NULL) {
3231 log_assert(width_ == other->width_);
3232 other->unpack();
3233 }
3234
3235 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3236 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3237 bits_.erase(bits_.begin() + i);
3238 width_--;
3239 if (other != NULL) {
3240 other->bits_.erase(other->bits_.begin() + i);
3241 other->width_--;
3242 }
3243 }
3244 }
3245
3246 check();
3247 }
3248
3249 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3250 {
3251 if (other)
3252 cover("kernel.rtlil.sigspec.remove_other");
3253 else
3254 cover("kernel.rtlil.sigspec.remove");
3255
3256 unpack();
3257
3258 if (other != NULL) {
3259 log_assert(width_ == other->width_);
3260 other->unpack();
3261 }
3262
3263 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3264 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3265 bits_.erase(bits_.begin() + i);
3266 width_--;
3267 if (other != NULL) {
3268 other->bits_.erase(other->bits_.begin() + i);
3269 other->width_--;
3270 }
3271 }
3272 }
3273
3274 check();
3275 }
3276
3277 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3278 {
3279 if (other)
3280 cover("kernel.rtlil.sigspec.extract_other");
3281 else
3282 cover("kernel.rtlil.sigspec.extract");
3283
3284 log_assert(other == NULL || width_ == other->width_);
3285
3286 RTLIL::SigSpec ret;
3287 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3288
3289 for (auto& pattern_chunk : pattern.chunks()) {
3290 if (other) {
3291 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3292 for (int i = 0; i < width_; i++)
3293 if (bits_match[i].wire &&
3294 bits_match[i].wire == pattern_chunk.wire &&
3295 bits_match[i].offset >= pattern_chunk.offset &&
3296 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3297 ret.append(bits_other[i]);
3298 } else {
3299 for (int i = 0; i < width_; i++)
3300 if (bits_match[i].wire &&
3301 bits_match[i].wire == pattern_chunk.wire &&
3302 bits_match[i].offset >= pattern_chunk.offset &&
3303 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3304 ret.append(bits_match[i]);
3305 }
3306 }
3307
3308 ret.check();
3309 return ret;
3310 }
3311
3312 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3313 {
3314 if (other)
3315 cover("kernel.rtlil.sigspec.extract_other");
3316 else
3317 cover("kernel.rtlil.sigspec.extract");
3318
3319 log_assert(other == NULL || width_ == other->width_);
3320
3321 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3322 RTLIL::SigSpec ret;
3323
3324 if (other) {
3325 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3326 for (int i = 0; i < width_; i++)
3327 if (bits_match[i].wire && pattern.count(bits_match[i]))
3328 ret.append(bits_other[i]);
3329 } else {
3330 for (int i = 0; i < width_; i++)
3331 if (bits_match[i].wire && pattern.count(bits_match[i]))
3332 ret.append(bits_match[i]);
3333 }
3334
3335 ret.check();
3336 return ret;
3337 }
3338
3339 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3340 {
3341 cover("kernel.rtlil.sigspec.replace_pos");
3342
3343 unpack();
3344 with.unpack();
3345
3346 log_assert(offset >= 0);
3347 log_assert(with.width_ >= 0);
3348 log_assert(offset+with.width_ <= width_);
3349
3350 for (int i = 0; i < with.width_; i++)
3351 bits_.at(offset + i) = with.bits_.at(i);
3352
3353 check();
3354 }
3355
3356 void RTLIL::SigSpec::remove_const()
3357 {
3358 if (packed())
3359 {
3360 cover("kernel.rtlil.sigspec.remove_const.packed");
3361
3362 std::vector<RTLIL::SigChunk> new_chunks;
3363 new_chunks.reserve(GetSize(chunks_));
3364
3365 width_ = 0;
3366 for (auto &chunk : chunks_)
3367 if (chunk.wire != NULL) {
3368 new_chunks.push_back(chunk);
3369 width_ += chunk.width;
3370 }
3371
3372 chunks_.swap(new_chunks);
3373 }
3374 else
3375 {
3376 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3377
3378 std::vector<RTLIL::SigBit> new_bits;
3379 new_bits.reserve(width_);
3380
3381 for (auto &bit : bits_)
3382 if (bit.wire != NULL)
3383 new_bits.push_back(bit);
3384
3385 bits_.swap(new_bits);
3386 width_ = bits_.size();
3387 }
3388
3389 check();
3390 }
3391
3392 void RTLIL::SigSpec::remove(int offset, int length)
3393 {
3394 cover("kernel.rtlil.sigspec.remove_pos");
3395
3396 unpack();
3397
3398 log_assert(offset >= 0);
3399 log_assert(length >= 0);
3400 log_assert(offset + length <= width_);
3401
3402 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3403 width_ = bits_.size();
3404
3405 check();
3406 }
3407
3408 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3409 {
3410 unpack();
3411 cover("kernel.rtlil.sigspec.extract_pos");
3412 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3413 }
3414
3415 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3416 {
3417 if (signal.width_ == 0)
3418 return;
3419
3420 if (width_ == 0) {
3421 *this = signal;
3422 return;
3423 }
3424
3425 cover("kernel.rtlil.sigspec.append");
3426
3427 if (packed() != signal.packed()) {
3428 pack();
3429 signal.pack();
3430 }
3431
3432 if (packed())
3433 for (auto &other_c : signal.chunks_)
3434 {
3435 auto &my_last_c = chunks_.back();
3436 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3437 auto &this_data = my_last_c.data;
3438 auto &other_data = other_c.data;
3439 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3440 my_last_c.width += other_c.width;
3441 } else
3442 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3443 my_last_c.width += other_c.width;
3444 } else
3445 chunks_.push_back(other_c);
3446 }
3447 else
3448 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3449
3450 width_ += signal.width_;
3451 check();
3452 }
3453
3454 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3455 {
3456 if (packed())
3457 {
3458 cover("kernel.rtlil.sigspec.append_bit.packed");
3459
3460 if (chunks_.size() == 0)
3461 chunks_.push_back(bit);
3462 else
3463 if (bit.wire == NULL)
3464 if (chunks_.back().wire == NULL) {
3465 chunks_.back().data.push_back(bit.data);
3466 chunks_.back().width++;
3467 } else
3468 chunks_.push_back(bit);
3469 else
3470 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3471 chunks_.back().width++;
3472 else
3473 chunks_.push_back(bit);
3474 }
3475 else
3476 {
3477 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3478 bits_.push_back(bit);
3479 }
3480
3481 width_++;
3482 check();
3483 }
3484
3485 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3486 {
3487 cover("kernel.rtlil.sigspec.extend_u0");
3488
3489 pack();
3490
3491 if (width_ > width)
3492 remove(width, width_ - width);
3493
3494 if (width_ < width) {
3495 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3496 if (!is_signed)
3497 padding = RTLIL::State::S0;
3498 while (width_ < width)
3499 append(padding);
3500 }
3501
3502 }
3503
3504 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3505 {
3506 cover("kernel.rtlil.sigspec.repeat");
3507
3508 RTLIL::SigSpec sig;
3509 for (int i = 0; i < num; i++)
3510 sig.append(*this);
3511 return sig;
3512 }
3513
3514 #ifndef NDEBUG
3515 void RTLIL::SigSpec::check() const
3516 {
3517 if (width_ > 64)
3518 {
3519 cover("kernel.rtlil.sigspec.check.skip");
3520 }
3521 else if (packed())
3522 {
3523 cover("kernel.rtlil.sigspec.check.packed");
3524
3525 int w = 0;
3526 for (size_t i = 0; i < chunks_.size(); i++) {
3527 const RTLIL::SigChunk &chunk = chunks_[i];
3528 if (chunk.wire == NULL) {
3529 if (i > 0)
3530 log_assert(chunks_[i-1].wire != NULL);
3531 log_assert(chunk.offset == 0);
3532 log_assert(chunk.data.size() == (size_t)chunk.width);
3533 } else {
3534 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3535 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3536 log_assert(chunk.offset >= 0);
3537 log_assert(chunk.width >= 0);
3538 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3539 log_assert(chunk.data.size() == 0);
3540 }
3541 w += chunk.width;
3542 }
3543 log_assert(w == width_);
3544 log_assert(bits_.empty());
3545 }
3546 else
3547 {
3548 cover("kernel.rtlil.sigspec.check.unpacked");
3549
3550 log_assert(width_ == GetSize(bits_));
3551 log_assert(chunks_.empty());
3552 }
3553 }
3554 #endif
3555
3556 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3557 {
3558 cover("kernel.rtlil.sigspec.comp_lt");
3559
3560 if (this == &other)
3561 return false;
3562
3563 if (width_ != other.width_)
3564 return width_ < other.width_;
3565
3566 pack();
3567 other.pack();
3568
3569 if (chunks_.size() != other.chunks_.size())
3570 return chunks_.size() < other.chunks_.size();
3571
3572 updhash();
3573 other.updhash();
3574
3575 if (hash_ != other.hash_)
3576 return hash_ < other.hash_;
3577
3578 for (size_t i = 0; i < chunks_.size(); i++)
3579 if (chunks_[i] != other.chunks_[i]) {
3580 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3581 return chunks_[i] < other.chunks_[i];
3582 }
3583
3584 cover("kernel.rtlil.sigspec.comp_lt.equal");
3585 return false;
3586 }
3587
3588 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3589 {
3590 cover("kernel.rtlil.sigspec.comp_eq");
3591
3592 if (this == &other)
3593 return true;
3594
3595 if (width_ != other.width_)
3596 return false;
3597
3598 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3599 // since the RHS will contain one SigChunk of width 0 causing
3600 // the size check below to fail
3601 if (width_ == 0)
3602 return true;
3603
3604 pack();
3605 other.pack();
3606
3607 if (chunks_.size() != other.chunks_.size())
3608 return false;
3609
3610 updhash();
3611 other.updhash();
3612
3613 if (hash_ != other.hash_)
3614 return false;
3615
3616 for (size_t i = 0; i < chunks_.size(); i++)
3617 if (chunks_[i] != other.chunks_[i]) {
3618 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3619 return false;
3620 }
3621
3622 cover("kernel.rtlil.sigspec.comp_eq.equal");
3623 return true;
3624 }
3625
3626 bool RTLIL::SigSpec::is_wire() const
3627 {
3628 cover("kernel.rtlil.sigspec.is_wire");
3629
3630 pack();
3631 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3632 }
3633
3634 bool RTLIL::SigSpec::is_chunk() const
3635 {
3636 cover("kernel.rtlil.sigspec.is_chunk");
3637
3638 pack();
3639 return GetSize(chunks_) == 1;
3640 }
3641
3642 bool RTLIL::SigSpec::is_fully_const() const
3643 {
3644 cover("kernel.rtlil.sigspec.is_fully_const");
3645
3646 pack();
3647 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3648 if (it->width > 0 && it->wire != NULL)
3649 return false;
3650 return true;
3651 }
3652
3653 bool RTLIL::SigSpec::is_fully_zero() const
3654 {
3655 cover("kernel.rtlil.sigspec.is_fully_zero");
3656
3657 pack();
3658 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3659 if (it->width > 0 && it->wire != NULL)
3660 return false;
3661 for (size_t i = 0; i < it->data.size(); i++)
3662 if (it->data[i] != RTLIL::State::S0)
3663 return false;
3664 }
3665 return true;
3666 }
3667
3668 bool RTLIL::SigSpec::is_fully_ones() const
3669 {
3670 cover("kernel.rtlil.sigspec.is_fully_ones");
3671
3672 pack();
3673 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3674 if (it->width > 0 && it->wire != NULL)
3675 return false;
3676 for (size_t i = 0; i < it->data.size(); i++)
3677 if (it->data[i] != RTLIL::State::S1)
3678 return false;
3679 }
3680 return true;
3681 }
3682
3683 bool RTLIL::SigSpec::is_fully_def() const
3684 {
3685 cover("kernel.rtlil.sigspec.is_fully_def");
3686
3687 pack();
3688 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3689 if (it->width > 0 && it->wire != NULL)
3690 return false;
3691 for (size_t i = 0; i < it->data.size(); i++)
3692 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3693 return false;
3694 }
3695 return true;
3696 }
3697
3698 bool RTLIL::SigSpec::is_fully_undef() const
3699 {
3700 cover("kernel.rtlil.sigspec.is_fully_undef");
3701
3702 pack();
3703 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3704 if (it->width > 0 && it->wire != NULL)
3705 return false;
3706 for (size_t i = 0; i < it->data.size(); i++)
3707 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3708 return false;
3709 }
3710 return true;
3711 }
3712
3713 bool RTLIL::SigSpec::has_const() const
3714 {
3715 cover("kernel.rtlil.sigspec.has_const");
3716
3717 pack();
3718 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3719 if (it->width > 0 && it->wire == NULL)
3720 return true;
3721 return false;
3722 }
3723
3724 bool RTLIL::SigSpec::has_marked_bits() const
3725 {
3726 cover("kernel.rtlil.sigspec.has_marked_bits");
3727
3728 pack();
3729 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3730 if (it->width > 0 && it->wire == NULL) {
3731 for (size_t i = 0; i < it->data.size(); i++)
3732 if (it->data[i] == RTLIL::State::Sm)
3733 return true;
3734 }
3735 return false;
3736 }
3737
3738 bool RTLIL::SigSpec::as_bool() const
3739 {
3740 cover("kernel.rtlil.sigspec.as_bool");
3741
3742 pack();
3743 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3744 if (width_)
3745 return RTLIL::Const(chunks_[0].data).as_bool();
3746 return false;
3747 }
3748
3749 int RTLIL::SigSpec::as_int(bool is_signed) const
3750 {
3751 cover("kernel.rtlil.sigspec.as_int");
3752
3753 pack();
3754 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3755 if (width_)
3756 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3757 return 0;
3758 }
3759
3760 std::string RTLIL::SigSpec::as_string() const
3761 {
3762 cover("kernel.rtlil.sigspec.as_string");
3763
3764 pack();
3765 std::string str;
3766 str.reserve(size());
3767 for (size_t i = chunks_.size(); i > 0; i--) {
3768 const RTLIL::SigChunk &chunk = chunks_[i-1];
3769 if (chunk.wire != NULL)
3770 str.append(chunk.width, '?');
3771 else
3772 str += RTLIL::Const(chunk.data).as_string();
3773 }
3774 return str;
3775 }
3776
3777 RTLIL::Const RTLIL::SigSpec::as_const() const
3778 {
3779 cover("kernel.rtlil.sigspec.as_const");
3780
3781 pack();
3782 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3783 if (width_)
3784 return chunks_[0].data;
3785 return RTLIL::Const();
3786 }
3787
3788 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3789 {
3790 cover("kernel.rtlil.sigspec.as_wire");
3791
3792 pack();
3793 log_assert(is_wire());
3794 return chunks_[0].wire;
3795 }
3796
3797 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3798 {
3799 cover("kernel.rtlil.sigspec.as_chunk");
3800
3801 pack();
3802 log_assert(is_chunk());
3803 return chunks_[0];
3804 }
3805
3806 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3807 {
3808 cover("kernel.rtlil.sigspec.as_bit");
3809
3810 log_assert(width_ == 1);
3811 if (packed())
3812 return RTLIL::SigBit(*chunks_.begin());
3813 else
3814 return bits_[0];
3815 }
3816
3817 bool RTLIL::SigSpec::match(const char* pattern) const
3818 {
3819 cover("kernel.rtlil.sigspec.match");
3820
3821 unpack();
3822 log_assert(int(strlen(pattern)) == GetSize(bits_));
3823
3824 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3825 if (*pattern == ' ')
3826 continue;
3827 if (*pattern == '*') {
3828 if (*it != State::Sz && *it != State::Sx)
3829 return false;
3830 continue;
3831 }
3832 if (*pattern == '0') {
3833 if (*it != State::S0)
3834 return false;
3835 } else
3836 if (*pattern == '1') {
3837 if (*it != State::S1)
3838 return false;
3839 } else
3840 log_abort();
3841 }
3842
3843 return true;
3844 }
3845
3846 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3847 {
3848 cover("kernel.rtlil.sigspec.to_sigbit_set");
3849
3850 pack();
3851 std::set<RTLIL::SigBit> sigbits;
3852 for (auto &c : chunks_)
3853 for (int i = 0; i < c.width; i++)
3854 sigbits.insert(RTLIL::SigBit(c, i));
3855 return sigbits;
3856 }
3857
3858 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3859 {
3860 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3861
3862 pack();
3863 pool<RTLIL::SigBit> sigbits;
3864 sigbits.reserve(size());
3865 for (auto &c : chunks_)
3866 for (int i = 0; i < c.width; i++)
3867 sigbits.insert(RTLIL::SigBit(c, i));
3868 return sigbits;
3869 }
3870
3871 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3872 {
3873 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3874
3875 unpack();
3876 return bits_;
3877 }
3878
3879 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3880 {
3881 cover("kernel.rtlil.sigspec.to_sigbit_map");
3882
3883 unpack();
3884 other.unpack();
3885
3886 log_assert(width_ == other.width_);
3887
3888 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3889 for (int i = 0; i < width_; i++)
3890 new_map[bits_[i]] = other.bits_[i];
3891
3892 return new_map;
3893 }
3894
3895 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3896 {
3897 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3898
3899 unpack();
3900 other.unpack();
3901
3902 log_assert(width_ == other.width_);
3903
3904 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3905 new_map.reserve(size());
3906 for (int i = 0; i < width_; i++)
3907 new_map[bits_[i]] = other.bits_[i];
3908
3909 return new_map;
3910 }
3911
3912 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3913 {
3914 size_t start = 0, end = 0;
3915 while ((end = text.find(sep, start)) != std::string::npos) {
3916 tokens.push_back(text.substr(start, end - start));
3917 start = end + 1;
3918 }
3919 tokens.push_back(text.substr(start));
3920 }
3921
3922 static int sigspec_parse_get_dummy_line_num()
3923 {
3924 return 0;
3925 }
3926
3927 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3928 {
3929 cover("kernel.rtlil.sigspec.parse");
3930
3931 AST::current_filename = "input";
3932
3933 std::vector<std::string> tokens;
3934 sigspec_parse_split(tokens, str, ',');
3935
3936 sig = RTLIL::SigSpec();
3937 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3938 {
3939 std::string netname = tokens[tokidx];
3940 std::string indices;
3941
3942 if (netname.size() == 0)
3943 continue;
3944
3945 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3946 cover("kernel.rtlil.sigspec.parse.const");
3947 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3948 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3949 if (ast == NULL)
3950 return false;
3951 sig.append(RTLIL::Const(ast->bits));
3952 delete ast;
3953 continue;
3954 }
3955
3956 if (module == NULL)
3957 return false;
3958
3959 cover("kernel.rtlil.sigspec.parse.net");
3960
3961 if (netname[0] != '$' && netname[0] != '\\')
3962 netname = "\\" + netname;
3963
3964 if (module->wires_.count(netname) == 0) {
3965 size_t indices_pos = netname.size()-1;
3966 if (indices_pos > 2 && netname[indices_pos] == ']')
3967 {
3968 indices_pos--;
3969 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3970 if (indices_pos > 0 && netname[indices_pos] == ':') {
3971 indices_pos--;
3972 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3973 }
3974 if (indices_pos > 0 && netname[indices_pos] == '[') {
3975 indices = netname.substr(indices_pos);
3976 netname = netname.substr(0, indices_pos);
3977 }
3978 }
3979 }
3980
3981 if (module->wires_.count(netname) == 0)
3982 return false;
3983
3984 RTLIL::Wire *wire = module->wires_.at(netname);
3985 if (!indices.empty()) {
3986 std::vector<std::string> index_tokens;
3987 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3988 if (index_tokens.size() == 1) {
3989 cover("kernel.rtlil.sigspec.parse.bit_sel");
3990 int a = atoi(index_tokens.at(0).c_str());
3991 if (a < 0 || a >= wire->width)
3992 return false;
3993 sig.append(RTLIL::SigSpec(wire, a));
3994 } else {
3995 cover("kernel.rtlil.sigspec.parse.part_sel");
3996 int a = atoi(index_tokens.at(0).c_str());
3997 int b = atoi(index_tokens.at(1).c_str());
3998 if (a > b) {
3999 int tmp = a;
4000 a = b, b = tmp;
4001 }
4002 if (a < 0 || a >= wire->width)
4003 return false;
4004 if (b < 0 || b >= wire->width)
4005 return false;
4006 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4007 }
4008 } else
4009 sig.append(wire);
4010 }
4011
4012 return true;
4013 }
4014
4015 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4016 {
4017 if (str.empty() || str[0] != '@')
4018 return parse(sig, module, str);
4019
4020 cover("kernel.rtlil.sigspec.parse.sel");
4021
4022 str = RTLIL::escape_id(str.substr(1));
4023 if (design->selection_vars.count(str) == 0)
4024 return false;
4025
4026 sig = RTLIL::SigSpec();
4027 RTLIL::Selection &sel = design->selection_vars.at(str);
4028 for (auto &it : module->wires_)
4029 if (sel.selected_member(module->name, it.first))
4030 sig.append(it.second);
4031
4032 return true;
4033 }
4034
4035 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4036 {
4037 if (str == "0") {
4038 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4039 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4040 return true;
4041 }
4042
4043 if (str == "~0") {
4044 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4045 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4046 return true;
4047 }
4048
4049 if (lhs.chunks_.size() == 1) {
4050 char *p = (char*)str.c_str(), *endptr;
4051 long int val = strtol(p, &endptr, 10);
4052 if (endptr && endptr != p && *endptr == 0) {
4053 sig = RTLIL::SigSpec(val, lhs.width_);
4054 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4055 return true;
4056 }
4057 }
4058
4059 return parse(sig, module, str);
4060 }
4061
4062 RTLIL::CaseRule::~CaseRule()
4063 {
4064 for (auto it = switches.begin(); it != switches.end(); it++)
4065 delete *it;
4066 }
4067
4068 bool RTLIL::CaseRule::empty() const
4069 {
4070 return actions.empty() && switches.empty();
4071 }
4072
4073 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4074 {
4075 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4076 new_caserule->compare = compare;
4077 new_caserule->actions = actions;
4078 for (auto &it : switches)
4079 new_caserule->switches.push_back(it->clone());
4080 return new_caserule;
4081 }
4082
4083 RTLIL::SwitchRule::~SwitchRule()
4084 {
4085 for (auto it = cases.begin(); it != cases.end(); it++)
4086 delete *it;
4087 }
4088
4089 bool RTLIL::SwitchRule::empty() const
4090 {
4091 return cases.empty();
4092 }
4093
4094 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4095 {
4096 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4097 new_switchrule->signal = signal;
4098 new_switchrule->attributes = attributes;
4099 for (auto &it : cases)
4100 new_switchrule->cases.push_back(it->clone());
4101 return new_switchrule;
4102
4103 }
4104
4105 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4106 {
4107 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4108 new_syncrule->type = type;
4109 new_syncrule->signal = signal;
4110 new_syncrule->actions = actions;
4111 return new_syncrule;
4112 }
4113
4114 RTLIL::Process::~Process()
4115 {
4116 for (auto it = syncs.begin(); it != syncs.end(); it++)
4117 delete *it;
4118 }
4119
4120 RTLIL::Process *RTLIL::Process::clone() const
4121 {
4122 RTLIL::Process *new_proc = new RTLIL::Process;
4123
4124 new_proc->name = name;
4125 new_proc->attributes = attributes;
4126
4127 RTLIL::CaseRule *rc_ptr = root_case.clone();
4128 new_proc->root_case = *rc_ptr;
4129 rc_ptr->switches.clear();
4130 delete rc_ptr;
4131
4132 for (auto &it : syncs)
4133 new_proc->syncs.push_back(it->clone());
4134
4135 return new_proc;
4136 }
4137
4138 #ifdef WITH_PYTHON
4139 RTLIL::Memory::~Memory()
4140 {
4141 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4142 }
4143 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4144 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4145 {
4146 return &all_memorys;
4147 }
4148 #endif
4149 YOSYS_NAMESPACE_END