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Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else if (attributes.count(id))
222 attributes.erase(id);
223 }
224
225 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
226 {
227 if (attributes.count(id) == 0)
228 return false;
229 return attributes.at(id).as_bool();
230 }
231
232 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
233 {
234 string attrval;
235 for (auto &s : data) {
236 if (!attrval.empty())
237 attrval += "|";
238 attrval += s;
239 }
240 attributes[id] = RTLIL::Const(attrval);
241 }
242
243 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
244 {
245 pool<string> union_data = get_strpool_attribute(id);
246 union_data.insert(data.begin(), data.end());
247 if (!union_data.empty())
248 set_strpool_attribute(id, union_data);
249 }
250
251 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
252 {
253 pool<string> data;
254 if (attributes.count(id) != 0)
255 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
256 data.insert(s);
257 return data;
258 }
259
260 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
261 {
262 if (src.empty())
263 attributes.erase("\\src");
264 else
265 attributes["\\src"] = src;
266 }
267
268 std::string RTLIL::AttrObject::get_src_attribute() const
269 {
270 std::string src;
271 if (attributes.count("\\src"))
272 src = attributes.at("\\src").decode_string();
273 return src;
274 }
275
276 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
277 {
278 if (full_selection)
279 return true;
280 if (selected_modules.count(mod_name) > 0)
281 return true;
282 if (selected_members.count(mod_name) > 0)
283 return true;
284 return false;
285 }
286
287 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
288 {
289 if (full_selection)
290 return true;
291 if (selected_modules.count(mod_name) > 0)
292 return true;
293 return false;
294 }
295
296 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
297 {
298 if (full_selection)
299 return true;
300 if (selected_modules.count(mod_name) > 0)
301 return true;
302 if (selected_members.count(mod_name) > 0)
303 if (selected_members.at(mod_name).count(memb_name) > 0)
304 return true;
305 return false;
306 }
307
308 void RTLIL::Selection::optimize(RTLIL::Design *design)
309 {
310 if (full_selection) {
311 selected_modules.clear();
312 selected_members.clear();
313 return;
314 }
315
316 std::vector<RTLIL::IdString> del_list, add_list;
317
318 del_list.clear();
319 for (auto mod_name : selected_modules) {
320 if (design->modules_.count(mod_name) == 0)
321 del_list.push_back(mod_name);
322 selected_members.erase(mod_name);
323 }
324 for (auto mod_name : del_list)
325 selected_modules.erase(mod_name);
326
327 del_list.clear();
328 for (auto &it : selected_members)
329 if (design->modules_.count(it.first) == 0)
330 del_list.push_back(it.first);
331 for (auto mod_name : del_list)
332 selected_members.erase(mod_name);
333
334 for (auto &it : selected_members) {
335 del_list.clear();
336 for (auto memb_name : it.second)
337 if (design->modules_[it.first]->count_id(memb_name) == 0)
338 del_list.push_back(memb_name);
339 for (auto memb_name : del_list)
340 it.second.erase(memb_name);
341 }
342
343 del_list.clear();
344 add_list.clear();
345 for (auto &it : selected_members)
346 if (it.second.size() == 0)
347 del_list.push_back(it.first);
348 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
349 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
350 add_list.push_back(it.first);
351 for (auto mod_name : del_list)
352 selected_members.erase(mod_name);
353 for (auto mod_name : add_list) {
354 selected_members.erase(mod_name);
355 selected_modules.insert(mod_name);
356 }
357
358 if (selected_modules.size() == design->modules_.size()) {
359 full_selection = true;
360 selected_modules.clear();
361 selected_members.clear();
362 }
363 }
364
365 RTLIL::Design::Design()
366 {
367 static unsigned int hashidx_count = 123456789;
368 hashidx_count = mkhash_xorshift(hashidx_count);
369 hashidx_ = hashidx_count;
370
371 refcount_modules_ = 0;
372 selection_stack.push_back(RTLIL::Selection());
373
374 #ifdef WITH_PYTHON
375 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
376 #endif
377 }
378
379 RTLIL::Design::~Design()
380 {
381 for (auto it = modules_.begin(); it != modules_.end(); ++it)
382 delete it->second;
383 for (auto n : verilog_packages)
384 delete n;
385 for (auto n : verilog_globals)
386 delete n;
387 #ifdef WITH_PYTHON
388 RTLIL::Design::get_all_designs()->erase(hashidx_);
389 #endif
390 }
391
392 #ifdef WITH_PYTHON
393 static std::map<unsigned int, RTLIL::Design*> all_designs;
394 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
395 {
396 return &all_designs;
397 }
398 #endif
399
400 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
401 {
402 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
403 }
404
405 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
406 {
407 return modules_.count(name) ? modules_.at(name) : NULL;
408 }
409
410 RTLIL::Module *RTLIL::Design::top_module()
411 {
412 RTLIL::Module *module = nullptr;
413 int module_count = 0;
414
415 for (auto mod : selected_modules()) {
416 if (mod->get_bool_attribute("\\top"))
417 return mod;
418 module_count++;
419 module = mod;
420 }
421
422 return module_count == 1 ? module : nullptr;
423 }
424
425 void RTLIL::Design::add(RTLIL::Module *module)
426 {
427 log_assert(modules_.count(module->name) == 0);
428 log_assert(refcount_modules_ == 0);
429 modules_[module->name] = module;
430 module->design = this;
431
432 for (auto mon : monitors)
433 mon->notify_module_add(module);
434
435 if (yosys_xtrace) {
436 log("#X# New Module: %s\n", log_id(module));
437 log_backtrace("-X- ", yosys_xtrace-1);
438 }
439 }
440
441 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
442 {
443 log_assert(modules_.count(name) == 0);
444 log_assert(refcount_modules_ == 0);
445
446 RTLIL::Module *module = new RTLIL::Module;
447 modules_[name] = module;
448 module->design = this;
449 module->name = name;
450
451 for (auto mon : monitors)
452 mon->notify_module_add(module);
453
454 if (yosys_xtrace) {
455 log("#X# New Module: %s\n", log_id(module));
456 log_backtrace("-X- ", yosys_xtrace-1);
457 }
458
459 return module;
460 }
461
462 void RTLIL::Design::scratchpad_unset(std::string varname)
463 {
464 scratchpad.erase(varname);
465 }
466
467 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
468 {
469 scratchpad[varname] = stringf("%d", value);
470 }
471
472 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
473 {
474 scratchpad[varname] = value ? "true" : "false";
475 }
476
477 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
478 {
479 scratchpad[varname] = value;
480 }
481
482 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
483 {
484 if (scratchpad.count(varname) == 0)
485 return default_value;
486
487 std::string str = scratchpad.at(varname);
488
489 if (str == "0" || str == "false")
490 return 0;
491
492 if (str == "1" || str == "true")
493 return 1;
494
495 char *endptr = nullptr;
496 long int parsed_value = strtol(str.c_str(), &endptr, 10);
497 return *endptr ? default_value : parsed_value;
498 }
499
500 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
501 {
502 if (scratchpad.count(varname) == 0)
503 return default_value;
504
505 std::string str = scratchpad.at(varname);
506
507 if (str == "0" || str == "false")
508 return false;
509
510 if (str == "1" || str == "true")
511 return true;
512
513 return default_value;
514 }
515
516 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
517 {
518 if (scratchpad.count(varname) == 0)
519 return default_value;
520 return scratchpad.at(varname);
521 }
522
523 void RTLIL::Design::remove(RTLIL::Module *module)
524 {
525 for (auto mon : monitors)
526 mon->notify_module_del(module);
527
528 if (yosys_xtrace) {
529 log("#X# Remove Module: %s\n", log_id(module));
530 log_backtrace("-X- ", yosys_xtrace-1);
531 }
532
533 log_assert(modules_.at(module->name) == module);
534 modules_.erase(module->name);
535 delete module;
536 }
537
538 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
539 {
540 modules_.erase(module->name);
541 module->name = new_name;
542 add(module);
543 }
544
545 void RTLIL::Design::sort()
546 {
547 scratchpad.sort();
548 modules_.sort(sort_by_id_str());
549 for (auto &it : modules_)
550 it.second->sort();
551 }
552
553 void RTLIL::Design::check()
554 {
555 #ifndef NDEBUG
556 for (auto &it : modules_) {
557 log_assert(this == it.second->design);
558 log_assert(it.first == it.second->name);
559 log_assert(!it.first.empty());
560 it.second->check();
561 }
562 #endif
563 }
564
565 void RTLIL::Design::optimize()
566 {
567 for (auto &it : modules_)
568 it.second->optimize();
569 for (auto &it : selection_stack)
570 it.optimize(this);
571 for (auto &it : selection_vars)
572 it.second.optimize(this);
573 }
574
575 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
576 {
577 if (!selected_active_module.empty() && mod_name != selected_active_module)
578 return false;
579 if (selection_stack.size() == 0)
580 return true;
581 return selection_stack.back().selected_module(mod_name);
582 }
583
584 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
585 {
586 if (!selected_active_module.empty() && mod_name != selected_active_module)
587 return false;
588 if (selection_stack.size() == 0)
589 return true;
590 return selection_stack.back().selected_whole_module(mod_name);
591 }
592
593 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
594 {
595 if (!selected_active_module.empty() && mod_name != selected_active_module)
596 return false;
597 if (selection_stack.size() == 0)
598 return true;
599 return selection_stack.back().selected_member(mod_name, memb_name);
600 }
601
602 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
603 {
604 return selected_module(mod->name);
605 }
606
607 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
608 {
609 return selected_whole_module(mod->name);
610 }
611
612 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
613 {
614 std::vector<RTLIL::Module*> result;
615 result.reserve(modules_.size());
616 for (auto &it : modules_)
617 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
618 result.push_back(it.second);
619 return result;
620 }
621
622 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
623 {
624 std::vector<RTLIL::Module*> result;
625 result.reserve(modules_.size());
626 for (auto &it : modules_)
627 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
628 result.push_back(it.second);
629 return result;
630 }
631
632 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
633 {
634 std::vector<RTLIL::Module*> result;
635 result.reserve(modules_.size());
636 for (auto &it : modules_)
637 if (it.second->get_blackbox_attribute())
638 continue;
639 else if (selected_whole_module(it.first))
640 result.push_back(it.second);
641 else if (selected_module(it.first))
642 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
643 return result;
644 }
645
646 RTLIL::Module::Module()
647 {
648 static unsigned int hashidx_count = 123456789;
649 hashidx_count = mkhash_xorshift(hashidx_count);
650 hashidx_ = hashidx_count;
651
652 design = nullptr;
653 refcount_wires_ = 0;
654 refcount_cells_ = 0;
655
656 #ifdef WITH_PYTHON
657 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
658 #endif
659 }
660
661 RTLIL::Module::~Module()
662 {
663 for (auto it = wires_.begin(); it != wires_.end(); ++it)
664 delete it->second;
665 for (auto it = memories.begin(); it != memories.end(); ++it)
666 delete it->second;
667 for (auto it = cells_.begin(); it != cells_.end(); ++it)
668 delete it->second;
669 for (auto it = processes.begin(); it != processes.end(); ++it)
670 delete it->second;
671 #ifdef WITH_PYTHON
672 RTLIL::Module::get_all_modules()->erase(hashidx_);
673 #endif
674 }
675
676 #ifdef WITH_PYTHON
677 static std::map<unsigned int, RTLIL::Module*> all_modules;
678 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
679 {
680 return &all_modules;
681 }
682 #endif
683
684 void RTLIL::Module::makeblackbox()
685 {
686 pool<RTLIL::Wire*> delwires;
687
688 for (auto it = wires_.begin(); it != wires_.end(); ++it)
689 if (!it->second->port_input && !it->second->port_output)
690 delwires.insert(it->second);
691
692 for (auto it = memories.begin(); it != memories.end(); ++it)
693 delete it->second;
694 memories.clear();
695
696 for (auto it = cells_.begin(); it != cells_.end(); ++it)
697 delete it->second;
698 cells_.clear();
699
700 for (auto it = processes.begin(); it != processes.end(); ++it)
701 delete it->second;
702 processes.clear();
703
704 remove(delwires);
705 set_bool_attribute("\\blackbox");
706 }
707
708 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
709 {
710 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
711 }
712
713 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
714 {
715 if (mayfail)
716 return RTLIL::IdString();
717 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
718 }
719
720
721 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
722 {
723 if (mayfail)
724 return RTLIL::IdString();
725 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
726 }
727
728 size_t RTLIL::Module::count_id(RTLIL::IdString id)
729 {
730 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
731 }
732
733 #ifndef NDEBUG
734 namespace {
735 struct InternalCellChecker
736 {
737 RTLIL::Module *module;
738 RTLIL::Cell *cell;
739 pool<RTLIL::IdString> expected_params, expected_ports;
740
741 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
742
743 void error(int linenr)
744 {
745 std::stringstream buf;
746 ILANG_BACKEND::dump_cell(buf, " ", cell);
747
748 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
749 module ? module->name.c_str() : "", module ? "." : "",
750 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
751 }
752
753 int param(const char *name)
754 {
755 if (cell->parameters.count(name) == 0)
756 error(__LINE__);
757 expected_params.insert(name);
758 return cell->parameters.at(name).as_int();
759 }
760
761 int param_bool(const char *name)
762 {
763 int v = param(name);
764 if (cell->parameters.at(name).bits.size() > 32)
765 error(__LINE__);
766 if (v != 0 && v != 1)
767 error(__LINE__);
768 return v;
769 }
770
771 void param_bits(const char *name, int width)
772 {
773 param(name);
774 if (int(cell->parameters.at(name).bits.size()) != width)
775 error(__LINE__);
776 }
777
778 void port(const char *name, int width)
779 {
780 if (!cell->hasPort(name))
781 error(__LINE__);
782 if (cell->getPort(name).size() != width)
783 error(__LINE__);
784 expected_ports.insert(name);
785 }
786
787 void check_expected(bool check_matched_sign = true)
788 {
789 for (auto &para : cell->parameters)
790 if (expected_params.count(para.first) == 0)
791 error(__LINE__);
792 for (auto &conn : cell->connections())
793 if (expected_ports.count(conn.first) == 0)
794 error(__LINE__);
795
796 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
797 bool a_is_signed = param("\\A_SIGNED") != 0;
798 bool b_is_signed = param("\\B_SIGNED") != 0;
799 if (a_is_signed != b_is_signed)
800 error(__LINE__);
801 }
802 }
803
804 void check_gate(const char *ports)
805 {
806 if (cell->parameters.size() != 0)
807 error(__LINE__);
808
809 for (const char *p = ports; *p; p++) {
810 char portname[3] = { '\\', *p, 0 };
811 if (!cell->hasPort(portname))
812 error(__LINE__);
813 if (cell->getPort(portname).size() != 1)
814 error(__LINE__);
815 }
816
817 for (auto &conn : cell->connections()) {
818 if (conn.first.size() != 2 || conn.first[0] != '\\')
819 error(__LINE__);
820 if (strchr(ports, conn.first[1]) == NULL)
821 error(__LINE__);
822 }
823 }
824
825 void check()
826 {
827 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
828 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
829 return;
830
831 if (cell->type.in("$not", "$pos", "$neg")) {
832 param_bool("\\A_SIGNED");
833 port("\\A", param("\\A_WIDTH"));
834 port("\\Y", param("\\Y_WIDTH"));
835 check_expected();
836 return;
837 }
838
839 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
840 param_bool("\\A_SIGNED");
841 param_bool("\\B_SIGNED");
842 port("\\A", param("\\A_WIDTH"));
843 port("\\B", param("\\B_WIDTH"));
844 port("\\Y", param("\\Y_WIDTH"));
845 check_expected();
846 return;
847 }
848
849 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
850 param_bool("\\A_SIGNED");
851 port("\\A", param("\\A_WIDTH"));
852 port("\\Y", param("\\Y_WIDTH"));
853 check_expected();
854 return;
855 }
856
857 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
858 param_bool("\\A_SIGNED");
859 param_bool("\\B_SIGNED");
860 port("\\A", param("\\A_WIDTH"));
861 port("\\B", param("\\B_WIDTH"));
862 port("\\Y", param("\\Y_WIDTH"));
863 check_expected(false);
864 return;
865 }
866
867 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
868 param_bool("\\A_SIGNED");
869 param_bool("\\B_SIGNED");
870 port("\\A", param("\\A_WIDTH"));
871 port("\\B", param("\\B_WIDTH"));
872 port("\\Y", param("\\Y_WIDTH"));
873 check_expected();
874 return;
875 }
876
877 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
878 param_bool("\\A_SIGNED");
879 param_bool("\\B_SIGNED");
880 port("\\A", param("\\A_WIDTH"));
881 port("\\B", param("\\B_WIDTH"));
882 port("\\Y", param("\\Y_WIDTH"));
883 check_expected(cell->type != "$pow");
884 return;
885 }
886
887 if (cell->type == "$fa") {
888 port("\\A", param("\\WIDTH"));
889 port("\\B", param("\\WIDTH"));
890 port("\\C", param("\\WIDTH"));
891 port("\\X", param("\\WIDTH"));
892 port("\\Y", param("\\WIDTH"));
893 check_expected();
894 return;
895 }
896
897 if (cell->type == "$lcu") {
898 port("\\P", param("\\WIDTH"));
899 port("\\G", param("\\WIDTH"));
900 port("\\CI", 1);
901 port("\\CO", param("\\WIDTH"));
902 check_expected();
903 return;
904 }
905
906 if (cell->type == "$alu") {
907 param_bool("\\A_SIGNED");
908 param_bool("\\B_SIGNED");
909 port("\\A", param("\\A_WIDTH"));
910 port("\\B", param("\\B_WIDTH"));
911 port("\\CI", 1);
912 port("\\BI", 1);
913 port("\\X", param("\\Y_WIDTH"));
914 port("\\Y", param("\\Y_WIDTH"));
915 port("\\CO", param("\\Y_WIDTH"));
916 check_expected();
917 return;
918 }
919
920 if (cell->type == "$macc") {
921 param("\\CONFIG");
922 param("\\CONFIG_WIDTH");
923 port("\\A", param("\\A_WIDTH"));
924 port("\\B", param("\\B_WIDTH"));
925 port("\\Y", param("\\Y_WIDTH"));
926 check_expected();
927 Macc().from_cell(cell);
928 return;
929 }
930
931 if (cell->type == "$logic_not") {
932 param_bool("\\A_SIGNED");
933 port("\\A", param("\\A_WIDTH"));
934 port("\\Y", param("\\Y_WIDTH"));
935 check_expected();
936 return;
937 }
938
939 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
940 param_bool("\\A_SIGNED");
941 param_bool("\\B_SIGNED");
942 port("\\A", param("\\A_WIDTH"));
943 port("\\B", param("\\B_WIDTH"));
944 port("\\Y", param("\\Y_WIDTH"));
945 check_expected(false);
946 return;
947 }
948
949 if (cell->type == "$slice") {
950 param("\\OFFSET");
951 port("\\A", param("\\A_WIDTH"));
952 port("\\Y", param("\\Y_WIDTH"));
953 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
954 error(__LINE__);
955 check_expected();
956 return;
957 }
958
959 if (cell->type == "$concat") {
960 port("\\A", param("\\A_WIDTH"));
961 port("\\B", param("\\B_WIDTH"));
962 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
963 check_expected();
964 return;
965 }
966
967 if (cell->type == "$mux") {
968 port("\\A", param("\\WIDTH"));
969 port("\\B", param("\\WIDTH"));
970 port("\\S", 1);
971 port("\\Y", param("\\WIDTH"));
972 check_expected();
973 return;
974 }
975
976 if (cell->type == "$pmux") {
977 port("\\A", param("\\WIDTH"));
978 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
979 port("\\S", param("\\S_WIDTH"));
980 port("\\Y", param("\\WIDTH"));
981 check_expected();
982 return;
983 }
984
985 if (cell->type == "$lut") {
986 param("\\LUT");
987 port("\\A", param("\\WIDTH"));
988 port("\\Y", 1);
989 check_expected();
990 return;
991 }
992
993 if (cell->type == "$sop") {
994 param("\\DEPTH");
995 param("\\TABLE");
996 port("\\A", param("\\WIDTH"));
997 port("\\Y", 1);
998 check_expected();
999 return;
1000 }
1001
1002 if (cell->type == "$sr") {
1003 param_bool("\\SET_POLARITY");
1004 param_bool("\\CLR_POLARITY");
1005 port("\\SET", param("\\WIDTH"));
1006 port("\\CLR", param("\\WIDTH"));
1007 port("\\Q", param("\\WIDTH"));
1008 check_expected();
1009 return;
1010 }
1011
1012 if (cell->type == "$ff") {
1013 port("\\D", param("\\WIDTH"));
1014 port("\\Q", param("\\WIDTH"));
1015 check_expected();
1016 return;
1017 }
1018
1019 if (cell->type == "$dff") {
1020 param_bool("\\CLK_POLARITY");
1021 port("\\CLK", 1);
1022 port("\\D", param("\\WIDTH"));
1023 port("\\Q", param("\\WIDTH"));
1024 check_expected();
1025 return;
1026 }
1027
1028 if (cell->type == "$dffe") {
1029 param_bool("\\CLK_POLARITY");
1030 param_bool("\\EN_POLARITY");
1031 port("\\CLK", 1);
1032 port("\\EN", 1);
1033 port("\\D", param("\\WIDTH"));
1034 port("\\Q", param("\\WIDTH"));
1035 check_expected();
1036 return;
1037 }
1038
1039 if (cell->type == "$dffsr") {
1040 param_bool("\\CLK_POLARITY");
1041 param_bool("\\SET_POLARITY");
1042 param_bool("\\CLR_POLARITY");
1043 port("\\CLK", 1);
1044 port("\\SET", param("\\WIDTH"));
1045 port("\\CLR", param("\\WIDTH"));
1046 port("\\D", param("\\WIDTH"));
1047 port("\\Q", param("\\WIDTH"));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == "$adff") {
1053 param_bool("\\CLK_POLARITY");
1054 param_bool("\\ARST_POLARITY");
1055 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1056 port("\\CLK", 1);
1057 port("\\ARST", 1);
1058 port("\\D", param("\\WIDTH"));
1059 port("\\Q", param("\\WIDTH"));
1060 check_expected();
1061 return;
1062 }
1063
1064 if (cell->type == "$dlatch") {
1065 param_bool("\\EN_POLARITY");
1066 port("\\EN", 1);
1067 port("\\D", param("\\WIDTH"));
1068 port("\\Q", param("\\WIDTH"));
1069 check_expected();
1070 return;
1071 }
1072
1073 if (cell->type == "$dlatchsr") {
1074 param_bool("\\EN_POLARITY");
1075 param_bool("\\SET_POLARITY");
1076 param_bool("\\CLR_POLARITY");
1077 port("\\EN", 1);
1078 port("\\SET", param("\\WIDTH"));
1079 port("\\CLR", param("\\WIDTH"));
1080 port("\\D", param("\\WIDTH"));
1081 port("\\Q", param("\\WIDTH"));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == "$fsm") {
1087 param("\\NAME");
1088 param_bool("\\CLK_POLARITY");
1089 param_bool("\\ARST_POLARITY");
1090 param("\\STATE_BITS");
1091 param("\\STATE_NUM");
1092 param("\\STATE_NUM_LOG2");
1093 param("\\STATE_RST");
1094 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1095 param("\\TRANS_NUM");
1096 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1097 port("\\CLK", 1);
1098 port("\\ARST", 1);
1099 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1100 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1101 check_expected();
1102 return;
1103 }
1104
1105 if (cell->type == "$memrd") {
1106 param("\\MEMID");
1107 param_bool("\\CLK_ENABLE");
1108 param_bool("\\CLK_POLARITY");
1109 param_bool("\\TRANSPARENT");
1110 port("\\CLK", 1);
1111 port("\\EN", 1);
1112 port("\\ADDR", param("\\ABITS"));
1113 port("\\DATA", param("\\WIDTH"));
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == "$memwr") {
1119 param("\\MEMID");
1120 param_bool("\\CLK_ENABLE");
1121 param_bool("\\CLK_POLARITY");
1122 param("\\PRIORITY");
1123 port("\\CLK", 1);
1124 port("\\EN", param("\\WIDTH"));
1125 port("\\ADDR", param("\\ABITS"));
1126 port("\\DATA", param("\\WIDTH"));
1127 check_expected();
1128 return;
1129 }
1130
1131 if (cell->type == "$meminit") {
1132 param("\\MEMID");
1133 param("\\PRIORITY");
1134 port("\\ADDR", param("\\ABITS"));
1135 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1136 check_expected();
1137 return;
1138 }
1139
1140 if (cell->type == "$mem") {
1141 param("\\MEMID");
1142 param("\\SIZE");
1143 param("\\OFFSET");
1144 param("\\INIT");
1145 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1146 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1147 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1148 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1149 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1150 port("\\RD_CLK", param("\\RD_PORTS"));
1151 port("\\RD_EN", param("\\RD_PORTS"));
1152 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1153 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1154 port("\\WR_CLK", param("\\WR_PORTS"));
1155 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1156 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1157 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1158 check_expected();
1159 return;
1160 }
1161
1162 if (cell->type == "$tribuf") {
1163 port("\\A", param("\\WIDTH"));
1164 port("\\Y", param("\\WIDTH"));
1165 port("\\EN", 1);
1166 check_expected();
1167 return;
1168 }
1169
1170 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1171 port("\\A", 1);
1172 port("\\EN", 1);
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == "$initstate") {
1178 port("\\Y", 1);
1179 check_expected();
1180 return;
1181 }
1182
1183 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1184 port("\\Y", param("\\WIDTH"));
1185 check_expected();
1186 return;
1187 }
1188
1189 if (cell->type == "$equiv") {
1190 port("\\A", 1);
1191 port("\\B", 1);
1192 port("\\Y", 1);
1193 check_expected();
1194 return;
1195 }
1196
1197 if (cell->type.in("$specify2", "$specify3")) {
1198 param_bool("\\FULL");
1199 param_bool("\\SRC_DST_PEN");
1200 param_bool("\\SRC_DST_POL");
1201 param("\\T_RISE_MIN");
1202 param("\\T_RISE_TYP");
1203 param("\\T_RISE_MAX");
1204 param("\\T_FALL_MIN");
1205 param("\\T_FALL_TYP");
1206 param("\\T_FALL_MAX");
1207 port("\\EN", 1);
1208 port("\\SRC", param("\\SRC_WIDTH"));
1209 port("\\DST", param("\\DST_WIDTH"));
1210 if (cell->type == "$specify3") {
1211 param_bool("\\EDGE_EN");
1212 param_bool("\\EDGE_POL");
1213 param_bool("\\DAT_DST_PEN");
1214 param_bool("\\DAT_DST_POL");
1215 port("\\DAT", param("\\DST_WIDTH"));
1216 }
1217 check_expected();
1218 return;
1219 }
1220
1221 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1222 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1223 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1224 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1225 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1226 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1227 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1228 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1229 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1230 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1231 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1232 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1233 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1234 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1235 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1236
1237 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1238
1239 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1240 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1241 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1242
1243 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1244 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1245 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1246 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1247
1248 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1249 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1250 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1251
1252 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1253 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1254 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1255 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1256
1257 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1258 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1259 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1260 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1261 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1262 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1263 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1264 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1265
1266 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1267 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1268 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1269 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1270 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1271 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1272 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1273 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1274
1275 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1276 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1277
1278 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1279 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1280 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1281 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1282 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1283 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1284 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1285 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1286
1287 error(__LINE__);
1288 }
1289 };
1290 }
1291 #endif
1292
1293 void RTLIL::Module::sort()
1294 {
1295 wires_.sort(sort_by_id_str());
1296 cells_.sort(sort_by_id_str());
1297 avail_parameters.sort(sort_by_id_str());
1298 memories.sort(sort_by_id_str());
1299 processes.sort(sort_by_id_str());
1300 for (auto &it : cells_)
1301 it.second->sort();
1302 for (auto &it : wires_)
1303 it.second->attributes.sort(sort_by_id_str());
1304 for (auto &it : memories)
1305 it.second->attributes.sort(sort_by_id_str());
1306 }
1307
1308 void RTLIL::Module::check()
1309 {
1310 #ifndef NDEBUG
1311 std::vector<bool> ports_declared;
1312 for (auto &it : wires_) {
1313 log_assert(this == it.second->module);
1314 log_assert(it.first == it.second->name);
1315 log_assert(!it.first.empty());
1316 log_assert(it.second->width >= 0);
1317 log_assert(it.second->port_id >= 0);
1318 for (auto &it2 : it.second->attributes)
1319 log_assert(!it2.first.empty());
1320 if (it.second->port_id) {
1321 log_assert(GetSize(ports) >= it.second->port_id);
1322 log_assert(ports.at(it.second->port_id-1) == it.first);
1323 log_assert(it.second->port_input || it.second->port_output);
1324 if (GetSize(ports_declared) < it.second->port_id)
1325 ports_declared.resize(it.second->port_id);
1326 log_assert(ports_declared[it.second->port_id-1] == false);
1327 ports_declared[it.second->port_id-1] = true;
1328 } else
1329 log_assert(!it.second->port_input && !it.second->port_output);
1330 }
1331 for (auto port_declared : ports_declared)
1332 log_assert(port_declared == true);
1333 log_assert(GetSize(ports) == GetSize(ports_declared));
1334
1335 for (auto &it : memories) {
1336 log_assert(it.first == it.second->name);
1337 log_assert(!it.first.empty());
1338 log_assert(it.second->width >= 0);
1339 log_assert(it.second->size >= 0);
1340 for (auto &it2 : it.second->attributes)
1341 log_assert(!it2.first.empty());
1342 }
1343
1344 for (auto &it : cells_) {
1345 log_assert(this == it.second->module);
1346 log_assert(it.first == it.second->name);
1347 log_assert(!it.first.empty());
1348 log_assert(!it.second->type.empty());
1349 for (auto &it2 : it.second->connections()) {
1350 log_assert(!it2.first.empty());
1351 it2.second.check();
1352 }
1353 for (auto &it2 : it.second->attributes)
1354 log_assert(!it2.first.empty());
1355 for (auto &it2 : it.second->parameters)
1356 log_assert(!it2.first.empty());
1357 InternalCellChecker checker(this, it.second);
1358 checker.check();
1359 }
1360
1361 for (auto &it : processes) {
1362 log_assert(it.first == it.second->name);
1363 log_assert(!it.first.empty());
1364 // FIXME: More checks here..
1365 }
1366
1367 for (auto &it : connections_) {
1368 log_assert(it.first.size() == it.second.size());
1369 log_assert(!it.first.has_const());
1370 it.first.check();
1371 it.second.check();
1372 }
1373
1374 for (auto &it : attributes)
1375 log_assert(!it.first.empty());
1376 #endif
1377 }
1378
1379 void RTLIL::Module::optimize()
1380 {
1381 }
1382
1383 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1384 {
1385 log_assert(new_mod->refcount_wires_ == 0);
1386 log_assert(new_mod->refcount_cells_ == 0);
1387
1388 new_mod->avail_parameters = avail_parameters;
1389
1390 for (auto &conn : connections_)
1391 new_mod->connect(conn);
1392
1393 for (auto &attr : attributes)
1394 new_mod->attributes[attr.first] = attr.second;
1395
1396 for (auto &it : wires_)
1397 new_mod->addWire(it.first, it.second);
1398
1399 for (auto &it : memories)
1400 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1401
1402 for (auto &it : cells_)
1403 new_mod->addCell(it.first, it.second);
1404
1405 for (auto &it : processes)
1406 new_mod->processes[it.first] = it.second->clone();
1407
1408 struct RewriteSigSpecWorker
1409 {
1410 RTLIL::Module *mod;
1411 void operator()(RTLIL::SigSpec &sig)
1412 {
1413 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1414 for (auto &c : chunks)
1415 if (c.wire != NULL)
1416 c.wire = mod->wires_.at(c.wire->name);
1417 sig = chunks;
1418 }
1419 };
1420
1421 RewriteSigSpecWorker rewriteSigSpecWorker;
1422 rewriteSigSpecWorker.mod = new_mod;
1423 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1424 new_mod->fixup_ports();
1425 }
1426
1427 RTLIL::Module *RTLIL::Module::clone() const
1428 {
1429 RTLIL::Module *new_mod = new RTLIL::Module;
1430 new_mod->name = name;
1431 cloneInto(new_mod);
1432 return new_mod;
1433 }
1434
1435 bool RTLIL::Module::has_memories() const
1436 {
1437 return !memories.empty();
1438 }
1439
1440 bool RTLIL::Module::has_processes() const
1441 {
1442 return !processes.empty();
1443 }
1444
1445 bool RTLIL::Module::has_memories_warn() const
1446 {
1447 if (!memories.empty())
1448 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1449 return !memories.empty();
1450 }
1451
1452 bool RTLIL::Module::has_processes_warn() const
1453 {
1454 if (!processes.empty())
1455 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1456 return !processes.empty();
1457 }
1458
1459 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1460 {
1461 std::vector<RTLIL::Wire*> result;
1462 result.reserve(wires_.size());
1463 for (auto &it : wires_)
1464 if (design->selected(this, it.second))
1465 result.push_back(it.second);
1466 return result;
1467 }
1468
1469 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1470 {
1471 std::vector<RTLIL::Cell*> result;
1472 result.reserve(wires_.size());
1473 for (auto &it : cells_)
1474 if (design->selected(this, it.second))
1475 result.push_back(it.second);
1476 return result;
1477 }
1478
1479 void RTLIL::Module::add(RTLIL::Wire *wire)
1480 {
1481 log_assert(!wire->name.empty());
1482 log_assert(count_id(wire->name) == 0);
1483 log_assert(refcount_wires_ == 0);
1484 wires_[wire->name] = wire;
1485 wire->module = this;
1486 }
1487
1488 void RTLIL::Module::add(RTLIL::Cell *cell)
1489 {
1490 log_assert(!cell->name.empty());
1491 log_assert(count_id(cell->name) == 0);
1492 log_assert(refcount_cells_ == 0);
1493 cells_[cell->name] = cell;
1494 cell->module = this;
1495 }
1496
1497 namespace {
1498 struct DeleteWireWorker
1499 {
1500 RTLIL::Module *module;
1501 const pool<RTLIL::Wire*> *wires_p;
1502
1503 void operator()(RTLIL::SigSpec &sig) {
1504 std::vector<RTLIL::SigChunk> chunks = sig;
1505 for (auto &c : chunks)
1506 if (c.wire != NULL && wires_p->count(c.wire)) {
1507 c.wire = module->addWire(NEW_ID, c.width);
1508 c.offset = 0;
1509 }
1510 sig = chunks;
1511 }
1512 };
1513 }
1514
1515 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1516 {
1517 log_assert(refcount_wires_ == 0);
1518
1519 DeleteWireWorker delete_wire_worker;
1520 delete_wire_worker.module = this;
1521 delete_wire_worker.wires_p = &wires;
1522 rewrite_sigspecs(delete_wire_worker);
1523
1524 for (auto &it : wires) {
1525 log_assert(wires_.count(it->name) != 0);
1526 wires_.erase(it->name);
1527 delete it;
1528 }
1529 }
1530
1531 void RTLIL::Module::remove(RTLIL::Cell *cell)
1532 {
1533 while (!cell->connections_.empty())
1534 cell->unsetPort(cell->connections_.begin()->first);
1535
1536 log_assert(cells_.count(cell->name) != 0);
1537 log_assert(refcount_cells_ == 0);
1538 cells_.erase(cell->name);
1539 delete cell;
1540 }
1541
1542 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1543 {
1544 log_assert(wires_[wire->name] == wire);
1545 log_assert(refcount_wires_ == 0);
1546 wires_.erase(wire->name);
1547 wire->name = new_name;
1548 add(wire);
1549 }
1550
1551 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1552 {
1553 log_assert(cells_[cell->name] == cell);
1554 log_assert(refcount_wires_ == 0);
1555 cells_.erase(cell->name);
1556 cell->name = new_name;
1557 add(cell);
1558 }
1559
1560 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1561 {
1562 log_assert(count_id(old_name) != 0);
1563 if (wires_.count(old_name))
1564 rename(wires_.at(old_name), new_name);
1565 else if (cells_.count(old_name))
1566 rename(cells_.at(old_name), new_name);
1567 else
1568 log_abort();
1569 }
1570
1571 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1572 {
1573 log_assert(wires_[w1->name] == w1);
1574 log_assert(wires_[w2->name] == w2);
1575 log_assert(refcount_wires_ == 0);
1576
1577 wires_.erase(w1->name);
1578 wires_.erase(w2->name);
1579
1580 std::swap(w1->name, w2->name);
1581
1582 wires_[w1->name] = w1;
1583 wires_[w2->name] = w2;
1584 }
1585
1586 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1587 {
1588 log_assert(cells_[c1->name] == c1);
1589 log_assert(cells_[c2->name] == c2);
1590 log_assert(refcount_cells_ == 0);
1591
1592 cells_.erase(c1->name);
1593 cells_.erase(c2->name);
1594
1595 std::swap(c1->name, c2->name);
1596
1597 cells_[c1->name] = c1;
1598 cells_[c2->name] = c2;
1599 }
1600
1601 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1602 {
1603 int index = 0;
1604 return uniquify(name, index);
1605 }
1606
1607 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1608 {
1609 if (index == 0) {
1610 if (count_id(name) == 0)
1611 return name;
1612 index++;
1613 }
1614
1615 while (1) {
1616 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1617 if (count_id(new_name) == 0)
1618 return new_name;
1619 index++;
1620 }
1621 }
1622
1623 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1624 {
1625 if (a->port_id && !b->port_id)
1626 return true;
1627 if (!a->port_id && b->port_id)
1628 return false;
1629
1630 if (a->port_id == b->port_id)
1631 return a->name < b->name;
1632 return a->port_id < b->port_id;
1633 }
1634
1635 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1636 {
1637 for (auto mon : monitors)
1638 mon->notify_connect(this, conn);
1639
1640 if (design)
1641 for (auto mon : design->monitors)
1642 mon->notify_connect(this, conn);
1643
1644 // ignore all attempts to assign constants to other constants
1645 if (conn.first.has_const()) {
1646 RTLIL::SigSig new_conn;
1647 for (int i = 0; i < GetSize(conn.first); i++)
1648 if (conn.first[i].wire) {
1649 new_conn.first.append(conn.first[i]);
1650 new_conn.second.append(conn.second[i]);
1651 }
1652 if (GetSize(new_conn.first))
1653 connect(new_conn);
1654 return;
1655 }
1656
1657 if (yosys_xtrace) {
1658 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1659 log_backtrace("-X- ", yosys_xtrace-1);
1660 }
1661
1662 log_assert(GetSize(conn.first) == GetSize(conn.second));
1663 connections_.push_back(conn);
1664 }
1665
1666 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1667 {
1668 connect(RTLIL::SigSig(lhs, rhs));
1669 }
1670
1671 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1672 {
1673 for (auto mon : monitors)
1674 mon->notify_connect(this, new_conn);
1675
1676 if (design)
1677 for (auto mon : design->monitors)
1678 mon->notify_connect(this, new_conn);
1679
1680 if (yosys_xtrace) {
1681 log("#X# New connections vector in %s:\n", log_id(this));
1682 for (auto &conn: new_conn)
1683 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1684 log_backtrace("-X- ", yosys_xtrace-1);
1685 }
1686
1687 connections_ = new_conn;
1688 }
1689
1690 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1691 {
1692 return connections_;
1693 }
1694
1695 void RTLIL::Module::fixup_ports()
1696 {
1697 std::vector<RTLIL::Wire*> all_ports;
1698
1699 for (auto &w : wires_)
1700 if (w.second->port_input || w.second->port_output)
1701 all_ports.push_back(w.second);
1702 else
1703 w.second->port_id = 0;
1704
1705 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1706
1707 ports.clear();
1708 for (size_t i = 0; i < all_ports.size(); i++) {
1709 ports.push_back(all_ports[i]->name);
1710 all_ports[i]->port_id = i+1;
1711 }
1712 }
1713
1714 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1715 {
1716 RTLIL::Wire *wire = new RTLIL::Wire;
1717 wire->name = name;
1718 wire->width = width;
1719 add(wire);
1720 return wire;
1721 }
1722
1723 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1724 {
1725 RTLIL::Wire *wire = addWire(name);
1726 wire->width = other->width;
1727 wire->start_offset = other->start_offset;
1728 wire->port_id = other->port_id;
1729 wire->port_input = other->port_input;
1730 wire->port_output = other->port_output;
1731 wire->upto = other->upto;
1732 wire->attributes = other->attributes;
1733 return wire;
1734 }
1735
1736 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1737 {
1738 RTLIL::Cell *cell = new RTLIL::Cell;
1739 cell->name = name;
1740 cell->type = type;
1741 add(cell);
1742 return cell;
1743 }
1744
1745 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1746 {
1747 RTLIL::Cell *cell = addCell(name, other->type);
1748 cell->connections_ = other->connections_;
1749 cell->parameters = other->parameters;
1750 cell->attributes = other->attributes;
1751 return cell;
1752 }
1753
1754 #define DEF_METHOD(_func, _y_size, _type) \
1755 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1756 RTLIL::Cell *cell = addCell(name, _type); \
1757 cell->parameters["\\A_SIGNED"] = is_signed; \
1758 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1759 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1760 cell->setPort("\\A", sig_a); \
1761 cell->setPort("\\Y", sig_y); \
1762 cell->set_src_attribute(src); \
1763 return cell; \
1764 } \
1765 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1766 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1767 add ## _func(name, sig_a, sig_y, is_signed, src); \
1768 return sig_y; \
1769 }
1770 DEF_METHOD(Not, sig_a.size(), "$not")
1771 DEF_METHOD(Pos, sig_a.size(), "$pos")
1772 DEF_METHOD(Neg, sig_a.size(), "$neg")
1773 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1774 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1775 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1776 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1777 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1778 DEF_METHOD(LogicNot, 1, "$logic_not")
1779 #undef DEF_METHOD
1780
1781 #define DEF_METHOD(_func, _y_size, _type) \
1782 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1783 RTLIL::Cell *cell = addCell(name, _type); \
1784 cell->parameters["\\A_SIGNED"] = is_signed; \
1785 cell->parameters["\\B_SIGNED"] = is_signed; \
1786 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1787 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1788 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1789 cell->setPort("\\A", sig_a); \
1790 cell->setPort("\\B", sig_b); \
1791 cell->setPort("\\Y", sig_y); \
1792 cell->set_src_attribute(src); \
1793 return cell; \
1794 } \
1795 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1796 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1797 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1798 return sig_y; \
1799 }
1800 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1801 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1802 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1803 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1804 DEF_METHOD(Shl, sig_a.size(), "$shl")
1805 DEF_METHOD(Shr, sig_a.size(), "$shr")
1806 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1807 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1808 DEF_METHOD(Shift, sig_a.size(), "$shift")
1809 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1810 DEF_METHOD(Lt, 1, "$lt")
1811 DEF_METHOD(Le, 1, "$le")
1812 DEF_METHOD(Eq, 1, "$eq")
1813 DEF_METHOD(Ne, 1, "$ne")
1814 DEF_METHOD(Eqx, 1, "$eqx")
1815 DEF_METHOD(Nex, 1, "$nex")
1816 DEF_METHOD(Ge, 1, "$ge")
1817 DEF_METHOD(Gt, 1, "$gt")
1818 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1819 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1820 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1821 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1822 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1823 DEF_METHOD(LogicAnd, 1, "$logic_and")
1824 DEF_METHOD(LogicOr, 1, "$logic_or")
1825 #undef DEF_METHOD
1826
1827 #define DEF_METHOD(_func, _type, _pmux) \
1828 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1829 RTLIL::Cell *cell = addCell(name, _type); \
1830 cell->parameters["\\WIDTH"] = sig_a.size(); \
1831 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1832 cell->setPort("\\A", sig_a); \
1833 cell->setPort("\\B", sig_b); \
1834 cell->setPort("\\S", sig_s); \
1835 cell->setPort("\\Y", sig_y); \
1836 cell->set_src_attribute(src); \
1837 return cell; \
1838 } \
1839 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1840 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1841 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1842 return sig_y; \
1843 }
1844 DEF_METHOD(Mux, "$mux", 0)
1845 DEF_METHOD(Pmux, "$pmux", 1)
1846 #undef DEF_METHOD
1847
1848 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1849 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1850 RTLIL::Cell *cell = addCell(name, _type); \
1851 cell->setPort("\\" #_P1, sig1); \
1852 cell->setPort("\\" #_P2, sig2); \
1853 cell->set_src_attribute(src); \
1854 return cell; \
1855 } \
1856 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1857 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1858 add ## _func(name, sig1, sig2, src); \
1859 return sig2; \
1860 }
1861 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1862 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1863 RTLIL::Cell *cell = addCell(name, _type); \
1864 cell->setPort("\\" #_P1, sig1); \
1865 cell->setPort("\\" #_P2, sig2); \
1866 cell->setPort("\\" #_P3, sig3); \
1867 cell->set_src_attribute(src); \
1868 return cell; \
1869 } \
1870 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1871 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1872 add ## _func(name, sig1, sig2, sig3, src); \
1873 return sig3; \
1874 }
1875 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1876 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1877 RTLIL::Cell *cell = addCell(name, _type); \
1878 cell->setPort("\\" #_P1, sig1); \
1879 cell->setPort("\\" #_P2, sig2); \
1880 cell->setPort("\\" #_P3, sig3); \
1881 cell->setPort("\\" #_P4, sig4); \
1882 cell->set_src_attribute(src); \
1883 return cell; \
1884 } \
1885 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1886 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1887 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1888 return sig4; \
1889 }
1890 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1891 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1892 RTLIL::Cell *cell = addCell(name, _type); \
1893 cell->setPort("\\" #_P1, sig1); \
1894 cell->setPort("\\" #_P2, sig2); \
1895 cell->setPort("\\" #_P3, sig3); \
1896 cell->setPort("\\" #_P4, sig4); \
1897 cell->setPort("\\" #_P5, sig5); \
1898 cell->set_src_attribute(src); \
1899 return cell; \
1900 } \
1901 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1902 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1903 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1904 return sig5; \
1905 }
1906 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1907 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1908 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1909 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1910 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1911 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1912 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1913 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1914 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1915 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1916 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1917 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1918 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1919 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1920 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1921 #undef DEF_METHOD_2
1922 #undef DEF_METHOD_3
1923 #undef DEF_METHOD_4
1924 #undef DEF_METHOD_5
1925
1926 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1927 {
1928 RTLIL::Cell *cell = addCell(name, "$pow");
1929 cell->parameters["\\A_SIGNED"] = a_signed;
1930 cell->parameters["\\B_SIGNED"] = b_signed;
1931 cell->parameters["\\A_WIDTH"] = sig_a.size();
1932 cell->parameters["\\B_WIDTH"] = sig_b.size();
1933 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1934 cell->setPort("\\A", sig_a);
1935 cell->setPort("\\B", sig_b);
1936 cell->setPort("\\Y", sig_y);
1937 cell->set_src_attribute(src);
1938 return cell;
1939 }
1940
1941 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1942 {
1943 RTLIL::Cell *cell = addCell(name, "$slice");
1944 cell->parameters["\\A_WIDTH"] = sig_a.size();
1945 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1946 cell->parameters["\\OFFSET"] = offset;
1947 cell->setPort("\\A", sig_a);
1948 cell->setPort("\\Y", sig_y);
1949 cell->set_src_attribute(src);
1950 return cell;
1951 }
1952
1953 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1954 {
1955 RTLIL::Cell *cell = addCell(name, "$concat");
1956 cell->parameters["\\A_WIDTH"] = sig_a.size();
1957 cell->parameters["\\B_WIDTH"] = sig_b.size();
1958 cell->setPort("\\A", sig_a);
1959 cell->setPort("\\B", sig_b);
1960 cell->setPort("\\Y", sig_y);
1961 cell->set_src_attribute(src);
1962 return cell;
1963 }
1964
1965 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1966 {
1967 RTLIL::Cell *cell = addCell(name, "$lut");
1968 cell->parameters["\\LUT"] = lut;
1969 cell->parameters["\\WIDTH"] = sig_a.size();
1970 cell->setPort("\\A", sig_a);
1971 cell->setPort("\\Y", sig_y);
1972 cell->set_src_attribute(src);
1973 return cell;
1974 }
1975
1976 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1977 {
1978 RTLIL::Cell *cell = addCell(name, "$tribuf");
1979 cell->parameters["\\WIDTH"] = sig_a.size();
1980 cell->setPort("\\A", sig_a);
1981 cell->setPort("\\EN", sig_en);
1982 cell->setPort("\\Y", sig_y);
1983 cell->set_src_attribute(src);
1984 return cell;
1985 }
1986
1987 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1988 {
1989 RTLIL::Cell *cell = addCell(name, "$assert");
1990 cell->setPort("\\A", sig_a);
1991 cell->setPort("\\EN", sig_en);
1992 cell->set_src_attribute(src);
1993 return cell;
1994 }
1995
1996 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1997 {
1998 RTLIL::Cell *cell = addCell(name, "$assume");
1999 cell->setPort("\\A", sig_a);
2000 cell->setPort("\\EN", sig_en);
2001 cell->set_src_attribute(src);
2002 return cell;
2003 }
2004
2005 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2006 {
2007 RTLIL::Cell *cell = addCell(name, "$live");
2008 cell->setPort("\\A", sig_a);
2009 cell->setPort("\\EN", sig_en);
2010 cell->set_src_attribute(src);
2011 return cell;
2012 }
2013
2014 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2015 {
2016 RTLIL::Cell *cell = addCell(name, "$fair");
2017 cell->setPort("\\A", sig_a);
2018 cell->setPort("\\EN", sig_en);
2019 cell->set_src_attribute(src);
2020 return cell;
2021 }
2022
2023 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2024 {
2025 RTLIL::Cell *cell = addCell(name, "$cover");
2026 cell->setPort("\\A", sig_a);
2027 cell->setPort("\\EN", sig_en);
2028 cell->set_src_attribute(src);
2029 return cell;
2030 }
2031
2032 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2033 {
2034 RTLIL::Cell *cell = addCell(name, "$equiv");
2035 cell->setPort("\\A", sig_a);
2036 cell->setPort("\\B", sig_b);
2037 cell->setPort("\\Y", sig_y);
2038 cell->set_src_attribute(src);
2039 return cell;
2040 }
2041
2042 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2043 {
2044 RTLIL::Cell *cell = addCell(name, "$sr");
2045 cell->parameters["\\SET_POLARITY"] = set_polarity;
2046 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2047 cell->parameters["\\WIDTH"] = sig_q.size();
2048 cell->setPort("\\SET", sig_set);
2049 cell->setPort("\\CLR", sig_clr);
2050 cell->setPort("\\Q", sig_q);
2051 cell->set_src_attribute(src);
2052 return cell;
2053 }
2054
2055 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2056 {
2057 RTLIL::Cell *cell = addCell(name, "$ff");
2058 cell->parameters["\\WIDTH"] = sig_q.size();
2059 cell->setPort("\\D", sig_d);
2060 cell->setPort("\\Q", sig_q);
2061 cell->set_src_attribute(src);
2062 return cell;
2063 }
2064
2065 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2066 {
2067 RTLIL::Cell *cell = addCell(name, "$dff");
2068 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2069 cell->parameters["\\WIDTH"] = sig_q.size();
2070 cell->setPort("\\CLK", sig_clk);
2071 cell->setPort("\\D", sig_d);
2072 cell->setPort("\\Q", sig_q);
2073 cell->set_src_attribute(src);
2074 return cell;
2075 }
2076
2077 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2078 {
2079 RTLIL::Cell *cell = addCell(name, "$dffe");
2080 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2081 cell->parameters["\\EN_POLARITY"] = en_polarity;
2082 cell->parameters["\\WIDTH"] = sig_q.size();
2083 cell->setPort("\\CLK", sig_clk);
2084 cell->setPort("\\EN", sig_en);
2085 cell->setPort("\\D", sig_d);
2086 cell->setPort("\\Q", sig_q);
2087 cell->set_src_attribute(src);
2088 return cell;
2089 }
2090
2091 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2092 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2093 {
2094 RTLIL::Cell *cell = addCell(name, "$dffsr");
2095 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2096 cell->parameters["\\SET_POLARITY"] = set_polarity;
2097 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2098 cell->parameters["\\WIDTH"] = sig_q.size();
2099 cell->setPort("\\CLK", sig_clk);
2100 cell->setPort("\\SET", sig_set);
2101 cell->setPort("\\CLR", sig_clr);
2102 cell->setPort("\\D", sig_d);
2103 cell->setPort("\\Q", sig_q);
2104 cell->set_src_attribute(src);
2105 return cell;
2106 }
2107
2108 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2109 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2110 {
2111 RTLIL::Cell *cell = addCell(name, "$adff");
2112 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2113 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2114 cell->parameters["\\ARST_VALUE"] = arst_value;
2115 cell->parameters["\\WIDTH"] = sig_q.size();
2116 cell->setPort("\\CLK", sig_clk);
2117 cell->setPort("\\ARST", sig_arst);
2118 cell->setPort("\\D", sig_d);
2119 cell->setPort("\\Q", sig_q);
2120 cell->set_src_attribute(src);
2121 return cell;
2122 }
2123
2124 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2125 {
2126 RTLIL::Cell *cell = addCell(name, "$dlatch");
2127 cell->parameters["\\EN_POLARITY"] = en_polarity;
2128 cell->parameters["\\WIDTH"] = sig_q.size();
2129 cell->setPort("\\EN", sig_en);
2130 cell->setPort("\\D", sig_d);
2131 cell->setPort("\\Q", sig_q);
2132 cell->set_src_attribute(src);
2133 return cell;
2134 }
2135
2136 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2137 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2138 {
2139 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2140 cell->parameters["\\EN_POLARITY"] = en_polarity;
2141 cell->parameters["\\SET_POLARITY"] = set_polarity;
2142 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2143 cell->parameters["\\WIDTH"] = sig_q.size();
2144 cell->setPort("\\EN", sig_en);
2145 cell->setPort("\\SET", sig_set);
2146 cell->setPort("\\CLR", sig_clr);
2147 cell->setPort("\\D", sig_d);
2148 cell->setPort("\\Q", sig_q);
2149 cell->set_src_attribute(src);
2150 return cell;
2151 }
2152
2153 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2154 {
2155 RTLIL::Cell *cell = addCell(name, "$_FF_");
2156 cell->setPort("\\D", sig_d);
2157 cell->setPort("\\Q", sig_q);
2158 cell->set_src_attribute(src);
2159 return cell;
2160 }
2161
2162 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2163 {
2164 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2165 cell->setPort("\\C", sig_clk);
2166 cell->setPort("\\D", sig_d);
2167 cell->setPort("\\Q", sig_q);
2168 cell->set_src_attribute(src);
2169 return cell;
2170 }
2171
2172 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2173 {
2174 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2175 cell->setPort("\\C", sig_clk);
2176 cell->setPort("\\E", sig_en);
2177 cell->setPort("\\D", sig_d);
2178 cell->setPort("\\Q", sig_q);
2179 cell->set_src_attribute(src);
2180 return cell;
2181 }
2182
2183 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2184 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2185 {
2186 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2187 cell->setPort("\\C", sig_clk);
2188 cell->setPort("\\S", sig_set);
2189 cell->setPort("\\R", sig_clr);
2190 cell->setPort("\\D", sig_d);
2191 cell->setPort("\\Q", sig_q);
2192 cell->set_src_attribute(src);
2193 return cell;
2194 }
2195
2196 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2197 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2198 {
2199 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2200 cell->setPort("\\C", sig_clk);
2201 cell->setPort("\\R", sig_arst);
2202 cell->setPort("\\D", sig_d);
2203 cell->setPort("\\Q", sig_q);
2204 cell->set_src_attribute(src);
2205 return cell;
2206 }
2207
2208 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2209 {
2210 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2211 cell->setPort("\\E", sig_en);
2212 cell->setPort("\\D", sig_d);
2213 cell->setPort("\\Q", sig_q);
2214 cell->set_src_attribute(src);
2215 return cell;
2216 }
2217
2218 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2219 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2220 {
2221 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2222 cell->setPort("\\E", sig_en);
2223 cell->setPort("\\S", sig_set);
2224 cell->setPort("\\R", sig_clr);
2225 cell->setPort("\\D", sig_d);
2226 cell->setPort("\\Q", sig_q);
2227 cell->set_src_attribute(src);
2228 return cell;
2229 }
2230
2231 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2232 {
2233 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2234 Cell *cell = addCell(name, "$anyconst");
2235 cell->setParam("\\WIDTH", width);
2236 cell->setPort("\\Y", sig);
2237 cell->set_src_attribute(src);
2238 return sig;
2239 }
2240
2241 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2242 {
2243 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2244 Cell *cell = addCell(name, "$anyseq");
2245 cell->setParam("\\WIDTH", width);
2246 cell->setPort("\\Y", sig);
2247 cell->set_src_attribute(src);
2248 return sig;
2249 }
2250
2251 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2252 {
2253 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2254 Cell *cell = addCell(name, "$allconst");
2255 cell->setParam("\\WIDTH", width);
2256 cell->setPort("\\Y", sig);
2257 cell->set_src_attribute(src);
2258 return sig;
2259 }
2260
2261 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2262 {
2263 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2264 Cell *cell = addCell(name, "$allseq");
2265 cell->setParam("\\WIDTH", width);
2266 cell->setPort("\\Y", sig);
2267 cell->set_src_attribute(src);
2268 return sig;
2269 }
2270
2271 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2272 {
2273 RTLIL::SigSpec sig = addWire(NEW_ID);
2274 Cell *cell = addCell(name, "$initstate");
2275 cell->setPort("\\Y", sig);
2276 cell->set_src_attribute(src);
2277 return sig;
2278 }
2279
2280 RTLIL::Wire::Wire()
2281 {
2282 static unsigned int hashidx_count = 123456789;
2283 hashidx_count = mkhash_xorshift(hashidx_count);
2284 hashidx_ = hashidx_count;
2285
2286 module = nullptr;
2287 width = 1;
2288 start_offset = 0;
2289 port_id = 0;
2290 port_input = false;
2291 port_output = false;
2292 upto = false;
2293
2294 #ifdef WITH_PYTHON
2295 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2296 #endif
2297 }
2298
2299 RTLIL::Wire::~Wire()
2300 {
2301 #ifdef WITH_PYTHON
2302 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2303 #endif
2304 }
2305
2306 #ifdef WITH_PYTHON
2307 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2308 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2309 {
2310 return &all_wires;
2311 }
2312 #endif
2313
2314 RTLIL::Memory::Memory()
2315 {
2316 static unsigned int hashidx_count = 123456789;
2317 hashidx_count = mkhash_xorshift(hashidx_count);
2318 hashidx_ = hashidx_count;
2319
2320 width = 1;
2321 start_offset = 0;
2322 size = 0;
2323 #ifdef WITH_PYTHON
2324 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2325 #endif
2326 }
2327
2328 RTLIL::Cell::Cell() : module(nullptr)
2329 {
2330 static unsigned int hashidx_count = 123456789;
2331 hashidx_count = mkhash_xorshift(hashidx_count);
2332 hashidx_ = hashidx_count;
2333
2334 // log("#memtrace# %p\n", this);
2335 memhasher();
2336
2337 #ifdef WITH_PYTHON
2338 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2339 #endif
2340 }
2341
2342 RTLIL::Cell::~Cell()
2343 {
2344 #ifdef WITH_PYTHON
2345 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2346 #endif
2347 }
2348
2349 #ifdef WITH_PYTHON
2350 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2351 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2352 {
2353 return &all_cells;
2354 }
2355 #endif
2356
2357 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2358 {
2359 return connections_.count(portname) != 0;
2360 }
2361
2362 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2363 {
2364 RTLIL::SigSpec signal;
2365 auto conn_it = connections_.find(portname);
2366
2367 if (conn_it != connections_.end())
2368 {
2369 for (auto mon : module->monitors)
2370 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2371
2372 if (module->design)
2373 for (auto mon : module->design->monitors)
2374 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2375
2376 if (yosys_xtrace) {
2377 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2378 log_backtrace("-X- ", yosys_xtrace-1);
2379 }
2380
2381 connections_.erase(conn_it);
2382 }
2383 }
2384
2385 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2386 {
2387 auto conn_it = connections_.find(portname);
2388
2389 if (conn_it == connections_.end()) {
2390 connections_[portname] = RTLIL::SigSpec();
2391 conn_it = connections_.find(portname);
2392 log_assert(conn_it != connections_.end());
2393 } else
2394 if (conn_it->second == signal)
2395 return;
2396
2397 for (auto mon : module->monitors)
2398 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2399
2400 if (module->design)
2401 for (auto mon : module->design->monitors)
2402 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2403
2404 if (yosys_xtrace) {
2405 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2406 log_backtrace("-X- ", yosys_xtrace-1);
2407 }
2408
2409 conn_it->second = signal;
2410 }
2411
2412 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2413 {
2414 return connections_.at(portname);
2415 }
2416
2417 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2418 {
2419 return connections_;
2420 }
2421
2422 bool RTLIL::Cell::known() const
2423 {
2424 if (yosys_celltypes.cell_known(type))
2425 return true;
2426 if (module && module->design && module->design->module(type))
2427 return true;
2428 return false;
2429 }
2430
2431 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2432 {
2433 if (yosys_celltypes.cell_known(type))
2434 return yosys_celltypes.cell_input(type, portname);
2435 if (module && module->design) {
2436 RTLIL::Module *m = module->design->module(type);
2437 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2438 return w && w->port_input;
2439 }
2440 return false;
2441 }
2442
2443 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2444 {
2445 if (yosys_celltypes.cell_known(type))
2446 return yosys_celltypes.cell_output(type, portname);
2447 if (module && module->design) {
2448 RTLIL::Module *m = module->design->module(type);
2449 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2450 return w && w->port_output;
2451 }
2452 return false;
2453 }
2454
2455 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2456 {
2457 return parameters.count(paramname) != 0;
2458 }
2459
2460 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2461 {
2462 parameters.erase(paramname);
2463 }
2464
2465 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2466 {
2467 parameters[paramname] = value;
2468 }
2469
2470 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2471 {
2472 return parameters.at(paramname);
2473 }
2474
2475 void RTLIL::Cell::sort()
2476 {
2477 connections_.sort(sort_by_id_str());
2478 parameters.sort(sort_by_id_str());
2479 attributes.sort(sort_by_id_str());
2480 }
2481
2482 void RTLIL::Cell::check()
2483 {
2484 #ifndef NDEBUG
2485 InternalCellChecker checker(NULL, this);
2486 checker.check();
2487 #endif
2488 }
2489
2490 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2491 {
2492 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2493 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2494 return;
2495
2496 if (type == "$mux" || type == "$pmux") {
2497 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2498 if (type == "$pmux")
2499 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2500 check();
2501 return;
2502 }
2503
2504 if (type == "$lut" || type == "$sop") {
2505 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2506 return;
2507 }
2508
2509 if (type == "$fa") {
2510 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2511 return;
2512 }
2513
2514 if (type == "$lcu") {
2515 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2516 return;
2517 }
2518
2519 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2520
2521 if (connections_.count("\\A")) {
2522 if (signedness_ab) {
2523 if (set_a_signed)
2524 parameters["\\A_SIGNED"] = true;
2525 else if (parameters.count("\\A_SIGNED") == 0)
2526 parameters["\\A_SIGNED"] = false;
2527 }
2528 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2529 }
2530
2531 if (connections_.count("\\B")) {
2532 if (signedness_ab) {
2533 if (set_b_signed)
2534 parameters["\\B_SIGNED"] = true;
2535 else if (parameters.count("\\B_SIGNED") == 0)
2536 parameters["\\B_SIGNED"] = false;
2537 }
2538 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2539 }
2540
2541 if (connections_.count("\\Y"))
2542 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2543
2544 if (connections_.count("\\Q"))
2545 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2546
2547 check();
2548 }
2549
2550 RTLIL::SigChunk::SigChunk()
2551 {
2552 wire = NULL;
2553 width = 0;
2554 offset = 0;
2555 }
2556
2557 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2558 {
2559 wire = NULL;
2560 data = value.bits;
2561 width = GetSize(data);
2562 offset = 0;
2563 }
2564
2565 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2566 {
2567 log_assert(wire != nullptr);
2568 this->wire = wire;
2569 this->width = wire->width;
2570 this->offset = 0;
2571 }
2572
2573 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2574 {
2575 log_assert(wire != nullptr);
2576 this->wire = wire;
2577 this->width = width;
2578 this->offset = offset;
2579 }
2580
2581 RTLIL::SigChunk::SigChunk(const std::string &str)
2582 {
2583 wire = NULL;
2584 data = RTLIL::Const(str).bits;
2585 width = GetSize(data);
2586 offset = 0;
2587 }
2588
2589 RTLIL::SigChunk::SigChunk(int val, int width)
2590 {
2591 wire = NULL;
2592 data = RTLIL::Const(val, width).bits;
2593 this->width = GetSize(data);
2594 offset = 0;
2595 }
2596
2597 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2598 {
2599 wire = NULL;
2600 data = RTLIL::Const(bit, width).bits;
2601 this->width = GetSize(data);
2602 offset = 0;
2603 }
2604
2605 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2606 {
2607 wire = bit.wire;
2608 offset = 0;
2609 if (wire == NULL)
2610 data = RTLIL::Const(bit.data).bits;
2611 else
2612 offset = bit.offset;
2613 width = 1;
2614 }
2615
2616 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2617 {
2618 wire = sigchunk.wire;
2619 data = sigchunk.data;
2620 width = sigchunk.width;
2621 offset = sigchunk.offset;
2622 }
2623
2624 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2625 {
2626 RTLIL::SigChunk ret;
2627 if (wire) {
2628 ret.wire = wire;
2629 ret.offset = this->offset + offset;
2630 ret.width = length;
2631 } else {
2632 for (int i = 0; i < length; i++)
2633 ret.data.push_back(data[offset+i]);
2634 ret.width = length;
2635 }
2636 return ret;
2637 }
2638
2639 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2640 {
2641 if (wire && other.wire)
2642 if (wire->name != other.wire->name)
2643 return wire->name < other.wire->name;
2644
2645 if (wire != other.wire)
2646 return wire < other.wire;
2647
2648 if (offset != other.offset)
2649 return offset < other.offset;
2650
2651 if (width != other.width)
2652 return width < other.width;
2653
2654 return data < other.data;
2655 }
2656
2657 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2658 {
2659 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2660 }
2661
2662 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2663 {
2664 if (*this == other)
2665 return false;
2666 return true;
2667 }
2668
2669 RTLIL::SigSpec::SigSpec()
2670 {
2671 width_ = 0;
2672 hash_ = 0;
2673 }
2674
2675 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2676 {
2677 *this = other;
2678 }
2679
2680 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2681 {
2682 cover("kernel.rtlil.sigspec.init.list");
2683
2684 width_ = 0;
2685 hash_ = 0;
2686
2687 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2688 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2689 append(*it);
2690 }
2691
2692 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2693 {
2694 cover("kernel.rtlil.sigspec.assign");
2695
2696 width_ = other.width_;
2697 hash_ = other.hash_;
2698 chunks_ = other.chunks_;
2699 bits_.clear();
2700
2701 if (!other.bits_.empty())
2702 {
2703 RTLIL::SigChunk *last = NULL;
2704 int last_end_offset = 0;
2705
2706 for (auto &bit : other.bits_) {
2707 if (last && bit.wire == last->wire) {
2708 if (bit.wire == NULL) {
2709 last->data.push_back(bit.data);
2710 last->width++;
2711 continue;
2712 } else if (last_end_offset == bit.offset) {
2713 last_end_offset++;
2714 last->width++;
2715 continue;
2716 }
2717 }
2718 chunks_.push_back(bit);
2719 last = &chunks_.back();
2720 last_end_offset = bit.offset + 1;
2721 }
2722
2723 check();
2724 }
2725
2726 return *this;
2727 }
2728
2729 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2730 {
2731 cover("kernel.rtlil.sigspec.init.const");
2732
2733 chunks_.push_back(RTLIL::SigChunk(value));
2734 width_ = chunks_.back().width;
2735 hash_ = 0;
2736 check();
2737 }
2738
2739 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2740 {
2741 cover("kernel.rtlil.sigspec.init.chunk");
2742
2743 chunks_.push_back(chunk);
2744 width_ = chunks_.back().width;
2745 hash_ = 0;
2746 check();
2747 }
2748
2749 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2750 {
2751 cover("kernel.rtlil.sigspec.init.wire");
2752
2753 chunks_.push_back(RTLIL::SigChunk(wire));
2754 width_ = chunks_.back().width;
2755 hash_ = 0;
2756 check();
2757 }
2758
2759 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2760 {
2761 cover("kernel.rtlil.sigspec.init.wire_part");
2762
2763 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2764 width_ = chunks_.back().width;
2765 hash_ = 0;
2766 check();
2767 }
2768
2769 RTLIL::SigSpec::SigSpec(const std::string &str)
2770 {
2771 cover("kernel.rtlil.sigspec.init.str");
2772
2773 chunks_.push_back(RTLIL::SigChunk(str));
2774 width_ = chunks_.back().width;
2775 hash_ = 0;
2776 check();
2777 }
2778
2779 RTLIL::SigSpec::SigSpec(int val, int width)
2780 {
2781 cover("kernel.rtlil.sigspec.init.int");
2782
2783 chunks_.push_back(RTLIL::SigChunk(val, width));
2784 width_ = width;
2785 hash_ = 0;
2786 check();
2787 }
2788
2789 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2790 {
2791 cover("kernel.rtlil.sigspec.init.state");
2792
2793 chunks_.push_back(RTLIL::SigChunk(bit, width));
2794 width_ = width;
2795 hash_ = 0;
2796 check();
2797 }
2798
2799 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2800 {
2801 cover("kernel.rtlil.sigspec.init.bit");
2802
2803 if (bit.wire == NULL)
2804 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2805 else
2806 for (int i = 0; i < width; i++)
2807 chunks_.push_back(bit);
2808 width_ = width;
2809 hash_ = 0;
2810 check();
2811 }
2812
2813 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2814 {
2815 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2816
2817 width_ = 0;
2818 hash_ = 0;
2819 for (auto &c : chunks)
2820 append(c);
2821 check();
2822 }
2823
2824 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2825 {
2826 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2827
2828 width_ = 0;
2829 hash_ = 0;
2830 for (auto &bit : bits)
2831 append_bit(bit);
2832 check();
2833 }
2834
2835 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2836 {
2837 cover("kernel.rtlil.sigspec.init.pool_bits");
2838
2839 width_ = 0;
2840 hash_ = 0;
2841 for (auto &bit : bits)
2842 append_bit(bit);
2843 check();
2844 }
2845
2846 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2847 {
2848 cover("kernel.rtlil.sigspec.init.stdset_bits");
2849
2850 width_ = 0;
2851 hash_ = 0;
2852 for (auto &bit : bits)
2853 append_bit(bit);
2854 check();
2855 }
2856
2857 RTLIL::SigSpec::SigSpec(bool bit)
2858 {
2859 cover("kernel.rtlil.sigspec.init.bool");
2860
2861 width_ = 0;
2862 hash_ = 0;
2863 append_bit(bit);
2864 check();
2865 }
2866
2867 void RTLIL::SigSpec::pack() const
2868 {
2869 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2870
2871 if (that->bits_.empty())
2872 return;
2873
2874 cover("kernel.rtlil.sigspec.convert.pack");
2875 log_assert(that->chunks_.empty());
2876
2877 std::vector<RTLIL::SigBit> old_bits;
2878 old_bits.swap(that->bits_);
2879
2880 RTLIL::SigChunk *last = NULL;
2881 int last_end_offset = 0;
2882
2883 for (auto &bit : old_bits) {
2884 if (last && bit.wire == last->wire) {
2885 if (bit.wire == NULL) {
2886 last->data.push_back(bit.data);
2887 last->width++;
2888 continue;
2889 } else if (last_end_offset == bit.offset) {
2890 last_end_offset++;
2891 last->width++;
2892 continue;
2893 }
2894 }
2895 that->chunks_.push_back(bit);
2896 last = &that->chunks_.back();
2897 last_end_offset = bit.offset + 1;
2898 }
2899
2900 check();
2901 }
2902
2903 void RTLIL::SigSpec::unpack() const
2904 {
2905 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2906
2907 if (that->chunks_.empty())
2908 return;
2909
2910 cover("kernel.rtlil.sigspec.convert.unpack");
2911 log_assert(that->bits_.empty());
2912
2913 that->bits_.reserve(that->width_);
2914 for (auto &c : that->chunks_)
2915 for (int i = 0; i < c.width; i++)
2916 that->bits_.push_back(RTLIL::SigBit(c, i));
2917
2918 that->chunks_.clear();
2919 that->hash_ = 0;
2920 }
2921
2922 void RTLIL::SigSpec::updhash() const
2923 {
2924 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2925
2926 if (that->hash_ != 0)
2927 return;
2928
2929 cover("kernel.rtlil.sigspec.hash");
2930 that->pack();
2931
2932 that->hash_ = mkhash_init;
2933 for (auto &c : that->chunks_)
2934 if (c.wire == NULL) {
2935 for (auto &v : c.data)
2936 that->hash_ = mkhash(that->hash_, v);
2937 } else {
2938 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2939 that->hash_ = mkhash(that->hash_, c.offset);
2940 that->hash_ = mkhash(that->hash_, c.width);
2941 }
2942
2943 if (that->hash_ == 0)
2944 that->hash_ = 1;
2945 }
2946
2947 void RTLIL::SigSpec::sort()
2948 {
2949 unpack();
2950 cover("kernel.rtlil.sigspec.sort");
2951 std::sort(bits_.begin(), bits_.end());
2952 }
2953
2954 void RTLIL::SigSpec::sort_and_unify()
2955 {
2956 unpack();
2957 cover("kernel.rtlil.sigspec.sort_and_unify");
2958
2959 // A copy of the bits vector is used to prevent duplicating the logic from
2960 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2961 // that isn't showing up as significant in profiles.
2962 std::vector<SigBit> unique_bits = bits_;
2963 std::sort(unique_bits.begin(), unique_bits.end());
2964 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2965 unique_bits.erase(last, unique_bits.end());
2966
2967 *this = unique_bits;
2968 }
2969
2970 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2971 {
2972 replace(pattern, with, this);
2973 }
2974
2975 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2976 {
2977 log_assert(other != NULL);
2978 log_assert(width_ == other->width_);
2979 log_assert(pattern.width_ == with.width_);
2980
2981 pattern.unpack();
2982 with.unpack();
2983 unpack();
2984 other->unpack();
2985
2986 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2987 if (pattern.bits_[i].wire != NULL) {
2988 for (int j = 0; j < GetSize(bits_); j++) {
2989 if (bits_[j] == pattern.bits_[i]) {
2990 other->bits_[j] = with.bits_[i];
2991 }
2992 }
2993 }
2994 }
2995
2996 other->check();
2997 }
2998
2999 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3000 {
3001 replace(rules, this);
3002 }
3003
3004 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3005 {
3006 cover("kernel.rtlil.sigspec.replace_dict");
3007
3008 log_assert(other != NULL);
3009 log_assert(width_ == other->width_);
3010
3011 unpack();
3012 other->unpack();
3013
3014 for (int i = 0; i < GetSize(bits_); i++) {
3015 auto it = rules.find(bits_[i]);
3016 if (it != rules.end())
3017 other->bits_[i] = it->second;
3018 }
3019
3020 other->check();
3021 }
3022
3023 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3024 {
3025 replace(rules, this);
3026 }
3027
3028 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3029 {
3030 cover("kernel.rtlil.sigspec.replace_map");
3031
3032 log_assert(other != NULL);
3033 log_assert(width_ == other->width_);
3034
3035 unpack();
3036 other->unpack();
3037
3038 for (int i = 0; i < GetSize(bits_); i++) {
3039 auto it = rules.find(bits_[i]);
3040 if (it != rules.end())
3041 other->bits_[i] = it->second;
3042 }
3043
3044 other->check();
3045 }
3046
3047 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3048 {
3049 remove2(pattern, NULL);
3050 }
3051
3052 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3053 {
3054 RTLIL::SigSpec tmp = *this;
3055 tmp.remove2(pattern, other);
3056 }
3057
3058 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3059 {
3060 if (other)
3061 cover("kernel.rtlil.sigspec.remove_other");
3062 else
3063 cover("kernel.rtlil.sigspec.remove");
3064
3065 unpack();
3066 if (other != NULL) {
3067 log_assert(width_ == other->width_);
3068 other->unpack();
3069 }
3070
3071 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3072 {
3073 if (bits_[i].wire == NULL) continue;
3074
3075 for (auto &pattern_chunk : pattern.chunks())
3076 if (bits_[i].wire == pattern_chunk.wire &&
3077 bits_[i].offset >= pattern_chunk.offset &&
3078 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3079 bits_.erase(bits_.begin() + i);
3080 width_--;
3081 if (other != NULL) {
3082 other->bits_.erase(other->bits_.begin() + i);
3083 other->width_--;
3084 }
3085 break;
3086 }
3087 }
3088
3089 check();
3090 }
3091
3092 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3093 {
3094 remove2(pattern, NULL);
3095 }
3096
3097 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3098 {
3099 RTLIL::SigSpec tmp = *this;
3100 tmp.remove2(pattern, other);
3101 }
3102
3103 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3104 {
3105 if (other)
3106 cover("kernel.rtlil.sigspec.remove_other");
3107 else
3108 cover("kernel.rtlil.sigspec.remove");
3109
3110 unpack();
3111
3112 if (other != NULL) {
3113 log_assert(width_ == other->width_);
3114 other->unpack();
3115 }
3116
3117 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3118 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3119 bits_.erase(bits_.begin() + i);
3120 width_--;
3121 if (other != NULL) {
3122 other->bits_.erase(other->bits_.begin() + i);
3123 other->width_--;
3124 }
3125 }
3126 }
3127
3128 check();
3129 }
3130
3131 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3132 {
3133 if (other)
3134 cover("kernel.rtlil.sigspec.remove_other");
3135 else
3136 cover("kernel.rtlil.sigspec.remove");
3137
3138 unpack();
3139
3140 if (other != NULL) {
3141 log_assert(width_ == other->width_);
3142 other->unpack();
3143 }
3144
3145 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3146 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3147 bits_.erase(bits_.begin() + i);
3148 width_--;
3149 if (other != NULL) {
3150 other->bits_.erase(other->bits_.begin() + i);
3151 other->width_--;
3152 }
3153 }
3154 }
3155
3156 check();
3157 }
3158
3159 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3160 {
3161 if (other)
3162 cover("kernel.rtlil.sigspec.extract_other");
3163 else
3164 cover("kernel.rtlil.sigspec.extract");
3165
3166 log_assert(other == NULL || width_ == other->width_);
3167
3168 RTLIL::SigSpec ret;
3169 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3170
3171 for (auto& pattern_chunk : pattern.chunks()) {
3172 if (other) {
3173 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3174 for (int i = 0; i < width_; i++)
3175 if (bits_match[i].wire &&
3176 bits_match[i].wire == pattern_chunk.wire &&
3177 bits_match[i].offset >= pattern_chunk.offset &&
3178 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3179 ret.append_bit(bits_other[i]);
3180 } else {
3181 for (int i = 0; i < width_; i++)
3182 if (bits_match[i].wire &&
3183 bits_match[i].wire == pattern_chunk.wire &&
3184 bits_match[i].offset >= pattern_chunk.offset &&
3185 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3186 ret.append_bit(bits_match[i]);
3187 }
3188 }
3189
3190 ret.check();
3191 return ret;
3192 }
3193
3194 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3195 {
3196 if (other)
3197 cover("kernel.rtlil.sigspec.extract_other");
3198 else
3199 cover("kernel.rtlil.sigspec.extract");
3200
3201 log_assert(other == NULL || width_ == other->width_);
3202
3203 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3204 RTLIL::SigSpec ret;
3205
3206 if (other) {
3207 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3208 for (int i = 0; i < width_; i++)
3209 if (bits_match[i].wire && pattern.count(bits_match[i]))
3210 ret.append_bit(bits_other[i]);
3211 } else {
3212 for (int i = 0; i < width_; i++)
3213 if (bits_match[i].wire && pattern.count(bits_match[i]))
3214 ret.append_bit(bits_match[i]);
3215 }
3216
3217 ret.check();
3218 return ret;
3219 }
3220
3221 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3222 {
3223 cover("kernel.rtlil.sigspec.replace_pos");
3224
3225 unpack();
3226 with.unpack();
3227
3228 log_assert(offset >= 0);
3229 log_assert(with.width_ >= 0);
3230 log_assert(offset+with.width_ <= width_);
3231
3232 for (int i = 0; i < with.width_; i++)
3233 bits_.at(offset + i) = with.bits_.at(i);
3234
3235 check();
3236 }
3237
3238 void RTLIL::SigSpec::remove_const()
3239 {
3240 if (packed())
3241 {
3242 cover("kernel.rtlil.sigspec.remove_const.packed");
3243
3244 std::vector<RTLIL::SigChunk> new_chunks;
3245 new_chunks.reserve(GetSize(chunks_));
3246
3247 width_ = 0;
3248 for (auto &chunk : chunks_)
3249 if (chunk.wire != NULL) {
3250 new_chunks.push_back(chunk);
3251 width_ += chunk.width;
3252 }
3253
3254 chunks_.swap(new_chunks);
3255 }
3256 else
3257 {
3258 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3259
3260 std::vector<RTLIL::SigBit> new_bits;
3261 new_bits.reserve(width_);
3262
3263 for (auto &bit : bits_)
3264 if (bit.wire != NULL)
3265 new_bits.push_back(bit);
3266
3267 bits_.swap(new_bits);
3268 width_ = bits_.size();
3269 }
3270
3271 check();
3272 }
3273
3274 void RTLIL::SigSpec::remove(int offset, int length)
3275 {
3276 cover("kernel.rtlil.sigspec.remove_pos");
3277
3278 unpack();
3279
3280 log_assert(offset >= 0);
3281 log_assert(length >= 0);
3282 log_assert(offset + length <= width_);
3283
3284 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3285 width_ = bits_.size();
3286
3287 check();
3288 }
3289
3290 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3291 {
3292 unpack();
3293 cover("kernel.rtlil.sigspec.extract_pos");
3294 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3295 }
3296
3297 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3298 {
3299 if (signal.width_ == 0)
3300 return;
3301
3302 if (width_ == 0) {
3303 *this = signal;
3304 return;
3305 }
3306
3307 cover("kernel.rtlil.sigspec.append");
3308
3309 if (packed() != signal.packed()) {
3310 pack();
3311 signal.pack();
3312 }
3313
3314 if (packed())
3315 for (auto &other_c : signal.chunks_)
3316 {
3317 auto &my_last_c = chunks_.back();
3318 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3319 auto &this_data = my_last_c.data;
3320 auto &other_data = other_c.data;
3321 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3322 my_last_c.width += other_c.width;
3323 } else
3324 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3325 my_last_c.width += other_c.width;
3326 } else
3327 chunks_.push_back(other_c);
3328 }
3329 else
3330 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3331
3332 width_ += signal.width_;
3333 check();
3334 }
3335
3336 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3337 {
3338 if (packed())
3339 {
3340 cover("kernel.rtlil.sigspec.append_bit.packed");
3341
3342 if (chunks_.size() == 0)
3343 chunks_.push_back(bit);
3344 else
3345 if (bit.wire == NULL)
3346 if (chunks_.back().wire == NULL) {
3347 chunks_.back().data.push_back(bit.data);
3348 chunks_.back().width++;
3349 } else
3350 chunks_.push_back(bit);
3351 else
3352 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3353 chunks_.back().width++;
3354 else
3355 chunks_.push_back(bit);
3356 }
3357 else
3358 {
3359 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3360 bits_.push_back(bit);
3361 }
3362
3363 width_++;
3364 check();
3365 }
3366
3367 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3368 {
3369 cover("kernel.rtlil.sigspec.extend_u0");
3370
3371 pack();
3372
3373 if (width_ > width)
3374 remove(width, width_ - width);
3375
3376 if (width_ < width) {
3377 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3378 if (!is_signed)
3379 padding = RTLIL::State::S0;
3380 while (width_ < width)
3381 append(padding);
3382 }
3383
3384 }
3385
3386 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3387 {
3388 cover("kernel.rtlil.sigspec.repeat");
3389
3390 RTLIL::SigSpec sig;
3391 for (int i = 0; i < num; i++)
3392 sig.append(*this);
3393 return sig;
3394 }
3395
3396 #ifndef NDEBUG
3397 void RTLIL::SigSpec::check() const
3398 {
3399 if (width_ > 64)
3400 {
3401 cover("kernel.rtlil.sigspec.check.skip");
3402 }
3403 else if (packed())
3404 {
3405 cover("kernel.rtlil.sigspec.check.packed");
3406
3407 int w = 0;
3408 for (size_t i = 0; i < chunks_.size(); i++) {
3409 const RTLIL::SigChunk chunk = chunks_[i];
3410 if (chunk.wire == NULL) {
3411 if (i > 0)
3412 log_assert(chunks_[i-1].wire != NULL);
3413 log_assert(chunk.offset == 0);
3414 log_assert(chunk.data.size() == (size_t)chunk.width);
3415 } else {
3416 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3417 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3418 log_assert(chunk.offset >= 0);
3419 log_assert(chunk.width >= 0);
3420 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3421 log_assert(chunk.data.size() == 0);
3422 }
3423 w += chunk.width;
3424 }
3425 log_assert(w == width_);
3426 log_assert(bits_.empty());
3427 }
3428 else
3429 {
3430 cover("kernel.rtlil.sigspec.check.unpacked");
3431
3432 log_assert(width_ == GetSize(bits_));
3433 log_assert(chunks_.empty());
3434 }
3435 }
3436 #endif
3437
3438 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3439 {
3440 cover("kernel.rtlil.sigspec.comp_lt");
3441
3442 if (this == &other)
3443 return false;
3444
3445 if (width_ != other.width_)
3446 return width_ < other.width_;
3447
3448 pack();
3449 other.pack();
3450
3451 if (chunks_.size() != other.chunks_.size())
3452 return chunks_.size() < other.chunks_.size();
3453
3454 updhash();
3455 other.updhash();
3456
3457 if (hash_ != other.hash_)
3458 return hash_ < other.hash_;
3459
3460 for (size_t i = 0; i < chunks_.size(); i++)
3461 if (chunks_[i] != other.chunks_[i]) {
3462 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3463 return chunks_[i] < other.chunks_[i];
3464 }
3465
3466 cover("kernel.rtlil.sigspec.comp_lt.equal");
3467 return false;
3468 }
3469
3470 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3471 {
3472 cover("kernel.rtlil.sigspec.comp_eq");
3473
3474 if (this == &other)
3475 return true;
3476
3477 if (width_ != other.width_)
3478 return false;
3479
3480 pack();
3481 other.pack();
3482
3483 if (chunks_.size() != chunks_.size())
3484 return false;
3485
3486 updhash();
3487 other.updhash();
3488
3489 if (hash_ != other.hash_)
3490 return false;
3491
3492 for (size_t i = 0; i < chunks_.size(); i++)
3493 if (chunks_[i] != other.chunks_[i]) {
3494 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3495 return false;
3496 }
3497
3498 cover("kernel.rtlil.sigspec.comp_eq.equal");
3499 return true;
3500 }
3501
3502 bool RTLIL::SigSpec::is_wire() const
3503 {
3504 cover("kernel.rtlil.sigspec.is_wire");
3505
3506 pack();
3507 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3508 }
3509
3510 bool RTLIL::SigSpec::is_chunk() const
3511 {
3512 cover("kernel.rtlil.sigspec.is_chunk");
3513
3514 pack();
3515 return GetSize(chunks_) == 1;
3516 }
3517
3518 bool RTLIL::SigSpec::is_fully_const() const
3519 {
3520 cover("kernel.rtlil.sigspec.is_fully_const");
3521
3522 pack();
3523 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3524 if (it->width > 0 && it->wire != NULL)
3525 return false;
3526 return true;
3527 }
3528
3529 bool RTLIL::SigSpec::is_fully_zero() const
3530 {
3531 cover("kernel.rtlil.sigspec.is_fully_zero");
3532
3533 pack();
3534 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3535 if (it->width > 0 && it->wire != NULL)
3536 return false;
3537 for (size_t i = 0; i < it->data.size(); i++)
3538 if (it->data[i] != RTLIL::State::S0)
3539 return false;
3540 }
3541 return true;
3542 }
3543
3544 bool RTLIL::SigSpec::is_fully_ones() const
3545 {
3546 cover("kernel.rtlil.sigspec.is_fully_ones");
3547
3548 pack();
3549 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3550 if (it->width > 0 && it->wire != NULL)
3551 return false;
3552 for (size_t i = 0; i < it->data.size(); i++)
3553 if (it->data[i] != RTLIL::State::S1)
3554 return false;
3555 }
3556 return true;
3557 }
3558
3559 bool RTLIL::SigSpec::is_fully_def() const
3560 {
3561 cover("kernel.rtlil.sigspec.is_fully_def");
3562
3563 pack();
3564 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3565 if (it->width > 0 && it->wire != NULL)
3566 return false;
3567 for (size_t i = 0; i < it->data.size(); i++)
3568 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3569 return false;
3570 }
3571 return true;
3572 }
3573
3574 bool RTLIL::SigSpec::is_fully_undef() const
3575 {
3576 cover("kernel.rtlil.sigspec.is_fully_undef");
3577
3578 pack();
3579 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3580 if (it->width > 0 && it->wire != NULL)
3581 return false;
3582 for (size_t i = 0; i < it->data.size(); i++)
3583 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3584 return false;
3585 }
3586 return true;
3587 }
3588
3589 bool RTLIL::SigSpec::has_const() const
3590 {
3591 cover("kernel.rtlil.sigspec.has_const");
3592
3593 pack();
3594 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3595 if (it->width > 0 && it->wire == NULL)
3596 return true;
3597 return false;
3598 }
3599
3600 bool RTLIL::SigSpec::has_marked_bits() const
3601 {
3602 cover("kernel.rtlil.sigspec.has_marked_bits");
3603
3604 pack();
3605 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3606 if (it->width > 0 && it->wire == NULL) {
3607 for (size_t i = 0; i < it->data.size(); i++)
3608 if (it->data[i] == RTLIL::State::Sm)
3609 return true;
3610 }
3611 return false;
3612 }
3613
3614 bool RTLIL::SigSpec::as_bool() const
3615 {
3616 cover("kernel.rtlil.sigspec.as_bool");
3617
3618 pack();
3619 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3620 if (width_)
3621 return RTLIL::Const(chunks_[0].data).as_bool();
3622 return false;
3623 }
3624
3625 int RTLIL::SigSpec::as_int(bool is_signed) const
3626 {
3627 cover("kernel.rtlil.sigspec.as_int");
3628
3629 pack();
3630 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3631 if (width_)
3632 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3633 return 0;
3634 }
3635
3636 std::string RTLIL::SigSpec::as_string() const
3637 {
3638 cover("kernel.rtlil.sigspec.as_string");
3639
3640 pack();
3641 std::string str;
3642 for (size_t i = chunks_.size(); i > 0; i--) {
3643 const RTLIL::SigChunk &chunk = chunks_[i-1];
3644 if (chunk.wire != NULL)
3645 for (int j = 0; j < chunk.width; j++)
3646 str += "?";
3647 else
3648 str += RTLIL::Const(chunk.data).as_string();
3649 }
3650 return str;
3651 }
3652
3653 RTLIL::Const RTLIL::SigSpec::as_const() const
3654 {
3655 cover("kernel.rtlil.sigspec.as_const");
3656
3657 pack();
3658 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3659 if (width_)
3660 return chunks_[0].data;
3661 return RTLIL::Const();
3662 }
3663
3664 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3665 {
3666 cover("kernel.rtlil.sigspec.as_wire");
3667
3668 pack();
3669 log_assert(is_wire());
3670 return chunks_[0].wire;
3671 }
3672
3673 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3674 {
3675 cover("kernel.rtlil.sigspec.as_chunk");
3676
3677 pack();
3678 log_assert(is_chunk());
3679 return chunks_[0];
3680 }
3681
3682 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3683 {
3684 cover("kernel.rtlil.sigspec.as_bit");
3685
3686 log_assert(width_ == 1);
3687 if (packed())
3688 return RTLIL::SigBit(*chunks_.begin());
3689 else
3690 return bits_[0];
3691 }
3692
3693 bool RTLIL::SigSpec::match(std::string pattern) const
3694 {
3695 cover("kernel.rtlil.sigspec.match");
3696
3697 pack();
3698 std::string str = as_string();
3699 log_assert(pattern.size() == str.size());
3700
3701 for (size_t i = 0; i < pattern.size(); i++) {
3702 if (pattern[i] == ' ')
3703 continue;
3704 if (pattern[i] == '*') {
3705 if (str[i] != 'z' && str[i] != 'x')
3706 return false;
3707 continue;
3708 }
3709 if (pattern[i] != str[i])
3710 return false;
3711 }
3712
3713 return true;
3714 }
3715
3716 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3717 {
3718 cover("kernel.rtlil.sigspec.to_sigbit_set");
3719
3720 pack();
3721 std::set<RTLIL::SigBit> sigbits;
3722 for (auto &c : chunks_)
3723 for (int i = 0; i < c.width; i++)
3724 sigbits.insert(RTLIL::SigBit(c, i));
3725 return sigbits;
3726 }
3727
3728 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3729 {
3730 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3731
3732 pack();
3733 pool<RTLIL::SigBit> sigbits;
3734 for (auto &c : chunks_)
3735 for (int i = 0; i < c.width; i++)
3736 sigbits.insert(RTLIL::SigBit(c, i));
3737 return sigbits;
3738 }
3739
3740 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3741 {
3742 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3743
3744 unpack();
3745 return bits_;
3746 }
3747
3748 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3749 {
3750 cover("kernel.rtlil.sigspec.to_sigbit_map");
3751
3752 unpack();
3753 other.unpack();
3754
3755 log_assert(width_ == other.width_);
3756
3757 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3758 for (int i = 0; i < width_; i++)
3759 new_map[bits_[i]] = other.bits_[i];
3760
3761 return new_map;
3762 }
3763
3764 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3765 {
3766 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3767
3768 unpack();
3769 other.unpack();
3770
3771 log_assert(width_ == other.width_);
3772
3773 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3774 for (int i = 0; i < width_; i++)
3775 new_map[bits_[i]] = other.bits_[i];
3776
3777 return new_map;
3778 }
3779
3780 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3781 {
3782 size_t start = 0, end = 0;
3783 while ((end = text.find(sep, start)) != std::string::npos) {
3784 tokens.push_back(text.substr(start, end - start));
3785 start = end + 1;
3786 }
3787 tokens.push_back(text.substr(start));
3788 }
3789
3790 static int sigspec_parse_get_dummy_line_num()
3791 {
3792 return 0;
3793 }
3794
3795 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3796 {
3797 cover("kernel.rtlil.sigspec.parse");
3798
3799 AST::current_filename = "input";
3800 AST::use_internal_line_num();
3801 AST::set_line_num(0);
3802
3803 std::vector<std::string> tokens;
3804 sigspec_parse_split(tokens, str, ',');
3805
3806 sig = RTLIL::SigSpec();
3807 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3808 {
3809 std::string netname = tokens[tokidx];
3810 std::string indices;
3811
3812 if (netname.size() == 0)
3813 continue;
3814
3815 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3816 cover("kernel.rtlil.sigspec.parse.const");
3817 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3818 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3819 if (ast == NULL)
3820 return false;
3821 sig.append(RTLIL::Const(ast->bits));
3822 delete ast;
3823 continue;
3824 }
3825
3826 if (module == NULL)
3827 return false;
3828
3829 cover("kernel.rtlil.sigspec.parse.net");
3830
3831 if (netname[0] != '$' && netname[0] != '\\')
3832 netname = "\\" + netname;
3833
3834 if (module->wires_.count(netname) == 0) {
3835 size_t indices_pos = netname.size()-1;
3836 if (indices_pos > 2 && netname[indices_pos] == ']')
3837 {
3838 indices_pos--;
3839 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3840 if (indices_pos > 0 && netname[indices_pos] == ':') {
3841 indices_pos--;
3842 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3843 }
3844 if (indices_pos > 0 && netname[indices_pos] == '[') {
3845 indices = netname.substr(indices_pos);
3846 netname = netname.substr(0, indices_pos);
3847 }
3848 }
3849 }
3850
3851 if (module->wires_.count(netname) == 0)
3852 return false;
3853
3854 RTLIL::Wire *wire = module->wires_.at(netname);
3855 if (!indices.empty()) {
3856 std::vector<std::string> index_tokens;
3857 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3858 if (index_tokens.size() == 1) {
3859 cover("kernel.rtlil.sigspec.parse.bit_sel");
3860 int a = atoi(index_tokens.at(0).c_str());
3861 if (a < 0 || a >= wire->width)
3862 return false;
3863 sig.append(RTLIL::SigSpec(wire, a));
3864 } else {
3865 cover("kernel.rtlil.sigspec.parse.part_sel");
3866 int a = atoi(index_tokens.at(0).c_str());
3867 int b = atoi(index_tokens.at(1).c_str());
3868 if (a > b) {
3869 int tmp = a;
3870 a = b, b = tmp;
3871 }
3872 if (a < 0 || a >= wire->width)
3873 return false;
3874 if (b < 0 || b >= wire->width)
3875 return false;
3876 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3877 }
3878 } else
3879 sig.append(wire);
3880 }
3881
3882 return true;
3883 }
3884
3885 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3886 {
3887 if (str.empty() || str[0] != '@')
3888 return parse(sig, module, str);
3889
3890 cover("kernel.rtlil.sigspec.parse.sel");
3891
3892 str = RTLIL::escape_id(str.substr(1));
3893 if (design->selection_vars.count(str) == 0)
3894 return false;
3895
3896 sig = RTLIL::SigSpec();
3897 RTLIL::Selection &sel = design->selection_vars.at(str);
3898 for (auto &it : module->wires_)
3899 if (sel.selected_member(module->name, it.first))
3900 sig.append(it.second);
3901
3902 return true;
3903 }
3904
3905 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3906 {
3907 if (str == "0") {
3908 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3909 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3910 return true;
3911 }
3912
3913 if (str == "~0") {
3914 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3915 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3916 return true;
3917 }
3918
3919 if (lhs.chunks_.size() == 1) {
3920 char *p = (char*)str.c_str(), *endptr;
3921 long int val = strtol(p, &endptr, 10);
3922 if (endptr && endptr != p && *endptr == 0) {
3923 sig = RTLIL::SigSpec(val, lhs.width_);
3924 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3925 return true;
3926 }
3927 }
3928
3929 return parse(sig, module, str);
3930 }
3931
3932 RTLIL::CaseRule::~CaseRule()
3933 {
3934 for (auto it = switches.begin(); it != switches.end(); it++)
3935 delete *it;
3936 }
3937
3938 bool RTLIL::CaseRule::empty() const
3939 {
3940 return actions.empty() && switches.empty();
3941 }
3942
3943 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3944 {
3945 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3946 new_caserule->compare = compare;
3947 new_caserule->actions = actions;
3948 for (auto &it : switches)
3949 new_caserule->switches.push_back(it->clone());
3950 return new_caserule;
3951 }
3952
3953 RTLIL::SwitchRule::~SwitchRule()
3954 {
3955 for (auto it = cases.begin(); it != cases.end(); it++)
3956 delete *it;
3957 }
3958
3959 bool RTLIL::SwitchRule::empty() const
3960 {
3961 return cases.empty();
3962 }
3963
3964 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3965 {
3966 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3967 new_switchrule->signal = signal;
3968 new_switchrule->attributes = attributes;
3969 for (auto &it : cases)
3970 new_switchrule->cases.push_back(it->clone());
3971 return new_switchrule;
3972
3973 }
3974
3975 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3976 {
3977 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3978 new_syncrule->type = type;
3979 new_syncrule->signal = signal;
3980 new_syncrule->actions = actions;
3981 return new_syncrule;
3982 }
3983
3984 RTLIL::Process::~Process()
3985 {
3986 for (auto it = syncs.begin(); it != syncs.end(); it++)
3987 delete *it;
3988 }
3989
3990 RTLIL::Process *RTLIL::Process::clone() const
3991 {
3992 RTLIL::Process *new_proc = new RTLIL::Process;
3993
3994 new_proc->name = name;
3995 new_proc->attributes = attributes;
3996
3997 RTLIL::CaseRule *rc_ptr = root_case.clone();
3998 new_proc->root_case = *rc_ptr;
3999 rc_ptr->switches.clear();
4000 delete rc_ptr;
4001
4002 for (auto &it : syncs)
4003 new_proc->syncs.push_back(it->clone());
4004
4005 return new_proc;
4006 }
4007
4008 #ifdef WITH_PYTHON
4009 RTLIL::Memory::~Memory()
4010 {
4011 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4012 }
4013 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4014 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4015 {
4016 return &all_memorys;
4017 }
4018 #endif
4019 YOSYS_NAMESPACE_END