2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
31 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
32 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
36 int RTLIL::IdString::last_created_idx_
[8];
37 int RTLIL::IdString::last_created_idx_ptr_
;
41 flags
= RTLIL::CONST_FLAG_NONE
;
44 RTLIL::Const::Const(std::string str
)
46 flags
= RTLIL::CONST_FLAG_STRING
;
47 for (int i
= str
.size()-1; i
>= 0; i
--) {
48 unsigned char ch
= str
[i
];
49 for (int j
= 0; j
< 8; j
++) {
50 bits
.push_back((ch
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
56 RTLIL::Const::Const(int val
, int width
)
58 flags
= RTLIL::CONST_FLAG_NONE
;
59 for (int i
= 0; i
< width
; i
++) {
60 bits
.push_back((val
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
65 RTLIL::Const::Const(RTLIL::State bit
, int width
)
67 flags
= RTLIL::CONST_FLAG_NONE
;
68 for (int i
= 0; i
< width
; i
++)
72 RTLIL::Const::Const(const std::vector
<bool> &bits
)
74 flags
= RTLIL::CONST_FLAG_NONE
;
76 this->bits
.push_back(b
? RTLIL::S1
: RTLIL::S0
);
79 RTLIL::Const::Const(const RTLIL::Const
&c
)
83 this->bits
.push_back(b
);
86 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
88 if (bits
.size() != other
.bits
.size())
89 return bits
.size() < other
.bits
.size();
90 for (size_t i
= 0; i
< bits
.size(); i
++)
91 if (bits
[i
] != other
.bits
[i
])
92 return bits
[i
] < other
.bits
[i
];
96 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
98 return bits
== other
.bits
;
101 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
103 return bits
!= other
.bits
;
106 bool RTLIL::Const::as_bool() const
108 for (size_t i
= 0; i
< bits
.size(); i
++)
109 if (bits
[i
] == RTLIL::S1
)
114 int RTLIL::Const::as_int(bool is_signed
) const
117 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
118 if (bits
[i
] == RTLIL::S1
)
120 if (is_signed
&& bits
.back() == RTLIL::S1
)
121 for (size_t i
= bits
.size(); i
< 32; i
++)
126 std::string
RTLIL::Const::as_string() const
129 for (size_t i
= bits
.size(); i
> 0; i
--)
131 case S0
: ret
+= "0"; break;
132 case S1
: ret
+= "1"; break;
133 case Sx
: ret
+= "x"; break;
134 case Sz
: ret
+= "z"; break;
135 case Sa
: ret
+= "-"; break;
136 case Sm
: ret
+= "m"; break;
141 RTLIL::Const
RTLIL::Const::from_string(std::string str
)
144 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
146 case '0': c
.bits
.push_back(State::S0
); break;
147 case '1': c
.bits
.push_back(State::S1
); break;
148 case 'x': c
.bits
.push_back(State::Sx
); break;
149 case 'z': c
.bits
.push_back(State::Sz
); break;
150 case 'm': c
.bits
.push_back(State::Sm
); break;
151 default: c
.bits
.push_back(State::Sa
);
156 std::string
RTLIL::Const::decode_string() const
159 std::vector
<char> string_chars
;
160 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
162 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
163 if (bits
[i
+ j
] == RTLIL::State::S1
)
166 string_chars
.push_back(ch
);
168 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
169 string
+= string_chars
[i
];
173 bool RTLIL::Const::is_fully_zero() const
175 cover("kernel.rtlil.const.is_fully_zero");
177 for (auto bit
: bits
)
178 if (bit
!= RTLIL::State::S0
)
184 bool RTLIL::Const::is_fully_ones() const
186 cover("kernel.rtlil.const.is_fully_ones");
188 for (auto bit
: bits
)
189 if (bit
!= RTLIL::State::S1
)
195 bool RTLIL::Const::is_fully_def() const
197 cover("kernel.rtlil.const.is_fully_def");
199 for (auto bit
: bits
)
200 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
206 bool RTLIL::Const::is_fully_undef() const
208 cover("kernel.rtlil.const.is_fully_undef");
210 for (auto bit
: bits
)
211 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
220 attributes
[id
] = RTLIL::Const(1);
221 else if (attributes
.count(id
))
222 attributes
.erase(id
);
225 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
227 if (attributes
.count(id
) == 0)
229 return attributes
.at(id
).as_bool();
232 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
235 for (auto &s
: data
) {
236 if (!attrval
.empty())
240 attributes
[id
] = RTLIL::Const(attrval
);
243 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
245 pool
<string
> union_data
= get_strpool_attribute(id
);
246 union_data
.insert(data
.begin(), data
.end());
247 if (!union_data
.empty())
248 set_strpool_attribute(id
, union_data
);
251 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
254 if (attributes
.count(id
) != 0)
255 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
260 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
263 attributes
.erase("\\src");
265 attributes
["\\src"] = src
;
268 std::string
RTLIL::AttrObject::get_src_attribute() const
271 if (attributes
.count("\\src"))
272 src
= attributes
.at("\\src").decode_string();
276 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
280 if (selected_modules
.count(mod_name
) > 0)
282 if (selected_members
.count(mod_name
) > 0)
287 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
291 if (selected_modules
.count(mod_name
) > 0)
296 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
300 if (selected_modules
.count(mod_name
) > 0)
302 if (selected_members
.count(mod_name
) > 0)
303 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
308 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
310 if (full_selection
) {
311 selected_modules
.clear();
312 selected_members
.clear();
316 std::vector
<RTLIL::IdString
> del_list
, add_list
;
319 for (auto mod_name
: selected_modules
) {
320 if (design
->modules_
.count(mod_name
) == 0)
321 del_list
.push_back(mod_name
);
322 selected_members
.erase(mod_name
);
324 for (auto mod_name
: del_list
)
325 selected_modules
.erase(mod_name
);
328 for (auto &it
: selected_members
)
329 if (design
->modules_
.count(it
.first
) == 0)
330 del_list
.push_back(it
.first
);
331 for (auto mod_name
: del_list
)
332 selected_members
.erase(mod_name
);
334 for (auto &it
: selected_members
) {
336 for (auto memb_name
: it
.second
)
337 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
338 del_list
.push_back(memb_name
);
339 for (auto memb_name
: del_list
)
340 it
.second
.erase(memb_name
);
345 for (auto &it
: selected_members
)
346 if (it
.second
.size() == 0)
347 del_list
.push_back(it
.first
);
348 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
349 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
350 add_list
.push_back(it
.first
);
351 for (auto mod_name
: del_list
)
352 selected_members
.erase(mod_name
);
353 for (auto mod_name
: add_list
) {
354 selected_members
.erase(mod_name
);
355 selected_modules
.insert(mod_name
);
358 if (selected_modules
.size() == design
->modules_
.size()) {
359 full_selection
= true;
360 selected_modules
.clear();
361 selected_members
.clear();
365 RTLIL::Design::Design()
367 static unsigned int hashidx_count
= 123456789;
368 hashidx_count
= mkhash_xorshift(hashidx_count
);
369 hashidx_
= hashidx_count
;
371 refcount_modules_
= 0;
372 selection_stack
.push_back(RTLIL::Selection());
375 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
379 RTLIL::Design::~Design()
381 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
383 for (auto n
: verilog_packages
)
385 for (auto n
: verilog_globals
)
388 RTLIL::Design::get_all_designs()->erase(hashidx_
);
393 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
394 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
400 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
402 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
405 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
407 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
410 RTLIL::Module
*RTLIL::Design::top_module()
412 RTLIL::Module
*module
= nullptr;
413 int module_count
= 0;
415 for (auto mod
: selected_modules()) {
416 if (mod
->get_bool_attribute("\\top"))
422 return module_count
== 1 ? module
: nullptr;
425 void RTLIL::Design::add(RTLIL::Module
*module
)
427 log_assert(modules_
.count(module
->name
) == 0);
428 log_assert(refcount_modules_
== 0);
429 modules_
[module
->name
] = module
;
430 module
->design
= this;
432 for (auto mon
: monitors
)
433 mon
->notify_module_add(module
);
436 log("#X# New Module: %s\n", log_id(module
));
437 log_backtrace("-X- ", yosys_xtrace
-1);
441 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
443 log_assert(modules_
.count(name
) == 0);
444 log_assert(refcount_modules_
== 0);
446 RTLIL::Module
*module
= new RTLIL::Module
;
447 modules_
[name
] = module
;
448 module
->design
= this;
451 for (auto mon
: monitors
)
452 mon
->notify_module_add(module
);
455 log("#X# New Module: %s\n", log_id(module
));
456 log_backtrace("-X- ", yosys_xtrace
-1);
462 void RTLIL::Design::scratchpad_unset(std::string varname
)
464 scratchpad
.erase(varname
);
467 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
469 scratchpad
[varname
] = stringf("%d", value
);
472 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
474 scratchpad
[varname
] = value
? "true" : "false";
477 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
479 scratchpad
[varname
] = value
;
482 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
484 if (scratchpad
.count(varname
) == 0)
485 return default_value
;
487 std::string str
= scratchpad
.at(varname
);
489 if (str
== "0" || str
== "false")
492 if (str
== "1" || str
== "true")
495 char *endptr
= nullptr;
496 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
497 return *endptr
? default_value
: parsed_value
;
500 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
502 if (scratchpad
.count(varname
) == 0)
503 return default_value
;
505 std::string str
= scratchpad
.at(varname
);
507 if (str
== "0" || str
== "false")
510 if (str
== "1" || str
== "true")
513 return default_value
;
516 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
518 if (scratchpad
.count(varname
) == 0)
519 return default_value
;
520 return scratchpad
.at(varname
);
523 void RTLIL::Design::remove(RTLIL::Module
*module
)
525 for (auto mon
: monitors
)
526 mon
->notify_module_del(module
);
529 log("#X# Remove Module: %s\n", log_id(module
));
530 log_backtrace("-X- ", yosys_xtrace
-1);
533 log_assert(modules_
.at(module
->name
) == module
);
534 modules_
.erase(module
->name
);
538 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
540 modules_
.erase(module
->name
);
541 module
->name
= new_name
;
545 void RTLIL::Design::sort()
548 modules_
.sort(sort_by_id_str());
549 for (auto &it
: modules_
)
553 void RTLIL::Design::check()
556 for (auto &it
: modules_
) {
557 log_assert(this == it
.second
->design
);
558 log_assert(it
.first
== it
.second
->name
);
559 log_assert(!it
.first
.empty());
565 void RTLIL::Design::optimize()
567 for (auto &it
: modules_
)
568 it
.second
->optimize();
569 for (auto &it
: selection_stack
)
571 for (auto &it
: selection_vars
)
572 it
.second
.optimize(this);
575 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
577 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
579 if (selection_stack
.size() == 0)
581 return selection_stack
.back().selected_module(mod_name
);
584 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
586 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
588 if (selection_stack
.size() == 0)
590 return selection_stack
.back().selected_whole_module(mod_name
);
593 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
595 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
597 if (selection_stack
.size() == 0)
599 return selection_stack
.back().selected_member(mod_name
, memb_name
);
602 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
604 return selected_module(mod
->name
);
607 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
609 return selected_whole_module(mod
->name
);
612 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
614 std::vector
<RTLIL::Module
*> result
;
615 result
.reserve(modules_
.size());
616 for (auto &it
: modules_
)
617 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
618 result
.push_back(it
.second
);
622 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
624 std::vector
<RTLIL::Module
*> result
;
625 result
.reserve(modules_
.size());
626 for (auto &it
: modules_
)
627 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
628 result
.push_back(it
.second
);
632 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
634 std::vector
<RTLIL::Module
*> result
;
635 result
.reserve(modules_
.size());
636 for (auto &it
: modules_
)
637 if (it
.second
->get_blackbox_attribute())
639 else if (selected_whole_module(it
.first
))
640 result
.push_back(it
.second
);
641 else if (selected_module(it
.first
))
642 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
646 RTLIL::Module::Module()
648 static unsigned int hashidx_count
= 123456789;
649 hashidx_count
= mkhash_xorshift(hashidx_count
);
650 hashidx_
= hashidx_count
;
657 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
661 RTLIL::Module::~Module()
663 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
665 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
667 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
669 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
672 RTLIL::Module::get_all_modules()->erase(hashidx_
);
677 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
678 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
684 void RTLIL::Module::makeblackbox()
686 pool
<RTLIL::Wire
*> delwires
;
688 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
689 if (!it
->second
->port_input
&& !it
->second
->port_output
)
690 delwires
.insert(it
->second
);
692 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
696 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
700 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
705 set_bool_attribute("\\blackbox");
708 void RTLIL::Module::reprocess_module(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Module
*>)
710 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
713 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, bool mayfail
)
716 return RTLIL::IdString();
717 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
721 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, dict
<RTLIL::IdString
, RTLIL::Module
*>, dict
<RTLIL::IdString
, RTLIL::IdString
>, bool mayfail
)
724 return RTLIL::IdString();
725 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
728 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
730 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
735 struct InternalCellChecker
737 RTLIL::Module
*module
;
739 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
741 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
743 void error(int linenr
)
745 std::stringstream buf
;
746 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
748 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
749 module
? module
->name
.c_str() : "", module
? "." : "",
750 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
753 int param(const char *name
)
755 if (cell
->parameters
.count(name
) == 0)
757 expected_params
.insert(name
);
758 return cell
->parameters
.at(name
).as_int();
761 int param_bool(const char *name
)
764 if (cell
->parameters
.at(name
).bits
.size() > 32)
766 if (v
!= 0 && v
!= 1)
771 void param_bits(const char *name
, int width
)
774 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
778 void port(const char *name
, int width
)
780 if (!cell
->hasPort(name
))
782 if (cell
->getPort(name
).size() != width
)
784 expected_ports
.insert(name
);
787 void check_expected(bool check_matched_sign
= true)
789 for (auto ¶
: cell
->parameters
)
790 if (expected_params
.count(para
.first
) == 0)
792 for (auto &conn
: cell
->connections())
793 if (expected_ports
.count(conn
.first
) == 0)
796 if (expected_params
.count("\\A_SIGNED") != 0 && expected_params
.count("\\B_SIGNED") && check_matched_sign
) {
797 bool a_is_signed
= param("\\A_SIGNED") != 0;
798 bool b_is_signed
= param("\\B_SIGNED") != 0;
799 if (a_is_signed
!= b_is_signed
)
804 void check_gate(const char *ports
)
806 if (cell
->parameters
.size() != 0)
809 for (const char *p
= ports
; *p
; p
++) {
810 char portname
[3] = { '\\', *p
, 0 };
811 if (!cell
->hasPort(portname
))
813 if (cell
->getPort(portname
).size() != 1)
817 for (auto &conn
: cell
->connections()) {
818 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
820 if (strchr(ports
, conn
.first
[1]) == NULL
)
827 if (cell
->type
.substr(0, 1) != "$" || cell
->type
.substr(0, 3) == "$__" || cell
->type
.substr(0, 8) == "$paramod" || cell
->type
.substr(0,10) == "$fmcombine" ||
828 cell
->type
.substr(0, 9) == "$verific$" || cell
->type
.substr(0, 7) == "$array:" || cell
->type
.substr(0, 8) == "$extern:")
831 if (cell
->type
.in("$not", "$pos", "$neg")) {
832 param_bool("\\A_SIGNED");
833 port("\\A", param("\\A_WIDTH"));
834 port("\\Y", param("\\Y_WIDTH"));
839 if (cell
->type
.in("$and", "$or", "$xor", "$xnor")) {
840 param_bool("\\A_SIGNED");
841 param_bool("\\B_SIGNED");
842 port("\\A", param("\\A_WIDTH"));
843 port("\\B", param("\\B_WIDTH"));
844 port("\\Y", param("\\Y_WIDTH"));
849 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
850 param_bool("\\A_SIGNED");
851 port("\\A", param("\\A_WIDTH"));
852 port("\\Y", param("\\Y_WIDTH"));
857 if (cell
->type
.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
858 param_bool("\\A_SIGNED");
859 param_bool("\\B_SIGNED");
860 port("\\A", param("\\A_WIDTH"));
861 port("\\B", param("\\B_WIDTH"));
862 port("\\Y", param("\\Y_WIDTH"));
863 check_expected(false);
867 if (cell
->type
.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
868 param_bool("\\A_SIGNED");
869 param_bool("\\B_SIGNED");
870 port("\\A", param("\\A_WIDTH"));
871 port("\\B", param("\\B_WIDTH"));
872 port("\\Y", param("\\Y_WIDTH"));
877 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
878 param_bool("\\A_SIGNED");
879 param_bool("\\B_SIGNED");
880 port("\\A", param("\\A_WIDTH"));
881 port("\\B", param("\\B_WIDTH"));
882 port("\\Y", param("\\Y_WIDTH"));
883 check_expected(cell
->type
!= "$pow");
887 if (cell
->type
== "$fa") {
888 port("\\A", param("\\WIDTH"));
889 port("\\B", param("\\WIDTH"));
890 port("\\C", param("\\WIDTH"));
891 port("\\X", param("\\WIDTH"));
892 port("\\Y", param("\\WIDTH"));
897 if (cell
->type
== "$lcu") {
898 port("\\P", param("\\WIDTH"));
899 port("\\G", param("\\WIDTH"));
901 port("\\CO", param("\\WIDTH"));
906 if (cell
->type
== "$alu") {
907 param_bool("\\A_SIGNED");
908 param_bool("\\B_SIGNED");
909 port("\\A", param("\\A_WIDTH"));
910 port("\\B", param("\\B_WIDTH"));
913 port("\\X", param("\\Y_WIDTH"));
914 port("\\Y", param("\\Y_WIDTH"));
915 port("\\CO", param("\\Y_WIDTH"));
920 if (cell
->type
== "$macc") {
922 param("\\CONFIG_WIDTH");
923 port("\\A", param("\\A_WIDTH"));
924 port("\\B", param("\\B_WIDTH"));
925 port("\\Y", param("\\Y_WIDTH"));
927 Macc().from_cell(cell
);
931 if (cell
->type
== "$logic_not") {
932 param_bool("\\A_SIGNED");
933 port("\\A", param("\\A_WIDTH"));
934 port("\\Y", param("\\Y_WIDTH"));
939 if (cell
->type
== "$logic_and" || cell
->type
== "$logic_or") {
940 param_bool("\\A_SIGNED");
941 param_bool("\\B_SIGNED");
942 port("\\A", param("\\A_WIDTH"));
943 port("\\B", param("\\B_WIDTH"));
944 port("\\Y", param("\\Y_WIDTH"));
945 check_expected(false);
949 if (cell
->type
== "$slice") {
951 port("\\A", param("\\A_WIDTH"));
952 port("\\Y", param("\\Y_WIDTH"));
953 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
959 if (cell
->type
== "$concat") {
960 port("\\A", param("\\A_WIDTH"));
961 port("\\B", param("\\B_WIDTH"));
962 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 if (cell
->type
== "$mux") {
968 port("\\A", param("\\WIDTH"));
969 port("\\B", param("\\WIDTH"));
971 port("\\Y", param("\\WIDTH"));
976 if (cell
->type
== "$pmux") {
977 port("\\A", param("\\WIDTH"));
978 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
979 port("\\S", param("\\S_WIDTH"));
980 port("\\Y", param("\\WIDTH"));
985 if (cell
->type
== "$lut") {
987 port("\\A", param("\\WIDTH"));
993 if (cell
->type
== "$sop") {
996 port("\\A", param("\\WIDTH"));
1002 if (cell
->type
== "$sr") {
1003 param_bool("\\SET_POLARITY");
1004 param_bool("\\CLR_POLARITY");
1005 port("\\SET", param("\\WIDTH"));
1006 port("\\CLR", param("\\WIDTH"));
1007 port("\\Q", param("\\WIDTH"));
1012 if (cell
->type
== "$ff") {
1013 port("\\D", param("\\WIDTH"));
1014 port("\\Q", param("\\WIDTH"));
1019 if (cell
->type
== "$dff") {
1020 param_bool("\\CLK_POLARITY");
1022 port("\\D", param("\\WIDTH"));
1023 port("\\Q", param("\\WIDTH"));
1028 if (cell
->type
== "$dffe") {
1029 param_bool("\\CLK_POLARITY");
1030 param_bool("\\EN_POLARITY");
1033 port("\\D", param("\\WIDTH"));
1034 port("\\Q", param("\\WIDTH"));
1039 if (cell
->type
== "$dffsr") {
1040 param_bool("\\CLK_POLARITY");
1041 param_bool("\\SET_POLARITY");
1042 param_bool("\\CLR_POLARITY");
1044 port("\\SET", param("\\WIDTH"));
1045 port("\\CLR", param("\\WIDTH"));
1046 port("\\D", param("\\WIDTH"));
1047 port("\\Q", param("\\WIDTH"));
1052 if (cell
->type
== "$adff") {
1053 param_bool("\\CLK_POLARITY");
1054 param_bool("\\ARST_POLARITY");
1055 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1058 port("\\D", param("\\WIDTH"));
1059 port("\\Q", param("\\WIDTH"));
1064 if (cell
->type
== "$dlatch") {
1065 param_bool("\\EN_POLARITY");
1067 port("\\D", param("\\WIDTH"));
1068 port("\\Q", param("\\WIDTH"));
1073 if (cell
->type
== "$dlatchsr") {
1074 param_bool("\\EN_POLARITY");
1075 param_bool("\\SET_POLARITY");
1076 param_bool("\\CLR_POLARITY");
1078 port("\\SET", param("\\WIDTH"));
1079 port("\\CLR", param("\\WIDTH"));
1080 port("\\D", param("\\WIDTH"));
1081 port("\\Q", param("\\WIDTH"));
1086 if (cell
->type
== "$fsm") {
1088 param_bool("\\CLK_POLARITY");
1089 param_bool("\\ARST_POLARITY");
1090 param("\\STATE_BITS");
1091 param("\\STATE_NUM");
1092 param("\\STATE_NUM_LOG2");
1093 param("\\STATE_RST");
1094 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1095 param("\\TRANS_NUM");
1096 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1099 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1100 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 if (cell
->type
== "$memrd") {
1107 param_bool("\\CLK_ENABLE");
1108 param_bool("\\CLK_POLARITY");
1109 param_bool("\\TRANSPARENT");
1112 port("\\ADDR", param("\\ABITS"));
1113 port("\\DATA", param("\\WIDTH"));
1118 if (cell
->type
== "$memwr") {
1120 param_bool("\\CLK_ENABLE");
1121 param_bool("\\CLK_POLARITY");
1122 param("\\PRIORITY");
1124 port("\\EN", param("\\WIDTH"));
1125 port("\\ADDR", param("\\ABITS"));
1126 port("\\DATA", param("\\WIDTH"));
1131 if (cell
->type
== "$meminit") {
1133 param("\\PRIORITY");
1134 port("\\ADDR", param("\\ABITS"));
1135 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 if (cell
->type
== "$mem") {
1145 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1146 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1147 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1148 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1149 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1150 port("\\RD_CLK", param("\\RD_PORTS"));
1151 port("\\RD_EN", param("\\RD_PORTS"));
1152 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1153 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1154 port("\\WR_CLK", param("\\WR_PORTS"));
1155 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1156 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1157 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 if (cell
->type
== "$tribuf") {
1163 port("\\A", param("\\WIDTH"));
1164 port("\\Y", param("\\WIDTH"));
1170 if (cell
->type
.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1177 if (cell
->type
== "$initstate") {
1183 if (cell
->type
.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1184 port("\\Y", param("\\WIDTH"));
1189 if (cell
->type
== "$equiv") {
1197 if (cell
->type
.in("$specify2", "$specify3")) {
1198 param_bool("\\FULL");
1199 param_bool("\\SRC_DST_PEN");
1200 param_bool("\\SRC_DST_POL");
1201 param("\\T_RISE_MIN");
1202 param("\\T_RISE_TYP");
1203 param("\\T_RISE_MAX");
1204 param("\\T_FALL_MIN");
1205 param("\\T_FALL_TYP");
1206 param("\\T_FALL_MAX");
1208 port("\\SRC", param("\\SRC_WIDTH"));
1209 port("\\DST", param("\\DST_WIDTH"));
1210 if (cell
->type
== "$specify3") {
1211 param_bool("\\EDGE_EN");
1212 param_bool("\\EDGE_POL");
1213 param_bool("\\DAT_DST_PEN");
1214 param_bool("\\DAT_DST_POL");
1215 port("\\DAT", param("\\DST_WIDTH"));
1221 if (cell
->type
== "$_BUF_") { check_gate("AY"); return; }
1222 if (cell
->type
== "$_NOT_") { check_gate("AY"); return; }
1223 if (cell
->type
== "$_AND_") { check_gate("ABY"); return; }
1224 if (cell
->type
== "$_NAND_") { check_gate("ABY"); return; }
1225 if (cell
->type
== "$_OR_") { check_gate("ABY"); return; }
1226 if (cell
->type
== "$_NOR_") { check_gate("ABY"); return; }
1227 if (cell
->type
== "$_XOR_") { check_gate("ABY"); return; }
1228 if (cell
->type
== "$_XNOR_") { check_gate("ABY"); return; }
1229 if (cell
->type
== "$_ANDNOT_") { check_gate("ABY"); return; }
1230 if (cell
->type
== "$_ORNOT_") { check_gate("ABY"); return; }
1231 if (cell
->type
== "$_MUX_") { check_gate("ABSY"); return; }
1232 if (cell
->type
== "$_AOI3_") { check_gate("ABCY"); return; }
1233 if (cell
->type
== "$_OAI3_") { check_gate("ABCY"); return; }
1234 if (cell
->type
== "$_AOI4_") { check_gate("ABCDY"); return; }
1235 if (cell
->type
== "$_OAI4_") { check_gate("ABCDY"); return; }
1237 if (cell
->type
== "$_TBUF_") { check_gate("AYE"); return; }
1239 if (cell
->type
== "$_MUX4_") { check_gate("ABCDSTY"); return; }
1240 if (cell
->type
== "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1241 if (cell
->type
== "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1243 if (cell
->type
== "$_SR_NN_") { check_gate("SRQ"); return; }
1244 if (cell
->type
== "$_SR_NP_") { check_gate("SRQ"); return; }
1245 if (cell
->type
== "$_SR_PN_") { check_gate("SRQ"); return; }
1246 if (cell
->type
== "$_SR_PP_") { check_gate("SRQ"); return; }
1248 if (cell
->type
== "$_FF_") { check_gate("DQ"); return; }
1249 if (cell
->type
== "$_DFF_N_") { check_gate("DQC"); return; }
1250 if (cell
->type
== "$_DFF_P_") { check_gate("DQC"); return; }
1252 if (cell
->type
== "$_DFFE_NN_") { check_gate("DQCE"); return; }
1253 if (cell
->type
== "$_DFFE_NP_") { check_gate("DQCE"); return; }
1254 if (cell
->type
== "$_DFFE_PN_") { check_gate("DQCE"); return; }
1255 if (cell
->type
== "$_DFFE_PP_") { check_gate("DQCE"); return; }
1257 if (cell
->type
== "$_DFF_NN0_") { check_gate("DQCR"); return; }
1258 if (cell
->type
== "$_DFF_NN1_") { check_gate("DQCR"); return; }
1259 if (cell
->type
== "$_DFF_NP0_") { check_gate("DQCR"); return; }
1260 if (cell
->type
== "$_DFF_NP1_") { check_gate("DQCR"); return; }
1261 if (cell
->type
== "$_DFF_PN0_") { check_gate("DQCR"); return; }
1262 if (cell
->type
== "$_DFF_PN1_") { check_gate("DQCR"); return; }
1263 if (cell
->type
== "$_DFF_PP0_") { check_gate("DQCR"); return; }
1264 if (cell
->type
== "$_DFF_PP1_") { check_gate("DQCR"); return; }
1266 if (cell
->type
== "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1267 if (cell
->type
== "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1268 if (cell
->type
== "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1269 if (cell
->type
== "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1270 if (cell
->type
== "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1271 if (cell
->type
== "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1272 if (cell
->type
== "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1273 if (cell
->type
== "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1275 if (cell
->type
== "$_DLATCH_N_") { check_gate("EDQ"); return; }
1276 if (cell
->type
== "$_DLATCH_P_") { check_gate("EDQ"); return; }
1278 if (cell
->type
== "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1279 if (cell
->type
== "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1280 if (cell
->type
== "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1281 if (cell
->type
== "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1282 if (cell
->type
== "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1283 if (cell
->type
== "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1284 if (cell
->type
== "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1285 if (cell
->type
== "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1293 void RTLIL::Module::sort()
1295 wires_
.sort(sort_by_id_str());
1296 cells_
.sort(sort_by_id_str());
1297 avail_parameters
.sort(sort_by_id_str());
1298 memories
.sort(sort_by_id_str());
1299 processes
.sort(sort_by_id_str());
1300 for (auto &it
: cells_
)
1302 for (auto &it
: wires_
)
1303 it
.second
->attributes
.sort(sort_by_id_str());
1304 for (auto &it
: memories
)
1305 it
.second
->attributes
.sort(sort_by_id_str());
1308 void RTLIL::Module::check()
1311 std::vector
<bool> ports_declared
;
1312 for (auto &it
: wires_
) {
1313 log_assert(this == it
.second
->module
);
1314 log_assert(it
.first
== it
.second
->name
);
1315 log_assert(!it
.first
.empty());
1316 log_assert(it
.second
->width
>= 0);
1317 log_assert(it
.second
->port_id
>= 0);
1318 for (auto &it2
: it
.second
->attributes
)
1319 log_assert(!it2
.first
.empty());
1320 if (it
.second
->port_id
) {
1321 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1322 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1323 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1324 if (GetSize(ports_declared
) < it
.second
->port_id
)
1325 ports_declared
.resize(it
.second
->port_id
);
1326 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1327 ports_declared
[it
.second
->port_id
-1] = true;
1329 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1331 for (auto port_declared
: ports_declared
)
1332 log_assert(port_declared
== true);
1333 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1335 for (auto &it
: memories
) {
1336 log_assert(it
.first
== it
.second
->name
);
1337 log_assert(!it
.first
.empty());
1338 log_assert(it
.second
->width
>= 0);
1339 log_assert(it
.second
->size
>= 0);
1340 for (auto &it2
: it
.second
->attributes
)
1341 log_assert(!it2
.first
.empty());
1344 for (auto &it
: cells_
) {
1345 log_assert(this == it
.second
->module
);
1346 log_assert(it
.first
== it
.second
->name
);
1347 log_assert(!it
.first
.empty());
1348 log_assert(!it
.second
->type
.empty());
1349 for (auto &it2
: it
.second
->connections()) {
1350 log_assert(!it2
.first
.empty());
1353 for (auto &it2
: it
.second
->attributes
)
1354 log_assert(!it2
.first
.empty());
1355 for (auto &it2
: it
.second
->parameters
)
1356 log_assert(!it2
.first
.empty());
1357 InternalCellChecker
checker(this, it
.second
);
1361 for (auto &it
: processes
) {
1362 log_assert(it
.first
== it
.second
->name
);
1363 log_assert(!it
.first
.empty());
1364 // FIXME: More checks here..
1367 for (auto &it
: connections_
) {
1368 log_assert(it
.first
.size() == it
.second
.size());
1369 log_assert(!it
.first
.has_const());
1374 for (auto &it
: attributes
)
1375 log_assert(!it
.first
.empty());
1379 void RTLIL::Module::optimize()
1383 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1385 log_assert(new_mod
->refcount_wires_
== 0);
1386 log_assert(new_mod
->refcount_cells_
== 0);
1388 new_mod
->avail_parameters
= avail_parameters
;
1390 for (auto &conn
: connections_
)
1391 new_mod
->connect(conn
);
1393 for (auto &attr
: attributes
)
1394 new_mod
->attributes
[attr
.first
] = attr
.second
;
1396 for (auto &it
: wires_
)
1397 new_mod
->addWire(it
.first
, it
.second
);
1399 for (auto &it
: memories
)
1400 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1402 for (auto &it
: cells_
)
1403 new_mod
->addCell(it
.first
, it
.second
);
1405 for (auto &it
: processes
)
1406 new_mod
->processes
[it
.first
] = it
.second
->clone();
1408 struct RewriteSigSpecWorker
1411 void operator()(RTLIL::SigSpec
&sig
)
1413 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1414 for (auto &c
: chunks
)
1416 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1421 RewriteSigSpecWorker rewriteSigSpecWorker
;
1422 rewriteSigSpecWorker
.mod
= new_mod
;
1423 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1424 new_mod
->fixup_ports();
1427 RTLIL::Module
*RTLIL::Module::clone() const
1429 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1430 new_mod
->name
= name
;
1435 bool RTLIL::Module::has_memories() const
1437 return !memories
.empty();
1440 bool RTLIL::Module::has_processes() const
1442 return !processes
.empty();
1445 bool RTLIL::Module::has_memories_warn() const
1447 if (!memories
.empty())
1448 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1449 return !memories
.empty();
1452 bool RTLIL::Module::has_processes_warn() const
1454 if (!processes
.empty())
1455 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1456 return !processes
.empty();
1459 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1461 std::vector
<RTLIL::Wire
*> result
;
1462 result
.reserve(wires_
.size());
1463 for (auto &it
: wires_
)
1464 if (design
->selected(this, it
.second
))
1465 result
.push_back(it
.second
);
1469 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1471 std::vector
<RTLIL::Cell
*> result
;
1472 result
.reserve(wires_
.size());
1473 for (auto &it
: cells_
)
1474 if (design
->selected(this, it
.second
))
1475 result
.push_back(it
.second
);
1479 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1481 log_assert(!wire
->name
.empty());
1482 log_assert(count_id(wire
->name
) == 0);
1483 log_assert(refcount_wires_
== 0);
1484 wires_
[wire
->name
] = wire
;
1485 wire
->module
= this;
1488 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1490 log_assert(!cell
->name
.empty());
1491 log_assert(count_id(cell
->name
) == 0);
1492 log_assert(refcount_cells_
== 0);
1493 cells_
[cell
->name
] = cell
;
1494 cell
->module
= this;
1498 struct DeleteWireWorker
1500 RTLIL::Module
*module
;
1501 const pool
<RTLIL::Wire
*> *wires_p
;
1503 void operator()(RTLIL::SigSpec
&sig
) {
1504 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1505 for (auto &c
: chunks
)
1506 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1507 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1515 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1517 log_assert(refcount_wires_
== 0);
1519 DeleteWireWorker delete_wire_worker
;
1520 delete_wire_worker
.module
= this;
1521 delete_wire_worker
.wires_p
= &wires
;
1522 rewrite_sigspecs(delete_wire_worker
);
1524 for (auto &it
: wires
) {
1525 log_assert(wires_
.count(it
->name
) != 0);
1526 wires_
.erase(it
->name
);
1531 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1533 while (!cell
->connections_
.empty())
1534 cell
->unsetPort(cell
->connections_
.begin()->first
);
1536 log_assert(cells_
.count(cell
->name
) != 0);
1537 log_assert(refcount_cells_
== 0);
1538 cells_
.erase(cell
->name
);
1542 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1544 log_assert(wires_
[wire
->name
] == wire
);
1545 log_assert(refcount_wires_
== 0);
1546 wires_
.erase(wire
->name
);
1547 wire
->name
= new_name
;
1551 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1553 log_assert(cells_
[cell
->name
] == cell
);
1554 log_assert(refcount_wires_
== 0);
1555 cells_
.erase(cell
->name
);
1556 cell
->name
= new_name
;
1560 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1562 log_assert(count_id(old_name
) != 0);
1563 if (wires_
.count(old_name
))
1564 rename(wires_
.at(old_name
), new_name
);
1565 else if (cells_
.count(old_name
))
1566 rename(cells_
.at(old_name
), new_name
);
1571 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1573 log_assert(wires_
[w1
->name
] == w1
);
1574 log_assert(wires_
[w2
->name
] == w2
);
1575 log_assert(refcount_wires_
== 0);
1577 wires_
.erase(w1
->name
);
1578 wires_
.erase(w2
->name
);
1580 std::swap(w1
->name
, w2
->name
);
1582 wires_
[w1
->name
] = w1
;
1583 wires_
[w2
->name
] = w2
;
1586 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1588 log_assert(cells_
[c1
->name
] == c1
);
1589 log_assert(cells_
[c2
->name
] == c2
);
1590 log_assert(refcount_cells_
== 0);
1592 cells_
.erase(c1
->name
);
1593 cells_
.erase(c2
->name
);
1595 std::swap(c1
->name
, c2
->name
);
1597 cells_
[c1
->name
] = c1
;
1598 cells_
[c2
->name
] = c2
;
1601 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1604 return uniquify(name
, index
);
1607 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1610 if (count_id(name
) == 0)
1616 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1617 if (count_id(new_name
) == 0)
1623 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1625 if (a
->port_id
&& !b
->port_id
)
1627 if (!a
->port_id
&& b
->port_id
)
1630 if (a
->port_id
== b
->port_id
)
1631 return a
->name
< b
->name
;
1632 return a
->port_id
< b
->port_id
;
1635 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1637 for (auto mon
: monitors
)
1638 mon
->notify_connect(this, conn
);
1641 for (auto mon
: design
->monitors
)
1642 mon
->notify_connect(this, conn
);
1644 // ignore all attempts to assign constants to other constants
1645 if (conn
.first
.has_const()) {
1646 RTLIL::SigSig new_conn
;
1647 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1648 if (conn
.first
[i
].wire
) {
1649 new_conn
.first
.append(conn
.first
[i
]);
1650 new_conn
.second
.append(conn
.second
[i
]);
1652 if (GetSize(new_conn
.first
))
1658 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1659 log_backtrace("-X- ", yosys_xtrace
-1);
1662 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1663 connections_
.push_back(conn
);
1666 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1668 connect(RTLIL::SigSig(lhs
, rhs
));
1671 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1673 for (auto mon
: monitors
)
1674 mon
->notify_connect(this, new_conn
);
1677 for (auto mon
: design
->monitors
)
1678 mon
->notify_connect(this, new_conn
);
1681 log("#X# New connections vector in %s:\n", log_id(this));
1682 for (auto &conn
: new_conn
)
1683 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1684 log_backtrace("-X- ", yosys_xtrace
-1);
1687 connections_
= new_conn
;
1690 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1692 return connections_
;
1695 void RTLIL::Module::fixup_ports()
1697 std::vector
<RTLIL::Wire
*> all_ports
;
1699 for (auto &w
: wires_
)
1700 if (w
.second
->port_input
|| w
.second
->port_output
)
1701 all_ports
.push_back(w
.second
);
1703 w
.second
->port_id
= 0;
1705 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1708 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1709 ports
.push_back(all_ports
[i
]->name
);
1710 all_ports
[i
]->port_id
= i
+1;
1714 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1716 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1718 wire
->width
= width
;
1723 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1725 RTLIL::Wire
*wire
= addWire(name
);
1726 wire
->width
= other
->width
;
1727 wire
->start_offset
= other
->start_offset
;
1728 wire
->port_id
= other
->port_id
;
1729 wire
->port_input
= other
->port_input
;
1730 wire
->port_output
= other
->port_output
;
1731 wire
->upto
= other
->upto
;
1732 wire
->attributes
= other
->attributes
;
1736 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1738 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1745 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1747 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1748 cell
->connections_
= other
->connections_
;
1749 cell
->parameters
= other
->parameters
;
1750 cell
->attributes
= other
->attributes
;
1754 #define DEF_METHOD(_func, _y_size, _type) \
1755 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1756 RTLIL::Cell *cell = addCell(name, _type); \
1757 cell->parameters["\\A_SIGNED"] = is_signed; \
1758 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1759 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1760 cell->setPort("\\A", sig_a); \
1761 cell->setPort("\\Y", sig_y); \
1762 cell->set_src_attribute(src); \
1765 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1766 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1767 add ## _func(name, sig_a, sig_y, is_signed, src); \
1770 DEF_METHOD(Not
, sig_a
.size(), "$not")
1771 DEF_METHOD(Pos
, sig_a
.size(), "$pos")
1772 DEF_METHOD(Neg
, sig_a
.size(), "$neg")
1773 DEF_METHOD(ReduceAnd
, 1, "$reduce_and")
1774 DEF_METHOD(ReduceOr
, 1, "$reduce_or")
1775 DEF_METHOD(ReduceXor
, 1, "$reduce_xor")
1776 DEF_METHOD(ReduceXnor
, 1, "$reduce_xnor")
1777 DEF_METHOD(ReduceBool
, 1, "$reduce_bool")
1778 DEF_METHOD(LogicNot
, 1, "$logic_not")
1781 #define DEF_METHOD(_func, _y_size, _type) \
1782 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1783 RTLIL::Cell *cell = addCell(name, _type); \
1784 cell->parameters["\\A_SIGNED"] = is_signed; \
1785 cell->parameters["\\B_SIGNED"] = is_signed; \
1786 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1787 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1788 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1789 cell->setPort("\\A", sig_a); \
1790 cell->setPort("\\B", sig_b); \
1791 cell->setPort("\\Y", sig_y); \
1792 cell->set_src_attribute(src); \
1795 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1796 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1797 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1800 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), "$and")
1801 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), "$or")
1802 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), "$xor")
1803 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), "$xnor")
1804 DEF_METHOD(Shl
, sig_a
.size(), "$shl")
1805 DEF_METHOD(Shr
, sig_a
.size(), "$shr")
1806 DEF_METHOD(Sshl
, sig_a
.size(), "$sshl")
1807 DEF_METHOD(Sshr
, sig_a
.size(), "$sshr")
1808 DEF_METHOD(Shift
, sig_a
.size(), "$shift")
1809 DEF_METHOD(Shiftx
, sig_a
.size(), "$shiftx")
1810 DEF_METHOD(Lt
, 1, "$lt")
1811 DEF_METHOD(Le
, 1, "$le")
1812 DEF_METHOD(Eq
, 1, "$eq")
1813 DEF_METHOD(Ne
, 1, "$ne")
1814 DEF_METHOD(Eqx
, 1, "$eqx")
1815 DEF_METHOD(Nex
, 1, "$nex")
1816 DEF_METHOD(Ge
, 1, "$ge")
1817 DEF_METHOD(Gt
, 1, "$gt")
1818 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), "$add")
1819 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), "$sub")
1820 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), "$mul")
1821 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), "$div")
1822 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), "$mod")
1823 DEF_METHOD(LogicAnd
, 1, "$logic_and")
1824 DEF_METHOD(LogicOr
, 1, "$logic_or")
1827 #define DEF_METHOD(_func, _type, _pmux) \
1828 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1829 RTLIL::Cell *cell = addCell(name, _type); \
1830 cell->parameters["\\WIDTH"] = sig_a.size(); \
1831 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1832 cell->setPort("\\A", sig_a); \
1833 cell->setPort("\\B", sig_b); \
1834 cell->setPort("\\S", sig_s); \
1835 cell->setPort("\\Y", sig_y); \
1836 cell->set_src_attribute(src); \
1839 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1840 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1841 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1844 DEF_METHOD(Mux
, "$mux", 0)
1845 DEF_METHOD(Pmux
, "$pmux", 1)
1848 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1849 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1850 RTLIL::Cell *cell = addCell(name, _type); \
1851 cell->setPort("\\" #_P1, sig1); \
1852 cell->setPort("\\" #_P2, sig2); \
1853 cell->set_src_attribute(src); \
1856 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1857 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1858 add ## _func(name, sig1, sig2, src); \
1861 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1862 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1863 RTLIL::Cell *cell = addCell(name, _type); \
1864 cell->setPort("\\" #_P1, sig1); \
1865 cell->setPort("\\" #_P2, sig2); \
1866 cell->setPort("\\" #_P3, sig3); \
1867 cell->set_src_attribute(src); \
1870 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1871 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1872 add ## _func(name, sig1, sig2, sig3, src); \
1875 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1876 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1877 RTLIL::Cell *cell = addCell(name, _type); \
1878 cell->setPort("\\" #_P1, sig1); \
1879 cell->setPort("\\" #_P2, sig2); \
1880 cell->setPort("\\" #_P3, sig3); \
1881 cell->setPort("\\" #_P4, sig4); \
1882 cell->set_src_attribute(src); \
1885 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1886 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1887 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1890 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1891 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1892 RTLIL::Cell *cell = addCell(name, _type); \
1893 cell->setPort("\\" #_P1, sig1); \
1894 cell->setPort("\\" #_P2, sig2); \
1895 cell->setPort("\\" #_P3, sig3); \
1896 cell->setPort("\\" #_P4, sig4); \
1897 cell->setPort("\\" #_P5, sig5); \
1898 cell->set_src_attribute(src); \
1901 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1902 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1903 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1906 DEF_METHOD_2(BufGate
, "$_BUF_", A
, Y
)
1907 DEF_METHOD_2(NotGate
, "$_NOT_", A
, Y
)
1908 DEF_METHOD_3(AndGate
, "$_AND_", A
, B
, Y
)
1909 DEF_METHOD_3(NandGate
, "$_NAND_", A
, B
, Y
)
1910 DEF_METHOD_3(OrGate
, "$_OR_", A
, B
, Y
)
1911 DEF_METHOD_3(NorGate
, "$_NOR_", A
, B
, Y
)
1912 DEF_METHOD_3(XorGate
, "$_XOR_", A
, B
, Y
)
1913 DEF_METHOD_3(XnorGate
, "$_XNOR_", A
, B
, Y
)
1914 DEF_METHOD_3(AndnotGate
, "$_ANDNOT_", A
, B
, Y
)
1915 DEF_METHOD_3(OrnotGate
, "$_ORNOT_", A
, B
, Y
)
1916 DEF_METHOD_4(MuxGate
, "$_MUX_", A
, B
, S
, Y
)
1917 DEF_METHOD_4(Aoi3Gate
, "$_AOI3_", A
, B
, C
, Y
)
1918 DEF_METHOD_4(Oai3Gate
, "$_OAI3_", A
, B
, C
, Y
)
1919 DEF_METHOD_5(Aoi4Gate
, "$_AOI4_", A
, B
, C
, D
, Y
)
1920 DEF_METHOD_5(Oai4Gate
, "$_OAI4_", A
, B
, C
, D
, Y
)
1926 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
1928 RTLIL::Cell
*cell
= addCell(name
, "$pow");
1929 cell
->parameters
["\\A_SIGNED"] = a_signed
;
1930 cell
->parameters
["\\B_SIGNED"] = b_signed
;
1931 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1932 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1933 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1934 cell
->setPort("\\A", sig_a
);
1935 cell
->setPort("\\B", sig_b
);
1936 cell
->setPort("\\Y", sig_y
);
1937 cell
->set_src_attribute(src
);
1941 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
, const std::string
&src
)
1943 RTLIL::Cell
*cell
= addCell(name
, "$slice");
1944 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1945 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1946 cell
->parameters
["\\OFFSET"] = offset
;
1947 cell
->setPort("\\A", sig_a
);
1948 cell
->setPort("\\Y", sig_y
);
1949 cell
->set_src_attribute(src
);
1953 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1955 RTLIL::Cell
*cell
= addCell(name
, "$concat");
1956 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1957 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1958 cell
->setPort("\\A", sig_a
);
1959 cell
->setPort("\\B", sig_b
);
1960 cell
->setPort("\\Y", sig_y
);
1961 cell
->set_src_attribute(src
);
1965 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const lut
, const std::string
&src
)
1967 RTLIL::Cell
*cell
= addCell(name
, "$lut");
1968 cell
->parameters
["\\LUT"] = lut
;
1969 cell
->parameters
["\\WIDTH"] = sig_a
.size();
1970 cell
->setPort("\\A", sig_a
);
1971 cell
->setPort("\\Y", sig_y
);
1972 cell
->set_src_attribute(src
);
1976 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1978 RTLIL::Cell
*cell
= addCell(name
, "$tribuf");
1979 cell
->parameters
["\\WIDTH"] = sig_a
.size();
1980 cell
->setPort("\\A", sig_a
);
1981 cell
->setPort("\\EN", sig_en
);
1982 cell
->setPort("\\Y", sig_y
);
1983 cell
->set_src_attribute(src
);
1987 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1989 RTLIL::Cell
*cell
= addCell(name
, "$assert");
1990 cell
->setPort("\\A", sig_a
);
1991 cell
->setPort("\\EN", sig_en
);
1992 cell
->set_src_attribute(src
);
1996 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1998 RTLIL::Cell
*cell
= addCell(name
, "$assume");
1999 cell
->setPort("\\A", sig_a
);
2000 cell
->setPort("\\EN", sig_en
);
2001 cell
->set_src_attribute(src
);
2005 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2007 RTLIL::Cell
*cell
= addCell(name
, "$live");
2008 cell
->setPort("\\A", sig_a
);
2009 cell
->setPort("\\EN", sig_en
);
2010 cell
->set_src_attribute(src
);
2014 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2016 RTLIL::Cell
*cell
= addCell(name
, "$fair");
2017 cell
->setPort("\\A", sig_a
);
2018 cell
->setPort("\\EN", sig_en
);
2019 cell
->set_src_attribute(src
);
2023 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2025 RTLIL::Cell
*cell
= addCell(name
, "$cover");
2026 cell
->setPort("\\A", sig_a
);
2027 cell
->setPort("\\EN", sig_en
);
2028 cell
->set_src_attribute(src
);
2032 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2034 RTLIL::Cell
*cell
= addCell(name
, "$equiv");
2035 cell
->setPort("\\A", sig_a
);
2036 cell
->setPort("\\B", sig_b
);
2037 cell
->setPort("\\Y", sig_y
);
2038 cell
->set_src_attribute(src
);
2042 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2044 RTLIL::Cell
*cell
= addCell(name
, "$sr");
2045 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2046 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2047 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2048 cell
->setPort("\\SET", sig_set
);
2049 cell
->setPort("\\CLR", sig_clr
);
2050 cell
->setPort("\\Q", sig_q
);
2051 cell
->set_src_attribute(src
);
2055 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2057 RTLIL::Cell
*cell
= addCell(name
, "$ff");
2058 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2059 cell
->setPort("\\D", sig_d
);
2060 cell
->setPort("\\Q", sig_q
);
2061 cell
->set_src_attribute(src
);
2065 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2067 RTLIL::Cell
*cell
= addCell(name
, "$dff");
2068 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2069 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2070 cell
->setPort("\\CLK", sig_clk
);
2071 cell
->setPort("\\D", sig_d
);
2072 cell
->setPort("\\Q", sig_q
);
2073 cell
->set_src_attribute(src
);
2077 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2079 RTLIL::Cell
*cell
= addCell(name
, "$dffe");
2080 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2081 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2082 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2083 cell
->setPort("\\CLK", sig_clk
);
2084 cell
->setPort("\\EN", sig_en
);
2085 cell
->setPort("\\D", sig_d
);
2086 cell
->setPort("\\Q", sig_q
);
2087 cell
->set_src_attribute(src
);
2091 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2092 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2094 RTLIL::Cell
*cell
= addCell(name
, "$dffsr");
2095 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2096 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2097 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2098 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2099 cell
->setPort("\\CLK", sig_clk
);
2100 cell
->setPort("\\SET", sig_set
);
2101 cell
->setPort("\\CLR", sig_clr
);
2102 cell
->setPort("\\D", sig_d
);
2103 cell
->setPort("\\Q", sig_q
);
2104 cell
->set_src_attribute(src
);
2108 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2109 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2111 RTLIL::Cell
*cell
= addCell(name
, "$adff");
2112 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2113 cell
->parameters
["\\ARST_POLARITY"] = arst_polarity
;
2114 cell
->parameters
["\\ARST_VALUE"] = arst_value
;
2115 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2116 cell
->setPort("\\CLK", sig_clk
);
2117 cell
->setPort("\\ARST", sig_arst
);
2118 cell
->setPort("\\D", sig_d
);
2119 cell
->setPort("\\Q", sig_q
);
2120 cell
->set_src_attribute(src
);
2124 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2126 RTLIL::Cell
*cell
= addCell(name
, "$dlatch");
2127 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2128 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2129 cell
->setPort("\\EN", sig_en
);
2130 cell
->setPort("\\D", sig_d
);
2131 cell
->setPort("\\Q", sig_q
);
2132 cell
->set_src_attribute(src
);
2136 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2137 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2139 RTLIL::Cell
*cell
= addCell(name
, "$dlatchsr");
2140 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2141 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2142 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2143 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2144 cell
->setPort("\\EN", sig_en
);
2145 cell
->setPort("\\SET", sig_set
);
2146 cell
->setPort("\\CLR", sig_clr
);
2147 cell
->setPort("\\D", sig_d
);
2148 cell
->setPort("\\Q", sig_q
);
2149 cell
->set_src_attribute(src
);
2153 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2155 RTLIL::Cell
*cell
= addCell(name
, "$_FF_");
2156 cell
->setPort("\\D", sig_d
);
2157 cell
->setPort("\\Q", sig_q
);
2158 cell
->set_src_attribute(src
);
2162 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2164 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2165 cell
->setPort("\\C", sig_clk
);
2166 cell
->setPort("\\D", sig_d
);
2167 cell
->setPort("\\Q", sig_q
);
2168 cell
->set_src_attribute(src
);
2172 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2174 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2175 cell
->setPort("\\C", sig_clk
);
2176 cell
->setPort("\\E", sig_en
);
2177 cell
->setPort("\\D", sig_d
);
2178 cell
->setPort("\\Q", sig_q
);
2179 cell
->set_src_attribute(src
);
2183 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2184 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2186 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2187 cell
->setPort("\\C", sig_clk
);
2188 cell
->setPort("\\S", sig_set
);
2189 cell
->setPort("\\R", sig_clr
);
2190 cell
->setPort("\\D", sig_d
);
2191 cell
->setPort("\\Q", sig_q
);
2192 cell
->set_src_attribute(src
);
2196 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2197 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2199 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2200 cell
->setPort("\\C", sig_clk
);
2201 cell
->setPort("\\R", sig_arst
);
2202 cell
->setPort("\\D", sig_d
);
2203 cell
->setPort("\\Q", sig_q
);
2204 cell
->set_src_attribute(src
);
2208 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2210 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2211 cell
->setPort("\\E", sig_en
);
2212 cell
->setPort("\\D", sig_d
);
2213 cell
->setPort("\\Q", sig_q
);
2214 cell
->set_src_attribute(src
);
2218 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2219 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2221 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2222 cell
->setPort("\\E", sig_en
);
2223 cell
->setPort("\\S", sig_set
);
2224 cell
->setPort("\\R", sig_clr
);
2225 cell
->setPort("\\D", sig_d
);
2226 cell
->setPort("\\Q", sig_q
);
2227 cell
->set_src_attribute(src
);
2231 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2233 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2234 Cell
*cell
= addCell(name
, "$anyconst");
2235 cell
->setParam("\\WIDTH", width
);
2236 cell
->setPort("\\Y", sig
);
2237 cell
->set_src_attribute(src
);
2241 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2243 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2244 Cell
*cell
= addCell(name
, "$anyseq");
2245 cell
->setParam("\\WIDTH", width
);
2246 cell
->setPort("\\Y", sig
);
2247 cell
->set_src_attribute(src
);
2251 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2253 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2254 Cell
*cell
= addCell(name
, "$allconst");
2255 cell
->setParam("\\WIDTH", width
);
2256 cell
->setPort("\\Y", sig
);
2257 cell
->set_src_attribute(src
);
2261 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2263 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2264 Cell
*cell
= addCell(name
, "$allseq");
2265 cell
->setParam("\\WIDTH", width
);
2266 cell
->setPort("\\Y", sig
);
2267 cell
->set_src_attribute(src
);
2271 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2273 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2274 Cell
*cell
= addCell(name
, "$initstate");
2275 cell
->setPort("\\Y", sig
);
2276 cell
->set_src_attribute(src
);
2282 static unsigned int hashidx_count
= 123456789;
2283 hashidx_count
= mkhash_xorshift(hashidx_count
);
2284 hashidx_
= hashidx_count
;
2291 port_output
= false;
2295 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2299 RTLIL::Wire::~Wire()
2302 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2307 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2308 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2314 RTLIL::Memory::Memory()
2316 static unsigned int hashidx_count
= 123456789;
2317 hashidx_count
= mkhash_xorshift(hashidx_count
);
2318 hashidx_
= hashidx_count
;
2324 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2328 RTLIL::Cell::Cell() : module(nullptr)
2330 static unsigned int hashidx_count
= 123456789;
2331 hashidx_count
= mkhash_xorshift(hashidx_count
);
2332 hashidx_
= hashidx_count
;
2334 // log("#memtrace# %p\n", this);
2338 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2342 RTLIL::Cell::~Cell()
2345 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2350 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2351 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2357 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2359 return connections_
.count(portname
) != 0;
2362 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2364 RTLIL::SigSpec signal
;
2365 auto conn_it
= connections_
.find(portname
);
2367 if (conn_it
!= connections_
.end())
2369 for (auto mon
: module
->monitors
)
2370 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2373 for (auto mon
: module
->design
->monitors
)
2374 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2377 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2378 log_backtrace("-X- ", yosys_xtrace
-1);
2381 connections_
.erase(conn_it
);
2385 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2387 auto conn_it
= connections_
.find(portname
);
2389 if (conn_it
== connections_
.end()) {
2390 connections_
[portname
] = RTLIL::SigSpec();
2391 conn_it
= connections_
.find(portname
);
2392 log_assert(conn_it
!= connections_
.end());
2394 if (conn_it
->second
== signal
)
2397 for (auto mon
: module
->monitors
)
2398 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2401 for (auto mon
: module
->design
->monitors
)
2402 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2405 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2406 log_backtrace("-X- ", yosys_xtrace
-1);
2409 conn_it
->second
= signal
;
2412 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2414 return connections_
.at(portname
);
2417 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2419 return connections_
;
2422 bool RTLIL::Cell::known() const
2424 if (yosys_celltypes
.cell_known(type
))
2426 if (module
&& module
->design
&& module
->design
->module(type
))
2431 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2433 if (yosys_celltypes
.cell_known(type
))
2434 return yosys_celltypes
.cell_input(type
, portname
);
2435 if (module
&& module
->design
) {
2436 RTLIL::Module
*m
= module
->design
->module(type
);
2437 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2438 return w
&& w
->port_input
;
2443 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2445 if (yosys_celltypes
.cell_known(type
))
2446 return yosys_celltypes
.cell_output(type
, portname
);
2447 if (module
&& module
->design
) {
2448 RTLIL::Module
*m
= module
->design
->module(type
);
2449 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2450 return w
&& w
->port_output
;
2455 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2457 return parameters
.count(paramname
) != 0;
2460 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2462 parameters
.erase(paramname
);
2465 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2467 parameters
[paramname
] = value
;
2470 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2472 return parameters
.at(paramname
);
2475 void RTLIL::Cell::sort()
2477 connections_
.sort(sort_by_id_str());
2478 parameters
.sort(sort_by_id_str());
2479 attributes
.sort(sort_by_id_str());
2482 void RTLIL::Cell::check()
2485 InternalCellChecker
checker(NULL
, this);
2490 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2492 if (type
.substr(0, 1) != "$" || type
.substr(0, 2) == "$_" || type
.substr(0, 8) == "$paramod" || type
.substr(0,10) == "$fmcombine" ||
2493 type
.substr(0, 9) == "$verific$" || type
.substr(0, 7) == "$array:" || type
.substr(0, 8) == "$extern:")
2496 if (type
== "$mux" || type
== "$pmux") {
2497 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2498 if (type
== "$pmux")
2499 parameters
["\\S_WIDTH"] = GetSize(connections_
["\\S"]);
2504 if (type
== "$lut" || type
== "$sop") {
2505 parameters
["\\WIDTH"] = GetSize(connections_
["\\A"]);
2509 if (type
== "$fa") {
2510 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2514 if (type
== "$lcu") {
2515 parameters
["\\WIDTH"] = GetSize(connections_
["\\CO"]);
2519 bool signedness_ab
= !type
.in("$slice", "$concat", "$macc");
2521 if (connections_
.count("\\A")) {
2522 if (signedness_ab
) {
2524 parameters
["\\A_SIGNED"] = true;
2525 else if (parameters
.count("\\A_SIGNED") == 0)
2526 parameters
["\\A_SIGNED"] = false;
2528 parameters
["\\A_WIDTH"] = GetSize(connections_
["\\A"]);
2531 if (connections_
.count("\\B")) {
2532 if (signedness_ab
) {
2534 parameters
["\\B_SIGNED"] = true;
2535 else if (parameters
.count("\\B_SIGNED") == 0)
2536 parameters
["\\B_SIGNED"] = false;
2538 parameters
["\\B_WIDTH"] = GetSize(connections_
["\\B"]);
2541 if (connections_
.count("\\Y"))
2542 parameters
["\\Y_WIDTH"] = GetSize(connections_
["\\Y"]);
2544 if (connections_
.count("\\Q"))
2545 parameters
["\\WIDTH"] = GetSize(connections_
["\\Q"]);
2550 RTLIL::SigChunk::SigChunk()
2557 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2561 width
= GetSize(data
);
2565 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2567 log_assert(wire
!= nullptr);
2569 this->width
= wire
->width
;
2573 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2575 log_assert(wire
!= nullptr);
2577 this->width
= width
;
2578 this->offset
= offset
;
2581 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2584 data
= RTLIL::Const(str
).bits
;
2585 width
= GetSize(data
);
2589 RTLIL::SigChunk::SigChunk(int val
, int width
)
2592 data
= RTLIL::Const(val
, width
).bits
;
2593 this->width
= GetSize(data
);
2597 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2600 data
= RTLIL::Const(bit
, width
).bits
;
2601 this->width
= GetSize(data
);
2605 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
2610 data
= RTLIL::Const(bit
.data
).bits
;
2612 offset
= bit
.offset
;
2616 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
) : data(sigchunk
.data
)
2618 wire
= sigchunk
.wire
;
2619 data
= sigchunk
.data
;
2620 width
= sigchunk
.width
;
2621 offset
= sigchunk
.offset
;
2624 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2626 RTLIL::SigChunk ret
;
2629 ret
.offset
= this->offset
+ offset
;
2632 for (int i
= 0; i
< length
; i
++)
2633 ret
.data
.push_back(data
[offset
+i
]);
2639 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2641 if (wire
&& other
.wire
)
2642 if (wire
->name
!= other
.wire
->name
)
2643 return wire
->name
< other
.wire
->name
;
2645 if (wire
!= other
.wire
)
2646 return wire
< other
.wire
;
2648 if (offset
!= other
.offset
)
2649 return offset
< other
.offset
;
2651 if (width
!= other
.width
)
2652 return width
< other
.width
;
2654 return data
< other
.data
;
2657 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2659 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2662 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2669 RTLIL::SigSpec::SigSpec()
2675 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2680 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2682 cover("kernel.rtlil.sigspec.init.list");
2687 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2688 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2692 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2694 cover("kernel.rtlil.sigspec.assign");
2696 width_
= other
.width_
;
2697 hash_
= other
.hash_
;
2698 chunks_
= other
.chunks_
;
2701 if (!other
.bits_
.empty())
2703 RTLIL::SigChunk
*last
= NULL
;
2704 int last_end_offset
= 0;
2706 for (auto &bit
: other
.bits_
) {
2707 if (last
&& bit
.wire
== last
->wire
) {
2708 if (bit
.wire
== NULL
) {
2709 last
->data
.push_back(bit
.data
);
2712 } else if (last_end_offset
== bit
.offset
) {
2718 chunks_
.push_back(bit
);
2719 last
= &chunks_
.back();
2720 last_end_offset
= bit
.offset
+ 1;
2729 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2731 cover("kernel.rtlil.sigspec.init.const");
2733 chunks_
.push_back(RTLIL::SigChunk(value
));
2734 width_
= chunks_
.back().width
;
2739 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2741 cover("kernel.rtlil.sigspec.init.chunk");
2743 chunks_
.push_back(chunk
);
2744 width_
= chunks_
.back().width
;
2749 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2751 cover("kernel.rtlil.sigspec.init.wire");
2753 chunks_
.push_back(RTLIL::SigChunk(wire
));
2754 width_
= chunks_
.back().width
;
2759 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2761 cover("kernel.rtlil.sigspec.init.wire_part");
2763 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2764 width_
= chunks_
.back().width
;
2769 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2771 cover("kernel.rtlil.sigspec.init.str");
2773 chunks_
.push_back(RTLIL::SigChunk(str
));
2774 width_
= chunks_
.back().width
;
2779 RTLIL::SigSpec::SigSpec(int val
, int width
)
2781 cover("kernel.rtlil.sigspec.init.int");
2783 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2789 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2791 cover("kernel.rtlil.sigspec.init.state");
2793 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2799 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2801 cover("kernel.rtlil.sigspec.init.bit");
2803 if (bit
.wire
== NULL
)
2804 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2806 for (int i
= 0; i
< width
; i
++)
2807 chunks_
.push_back(bit
);
2813 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2815 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2819 for (auto &c
: chunks
)
2824 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2826 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2830 for (auto &bit
: bits
)
2835 RTLIL::SigSpec::SigSpec(pool
<RTLIL::SigBit
> bits
)
2837 cover("kernel.rtlil.sigspec.init.pool_bits");
2841 for (auto &bit
: bits
)
2846 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2848 cover("kernel.rtlil.sigspec.init.stdset_bits");
2852 for (auto &bit
: bits
)
2857 RTLIL::SigSpec::SigSpec(bool bit
)
2859 cover("kernel.rtlil.sigspec.init.bool");
2867 void RTLIL::SigSpec::pack() const
2869 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2871 if (that
->bits_
.empty())
2874 cover("kernel.rtlil.sigspec.convert.pack");
2875 log_assert(that
->chunks_
.empty());
2877 std::vector
<RTLIL::SigBit
> old_bits
;
2878 old_bits
.swap(that
->bits_
);
2880 RTLIL::SigChunk
*last
= NULL
;
2881 int last_end_offset
= 0;
2883 for (auto &bit
: old_bits
) {
2884 if (last
&& bit
.wire
== last
->wire
) {
2885 if (bit
.wire
== NULL
) {
2886 last
->data
.push_back(bit
.data
);
2889 } else if (last_end_offset
== bit
.offset
) {
2895 that
->chunks_
.push_back(bit
);
2896 last
= &that
->chunks_
.back();
2897 last_end_offset
= bit
.offset
+ 1;
2903 void RTLIL::SigSpec::unpack() const
2905 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2907 if (that
->chunks_
.empty())
2910 cover("kernel.rtlil.sigspec.convert.unpack");
2911 log_assert(that
->bits_
.empty());
2913 that
->bits_
.reserve(that
->width_
);
2914 for (auto &c
: that
->chunks_
)
2915 for (int i
= 0; i
< c
.width
; i
++)
2916 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
2918 that
->chunks_
.clear();
2922 void RTLIL::SigSpec::updhash() const
2924 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2926 if (that
->hash_
!= 0)
2929 cover("kernel.rtlil.sigspec.hash");
2932 that
->hash_
= mkhash_init
;
2933 for (auto &c
: that
->chunks_
)
2934 if (c
.wire
== NULL
) {
2935 for (auto &v
: c
.data
)
2936 that
->hash_
= mkhash(that
->hash_
, v
);
2938 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
2939 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
2940 that
->hash_
= mkhash(that
->hash_
, c
.width
);
2943 if (that
->hash_
== 0)
2947 void RTLIL::SigSpec::sort()
2950 cover("kernel.rtlil.sigspec.sort");
2951 std::sort(bits_
.begin(), bits_
.end());
2954 void RTLIL::SigSpec::sort_and_unify()
2957 cover("kernel.rtlil.sigspec.sort_and_unify");
2959 // A copy of the bits vector is used to prevent duplicating the logic from
2960 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2961 // that isn't showing up as significant in profiles.
2962 std::vector
<SigBit
> unique_bits
= bits_
;
2963 std::sort(unique_bits
.begin(), unique_bits
.end());
2964 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
2965 unique_bits
.erase(last
, unique_bits
.end());
2967 *this = unique_bits
;
2970 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
2972 replace(pattern
, with
, this);
2975 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
2977 log_assert(other
!= NULL
);
2978 log_assert(width_
== other
->width_
);
2979 log_assert(pattern
.width_
== with
.width_
);
2986 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
2987 if (pattern
.bits_
[i
].wire
!= NULL
) {
2988 for (int j
= 0; j
< GetSize(bits_
); j
++) {
2989 if (bits_
[j
] == pattern
.bits_
[i
]) {
2990 other
->bits_
[j
] = with
.bits_
[i
];
2999 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3001 replace(rules
, this);
3004 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3006 cover("kernel.rtlil.sigspec.replace_dict");
3008 log_assert(other
!= NULL
);
3009 log_assert(width_
== other
->width_
);
3014 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3015 auto it
= rules
.find(bits_
[i
]);
3016 if (it
!= rules
.end())
3017 other
->bits_
[i
] = it
->second
;
3023 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3025 replace(rules
, this);
3028 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3030 cover("kernel.rtlil.sigspec.replace_map");
3032 log_assert(other
!= NULL
);
3033 log_assert(width_
== other
->width_
);
3038 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3039 auto it
= rules
.find(bits_
[i
]);
3040 if (it
!= rules
.end())
3041 other
->bits_
[i
] = it
->second
;
3047 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3049 remove2(pattern
, NULL
);
3052 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3054 RTLIL::SigSpec tmp
= *this;
3055 tmp
.remove2(pattern
, other
);
3058 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3061 cover("kernel.rtlil.sigspec.remove_other");
3063 cover("kernel.rtlil.sigspec.remove");
3066 if (other
!= NULL
) {
3067 log_assert(width_
== other
->width_
);
3071 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3073 if (bits_
[i
].wire
== NULL
) continue;
3075 for (auto &pattern_chunk
: pattern
.chunks())
3076 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3077 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3078 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3079 bits_
.erase(bits_
.begin() + i
);
3081 if (other
!= NULL
) {
3082 other
->bits_
.erase(other
->bits_
.begin() + i
);
3092 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3094 remove2(pattern
, NULL
);
3097 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3099 RTLIL::SigSpec tmp
= *this;
3100 tmp
.remove2(pattern
, other
);
3103 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3106 cover("kernel.rtlil.sigspec.remove_other");
3108 cover("kernel.rtlil.sigspec.remove");
3112 if (other
!= NULL
) {
3113 log_assert(width_
== other
->width_
);
3117 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3118 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3119 bits_
.erase(bits_
.begin() + i
);
3121 if (other
!= NULL
) {
3122 other
->bits_
.erase(other
->bits_
.begin() + i
);
3131 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3134 cover("kernel.rtlil.sigspec.remove_other");
3136 cover("kernel.rtlil.sigspec.remove");
3140 if (other
!= NULL
) {
3141 log_assert(width_
== other
->width_
);
3145 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3146 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3147 bits_
.erase(bits_
.begin() + i
);
3149 if (other
!= NULL
) {
3150 other
->bits_
.erase(other
->bits_
.begin() + i
);
3159 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3162 cover("kernel.rtlil.sigspec.extract_other");
3164 cover("kernel.rtlil.sigspec.extract");
3166 log_assert(other
== NULL
|| width_
== other
->width_
);
3169 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3171 for (auto& pattern_chunk
: pattern
.chunks()) {
3173 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3174 for (int i
= 0; i
< width_
; i
++)
3175 if (bits_match
[i
].wire
&&
3176 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3177 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3178 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3179 ret
.append_bit(bits_other
[i
]);
3181 for (int i
= 0; i
< width_
; i
++)
3182 if (bits_match
[i
].wire
&&
3183 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3184 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3185 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3186 ret
.append_bit(bits_match
[i
]);
3194 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3197 cover("kernel.rtlil.sigspec.extract_other");
3199 cover("kernel.rtlil.sigspec.extract");
3201 log_assert(other
== NULL
|| width_
== other
->width_
);
3203 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3207 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3208 for (int i
= 0; i
< width_
; i
++)
3209 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3210 ret
.append_bit(bits_other
[i
]);
3212 for (int i
= 0; i
< width_
; i
++)
3213 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3214 ret
.append_bit(bits_match
[i
]);
3221 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3223 cover("kernel.rtlil.sigspec.replace_pos");
3228 log_assert(offset
>= 0);
3229 log_assert(with
.width_
>= 0);
3230 log_assert(offset
+with
.width_
<= width_
);
3232 for (int i
= 0; i
< with
.width_
; i
++)
3233 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3238 void RTLIL::SigSpec::remove_const()
3242 cover("kernel.rtlil.sigspec.remove_const.packed");
3244 std::vector
<RTLIL::SigChunk
> new_chunks
;
3245 new_chunks
.reserve(GetSize(chunks_
));
3248 for (auto &chunk
: chunks_
)
3249 if (chunk
.wire
!= NULL
) {
3250 new_chunks
.push_back(chunk
);
3251 width_
+= chunk
.width
;
3254 chunks_
.swap(new_chunks
);
3258 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3260 std::vector
<RTLIL::SigBit
> new_bits
;
3261 new_bits
.reserve(width_
);
3263 for (auto &bit
: bits_
)
3264 if (bit
.wire
!= NULL
)
3265 new_bits
.push_back(bit
);
3267 bits_
.swap(new_bits
);
3268 width_
= bits_
.size();
3274 void RTLIL::SigSpec::remove(int offset
, int length
)
3276 cover("kernel.rtlil.sigspec.remove_pos");
3280 log_assert(offset
>= 0);
3281 log_assert(length
>= 0);
3282 log_assert(offset
+ length
<= width_
);
3284 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3285 width_
= bits_
.size();
3290 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3293 cover("kernel.rtlil.sigspec.extract_pos");
3294 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3297 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3299 if (signal
.width_
== 0)
3307 cover("kernel.rtlil.sigspec.append");
3309 if (packed() != signal
.packed()) {
3315 for (auto &other_c
: signal
.chunks_
)
3317 auto &my_last_c
= chunks_
.back();
3318 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3319 auto &this_data
= my_last_c
.data
;
3320 auto &other_data
= other_c
.data
;
3321 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3322 my_last_c
.width
+= other_c
.width
;
3324 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3325 my_last_c
.width
+= other_c
.width
;
3327 chunks_
.push_back(other_c
);
3330 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3332 width_
+= signal
.width_
;
3336 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
3340 cover("kernel.rtlil.sigspec.append_bit.packed");
3342 if (chunks_
.size() == 0)
3343 chunks_
.push_back(bit
);
3345 if (bit
.wire
== NULL
)
3346 if (chunks_
.back().wire
== NULL
) {
3347 chunks_
.back().data
.push_back(bit
.data
);
3348 chunks_
.back().width
++;
3350 chunks_
.push_back(bit
);
3352 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3353 chunks_
.back().width
++;
3355 chunks_
.push_back(bit
);
3359 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3360 bits_
.push_back(bit
);
3367 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3369 cover("kernel.rtlil.sigspec.extend_u0");
3374 remove(width
, width_
- width
);
3376 if (width_
< width
) {
3377 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3379 padding
= RTLIL::State::S0
;
3380 while (width_
< width
)
3386 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3388 cover("kernel.rtlil.sigspec.repeat");
3391 for (int i
= 0; i
< num
; i
++)
3397 void RTLIL::SigSpec::check() const
3401 cover("kernel.rtlil.sigspec.check.skip");
3405 cover("kernel.rtlil.sigspec.check.packed");
3408 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3409 const RTLIL::SigChunk chunk
= chunks_
[i
];
3410 if (chunk
.wire
== NULL
) {
3412 log_assert(chunks_
[i
-1].wire
!= NULL
);
3413 log_assert(chunk
.offset
== 0);
3414 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3416 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3417 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3418 log_assert(chunk
.offset
>= 0);
3419 log_assert(chunk
.width
>= 0);
3420 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3421 log_assert(chunk
.data
.size() == 0);
3425 log_assert(w
== width_
);
3426 log_assert(bits_
.empty());
3430 cover("kernel.rtlil.sigspec.check.unpacked");
3432 log_assert(width_
== GetSize(bits_
));
3433 log_assert(chunks_
.empty());
3438 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3440 cover("kernel.rtlil.sigspec.comp_lt");
3445 if (width_
!= other
.width_
)
3446 return width_
< other
.width_
;
3451 if (chunks_
.size() != other
.chunks_
.size())
3452 return chunks_
.size() < other
.chunks_
.size();
3457 if (hash_
!= other
.hash_
)
3458 return hash_
< other
.hash_
;
3460 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3461 if (chunks_
[i
] != other
.chunks_
[i
]) {
3462 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3463 return chunks_
[i
] < other
.chunks_
[i
];
3466 cover("kernel.rtlil.sigspec.comp_lt.equal");
3470 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3472 cover("kernel.rtlil.sigspec.comp_eq");
3477 if (width_
!= other
.width_
)
3483 if (chunks_
.size() != chunks_
.size())
3489 if (hash_
!= other
.hash_
)
3492 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3493 if (chunks_
[i
] != other
.chunks_
[i
]) {
3494 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3498 cover("kernel.rtlil.sigspec.comp_eq.equal");
3502 bool RTLIL::SigSpec::is_wire() const
3504 cover("kernel.rtlil.sigspec.is_wire");
3507 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3510 bool RTLIL::SigSpec::is_chunk() const
3512 cover("kernel.rtlil.sigspec.is_chunk");
3515 return GetSize(chunks_
) == 1;
3518 bool RTLIL::SigSpec::is_fully_const() const
3520 cover("kernel.rtlil.sigspec.is_fully_const");
3523 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3524 if (it
->width
> 0 && it
->wire
!= NULL
)
3529 bool RTLIL::SigSpec::is_fully_zero() const
3531 cover("kernel.rtlil.sigspec.is_fully_zero");
3534 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3535 if (it
->width
> 0 && it
->wire
!= NULL
)
3537 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3538 if (it
->data
[i
] != RTLIL::State::S0
)
3544 bool RTLIL::SigSpec::is_fully_ones() const
3546 cover("kernel.rtlil.sigspec.is_fully_ones");
3549 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3550 if (it
->width
> 0 && it
->wire
!= NULL
)
3552 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3553 if (it
->data
[i
] != RTLIL::State::S1
)
3559 bool RTLIL::SigSpec::is_fully_def() const
3561 cover("kernel.rtlil.sigspec.is_fully_def");
3564 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3565 if (it
->width
> 0 && it
->wire
!= NULL
)
3567 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3568 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3574 bool RTLIL::SigSpec::is_fully_undef() const
3576 cover("kernel.rtlil.sigspec.is_fully_undef");
3579 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3580 if (it
->width
> 0 && it
->wire
!= NULL
)
3582 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3583 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3589 bool RTLIL::SigSpec::has_const() const
3591 cover("kernel.rtlil.sigspec.has_const");
3594 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3595 if (it
->width
> 0 && it
->wire
== NULL
)
3600 bool RTLIL::SigSpec::has_marked_bits() const
3602 cover("kernel.rtlil.sigspec.has_marked_bits");
3605 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3606 if (it
->width
> 0 && it
->wire
== NULL
) {
3607 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3608 if (it
->data
[i
] == RTLIL::State::Sm
)
3614 bool RTLIL::SigSpec::as_bool() const
3616 cover("kernel.rtlil.sigspec.as_bool");
3619 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3621 return RTLIL::Const(chunks_
[0].data
).as_bool();
3625 int RTLIL::SigSpec::as_int(bool is_signed
) const
3627 cover("kernel.rtlil.sigspec.as_int");
3630 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3632 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3636 std::string
RTLIL::SigSpec::as_string() const
3638 cover("kernel.rtlil.sigspec.as_string");
3642 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3643 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3644 if (chunk
.wire
!= NULL
)
3645 for (int j
= 0; j
< chunk
.width
; j
++)
3648 str
+= RTLIL::Const(chunk
.data
).as_string();
3653 RTLIL::Const
RTLIL::SigSpec::as_const() const
3655 cover("kernel.rtlil.sigspec.as_const");
3658 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3660 return chunks_
[0].data
;
3661 return RTLIL::Const();
3664 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3666 cover("kernel.rtlil.sigspec.as_wire");
3669 log_assert(is_wire());
3670 return chunks_
[0].wire
;
3673 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3675 cover("kernel.rtlil.sigspec.as_chunk");
3678 log_assert(is_chunk());
3682 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3684 cover("kernel.rtlil.sigspec.as_bit");
3686 log_assert(width_
== 1);
3688 return RTLIL::SigBit(*chunks_
.begin());
3693 bool RTLIL::SigSpec::match(std::string pattern
) const
3695 cover("kernel.rtlil.sigspec.match");
3698 std::string str
= as_string();
3699 log_assert(pattern
.size() == str
.size());
3701 for (size_t i
= 0; i
< pattern
.size(); i
++) {
3702 if (pattern
[i
] == ' ')
3704 if (pattern
[i
] == '*') {
3705 if (str
[i
] != 'z' && str
[i
] != 'x')
3709 if (pattern
[i
] != str
[i
])
3716 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3718 cover("kernel.rtlil.sigspec.to_sigbit_set");
3721 std::set
<RTLIL::SigBit
> sigbits
;
3722 for (auto &c
: chunks_
)
3723 for (int i
= 0; i
< c
.width
; i
++)
3724 sigbits
.insert(RTLIL::SigBit(c
, i
));
3728 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3730 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3733 pool
<RTLIL::SigBit
> sigbits
;
3734 for (auto &c
: chunks_
)
3735 for (int i
= 0; i
< c
.width
; i
++)
3736 sigbits
.insert(RTLIL::SigBit(c
, i
));
3740 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3742 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3748 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3750 cover("kernel.rtlil.sigspec.to_sigbit_map");
3755 log_assert(width_
== other
.width_
);
3757 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3758 for (int i
= 0; i
< width_
; i
++)
3759 new_map
[bits_
[i
]] = other
.bits_
[i
];
3764 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3766 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3771 log_assert(width_
== other
.width_
);
3773 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3774 for (int i
= 0; i
< width_
; i
++)
3775 new_map
[bits_
[i
]] = other
.bits_
[i
];
3780 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3782 size_t start
= 0, end
= 0;
3783 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3784 tokens
.push_back(text
.substr(start
, end
- start
));
3787 tokens
.push_back(text
.substr(start
));
3790 static int sigspec_parse_get_dummy_line_num()
3795 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3797 cover("kernel.rtlil.sigspec.parse");
3799 AST::current_filename
= "input";
3800 AST::use_internal_line_num();
3801 AST::set_line_num(0);
3803 std::vector
<std::string
> tokens
;
3804 sigspec_parse_split(tokens
, str
, ',');
3806 sig
= RTLIL::SigSpec();
3807 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3809 std::string netname
= tokens
[tokidx
];
3810 std::string indices
;
3812 if (netname
.size() == 0)
3815 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3816 cover("kernel.rtlil.sigspec.parse.const");
3817 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3818 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3821 sig
.append(RTLIL::Const(ast
->bits
));
3829 cover("kernel.rtlil.sigspec.parse.net");
3831 if (netname
[0] != '$' && netname
[0] != '\\')
3832 netname
= "\\" + netname
;
3834 if (module
->wires_
.count(netname
) == 0) {
3835 size_t indices_pos
= netname
.size()-1;
3836 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3839 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3840 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3842 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3844 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3845 indices
= netname
.substr(indices_pos
);
3846 netname
= netname
.substr(0, indices_pos
);
3851 if (module
->wires_
.count(netname
) == 0)
3854 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3855 if (!indices
.empty()) {
3856 std::vector
<std::string
> index_tokens
;
3857 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3858 if (index_tokens
.size() == 1) {
3859 cover("kernel.rtlil.sigspec.parse.bit_sel");
3860 int a
= atoi(index_tokens
.at(0).c_str());
3861 if (a
< 0 || a
>= wire
->width
)
3863 sig
.append(RTLIL::SigSpec(wire
, a
));
3865 cover("kernel.rtlil.sigspec.parse.part_sel");
3866 int a
= atoi(index_tokens
.at(0).c_str());
3867 int b
= atoi(index_tokens
.at(1).c_str());
3872 if (a
< 0 || a
>= wire
->width
)
3874 if (b
< 0 || b
>= wire
->width
)
3876 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3885 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3887 if (str
.empty() || str
[0] != '@')
3888 return parse(sig
, module
, str
);
3890 cover("kernel.rtlil.sigspec.parse.sel");
3892 str
= RTLIL::escape_id(str
.substr(1));
3893 if (design
->selection_vars
.count(str
) == 0)
3896 sig
= RTLIL::SigSpec();
3897 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3898 for (auto &it
: module
->wires_
)
3899 if (sel
.selected_member(module
->name
, it
.first
))
3900 sig
.append(it
.second
);
3905 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3908 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3909 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3914 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3915 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
3919 if (lhs
.chunks_
.size() == 1) {
3920 char *p
= (char*)str
.c_str(), *endptr
;
3921 long int val
= strtol(p
, &endptr
, 10);
3922 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
3923 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
3924 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3929 return parse(sig
, module
, str
);
3932 RTLIL::CaseRule::~CaseRule()
3934 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
3938 bool RTLIL::CaseRule::empty() const
3940 return actions
.empty() && switches
.empty();
3943 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
3945 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
3946 new_caserule
->compare
= compare
;
3947 new_caserule
->actions
= actions
;
3948 for (auto &it
: switches
)
3949 new_caserule
->switches
.push_back(it
->clone());
3950 return new_caserule
;
3953 RTLIL::SwitchRule::~SwitchRule()
3955 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
3959 bool RTLIL::SwitchRule::empty() const
3961 return cases
.empty();
3964 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
3966 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
3967 new_switchrule
->signal
= signal
;
3968 new_switchrule
->attributes
= attributes
;
3969 for (auto &it
: cases
)
3970 new_switchrule
->cases
.push_back(it
->clone());
3971 return new_switchrule
;
3975 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
3977 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
3978 new_syncrule
->type
= type
;
3979 new_syncrule
->signal
= signal
;
3980 new_syncrule
->actions
= actions
;
3981 return new_syncrule
;
3984 RTLIL::Process::~Process()
3986 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
3990 RTLIL::Process
*RTLIL::Process::clone() const
3992 RTLIL::Process
*new_proc
= new RTLIL::Process
;
3994 new_proc
->name
= name
;
3995 new_proc
->attributes
= attributes
;
3997 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
3998 new_proc
->root_case
= *rc_ptr
;
3999 rc_ptr
->switches
.clear();
4002 for (auto &it
: syncs
)
4003 new_proc
->syncs
.push_back(it
->clone());
4009 RTLIL::Memory::~Memory()
4011 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4013 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4014 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4016 return &all_memorys
;