kernel/rtlil.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/compatibility.h"
  21 #include "kernel/rtlil.h"
  22 #include "kernel/log.h"
  23 #include "frontends/verilog/verilog_frontend.h"
  24 #include "backends/ilang/ilang_backend.h"
  25
  26 #include <assert.h>
  27 #include <string.h>
  28 #include <algorithm>
  29
  30 int RTLIL::autoidx = 1;
  31
  32 RTLIL::Const::Const()
  33 {
  34         flags = RTLIL::CONST_FLAG_NONE;
  35 }
  36
  37 RTLIL::Const::Const(std::string str)
  38 {
  39         flags = RTLIL::CONST_FLAG_STRING;
  40         for (int i = str.size()-1; i >= 0; i--) {
  41                 unsigned char ch = str[i];
  42                 for (int j = 0; j < 8; j++) {
  43                         bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
  44                         ch = ch >> 1;
  45                 }
  46         }
  47 }
  48
  49 RTLIL::Const::Const(int val, int width)
  50 {
  51         flags = RTLIL::CONST_FLAG_NONE;
  52         for (int i = 0; i < width; i++) {
  53                 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
  54                 val = val >> 1;
  55         }
  56 }
  57
  58 RTLIL::Const::Const(RTLIL::State bit, int width)
  59 {
  60         flags = RTLIL::CONST_FLAG_NONE;
  61         for (int i = 0; i < width; i++)
  62                 bits.push_back(bit);
  63 }
  64
  65 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
  66 {
  67         if (bits.size() != other.bits.size())
  68                 return bits.size() < other.bits.size();
  69         for (size_t i = 0; i < bits.size(); i++)
  70                 if (bits[i] != other.bits[i])
  71                         return bits[i] < other.bits[i];
  72         return false;
  73 }
  74
  75 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
  76 {
  77         return bits == other.bits;
  78 }
  79
  80 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
  81 {
  82         return bits != other.bits;
  83 }
  84
  85 bool RTLIL::Const::as_bool() const
  86 {
  87         for (size_t i = 0; i < bits.size(); i++)
  88                 if (bits[i] == RTLIL::S1)
  89                         return true;
  90         return false;
  91 }
  92
  93 int RTLIL::Const::as_int() const
  94 {
  95         int ret = 0;
  96         for (size_t i = 0; i < bits.size() && i < 32; i++)
  97                 if (bits[i] == RTLIL::S1)
  98                         ret |= 1 << i;
  99         return ret;
 100 }
 101
 102 std::string RTLIL::Const::as_string() const
 103 {
 104         std::string ret;
 105         for (size_t i = bits.size(); i > 0; i--)
 106                 switch (bits[i-1]) {
 107                         case S0: ret += "0"; break;
 108                         case S1: ret += "1"; break;
 109                         case Sx: ret += "x"; break;
 110                         case Sz: ret += "z"; break;
 111                         case Sa: ret += "-"; break;
 112                         case Sm: ret += "m"; break;
 113                 }
 114         return ret;
 115 }
 116
 117 std::string RTLIL::Const::decode_string() const
 118 {
 119         std::string string;
 120         std::vector <char> string_chars;
 121         for (int i = 0; i < int (bits.size()); i += 8) {
 122                 char ch = 0;
 123                 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
 124                         if (bits[i + j] == RTLIL::State::S1)
 125                                 ch |= 1 << j;
 126                 if (ch != 0)
 127                         string_chars.push_back(ch);
 128         }
 129         for (int i = int (string_chars.size()) - 1; i >= 0; i--)
 130                 string += string_chars[i];
 131         return string;
 132 }
 133
 134 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
 135 {
 136         if (full_selection)
 137                 return true;
 138         if (selected_modules.count(mod_name) > 0)
 139                 return true;
 140         if (selected_members.count(mod_name) > 0)
 141                 return true;
 142         return false;
 143 }
 144
 145 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
 146 {
 147         if (full_selection)
 148                 return true;
 149         if (selected_modules.count(mod_name) > 0)
 150                 return true;
 151         return false;
 152 }
 153
 154 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 155 {
 156         if (full_selection)
 157                 return true;
 158         if (selected_modules.count(mod_name) > 0)
 159                 return true;
 160         if (selected_members.count(mod_name) > 0)
 161                 if (selected_members.at(mod_name).count(memb_name) > 0)
 162                         return true;
 163         return false;
 164 }
 165
 166 void RTLIL::Selection::optimize(RTLIL::Design *design)
 167 {
 168         if (full_selection) {
 169                 selected_modules.clear();
 170                 selected_members.clear();
 171                 return;
 172         }
 173
 174         std::vector<RTLIL::IdString> del_list, add_list;
 175
 176         del_list.clear();
 177         for (auto mod_name : selected_modules) {
 178                 if (design->modules.count(mod_name) == 0)
 179                         del_list.push_back(mod_name);
 180                 selected_members.erase(mod_name);
 181         }
 182         for (auto mod_name : del_list)
 183                 selected_modules.erase(mod_name);
 184
 185         del_list.clear();
 186         for (auto &it : selected_members)
 187                 if (design->modules.count(it.first) == 0)
 188                         del_list.push_back(it.first);
 189         for (auto mod_name : del_list)
 190                 selected_members.erase(mod_name);
 191
 192         for (auto &it : selected_members) {
 193                 del_list.clear();
 194                 for (auto memb_name : it.second)
 195                         if (design->modules[it.first]->count_id(memb_name) == 0)
 196                                 del_list.push_back(memb_name);
 197                 for (auto memb_name : del_list)
 198                         it.second.erase(memb_name);
 199         }
 200
 201         del_list.clear();
 202         add_list.clear();
 203         for (auto &it : selected_members)
 204                 if (it.second.size() == 0)
 205                         del_list.push_back(it.first);
 206                 else if (it.second.size() == design->modules[it.first]->wires.size() + design->modules[it.first]->memories.size() +
 207                                 design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size())
 208                         add_list.push_back(it.first);
 209         for (auto mod_name : del_list)
 210                 selected_members.erase(mod_name);
 211         for (auto mod_name : add_list) {
 212                 selected_members.erase(mod_name);
 213                 selected_modules.insert(mod_name);
 214         }
 215
 216         if (selected_modules.size() == design->modules.size()) {
 217                 full_selection = true;
 218                 selected_modules.clear();
 219                 selected_members.clear();
 220         }
 221 }
 222
 223 RTLIL::Design::~Design()
 224 {
 225         for (auto it = modules.begin(); it != modules.end(); it++)
 226                 delete it->second;
 227 }
 228
 229 void RTLIL::Design::check()
 230 {
 231 #ifndef NDEBUG
 232         for (auto &it : modules) {
 233                 assert(it.first == it.second->name);
 234                 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 235                 it.second->check();
 236         }
 237 #endif
 238 }
 239
 240 void RTLIL::Design::optimize()
 241 {
 242         for (auto &it : modules)
 243                 it.second->optimize();
 244         for (auto &it : selection_stack)
 245                 it.optimize(this);
 246         for (auto &it : selection_vars)
 247                 it.second.optimize(this);
 248 }
 249
 250 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
 251 {
 252         if (!selected_active_module.empty() && mod_name != selected_active_module)
 253                 return false;
 254         if (selection_stack.size() == 0)
 255                 return true;
 256         return selection_stack.back().selected_module(mod_name);
 257 }
 258
 259 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
 260 {
 261         if (!selected_active_module.empty() && mod_name != selected_active_module)
 262                 return false;
 263         if (selection_stack.size() == 0)
 264                 return true;
 265         return selection_stack.back().selected_whole_module(mod_name);
 266 }
 267
 268 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 269 {
 270         if (!selected_active_module.empty() && mod_name != selected_active_module)
 271                 return false;
 272         if (selection_stack.size() == 0)
 273                 return true;
 274         return selection_stack.back().selected_member(mod_name, memb_name);
 275 }
 276
 277 RTLIL::Module::~Module()
 278 {
 279         for (auto it = wires.begin(); it != wires.end(); it++)
 280                 delete it->second;
 281         for (auto it = memories.begin(); it != memories.end(); it++)
 282                 delete it->second;
 283         for (auto it = cells.begin(); it != cells.end(); it++)
 284                 delete it->second;
 285         for (auto it = processes.begin(); it != processes.end(); it++)
 286                 delete it->second;
 287 }
 288
 289 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
 290 {
 291         log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 292 }
 293
 294 size_t RTLIL::Module::count_id(RTLIL::IdString id)
 295 {
 296         return wires.count(id) + memories.count(id) + cells.count(id) + processes.count(id);
 297 }
 298
 299 #ifndef NDEBUG
 300 namespace {
 301         struct InternalCellChecker
 302         {
 303                 RTLIL::Module *module;
 304                 RTLIL::Cell *cell;
 305                 std::set<RTLIL::IdString> expected_params, expected_ports;
 306
 307                 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
 308
 309                 void error(int linenr)
 310                 {
 311                         char *ptr;
 312                         size_t size;
 313
 314                         FILE *f = open_memstream(&ptr, &size);
 315                         ILANG_BACKEND::dump_cell(f, "  ", cell);
 316                         fputc(0, f);
 317                         fclose(f);
 318
 319                         log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
 320                                         module ? module->name.c_str() : "", module ? "." : "",
 321                                         cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
 322                 }
 323
 324                 int param(const char *name)
 325                 {
 326                         if (cell->parameters.count(name) == 0)
 327                                 error(__LINE__);
 328                         expected_params.insert(name);
 329                         return cell->parameters.at(name).as_int();
 330                 }
 331
 332                 int param_bool(const char *name)
 333                 {
 334                         int v = param(name);
 335                         if (cell->parameters.at(name).bits.size() > 32)
 336                                 error(__LINE__);
 337                         if (v != 0 && v != 1)
 338                                 error(__LINE__);
 339                         return v;
 340                 }
 341
 342                 void param_bits(const char *name, int width)
 343                 {
 344                         param(name);
 345                         if (int(cell->parameters.at(name).bits.size()) != width)
 346                                 error(__LINE__);
 347                 }
 348
 349                 void port(const char *name, int width)
 350                 {
 351                         if (cell->connections.count(name) == 0)
 352                                 error(__LINE__);
 353                         if (cell->connections.at(name).size() != width)
 354                                 error(__LINE__);
 355                         expected_ports.insert(name);
 356                 }
 357
 358                 void check_expected(bool check_matched_sign = true)
 359                 {
 360                         for (auto &para : cell->parameters)
 361                                 if (expected_params.count(para.first) == 0)
 362                                         error(__LINE__);
 363                         for (auto &conn : cell->connections)
 364                                 if (expected_ports.count(conn.first) == 0)
 365                                         error(__LINE__);
 366
 367                         if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
 368                                 bool a_is_signed = param("\\A_SIGNED") != 0;
 369                                 bool b_is_signed = param("\\B_SIGNED") != 0;
 370                                 if (a_is_signed != b_is_signed)
 371                                         error(__LINE__);
 372                         }
 373                 }
 374
 375                 void check_gate(const char *ports)
 376                 {
 377                         if (cell->parameters.size() != 0)
 378                                 error(__LINE__);
 379
 380                         for (const char *p = ports; *p; p++) {
 381                                 char portname[3] = { '\\', *p, 0 };
 382                                 if (cell->connections.count(portname) == 0)
 383                                         error(__LINE__);
 384                                 if (cell->connections.at(portname).size() != 1)
 385                                         error(__LINE__);
 386                         }
 387
 388                         for (auto &conn : cell->connections) {
 389                                 if (conn.first.size() != 2 || conn.first.at(0) != '\\')
 390                                         error(__LINE__);
 391                                 if (strchr(ports, conn.first.at(1)) == NULL)
 392                                         error(__LINE__);
 393                         }
 394                 }
 395
 396                 void check()
 397                 {
 398                         if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
 399                                         cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:")
 400                                 return;
 401
 402                         if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
 403                                 param_bool("\\A_SIGNED");
 404                                 port("\\A", param("\\A_WIDTH"));
 405                                 port("\\Y", param("\\Y_WIDTH"));
 406                                 check_expected();
 407                                 return;
 408                         }
 409
 410                         if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
 411                                 param_bool("\\A_SIGNED");
 412                                 param_bool("\\B_SIGNED");
 413                                 port("\\A", param("\\A_WIDTH"));
 414                                 port("\\B", param("\\B_WIDTH"));
 415                                 port("\\Y", param("\\Y_WIDTH"));
 416                                 check_expected();
 417                                 return;
 418                         }
 419
 420                         if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
 421                                         cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
 422                                 param_bool("\\A_SIGNED");
 423                                 port("\\A", param("\\A_WIDTH"));
 424                                 port("\\Y", param("\\Y_WIDTH"));
 425                                 check_expected();
 426                                 return;
 427                         }
 428
 429                         if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
 430                                 param_bool("\\A_SIGNED");
 431                                 param_bool("\\B_SIGNED");
 432                                 port("\\A", param("\\A_WIDTH"));
 433                                 port("\\B", param("\\B_WIDTH"));
 434                                 port("\\Y", param("\\Y_WIDTH"));
 435                                 check_expected(false);
 436                                 return;
 437                         }
 438
 439                         if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
 440                                         cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
 441                                 param_bool("\\A_SIGNED");
 442                                 param_bool("\\B_SIGNED");
 443                                 port("\\A", param("\\A_WIDTH"));
 444                                 port("\\B", param("\\B_WIDTH"));
 445                                 port("\\Y", param("\\Y_WIDTH"));
 446                                 check_expected();
 447                                 return;
 448                         }
 449
 450                         if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
 451                                         cell->type == "$mod" || cell->type == "$pow") {
 452                                 param_bool("\\A_SIGNED");
 453                                 param_bool("\\B_SIGNED");
 454                                 port("\\A", param("\\A_WIDTH"));
 455                                 port("\\B", param("\\B_WIDTH"));
 456                                 port("\\Y", param("\\Y_WIDTH"));
 457                                 check_expected(cell->type != "$pow");
 458                                 return;
 459                         }
 460
 461                         if (cell->type == "$logic_not") {
 462                                 param_bool("\\A_SIGNED");
 463                                 port("\\A", param("\\A_WIDTH"));
 464                                 port("\\Y", param("\\Y_WIDTH"));
 465                                 check_expected();
 466                                 return;
 467                         }
 468
 469                         if (cell->type == "$logic_and" || cell->type == "$logic_or") {
 470                                 param_bool("\\A_SIGNED");
 471                                 param_bool("\\B_SIGNED");
 472                                 port("\\A", param("\\A_WIDTH"));
 473                                 port("\\B", param("\\B_WIDTH"));
 474                                 port("\\Y", param("\\Y_WIDTH"));
 475                                 check_expected(false);
 476                                 return;
 477                         }
 478
 479                         if (cell->type == "$slice") {
 480                                 param("\\OFFSET");
 481                                 port("\\A", param("\\A_WIDTH"));
 482                                 port("\\Y", param("\\Y_WIDTH"));
 483                                 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
 484                                         error(__LINE__);
 485                                 check_expected();
 486                                 return;
 487                         }
 488
 489                         if (cell->type == "$concat") {
 490                                 port("\\A", param("\\A_WIDTH"));
 491                                 port("\\B", param("\\B_WIDTH"));
 492                                 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
 493                                 check_expected();
 494                                 return;
 495                         }
 496
 497                         if (cell->type == "$mux") {
 498                                 port("\\A", param("\\WIDTH"));
 499                                 port("\\B", param("\\WIDTH"));
 500                                 port("\\S", 1);
 501                                 port("\\Y", param("\\WIDTH"));
 502                                 check_expected();
 503                                 return;
 504                         }
 505
 506                         if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
 507                                 port("\\A", param("\\WIDTH"));
 508                                 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
 509                                 port("\\S", param("\\S_WIDTH"));
 510                                 port("\\Y", param("\\WIDTH"));
 511                                 check_expected();
 512                                 return;
 513                         }
 514
 515                         if (cell->type == "$lut") {
 516                                 param("\\LUT");
 517                                 port("\\I", param("\\WIDTH"));
 518                                 port("\\O", 1);
 519                                 check_expected();
 520                                 return;
 521                         }
 522
 523                         if (cell->type == "$sr") {
 524                                 param_bool("\\SET_POLARITY");
 525                                 param_bool("\\CLR_POLARITY");
 526                                 port("\\SET", param("\\WIDTH"));
 527                                 port("\\CLR", param("\\WIDTH"));
 528                                 port("\\Q",   param("\\WIDTH"));
 529                                 check_expected();
 530                                 return;
 531                         }
 532
 533                         if (cell->type == "$dff") {
 534                                 param_bool("\\CLK_POLARITY");
 535                                 port("\\CLK", 1);
 536                                 port("\\D", param("\\WIDTH"));
 537                                 port("\\Q", param("\\WIDTH"));
 538                                 check_expected();
 539                                 return;
 540                         }
 541
 542                         if (cell->type == "$dffsr") {
 543                                 param_bool("\\CLK_POLARITY");
 544                                 param_bool("\\SET_POLARITY");
 545                                 param_bool("\\CLR_POLARITY");
 546                                 port("\\CLK", 1);
 547                                 port("\\SET", param("\\WIDTH"));
 548                                 port("\\CLR", param("\\WIDTH"));
 549                                 port("\\D", param("\\WIDTH"));
 550                                 port("\\Q", param("\\WIDTH"));
 551                                 check_expected();
 552                                 return;
 553                         }
 554
 555                         if (cell->type == "$adff") {
 556                                 param_bool("\\CLK_POLARITY");
 557                                 param_bool("\\ARST_POLARITY");
 558                                 param_bits("\\ARST_VALUE", param("\\WIDTH"));
 559                                 port("\\CLK", 1);
 560                                 port("\\ARST", 1);
 561                                 port("\\D", param("\\WIDTH"));
 562                                 port("\\Q", param("\\WIDTH"));
 563                                 check_expected();
 564                                 return;
 565                         }
 566
 567                         if (cell->type == "$dlatch") {
 568                                 param_bool("\\EN_POLARITY");
 569                                 port("\\EN", 1);
 570                                 port("\\D", param("\\WIDTH"));
 571                                 port("\\Q", param("\\WIDTH"));
 572                                 check_expected();
 573                                 return;
 574                         }
 575
 576                         if (cell->type == "$dlatchsr") {
 577                                 param_bool("\\EN_POLARITY");
 578                                 param_bool("\\SET_POLARITY");
 579                                 param_bool("\\CLR_POLARITY");
 580                                 port("\\EN", 1);
 581                                 port("\\SET", param("\\WIDTH"));
 582                                 port("\\CLR", param("\\WIDTH"));
 583                                 port("\\D", param("\\WIDTH"));
 584                                 port("\\Q", param("\\WIDTH"));
 585                                 check_expected();
 586                                 return;
 587                         }
 588
 589                         if (cell->type == "$fsm") {
 590                                 param("\\NAME");
 591                                 param_bool("\\CLK_POLARITY");
 592                                 param_bool("\\ARST_POLARITY");
 593                                 param("\\STATE_BITS");
 594                                 param("\\STATE_NUM");
 595                                 param("\\STATE_NUM_LOG2");
 596                                 param("\\STATE_RST");
 597                                 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
 598                                 param("\\TRANS_NUM");
 599                                 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
 600                                 port("\\CLK", 1);
 601                                 port("\\ARST", 1);
 602                                 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
 603                                 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
 604                                 check_expected();
 605                                 return;
 606                         }
 607
 608                         if (cell->type == "$memrd") {
 609                                 param("\\MEMID");
 610                                 param_bool("\\CLK_ENABLE");
 611                                 param_bool("\\CLK_POLARITY");
 612                                 param_bool("\\TRANSPARENT");
 613                                 port("\\CLK", 1);
 614                                 port("\\ADDR", param("\\ABITS"));
 615                                 port("\\DATA", param("\\WIDTH"));
 616                                 check_expected();
 617                                 return;
 618                         }
 619
 620                         if (cell->type == "$memwr") {
 621                                 param("\\MEMID");
 622                                 param_bool("\\CLK_ENABLE");
 623                                 param_bool("\\CLK_POLARITY");
 624                                 param("\\PRIORITY");
 625                                 port("\\CLK", 1);
 626                                 port("\\EN", param("\\WIDTH"));
 627                                 port("\\ADDR", param("\\ABITS"));
 628                                 port("\\DATA", param("\\WIDTH"));
 629                                 check_expected();
 630                                 return;
 631                         }
 632
 633                         if (cell->type == "$mem") {
 634                                 param("\\MEMID");
 635                                 param("\\SIZE");
 636                                 param("\\OFFSET");
 637                                 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
 638                                 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
 639                                 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
 640                                 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
 641                                 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
 642                                 port("\\RD_CLK", param("\\RD_PORTS"));
 643                                 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
 644                                 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
 645                                 port("\\WR_CLK", param("\\WR_PORTS"));
 646                                 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
 647                                 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
 648                                 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
 649                                 check_expected();
 650                                 return;
 651                         }
 652
 653                         if (cell->type == "$assert") {
 654                                 port("\\A", 1);
 655                                 port("\\EN", 1);
 656                                 check_expected();
 657                                 return;
 658                         }
 659
 660                         if (cell->type == "$_INV_") { check_gate("AY"); return; }
 661                         if (cell->type == "$_AND_") { check_gate("ABY"); return; }
 662                         if (cell->type == "$_OR_")  { check_gate("ABY"); return; }
 663                         if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
 664                         if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
 665
 666                         if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
 667                         if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
 668                         if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
 669                         if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
 670
 671                         if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
 672                         if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
 673
 674                         if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
 675                         if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
 676                         if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
 677                         if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
 678                         if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
 679                         if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
 680                         if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
 681                         if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
 682
 683                         if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
 684                         if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
 685                         if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
 686                         if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
 687                         if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
 688                         if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
 689                         if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
 690                         if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
 691
 692                         if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
 693                         if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
 694
 695                         if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
 696                         if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
 697                         if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
 698                         if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
 699                         if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
 700                         if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
 701                         if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
 702                         if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
 703
 704                         error(__LINE__);
 705                 }
 706         };
 707 }
 708 #endif
 709
 710 void RTLIL::Module::check()
 711 {
 712 #ifndef NDEBUG
 713         for (auto &it : wires) {
 714                 assert(it.first == it.second->name);
 715                 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 716                 assert(it.second->width >= 0);
 717                 assert(it.second->port_id >= 0);
 718                 for (auto &it2 : it.second->attributes) {
 719                         assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 720                 }
 721         }
 722
 723         for (auto &it : memories) {
 724                 assert(it.first == it.second->name);
 725                 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 726                 assert(it.second->width >= 0);
 727                 assert(it.second->size >= 0);
 728                 for (auto &it2 : it.second->attributes) {
 729                         assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 730                 }
 731         }
 732
 733         for (auto &it : cells) {
 734                 assert(it.first == it.second->name);
 735                 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 736                 assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
 737                 for (auto &it2 : it.second->connections) {
 738                         assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 739                         it2.second.check();
 740                 }
 741                 for (auto &it2 : it.second->attributes) {
 742                         assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 743                 }
 744                 for (auto &it2 : it.second->parameters) {
 745                         assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 746                 }
 747                 InternalCellChecker checker(this, it.second);
 748                 checker.check();
 749         }
 750
 751         for (auto &it : processes) {
 752                 assert(it.first == it.second->name);
 753                 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 754                 // FIXME: More checks here..
 755         }
 756
 757         for (auto &it : connections) {
 758                 assert(it.first.size() == it.second.size());
 759                 it.first.check();
 760                 it.second.check();
 761         }
 762
 763         for (auto &it : attributes) {
 764                 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 765         }
 766 #endif
 767 }
 768
 769 void RTLIL::Module::optimize()
 770 {
 771         for (auto &it : cells)
 772                 it.second->optimize();
 773         for (auto &it : processes)
 774                 it.second->optimize();
 775         for (auto &it : connections) {
 776                 it.first.optimize();
 777                 it.second.optimize();
 778         }
 779 }
 780
 781 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 782 {
 783         new_mod->name = name;
 784         new_mod->connections = connections;
 785         new_mod->attributes = attributes;
 786
 787         for (auto &it : wires)
 788                 new_mod->wires[it.first] = new RTLIL::Wire(*it.second);
 789
 790         for (auto &it : memories)
 791                 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
 792
 793         for (auto &it : cells)
 794                 new_mod->cells[it.first] = new RTLIL::Cell(*it.second);
 795
 796         for (auto &it : processes)
 797                 new_mod->processes[it.first] = it.second->clone();
 798
 799         struct RewriteSigSpecWorker
 800         {
 801                 RTLIL::Module *mod;
 802                 void operator()(RTLIL::SigSpec &sig)
 803                 {
 804                         std::vector<RTLIL::SigChunk> chunks = sig.chunks();
 805                         for (auto &c : chunks)
 806                                 if (c.wire != NULL)
 807                                         c.wire = mod->wires.at(c.wire->name);
 808                         sig = chunks;
 809                 }
 810         };
 811
 812         RewriteSigSpecWorker rewriteSigSpecWorker;
 813         rewriteSigSpecWorker.mod = new_mod;
 814         new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
 815 }
 816
 817 RTLIL::Module *RTLIL::Module::clone() const
 818 {
 819         RTLIL::Module *new_mod = new RTLIL::Module;
 820         cloneInto(new_mod);
 821         return new_mod;
 822 }
 823
 824 void RTLIL::Module::add(RTLIL::Wire *wire)
 825 {
 826         assert(!wire->name.empty());
 827         assert(count_id(wire->name) == 0);
 828         wires[wire->name] = wire;
 829 }
 830
 831 void RTLIL::Module::add(RTLIL::Cell *cell)
 832 {
 833         assert(!cell->name.empty());
 834         assert(count_id(cell->name) == 0);
 835         cells[cell->name] = cell;
 836 }
 837
 838 void RTLIL::Module::remove(RTLIL::Cell *cell)
 839 {
 840         assert(cells.count(cell->name) != 0);
 841         cells.erase(cell->name);
 842         delete cell;
 843 }
 844
 845 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 846 {
 847         if (a->port_id && !b->port_id)
 848                 return true;
 849         if (!a->port_id && b->port_id)
 850                 return false;
 851
 852         if (a->port_id == b->port_id)
 853                 return a->name < b->name;
 854         return a->port_id < b->port_id;
 855 }
 856
 857 void RTLIL::Module::fixup_ports()
 858 {
 859         std::vector<RTLIL::Wire*> all_ports;
 860
 861         for (auto &w : wires)
 862                 if (w.second->port_input || w.second->port_output)
 863                         all_ports.push_back(w.second);
 864                 else
 865                         w.second->port_id = 0;
 866
 867         std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
 868         for (size_t i = 0; i < all_ports.size(); i++)
 869                 all_ports[i]->port_id = i+1;
 870 }
 871
 872 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
 873 {
 874         RTLIL::Wire *wire = new RTLIL::Wire;
 875         wire->name = name;
 876         wire->width = width;
 877         add(wire);
 878         return wire;
 879 }
 880
 881 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
 882 {
 883         RTLIL::Cell *cell = new RTLIL::Cell;
 884         cell->name = name;
 885         cell->type = type;
 886         add(cell);
 887         return cell;
 888 }
 889
 890 #define DEF_METHOD(_func, _y_size, _type) \
 891         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
 892                 RTLIL::Cell *cell = new RTLIL::Cell;                \
 893                 cell->name = name;                                  \
 894                 cell->type = _type;                                 \
 895                 cell->parameters["\\A_SIGNED"] = is_signed;         \
 896                 cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 897                 cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
 898                 cell->connections["\\A"] = sig_a;                   \
 899                 cell->connections["\\Y"] = sig_y;                   \
 900                 add(cell);                                          \
 901                 return cell;                                        \
 902         } \
 903         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
 904                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);    \
 905                 add ## _func(name, sig_a, sig_y, is_signed);        \
 906                 return sig_y;                                       \
 907         }
 908 DEF_METHOD(Not,        sig_a.size(), "$not")
 909 DEF_METHOD(Pos,        sig_a.size(), "$pos")
 910 DEF_METHOD(Bu0,        sig_a.size(), "$bu0")
 911 DEF_METHOD(Neg,        sig_a.size(), "$neg")
 912 DEF_METHOD(ReduceAnd,  1, "$reduce_and")
 913 DEF_METHOD(ReduceOr,   1, "$reduce_or")
 914 DEF_METHOD(ReduceXor,  1, "$reduce_xor")
 915 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
 916 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
 917 DEF_METHOD(LogicNot,   1, "$logic_not")
 918 #undef DEF_METHOD
 919
 920 #define DEF_METHOD(_func, _y_size, _type) \
 921         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
 922                 RTLIL::Cell *cell = new RTLIL::Cell;                \
 923                 cell->name = name;                                  \
 924                 cell->type = _type;                                 \
 925                 cell->parameters["\\A_SIGNED"] = is_signed;         \
 926                 cell->parameters["\\B_SIGNED"] = is_signed;         \
 927                 cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 928                 cell->parameters["\\B_WIDTH"] = sig_b.size();        \
 929                 cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
 930                 cell->connections["\\A"] = sig_a;                   \
 931                 cell->connections["\\B"] = sig_b;                   \
 932                 cell->connections["\\Y"] = sig_y;                   \
 933                 add(cell);                                          \
 934                 return cell;                                        \
 935         } \
 936         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
 937                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);    \
 938                 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
 939                 return sig_y;                                       \
 940         }
 941 DEF_METHOD(And,      std::max(sig_a.size(), sig_b.size()), "$and")
 942 DEF_METHOD(Or,       std::max(sig_a.size(), sig_b.size()), "$or")
 943 DEF_METHOD(Xor,      std::max(sig_a.size(), sig_b.size()), "$xor")
 944 DEF_METHOD(Xnor,     std::max(sig_a.size(), sig_b.size()), "$xnor")
 945 DEF_METHOD(Shl,      sig_a.size(), "$shl")
 946 DEF_METHOD(Shr,      sig_a.size(), "$shr")
 947 DEF_METHOD(Sshl,     sig_a.size(), "$sshl")
 948 DEF_METHOD(Sshr,     sig_a.size(), "$sshr")
 949 DEF_METHOD(Lt,       1, "$lt")
 950 DEF_METHOD(Le,       1, "$le")
 951 DEF_METHOD(Eq,       1, "$eq")
 952 DEF_METHOD(Ne,       1, "$ne")
 953 DEF_METHOD(Eqx,      1, "$eqx")
 954 DEF_METHOD(Nex,      1, "$nex")
 955 DEF_METHOD(Ge,       1, "$ge")
 956 DEF_METHOD(Gt,       1, "$gt")
 957 DEF_METHOD(Add,      std::max(sig_a.size(), sig_b.size()), "$add")
 958 DEF_METHOD(Sub,      std::max(sig_a.size(), sig_b.size()), "$sub")
 959 DEF_METHOD(Mul,      std::max(sig_a.size(), sig_b.size()), "$mul")
 960 DEF_METHOD(Div,      std::max(sig_a.size(), sig_b.size()), "$div")
 961 DEF_METHOD(Mod,      std::max(sig_a.size(), sig_b.size()), "$mod")
 962 DEF_METHOD(LogicAnd, 1, "$logic_and")
 963 DEF_METHOD(LogicOr,  1, "$logic_or")
 964 #undef DEF_METHOD
 965
 966 #define DEF_METHOD(_func, _type, _pmux) \
 967         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
 968                 RTLIL::Cell *cell = new RTLIL::Cell;                     \
 969                 cell->name = name;                                       \
 970                 cell->type = _type;                                      \
 971                 cell->parameters["\\WIDTH"] = sig_a.size();               \
 972                 cell->parameters["\\WIDTH"] = sig_b.size();               \
 973                 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size();  \
 974                 cell->connections["\\A"] = sig_a;                        \
 975                 cell->connections["\\B"] = sig_b;                        \
 976                 cell->connections["\\S"] = sig_s;                        \
 977                 cell->connections["\\Y"] = sig_y;                        \
 978                 add(cell);                                               \
 979                 return cell;                                             \
 980         } \
 981         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
 982                 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size());     \
 983                 add ## _func(name, sig_a, sig_b, sig_s, sig_y);          \
 984                 return sig_y;                                            \
 985         }
 986 DEF_METHOD(Mux,      "$mux",        0)
 987 DEF_METHOD(Pmux,     "$pmux",       1)
 988 DEF_METHOD(SafePmux, "$safe_pmux",  1)
 989 #undef DEF_METHOD
 990
 991 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
 992         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
 993                 RTLIL::Cell *cell = new RTLIL::Cell;        \
 994                 cell->name = name;                          \
 995                 cell->type = _type;                         \
 996                 cell->connections["\\" #_P1] = sig1;        \
 997                 cell->connections["\\" #_P2] = sig2;        \
 998                 add(cell);                                  \
 999                 return cell;                                \
1000         } \
1001         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1002                 RTLIL::SigSpec sig2 = addWire(NEW_ID);      \
1003                 add ## _func(name, sig1, sig2);             \
1004                 return sig2;                                \
1005         }
1006 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1007         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1008                 RTLIL::Cell *cell = new RTLIL::Cell;        \
1009                 cell->name = name;                          \
1010                 cell->type = _type;                         \
1011                 cell->connections["\\" #_P1] = sig1;        \
1012                 cell->connections["\\" #_P2] = sig2;        \
1013                 cell->connections["\\" #_P3] = sig3;        \
1014                 add(cell);                                  \
1015                 return cell;                                \
1016         } \
1017         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1018                 RTLIL::SigSpec sig3 = addWire(NEW_ID);      \
1019                 add ## _func(name, sig1, sig2, sig3);       \
1020                 return sig3;                                \
1021         }
1022 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1023         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1024                 RTLIL::Cell *cell = new RTLIL::Cell;        \
1025                 cell->name = name;                          \
1026                 cell->type = _type;                         \
1027                 cell->connections["\\" #_P1] = sig1;        \
1028                 cell->connections["\\" #_P2] = sig2;        \
1029                 cell->connections["\\" #_P3] = sig3;        \
1030                 cell->connections["\\" #_P4] = sig4;        \
1031                 add(cell);                                  \
1032                 return cell;                                \
1033         } \
1034         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1035                 RTLIL::SigSpec sig4 = addWire(NEW_ID);      \
1036                 add ## _func(name, sig1, sig2, sig3, sig4); \
1037                 return sig4;                                \
1038         }
1039 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1040 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1041 DEF_METHOD_3(OrGate,  "$_OR_",  A, B, Y)
1042 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1043 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1044 #undef DEF_METHOD_2
1045 #undef DEF_METHOD_3
1046 #undef DEF_METHOD_4
1047
1048 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1049 {
1050         RTLIL::Cell *cell = new RTLIL::Cell;
1051         cell->name = name;
1052         cell->type = "$pow";
1053         cell->parameters["\\A_SIGNED"] = a_signed;
1054         cell->parameters["\\B_SIGNED"] = b_signed;
1055         cell->parameters["\\A_WIDTH"] = sig_a.size();
1056         cell->parameters["\\B_WIDTH"] = sig_b.size();
1057         cell->parameters["\\Y_WIDTH"] = sig_y.size();
1058         cell->connections["\\A"] = sig_a;
1059         cell->connections["\\B"] = sig_b;
1060         cell->connections["\\Y"] = sig_y;
1061         add(cell);
1062         return cell;
1063 }
1064
1065 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1066 {
1067         RTLIL::Cell *cell = new RTLIL::Cell;
1068         cell->name = name;
1069         cell->type = "$slice";
1070         cell->parameters["\\A_WIDTH"] = sig_a.size();
1071         cell->parameters["\\Y_WIDTH"] = sig_y.size();
1072         cell->parameters["\\OFFSET"] = offset;
1073         cell->connections["\\A"] = sig_a;
1074         cell->connections["\\Y"] = sig_y;
1075         add(cell);
1076         return cell;
1077 }
1078
1079 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1080 {
1081         RTLIL::Cell *cell = new RTLIL::Cell;
1082         cell->name = name;
1083         cell->type = "$concat";
1084         cell->parameters["\\A_WIDTH"] = sig_a.size();
1085         cell->parameters["\\B_WIDTH"] = sig_b.size();
1086         cell->connections["\\A"] = sig_a;
1087         cell->connections["\\B"] = sig_b;
1088         cell->connections["\\Y"] = sig_y;
1089         add(cell);
1090         return cell;
1091 }
1092
1093 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1094 {
1095         RTLIL::Cell *cell = new RTLIL::Cell;
1096         cell->name = name;
1097         cell->type = "$lut";
1098         cell->parameters["\\LUT"] = lut;
1099         cell->parameters["\\WIDTH"] = sig_i.size();
1100         cell->connections["\\I"] = sig_i;
1101         cell->connections["\\O"] = sig_o;
1102         add(cell);
1103         return cell;
1104 }
1105
1106 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1107 {
1108         RTLIL::Cell *cell = new RTLIL::Cell;
1109         cell->name = name;
1110         cell->type = "$assert";
1111         cell->connections["\\A"] = sig_a;
1112         cell->connections["\\EN"] = sig_en;
1113         add(cell);
1114         return cell;
1115 }
1116
1117 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1118 {
1119         RTLIL::Cell *cell = new RTLIL::Cell;
1120         cell->name = name;
1121         cell->type = "$sr";
1122         cell->parameters["\\SET_POLARITY"] = set_polarity;
1123         cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1124         cell->parameters["\\WIDTH"] = sig_q.size();
1125         cell->connections["\\SET"] = sig_set;
1126         cell->connections["\\CLR"] = sig_clr;
1127         cell->connections["\\Q"] = sig_q;
1128         add(cell);
1129         return cell;
1130 }
1131
1132 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d,   RTLIL::SigSpec sig_q, bool clk_polarity)
1133 {
1134         RTLIL::Cell *cell = new RTLIL::Cell;
1135         cell->name = name;
1136         cell->type = "$dff";
1137         cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1138         cell->parameters["\\WIDTH"] = sig_q.size();
1139         cell->connections["\\CLK"] = sig_clk;
1140         cell->connections["\\D"] = sig_d;
1141         cell->connections["\\Q"] = sig_q;
1142         add(cell);
1143         return cell;
1144 }
1145
1146 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1147                 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1148 {
1149         RTLIL::Cell *cell = new RTLIL::Cell;
1150         cell->name = name;
1151         cell->type = "$dffsr";
1152         cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1153         cell->parameters["\\SET_POLARITY"] = set_polarity;
1154         cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1155         cell->parameters["\\WIDTH"] = sig_q.size();
1156         cell->connections["\\CLK"] = sig_clk;
1157         cell->connections["\\SET"] = sig_set;
1158         cell->connections["\\CLR"] = sig_clr;
1159         cell->connections["\\D"] = sig_d;
1160         cell->connections["\\Q"] = sig_q;
1161         add(cell);
1162         return cell;
1163 }
1164
1165 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1166                 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1167 {
1168         RTLIL::Cell *cell = new RTLIL::Cell;
1169         cell->name = name;
1170         cell->type = "$adff";
1171         cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1172         cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1173         cell->parameters["\\ARST_VALUE"] = arst_value;
1174         cell->parameters["\\WIDTH"] = sig_q.size();
1175         cell->connections["\\CLK"] = sig_clk;
1176         cell->connections["\\ARST"] = sig_arst;
1177         cell->connections["\\D"] = sig_d;
1178         cell->connections["\\Q"] = sig_q;
1179         add(cell);
1180         return cell;
1181 }
1182
1183 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1184 {
1185         RTLIL::Cell *cell = new RTLIL::Cell;
1186         cell->name = name;
1187         cell->type = "$dlatch";
1188         cell->parameters["\\EN_POLARITY"] = en_polarity;
1189         cell->parameters["\\WIDTH"] = sig_q.size();
1190         cell->connections["\\EN"] = sig_en;
1191         cell->connections["\\D"] = sig_d;
1192         cell->connections["\\Q"] = sig_q;
1193         add(cell);
1194         return cell;
1195 }
1196
1197 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1198                 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1199 {
1200         RTLIL::Cell *cell = new RTLIL::Cell;
1201         cell->name = name;
1202         cell->type = "$dlatchsr";
1203         cell->parameters["\\EN_POLARITY"] = en_polarity;
1204         cell->parameters["\\SET_POLARITY"] = set_polarity;
1205         cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1206         cell->parameters["\\WIDTH"] = sig_q.size();
1207         cell->connections["\\EN"] = sig_en;
1208         cell->connections["\\SET"] = sig_set;
1209         cell->connections["\\CLR"] = sig_clr;
1210         cell->connections["\\D"] = sig_d;
1211         cell->connections["\\Q"] = sig_q;
1212         add(cell);
1213         return cell;
1214 }
1215
1216 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1217 {
1218         RTLIL::Cell *cell = new RTLIL::Cell;
1219         cell->name = name;
1220         cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
1221         cell->connections["\\C"] = sig_clk;
1222         cell->connections["\\D"] = sig_d;
1223         cell->connections["\\Q"] = sig_q;
1224         add(cell);
1225         return cell;
1226 }
1227
1228 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1229                 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1230 {
1231         RTLIL::Cell *cell = new RTLIL::Cell;
1232         cell->name = name;
1233         cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1234         cell->connections["\\C"] = sig_clk;
1235         cell->connections["\\S"] = sig_set;
1236         cell->connections["\\R"] = sig_clr;
1237         cell->connections["\\D"] = sig_d;
1238         cell->connections["\\Q"] = sig_q;
1239         add(cell);
1240         return cell;
1241 }
1242
1243 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1244                 bool arst_value, bool clk_polarity, bool arst_polarity)
1245 {
1246         RTLIL::Cell *cell = new RTLIL::Cell;
1247         cell->name = name;
1248         cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
1249         cell->connections["\\C"] = sig_clk;
1250         cell->connections["\\R"] = sig_arst;
1251         cell->connections["\\D"] = sig_d;
1252         cell->connections["\\Q"] = sig_q;
1253         add(cell);
1254         return cell;
1255 }
1256
1257 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1258 {
1259         RTLIL::Cell *cell = new RTLIL::Cell;
1260         cell->name = name;
1261         cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
1262         cell->connections["\\E"] = sig_en;
1263         cell->connections["\\D"] = sig_d;
1264         cell->connections["\\Q"] = sig_q;
1265         add(cell);
1266         return cell;
1267 }
1268
1269 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1270                 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1271 {
1272         RTLIL::Cell *cell = new RTLIL::Cell;
1273         cell->name = name;
1274         cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1275         cell->connections["\\E"] = sig_en;
1276         cell->connections["\\S"] = sig_set;
1277         cell->connections["\\R"] = sig_clr;
1278         cell->connections["\\D"] = sig_d;
1279         cell->connections["\\Q"] = sig_q;
1280         add(cell);
1281         return cell;
1282 }
1283
1284
1285 RTLIL::Wire::Wire()
1286 {
1287         width = 1;
1288         start_offset = 0;
1289         port_id = 0;
1290         port_input = false;
1291         port_output = false;
1292 }
1293
1294 RTLIL::Memory::Memory()
1295 {
1296         width = 1;
1297         size = 0;
1298 }
1299
1300 void RTLIL::Cell::optimize()
1301 {
1302         for (auto &it : connections)
1303                 it.second.optimize();
1304 }
1305
1306 void RTLIL::Cell::check()
1307 {
1308         InternalCellChecker checker(NULL, this);
1309         checker.check();
1310 }
1311
1312 RTLIL::SigChunk::SigChunk()
1313 {
1314         wire = NULL;
1315         width = 0;
1316         offset = 0;
1317 }
1318
1319 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1320 {
1321         wire = NULL;
1322         data = value;
1323         width = data.bits.size();
1324         offset = 0;
1325 }
1326
1327 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1328 {
1329         this->wire = wire;
1330         this->width = wire->width;
1331         this->offset = 0;
1332 }
1333
1334 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1335 {
1336         this->wire = wire;
1337         this->width = width;
1338         this->offset = offset;
1339 }
1340
1341 RTLIL::SigChunk::SigChunk(const std::string &str)
1342 {
1343         wire = NULL;
1344         data = RTLIL::Const(str);
1345         width = data.bits.size();
1346         offset = 0;
1347 }
1348
1349 RTLIL::SigChunk::SigChunk(int val, int width)
1350 {
1351         wire = NULL;
1352         data = RTLIL::Const(val, width);
1353         this->width = data.bits.size();
1354         offset = 0;
1355 }
1356
1357 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1358 {
1359         wire = NULL;
1360         data = RTLIL::Const(bit, width);
1361         this->width = data.bits.size();
1362         offset = 0;
1363 }
1364
1365 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1366 {
1367         wire = bit.wire;
1368         if (wire == NULL)
1369                 data = RTLIL::Const(bit.data);
1370         offset = bit.offset;
1371         width = 1;
1372 }
1373
1374 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1375 {
1376         RTLIL::SigChunk ret;
1377         if (wire) {
1378                 ret.wire = wire;
1379                 ret.offset = this->offset + offset;
1380                 ret.width = length;
1381         } else {
1382                 for (int i = 0; i < length; i++)
1383                         ret.data.bits.push_back(data.bits[offset+i]);
1384                 ret.width = length;
1385         }
1386         return ret;
1387 }
1388
1389 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1390 {
1391         if (wire && other.wire)
1392                 if (wire->name != other.wire->name)
1393                         return wire->name < other.wire->name;
1394
1395         if (wire != other.wire)
1396                 return wire < other.wire;
1397
1398         if (offset != other.offset)
1399                 return offset < other.offset;
1400
1401         if (width != other.width)
1402                 return width < other.width;
1403
1404         return data.bits < other.data.bits;
1405 }
1406
1407 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1408 {
1409         if (wire != other.wire || width != other.width || offset != other.offset)
1410                 return false;
1411         if (data.bits != other.data.bits)
1412                 return false;
1413         return true;
1414 }
1415
1416 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1417 {
1418         if (*this == other)
1419                 return false;
1420         return true;
1421 }
1422
1423 RTLIL::SigSpec::SigSpec()
1424 {
1425         width_ = 0;
1426 }
1427
1428 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1429 {
1430         chunks_.push_back(RTLIL::SigChunk(value));
1431         width_ = chunks_.back().width;
1432         check();
1433 }
1434
1435 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1436 {
1437         chunks_.push_back(chunk);
1438         width_ = chunks_.back().width;
1439         check();
1440 }
1441
1442 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1443 {
1444         chunks_.push_back(RTLIL::SigChunk(wire));
1445         width_ = chunks_.back().width;
1446         check();
1447 }
1448
1449 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1450 {
1451         chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1452         width_ = chunks_.back().width;
1453         check();
1454 }
1455
1456 RTLIL::SigSpec::SigSpec(const std::string &str)
1457 {
1458         chunks_.push_back(RTLIL::SigChunk(str));
1459         width_ = chunks_.back().width;
1460         check();
1461 }
1462
1463 RTLIL::SigSpec::SigSpec(int val, int width)
1464 {
1465         chunks_.push_back(RTLIL::SigChunk(val, width));
1466         width_ = width;
1467         check();
1468 }
1469
1470 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1471 {
1472         chunks_.push_back(RTLIL::SigChunk(bit, width));
1473         width_ = width;
1474         check();
1475 }
1476
1477 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1478 {
1479         if (bit.wire == NULL)
1480                 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1481         else
1482                 for (int i = 0; i < width; i++)
1483                         chunks_.push_back(bit);
1484         width_ = width;
1485         check();
1486 }
1487
1488 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1489 {
1490         width_ = 0;
1491         for (auto &c : chunks)
1492                 append(c);
1493         check();
1494 }
1495
1496 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1497 {
1498         width_ = 0;
1499         for (auto &bit : bits)
1500                 append_bit(bit);
1501         check();
1502 }
1503
1504 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1505 {
1506         width_ = 0;
1507         for (auto &bit : bits)
1508                 append_bit(bit);
1509         check();
1510 }
1511
1512 void RTLIL::SigSpec::pack() const
1513 {
1514         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1515
1516         if (that->bits_.empty())
1517                 return;
1518
1519         log_assert(that->chunks_.empty());
1520
1521         std::vector<RTLIL::SigBit> old_bits;
1522         old_bits.swap(that->bits_);
1523
1524         that->width_ = 0;
1525         for (auto &bit : old_bits)
1526                 that->append_bit(bit);
1527 }
1528
1529 void RTLIL::SigSpec::unpack() const
1530 {
1531         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1532
1533         if (that->chunks_.empty())
1534                 return;
1535
1536         log_assert(that->bits_.empty());
1537
1538         that->bits_.reserve(that->width_);
1539         for (auto &c : that->chunks_)
1540                 for (int i = 0; i < c.width; i++)
1541                         that->bits_.push_back(RTLIL::SigBit(c, i));
1542
1543         that->chunks_.clear();
1544 }
1545
1546 bool RTLIL::SigSpec::packed() const
1547 {
1548         return bits_.empty();
1549 }
1550
1551 void RTLIL::SigSpec::expand()
1552 {
1553         pack();
1554         std::vector<RTLIL::SigChunk> new_chunks;
1555         for (size_t i = 0; i < chunks_.size(); i++) {
1556                 for (int j = 0; j < chunks_[i].width; j++)
1557                         new_chunks.push_back(chunks_[i].extract(j, 1));
1558         }
1559         chunks_.swap(new_chunks);
1560         check();
1561 }
1562
1563 void RTLIL::SigSpec::optimize()
1564 {
1565         pack();
1566         std::vector<RTLIL::SigChunk> new_chunks;
1567         for (auto &c : chunks_)
1568                 if (new_chunks.size() == 0) {
1569                         new_chunks.push_back(c);
1570                 } else {
1571                         RTLIL::SigChunk &cc = new_chunks.back();
1572                         if (c.wire == NULL && cc.wire == NULL)
1573                                 cc.data.bits.insert(cc.data.bits.end(), c.data.bits.begin(), c.data.bits.end());
1574                         if (c.wire == cc.wire && (c.wire == NULL || cc.offset + cc.width == c.offset))
1575                                 cc.width += c.width;
1576                         else
1577                                 new_chunks.push_back(c);
1578                 }
1579         chunks_.swap(new_chunks);
1580         check();
1581 }
1582
1583 RTLIL::SigSpec RTLIL::SigSpec::optimized() const
1584 {
1585         pack();
1586         RTLIL::SigSpec ret = *this;
1587         ret.optimize();
1588         return ret;
1589 }
1590
1591 void RTLIL::SigSpec::sort()
1592 {
1593         unpack();
1594         std::sort(bits_.begin(), bits_.end());
1595 }
1596
1597 void RTLIL::SigSpec::sort_and_unify()
1598 {
1599         *this = this->to_sigbit_set();
1600 }
1601
1602 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
1603 {
1604         replace(pattern, with, this);
1605 }
1606
1607 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
1608 {
1609         unpack();
1610         pattern.unpack();
1611         with.unpack();
1612
1613         assert(other != NULL);
1614         assert(width_ == other->width_);
1615         other->unpack();
1616
1617         assert(pattern.width_ == with.width_);
1618
1619         std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
1620         for (int i = 0; i < SIZE(pattern.bits_); i++)
1621                 if (pattern.bits_[i].wire != NULL)
1622                         pattern_map[pattern.bits_[i]] = with.bits_[i];
1623
1624         for (int i = 0; i < SIZE(bits_); i++)
1625                 if (pattern_map.count(bits_[i]))
1626                         other->bits_[i] = pattern_map.at(bits_[i]);
1627
1628         other->check();
1629 }
1630
1631 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
1632 {
1633         remove2(pattern, NULL);
1634 }
1635
1636 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
1637 {
1638         RTLIL::SigSpec tmp = *this;
1639         tmp.remove2(pattern, other);
1640 }
1641
1642 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
1643 {
1644         unpack();
1645
1646         if (other != NULL) {
1647                 assert(width_ == other->width_);
1648                 other->unpack();
1649         }
1650
1651         std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
1652         std::vector<RTLIL::SigBit> new_bits, new_other_bits;
1653
1654         for (int i = 0; i < SIZE(bits_); i++) {
1655                 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
1656                         continue;
1657                 if (other != NULL)
1658                         new_other_bits.push_back(other->bits_[i]);
1659                 new_bits.push_back(bits_[i]);
1660         }
1661
1662         bits_.swap(new_bits);
1663         width_ = SIZE(bits_);
1664
1665         if (other != NULL) {
1666                 other->bits_.swap(new_other_bits);
1667                 other->width_ = SIZE(other->bits_);
1668         }
1669
1670         check();
1671 }
1672
1673 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const
1674 {
1675         pack();
1676         pattern.pack();
1677
1678         if (other != NULL)
1679                 other->pack();
1680
1681         assert(other == NULL || width_ == other->width_);
1682
1683         std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
1684         std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
1685         RTLIL::SigSpec ret;
1686
1687         if (other) {
1688                 std::vector<RTLIL::SigBit> bits_other = other ? other->to_sigbit_vector() : bits_match;
1689                 for (int i = 0; i < width_; i++)
1690                         if (bits_match[i].wire && pat.count(bits_match[i]))
1691                                 ret.append_bit(bits_other[i]);
1692         } else {
1693                 for (int i = 0; i < width_; i++)
1694                         if (bits_match[i].wire && pat.count(bits_match[i]))
1695                                 ret.append_bit(bits_match[i]);
1696         }
1697
1698         ret.check();
1699         return ret;
1700 }
1701
1702 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
1703 {
1704         unpack();
1705         with.unpack();
1706
1707         assert(offset >= 0);
1708         assert(with.width_ >= 0);
1709         assert(offset+with.width_ <= width_);
1710
1711         for (int i = 0; i < with.width_; i++)
1712                 bits_.at(offset + i) = with.bits_.at(i);
1713
1714         check();
1715 }
1716
1717 void RTLIL::SigSpec::remove_const()
1718 {
1719         unpack();
1720
1721         std::vector<RTLIL::SigBit> new_bits;
1722         new_bits.reserve(width_);
1723
1724         for (auto &bit : bits_)
1725                 if (bit.wire != NULL)
1726                         new_bits.push_back(bit);
1727
1728         bits_.swap(new_bits);
1729         width_ = bits_.size();
1730
1731         check();
1732 }
1733
1734 void RTLIL::SigSpec::remove(int offset, int length)
1735 {
1736         unpack();
1737
1738         assert(offset >= 0);
1739         assert(length >= 0);
1740         assert(offset + length <= width_);
1741
1742         bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
1743         width_ = bits_.size();
1744
1745         check();
1746 }
1747
1748 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
1749 {
1750         unpack();
1751         return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
1752 }
1753
1754 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
1755 {
1756         pack();
1757         signal.pack();
1758
1759         for (size_t i = 0; i < signal.chunks_.size(); i++) {
1760                 chunks_.push_back(signal.chunks_[i]);
1761                 width_ += signal.chunks_[i].width;
1762         }
1763
1764         // check();
1765 }
1766
1767 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
1768 {
1769         if (packed())
1770         {
1771                 if (chunks_.size() == 0)
1772                         chunks_.push_back(bit);
1773                 else
1774                         if (bit.wire == NULL)
1775                                 if (chunks_.back().wire == NULL) {
1776                                         chunks_.back().data.bits.push_back(bit.data);
1777                                         chunks_.back().width++;
1778                                 } else
1779                                         chunks_.push_back(bit);
1780                         else
1781                                 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
1782                                         chunks_.back().width++;
1783                                 else
1784                                         chunks_.push_back(bit);
1785         }
1786         else
1787                 bits_.push_back(bit);
1788
1789         width_++;
1790
1791         // check();
1792 }
1793
1794 bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool do_override)
1795 {
1796         pack();
1797         signal.pack();
1798
1799         bool no_collisions = true;
1800
1801         assert(width_ == signal.width_);
1802         expand();
1803         signal.expand();
1804
1805         for (size_t i = 0; i < chunks_.size(); i++) {
1806                 bool self_free = chunks_[i].wire == NULL && chunks_[i].data.bits[0] == freeState;
1807                 bool other_free = signal.chunks_[i].wire == NULL && signal.chunks_[i].data.bits[0] == freeState;
1808                 if (!self_free && !other_free) {
1809                         if (do_override)
1810                                 chunks_[i] = signal.chunks_[i];
1811                         else
1812                                 chunks_[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1);
1813                         no_collisions = false;
1814                 }
1815                 if (self_free && !other_free)
1816                         chunks_[i] = signal.chunks_[i];
1817         }
1818
1819         optimize();
1820         return no_collisions;
1821 }
1822
1823 void RTLIL::SigSpec::extend(int width, bool is_signed)
1824 {
1825         pack();
1826
1827         if (width_ > width)
1828                 remove(width, width_ - width);
1829
1830         if (width_ < width) {
1831                 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
1832                 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
1833                                 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
1834                         padding = RTLIL::SigSpec(RTLIL::State::S0);
1835                 while (width_ < width)
1836                         append(padding);
1837         }
1838
1839         optimize();
1840 }
1841
1842 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
1843 {
1844         pack();
1845
1846         if (width_ > width)
1847                 remove(width, width_ - width);
1848
1849         if (width_ < width) {
1850                 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
1851                 if (!is_signed)
1852                         padding = RTLIL::SigSpec(RTLIL::State::S0);
1853                 while (width_ < width)
1854                         append(padding);
1855         }
1856
1857         optimize();
1858 }
1859
1860 void RTLIL::SigSpec::check() const
1861 {
1862         if (packed())
1863         {
1864                 int w = 0;
1865                 for (size_t i = 0; i < chunks_.size(); i++) {
1866                         const RTLIL::SigChunk chunk = chunks_[i];
1867                         if (chunk.wire == NULL) {
1868                                 assert(chunk.offset == 0);
1869                                 assert(chunk.data.bits.size() == (size_t)chunk.width);
1870                         } else {
1871                                 assert(chunk.offset >= 0);
1872                                 assert(chunk.width >= 0);
1873                                 assert(chunk.offset + chunk.width <= chunk.wire->width);
1874                                 assert(chunk.data.bits.size() == 0);
1875                         }
1876                         w += chunk.width;
1877                 }
1878                 assert(w == width_);
1879                 assert(bits_.empty());
1880         }
1881         else
1882         {
1883                 assert(width_ == SIZE(bits_));
1884                 assert(chunks_.empty());
1885         }
1886 }
1887
1888 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
1889 {
1890         pack();
1891         other.pack();
1892
1893         if (width_ != other.width_)
1894                 return width_ < other.width_;
1895
1896         RTLIL::SigSpec a = *this, b = other;
1897         a.optimize();
1898         b.optimize();
1899
1900         if (a.chunks_.size() != b.chunks_.size())
1901                 return a.chunks_.size() < b.chunks_.size();
1902
1903         for (size_t i = 0; i < a.chunks_.size(); i++)
1904                 if (a.chunks_[i] != b.chunks_[i])
1905                         return a.chunks_[i] < b.chunks_[i];
1906
1907         return false;
1908 }
1909
1910 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
1911 {
1912         pack();
1913         other.pack();
1914
1915         if (width_ != other.width_)
1916                 return false;
1917
1918         RTLIL::SigSpec a = *this, b = other;
1919         a.optimize();
1920         b.optimize();
1921
1922         if (a.chunks_.size() != b.chunks_.size())
1923                 return false;
1924
1925         for (size_t i = 0; i < a.chunks_.size(); i++)
1926                 if (a.chunks_[i] != b.chunks_[i])
1927                         return false;
1928
1929         return true;
1930 }
1931
1932 bool RTLIL::SigSpec::operator !=(const RTLIL::SigSpec &other) const
1933 {
1934         if (*this == other)
1935                 return false;
1936         return true;
1937 }
1938
1939 bool RTLIL::SigSpec::is_fully_const() const
1940 {
1941         pack();
1942         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
1943                 if (it->width > 0 && it->wire != NULL)
1944                         return false;
1945         return true;
1946 }
1947
1948 bool RTLIL::SigSpec::is_fully_def() const
1949 {
1950         pack();
1951         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
1952                 if (it->width > 0 && it->wire != NULL)
1953                         return false;
1954                 for (size_t i = 0; i < it->data.bits.size(); i++)
1955                         if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
1956                                 return false;
1957         }
1958         return true;
1959 }
1960
1961 bool RTLIL::SigSpec::is_fully_undef() const
1962 {
1963         pack();
1964         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
1965                 if (it->width > 0 && it->wire != NULL)
1966                         return false;
1967                 for (size_t i = 0; i < it->data.bits.size(); i++)
1968                         if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
1969                                 return false;
1970         }
1971         return true;
1972 }
1973
1974 bool RTLIL::SigSpec::has_marked_bits() const
1975 {
1976         pack();
1977         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
1978                 if (it->width > 0 && it->wire == NULL) {
1979                         for (size_t i = 0; i < it->data.bits.size(); i++)
1980                                 if (it->data.bits[i] == RTLIL::State::Sm)
1981                                         return true;
1982                 }
1983         return false;
1984 }
1985
1986 bool RTLIL::SigSpec::as_bool() const
1987 {
1988         pack();
1989         assert(is_fully_const());
1990         SigSpec sig = *this;
1991         sig.optimize();
1992         if (sig.width_)
1993                 return sig.chunks_[0].data.as_bool();
1994         return false;
1995 }
1996
1997 int RTLIL::SigSpec::as_int() const
1998 {
1999         pack();
2000         assert(is_fully_const());
2001         SigSpec sig = *this;
2002         sig.optimize();
2003         if (sig.width_)
2004                 return sig.chunks_[0].data.as_int();
2005         return 0;
2006 }
2007
2008 std::string RTLIL::SigSpec::as_string() const
2009 {
2010         pack();
2011         std::string str;
2012         for (size_t i = chunks_.size(); i > 0; i--) {
2013                 const RTLIL::SigChunk &chunk = chunks_[i-1];
2014                 if (chunk.wire != NULL)
2015                         for (int j = 0; j < chunk.width; j++)
2016                                 str += "?";
2017                 else
2018                         str += chunk.data.as_string();
2019         }
2020         return str;
2021 }
2022
2023 RTLIL::Const RTLIL::SigSpec::as_const() const
2024 {
2025         pack();
2026         assert(is_fully_const());
2027         SigSpec sig = *this;
2028         sig.optimize();
2029         if (sig.width_)
2030                 return sig.chunks_[0].data;
2031         return RTLIL::Const();
2032 }
2033
2034 bool RTLIL::SigSpec::match(std::string pattern) const
2035 {
2036         pack();
2037         std::string str = as_string();
2038         assert(pattern.size() == str.size());
2039
2040         for (size_t i = 0; i < pattern.size(); i++) {
2041                 if (pattern[i] == ' ')
2042                         continue;
2043                 if (pattern[i] == '*') {
2044                         if (str[i] != 'z' && str[i] != 'x')
2045                                 return false;
2046                         continue;
2047                 }
2048                 if (pattern[i] != str[i])
2049                         return false;
2050         }
2051
2052         return true;
2053 }
2054
2055 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2056 {
2057         pack();
2058         std::set<RTLIL::SigBit> sigbits;
2059         for (auto &c : chunks_)
2060                 for (int i = 0; i < c.width; i++)
2061                         sigbits.insert(RTLIL::SigBit(c, i));
2062         return sigbits;
2063 }
2064
2065 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2066 {
2067         unpack();
2068         return bits_;
2069 }
2070
2071 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2072 {
2073         pack();
2074         log_assert(width_ == 1);
2075         for (auto &c : chunks_)
2076                 if (c.width)
2077                         return RTLIL::SigBit(c);
2078         log_abort();
2079 }
2080
2081 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2082 {
2083         size_t start = 0, end = 0;
2084         while ((end = text.find(sep, start)) != std::string::npos) {
2085                 tokens.push_back(text.substr(start, end - start));
2086                 start = end + 1;
2087         }
2088         tokens.push_back(text.substr(start));
2089 }
2090
2091 static int sigspec_parse_get_dummy_line_num()
2092 {
2093         return 0;
2094 }
2095
2096 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2097 {
2098         std::vector<std::string> tokens;
2099         sigspec_parse_split(tokens, str, ',');
2100
2101         sig = RTLIL::SigSpec();
2102         for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2103         {
2104                 std::string netname = tokens[tokidx];
2105                 std::string indices;
2106
2107                 if (netname.size() == 0)
2108                         continue;
2109
2110                 if ('0' <= netname[0] && netname[0] <= '9') {
2111                         AST::get_line_num = sigspec_parse_get_dummy_line_num;
2112                         AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2113                         if (ast == NULL)
2114                                 return false;
2115                         sig.append(RTLIL::Const(ast->bits));
2116                         delete ast;
2117                         continue;
2118                 }
2119
2120                 if (module == NULL)
2121                         return false;
2122
2123                 if (netname[0] != '$' && netname[0] != '\\')
2124                         netname = "\\" + netname;
2125
2126                 if (module->wires.count(netname) == 0) {
2127                         size_t indices_pos = netname.size()-1;
2128                         if (indices_pos > 2 && netname[indices_pos] == ']')
2129                         {
2130                                 indices_pos--;
2131                                 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2132                                 if (indices_pos > 0 && netname[indices_pos] == ':') {
2133                                         indices_pos--;
2134                                         while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2135                                 }
2136                                 if (indices_pos > 0 && netname[indices_pos] == '[') {
2137                                         indices = netname.substr(indices_pos);
2138                                         netname = netname.substr(0, indices_pos);
2139                                 }
2140                         }
2141                 }
2142
2143                 if (module->wires.count(netname) == 0)
2144                         return false;
2145
2146                 RTLIL::Wire *wire = module->wires.at(netname);
2147                 if (!indices.empty()) {
2148                         std::vector<std::string> index_tokens;
2149                         sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2150                         if (index_tokens.size() == 1)
2151                                 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2152                         else {
2153                                 int a = atoi(index_tokens.at(0).c_str());
2154                                 int b = atoi(index_tokens.at(1).c_str());
2155                                 if (a > b) {
2156                                         int tmp = a;
2157                                         a = b, b = tmp;
2158                                 }
2159                                 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2160                         }
2161                 } else
2162                         sig.append(wire);
2163         }
2164
2165         return true;
2166 }
2167
2168 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2169 {
2170         if (str.empty() || str[0] != '@')
2171                 return parse(sig, module, str);
2172
2173         str = RTLIL::escape_id(str.substr(1));
2174         if (design->selection_vars.count(str) == 0)
2175                 return false;
2176
2177         sig = RTLIL::SigSpec();
2178         RTLIL::Selection &sel = design->selection_vars.at(str);
2179         for (auto &it : module->wires)
2180                 if (sel.selected_member(module->name, it.first))
2181                         sig.append(it.second);
2182
2183         return true;
2184 }
2185
2186 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2187 {
2188         if (str == "0") {
2189                 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2190                 return true;
2191         }
2192
2193         if (str == "~0") {
2194                 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2195                 return true;
2196         }
2197
2198         if (lhs.chunks_.size() == 1) {
2199                 char *p = (char*)str.c_str(), *endptr;
2200                 long long int val = strtoll(p, &endptr, 10);
2201                 if (endptr && endptr != p && *endptr == 0) {
2202                         sig = RTLIL::SigSpec(val, lhs.width_);
2203                         return true;
2204                 }
2205         }
2206
2207         return parse(sig, module, str);
2208 }
2209
2210 RTLIL::CaseRule::~CaseRule()
2211 {
2212         for (auto it = switches.begin(); it != switches.end(); it++)
2213                 delete *it;
2214 }
2215
2216 void RTLIL::CaseRule::optimize()
2217 {
2218         for (auto it : switches)
2219                 it->optimize();
2220         for (auto &it : compare)
2221                 it.optimize();
2222         for (auto &it : actions) {
2223                 it.first.optimize();
2224                 it.second.optimize();
2225         }
2226 }
2227
2228 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2229 {
2230         RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2231         new_caserule->compare = compare;
2232         new_caserule->actions = actions;
2233         for (auto &it : switches)
2234                 new_caserule->switches.push_back(it->clone());
2235         return new_caserule;
2236 }
2237
2238 RTLIL::SwitchRule::~SwitchRule()
2239 {
2240         for (auto it = cases.begin(); it != cases.end(); it++)
2241                 delete *it;
2242 }
2243
2244 void RTLIL::SwitchRule::optimize()
2245 {
2246         signal.optimize();
2247         for (auto it : cases)
2248                 it->optimize();
2249 }
2250
2251 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2252 {
2253         RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2254         new_switchrule->signal = signal;
2255         new_switchrule->attributes = attributes;
2256         for (auto &it : cases)
2257                 new_switchrule->cases.push_back(it->clone());
2258         return new_switchrule;
2259
2260 }
2261
2262 void RTLIL::SyncRule::optimize()
2263 {
2264         signal.optimize();
2265         for (auto &it : actions) {
2266                 it.first.optimize();
2267                 it.second.optimize();
2268         }
2269 }
2270
2271 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2272 {
2273         RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2274         new_syncrule->type = type;
2275         new_syncrule->signal = signal;
2276         new_syncrule->actions = actions;
2277         return new_syncrule;
2278 }
2279
2280 RTLIL::Process::~Process()
2281 {
2282         for (auto it = syncs.begin(); it != syncs.end(); it++)
2283                 delete *it;
2284 }
2285
2286 void RTLIL::Process::optimize()
2287 {
2288         root_case.optimize();
2289         for (auto it : syncs)
2290                 it->optimize();
2291 }
2292
2293 RTLIL::Process *RTLIL::Process::clone() const
2294 {
2295         RTLIL::Process *new_proc = new RTLIL::Process;
2296
2297         new_proc->name = name;
2298         new_proc->attributes = attributes;
2299
2300         RTLIL::CaseRule *rc_ptr = root_case.clone();
2301         new_proc->root_case = *rc_ptr;
2302         rc_ptr->switches.clear();
2303         delete rc_ptr;
2304
2305         for (auto &it : syncs)
2306                 new_proc->syncs.push_back(it->clone());
2307
2308         return new_proc;
2309 }
2310