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Added is_signed argument to SigSpec.as_int() and Const.as_int()
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int(bool is_signed) const
96 {
97 int32_t ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 if (is_signed && bits.back() == RTLIL::S1)
102 for (size_t i = bits.size(); i < 32; i++)
103 ret |= 1 << i;
104 return ret;
105 }
106
107 std::string RTLIL::Const::as_string() const
108 {
109 std::string ret;
110 for (size_t i = bits.size(); i > 0; i--)
111 switch (bits[i-1]) {
112 case S0: ret += "0"; break;
113 case S1: ret += "1"; break;
114 case Sx: ret += "x"; break;
115 case Sz: ret += "z"; break;
116 case Sa: ret += "-"; break;
117 case Sm: ret += "m"; break;
118 }
119 return ret;
120 }
121
122 std::string RTLIL::Const::decode_string() const
123 {
124 std::string string;
125 std::vector <char> string_chars;
126 for (int i = 0; i < int (bits.size()); i += 8) {
127 char ch = 0;
128 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
129 if (bits[i + j] == RTLIL::State::S1)
130 ch |= 1 << j;
131 if (ch != 0)
132 string_chars.push_back(ch);
133 }
134 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
135 string += string_chars[i];
136 return string;
137 }
138
139 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
140 {
141 if (full_selection)
142 return true;
143 if (selected_modules.count(mod_name) > 0)
144 return true;
145 if (selected_members.count(mod_name) > 0)
146 return true;
147 return false;
148 }
149
150 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
151 {
152 if (full_selection)
153 return true;
154 if (selected_modules.count(mod_name) > 0)
155 return true;
156 return false;
157 }
158
159 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
160 {
161 if (full_selection)
162 return true;
163 if (selected_modules.count(mod_name) > 0)
164 return true;
165 if (selected_members.count(mod_name) > 0)
166 if (selected_members.at(mod_name).count(memb_name) > 0)
167 return true;
168 return false;
169 }
170
171 void RTLIL::Selection::optimize(RTLIL::Design *design)
172 {
173 if (full_selection) {
174 selected_modules.clear();
175 selected_members.clear();
176 return;
177 }
178
179 std::vector<RTLIL::IdString> del_list, add_list;
180
181 del_list.clear();
182 for (auto mod_name : selected_modules) {
183 if (design->modules_.count(mod_name) == 0)
184 del_list.push_back(mod_name);
185 selected_members.erase(mod_name);
186 }
187 for (auto mod_name : del_list)
188 selected_modules.erase(mod_name);
189
190 del_list.clear();
191 for (auto &it : selected_members)
192 if (design->modules_.count(it.first) == 0)
193 del_list.push_back(it.first);
194 for (auto mod_name : del_list)
195 selected_members.erase(mod_name);
196
197 for (auto &it : selected_members) {
198 del_list.clear();
199 for (auto memb_name : it.second)
200 if (design->modules_[it.first]->count_id(memb_name) == 0)
201 del_list.push_back(memb_name);
202 for (auto memb_name : del_list)
203 it.second.erase(memb_name);
204 }
205
206 del_list.clear();
207 add_list.clear();
208 for (auto &it : selected_members)
209 if (it.second.size() == 0)
210 del_list.push_back(it.first);
211 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
212 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
213 add_list.push_back(it.first);
214 for (auto mod_name : del_list)
215 selected_members.erase(mod_name);
216 for (auto mod_name : add_list) {
217 selected_members.erase(mod_name);
218 selected_modules.insert(mod_name);
219 }
220
221 if (selected_modules.size() == design->modules_.size()) {
222 full_selection = true;
223 selected_modules.clear();
224 selected_members.clear();
225 }
226 }
227
228 RTLIL::Design::Design()
229 {
230 refcount_modules_ = 0;
231 }
232
233 RTLIL::Design::~Design()
234 {
235 for (auto it = modules_.begin(); it != modules_.end(); it++)
236 delete it->second;
237 }
238
239 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
240 {
241 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
242 }
243
244 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
245 {
246 return modules_.count(name) ? modules_.at(name) : NULL;
247 }
248
249 void RTLIL::Design::add(RTLIL::Module *module)
250 {
251 log_assert(modules_.count(module->name) == 0);
252 log_assert(refcount_modules_ == 0);
253 modules_[module->name] = module;
254 module->design = this;
255
256 for (auto mon : monitors)
257 mon->notify_module_add(module);
258 }
259
260 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
261 {
262 log_assert(modules_.count(name) == 0);
263 log_assert(refcount_modules_ == 0);
264
265 RTLIL::Module *module = new RTLIL::Module;
266 modules_[name] = module;
267 module->design = this;
268 module->name = name;
269
270 for (auto mon : monitors)
271 mon->notify_module_add(module);
272
273 return module;
274 }
275
276 void RTLIL::Design::remove(RTLIL::Module *module)
277 {
278 for (auto mon : monitors)
279 mon->notify_module_del(module);
280
281 log_assert(modules_.at(module->name) == module);
282 modules_.erase(module->name);
283 delete module;
284 }
285
286 void RTLIL::Design::check()
287 {
288 #ifndef NDEBUG
289 for (auto &it : modules_) {
290 log_assert(this == it.second->design);
291 log_assert(it.first == it.second->name);
292 log_assert(!it.first.empty());
293 it.second->check();
294 }
295 #endif
296 }
297
298 void RTLIL::Design::optimize()
299 {
300 for (auto &it : modules_)
301 it.second->optimize();
302 for (auto &it : selection_stack)
303 it.optimize(this);
304 for (auto &it : selection_vars)
305 it.second.optimize(this);
306 }
307
308 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
309 {
310 if (!selected_active_module.empty() && mod_name != selected_active_module)
311 return false;
312 if (selection_stack.size() == 0)
313 return true;
314 return selection_stack.back().selected_module(mod_name);
315 }
316
317 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
318 {
319 if (!selected_active_module.empty() && mod_name != selected_active_module)
320 return false;
321 if (selection_stack.size() == 0)
322 return true;
323 return selection_stack.back().selected_whole_module(mod_name);
324 }
325
326 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
327 {
328 if (!selected_active_module.empty() && mod_name != selected_active_module)
329 return false;
330 if (selection_stack.size() == 0)
331 return true;
332 return selection_stack.back().selected_member(mod_name, memb_name);
333 }
334
335 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
336 {
337 return selected_module(mod->name);
338 }
339
340 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
341 {
342 return selected_whole_module(mod->name);
343 }
344
345 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
346 {
347 std::vector<RTLIL::Module*> result;
348 result.reserve(modules_.size());
349 for (auto &it : modules_)
350 if (selected_module(it.first))
351 result.push_back(it.second);
352 return result;
353 }
354
355 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
356 {
357 std::vector<RTLIL::Module*> result;
358 result.reserve(modules_.size());
359 for (auto &it : modules_)
360 if (selected_whole_module(it.first))
361 result.push_back(it.second);
362 return result;
363 }
364
365 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
366 {
367 std::vector<RTLIL::Module*> result;
368 result.reserve(modules_.size());
369 for (auto &it : modules_)
370 if (selected_whole_module(it.first))
371 result.push_back(it.second);
372 else if (selected_module(it.first))
373 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
374 return result;
375 }
376
377 RTLIL::Module::Module()
378 {
379 design = nullptr;
380 refcount_wires_ = 0;
381 refcount_cells_ = 0;
382 }
383
384 RTLIL::Module::~Module()
385 {
386 for (auto it = wires_.begin(); it != wires_.end(); it++)
387 delete it->second;
388 for (auto it = memories.begin(); it != memories.end(); it++)
389 delete it->second;
390 for (auto it = cells_.begin(); it != cells_.end(); it++)
391 delete it->second;
392 for (auto it = processes.begin(); it != processes.end(); it++)
393 delete it->second;
394 }
395
396 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
397 {
398 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
399 }
400
401 size_t RTLIL::Module::count_id(RTLIL::IdString id)
402 {
403 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
404 }
405
406 #ifndef NDEBUG
407 namespace {
408 struct InternalCellChecker
409 {
410 RTLIL::Module *module;
411 RTLIL::Cell *cell;
412 std::set<RTLIL::IdString> expected_params, expected_ports;
413
414 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
415
416 void error(int linenr)
417 {
418 std::stringstream buf;
419 ILANG_BACKEND::dump_cell(buf, " ", cell);
420
421 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
422 module ? module->name.c_str() : "", module ? "." : "",
423 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
424 }
425
426 int param(const char *name)
427 {
428 if (cell->parameters.count(name) == 0)
429 error(__LINE__);
430 expected_params.insert(name);
431 return cell->parameters.at(name).as_int();
432 }
433
434 int param_bool(const char *name)
435 {
436 int v = param(name);
437 if (cell->parameters.at(name).bits.size() > 32)
438 error(__LINE__);
439 if (v != 0 && v != 1)
440 error(__LINE__);
441 return v;
442 }
443
444 void param_bits(const char *name, int width)
445 {
446 param(name);
447 if (int(cell->parameters.at(name).bits.size()) != width)
448 error(__LINE__);
449 }
450
451 void port(const char *name, int width)
452 {
453 if (!cell->hasPort(name))
454 error(__LINE__);
455 if (cell->getPort(name).size() != width)
456 error(__LINE__);
457 expected_ports.insert(name);
458 }
459
460 void check_expected(bool check_matched_sign = true)
461 {
462 for (auto &para : cell->parameters)
463 if (expected_params.count(para.first) == 0)
464 error(__LINE__);
465 for (auto &conn : cell->connections())
466 if (expected_ports.count(conn.first) == 0)
467 error(__LINE__);
468
469 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
470 bool a_is_signed = param("\\A_SIGNED") != 0;
471 bool b_is_signed = param("\\B_SIGNED") != 0;
472 if (a_is_signed != b_is_signed)
473 error(__LINE__);
474 }
475 }
476
477 void check_gate(const char *ports)
478 {
479 if (cell->parameters.size() != 0)
480 error(__LINE__);
481
482 for (const char *p = ports; *p; p++) {
483 char portname[3] = { '\\', *p, 0 };
484 if (!cell->hasPort(portname))
485 error(__LINE__);
486 if (cell->getPort(portname).size() != 1)
487 error(__LINE__);
488 }
489
490 for (auto &conn : cell->connections()) {
491 if (conn.first.size() != 2 || conn.first[0] != '\\')
492 error(__LINE__);
493 if (strchr(ports, conn.first[1]) == NULL)
494 error(__LINE__);
495 }
496 }
497
498 void check()
499 {
500 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
501 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
502 return;
503
504 if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
505 param_bool("\\A_SIGNED");
506 port("\\A", param("\\A_WIDTH"));
507 port("\\Y", param("\\Y_WIDTH"));
508 check_expected();
509 return;
510 }
511
512 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
513 param_bool("\\A_SIGNED");
514 param_bool("\\B_SIGNED");
515 port("\\A", param("\\A_WIDTH"));
516 port("\\B", param("\\B_WIDTH"));
517 port("\\Y", param("\\Y_WIDTH"));
518 check_expected();
519 return;
520 }
521
522 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
523 param_bool("\\A_SIGNED");
524 port("\\A", param("\\A_WIDTH"));
525 port("\\Y", param("\\Y_WIDTH"));
526 check_expected();
527 return;
528 }
529
530 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
531 param_bool("\\A_SIGNED");
532 param_bool("\\B_SIGNED");
533 port("\\A", param("\\A_WIDTH"));
534 port("\\B", param("\\B_WIDTH"));
535 port("\\Y", param("\\Y_WIDTH"));
536 check_expected(false);
537 return;
538 }
539
540 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
541 param_bool("\\A_SIGNED");
542 param_bool("\\B_SIGNED");
543 port("\\A", param("\\A_WIDTH"));
544 port("\\B", param("\\B_WIDTH"));
545 port("\\Y", param("\\Y_WIDTH"));
546 check_expected();
547 return;
548 }
549
550 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
551 param_bool("\\A_SIGNED");
552 param_bool("\\B_SIGNED");
553 port("\\A", param("\\A_WIDTH"));
554 port("\\B", param("\\B_WIDTH"));
555 port("\\Y", param("\\Y_WIDTH"));
556 check_expected(cell->type != "$pow");
557 return;
558 }
559
560 if (cell->type == "$logic_not") {
561 param_bool("\\A_SIGNED");
562 port("\\A", param("\\A_WIDTH"));
563 port("\\Y", param("\\Y_WIDTH"));
564 check_expected();
565 return;
566 }
567
568 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
569 param_bool("\\A_SIGNED");
570 param_bool("\\B_SIGNED");
571 port("\\A", param("\\A_WIDTH"));
572 port("\\B", param("\\B_WIDTH"));
573 port("\\Y", param("\\Y_WIDTH"));
574 check_expected(false);
575 return;
576 }
577
578 if (cell->type == "$slice") {
579 param("\\OFFSET");
580 port("\\A", param("\\A_WIDTH"));
581 port("\\Y", param("\\Y_WIDTH"));
582 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
583 error(__LINE__);
584 check_expected();
585 return;
586 }
587
588 if (cell->type == "$concat") {
589 port("\\A", param("\\A_WIDTH"));
590 port("\\B", param("\\B_WIDTH"));
591 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
592 check_expected();
593 return;
594 }
595
596 if (cell->type == "$mux") {
597 port("\\A", param("\\WIDTH"));
598 port("\\B", param("\\WIDTH"));
599 port("\\S", 1);
600 port("\\Y", param("\\WIDTH"));
601 check_expected();
602 return;
603 }
604
605 if (cell->type == "$pmux") {
606 port("\\A", param("\\WIDTH"));
607 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
608 port("\\S", param("\\S_WIDTH"));
609 port("\\Y", param("\\WIDTH"));
610 check_expected();
611 return;
612 }
613
614 if (cell->type == "$lut") {
615 param("\\LUT");
616 port("\\A", param("\\WIDTH"));
617 port("\\Y", 1);
618 check_expected();
619 return;
620 }
621
622 if (cell->type == "$sr") {
623 param_bool("\\SET_POLARITY");
624 param_bool("\\CLR_POLARITY");
625 port("\\SET", param("\\WIDTH"));
626 port("\\CLR", param("\\WIDTH"));
627 port("\\Q", param("\\WIDTH"));
628 check_expected();
629 return;
630 }
631
632 if (cell->type == "$dff") {
633 param_bool("\\CLK_POLARITY");
634 port("\\CLK", 1);
635 port("\\D", param("\\WIDTH"));
636 port("\\Q", param("\\WIDTH"));
637 check_expected();
638 return;
639 }
640
641 if (cell->type == "$dffsr") {
642 param_bool("\\CLK_POLARITY");
643 param_bool("\\SET_POLARITY");
644 param_bool("\\CLR_POLARITY");
645 port("\\CLK", 1);
646 port("\\SET", param("\\WIDTH"));
647 port("\\CLR", param("\\WIDTH"));
648 port("\\D", param("\\WIDTH"));
649 port("\\Q", param("\\WIDTH"));
650 check_expected();
651 return;
652 }
653
654 if (cell->type == "$adff") {
655 param_bool("\\CLK_POLARITY");
656 param_bool("\\ARST_POLARITY");
657 param_bits("\\ARST_VALUE", param("\\WIDTH"));
658 port("\\CLK", 1);
659 port("\\ARST", 1);
660 port("\\D", param("\\WIDTH"));
661 port("\\Q", param("\\WIDTH"));
662 check_expected();
663 return;
664 }
665
666 if (cell->type == "$dlatch") {
667 param_bool("\\EN_POLARITY");
668 port("\\EN", 1);
669 port("\\D", param("\\WIDTH"));
670 port("\\Q", param("\\WIDTH"));
671 check_expected();
672 return;
673 }
674
675 if (cell->type == "$dlatchsr") {
676 param_bool("\\EN_POLARITY");
677 param_bool("\\SET_POLARITY");
678 param_bool("\\CLR_POLARITY");
679 port("\\EN", 1);
680 port("\\SET", param("\\WIDTH"));
681 port("\\CLR", param("\\WIDTH"));
682 port("\\D", param("\\WIDTH"));
683 port("\\Q", param("\\WIDTH"));
684 check_expected();
685 return;
686 }
687
688 if (cell->type == "$fsm") {
689 param("\\NAME");
690 param_bool("\\CLK_POLARITY");
691 param_bool("\\ARST_POLARITY");
692 param("\\STATE_BITS");
693 param("\\STATE_NUM");
694 param("\\STATE_NUM_LOG2");
695 param("\\STATE_RST");
696 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
697 param("\\TRANS_NUM");
698 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
699 port("\\CLK", 1);
700 port("\\ARST", 1);
701 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
702 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
703 check_expected();
704 return;
705 }
706
707 if (cell->type == "$memrd") {
708 param("\\MEMID");
709 param_bool("\\CLK_ENABLE");
710 param_bool("\\CLK_POLARITY");
711 param_bool("\\TRANSPARENT");
712 port("\\CLK", 1);
713 port("\\ADDR", param("\\ABITS"));
714 port("\\DATA", param("\\WIDTH"));
715 check_expected();
716 return;
717 }
718
719 if (cell->type == "$memwr") {
720 param("\\MEMID");
721 param_bool("\\CLK_ENABLE");
722 param_bool("\\CLK_POLARITY");
723 param("\\PRIORITY");
724 port("\\CLK", 1);
725 port("\\EN", param("\\WIDTH"));
726 port("\\ADDR", param("\\ABITS"));
727 port("\\DATA", param("\\WIDTH"));
728 check_expected();
729 return;
730 }
731
732 if (cell->type == "$mem") {
733 param("\\MEMID");
734 param("\\SIZE");
735 param("\\OFFSET");
736 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
737 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
738 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
739 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
740 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
741 port("\\RD_CLK", param("\\RD_PORTS"));
742 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
743 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
744 port("\\WR_CLK", param("\\WR_PORTS"));
745 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
746 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
747 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
748 check_expected();
749 return;
750 }
751
752 if (cell->type == "$assert") {
753 port("\\A", 1);
754 port("\\EN", 1);
755 check_expected();
756 return;
757 }
758
759 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
760 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
761 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
762 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
763 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
764 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
765 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
766 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
767 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
768 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
769 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
770 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
771
772 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
773 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
774 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
775 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
776
777 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
778 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
779
780 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
781 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
782 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
783 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
784 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
785 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
786 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
787 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
788
789 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
790 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
791 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
792 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
793 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
794 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
795 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
796 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
797
798 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
799 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
800
801 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
802 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
803 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
804 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
805 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
806 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
807 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
808 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
809
810 error(__LINE__);
811 }
812 };
813 }
814 #endif
815
816 void RTLIL::Module::check()
817 {
818 #ifndef NDEBUG
819 std::vector<bool> ports_declared;
820 for (auto &it : wires_) {
821 log_assert(this == it.second->module);
822 log_assert(it.first == it.second->name);
823 log_assert(!it.first.empty());
824 log_assert(it.second->width >= 0);
825 log_assert(it.second->port_id >= 0);
826 for (auto &it2 : it.second->attributes)
827 log_assert(!it2.first.empty());
828 if (it.second->port_id) {
829 log_assert(SIZE(ports) >= it.second->port_id);
830 log_assert(ports.at(it.second->port_id-1) == it.first);
831 log_assert(it.second->port_input || it.second->port_output);
832 if (SIZE(ports_declared) < it.second->port_id)
833 ports_declared.resize(it.second->port_id);
834 log_assert(ports_declared[it.second->port_id-1] == false);
835 ports_declared[it.second->port_id-1] = true;
836 } else
837 log_assert(!it.second->port_input && !it.second->port_output);
838 }
839 for (auto port_declared : ports_declared)
840 log_assert(port_declared == true);
841 log_assert(SIZE(ports) == SIZE(ports_declared));
842
843 for (auto &it : memories) {
844 log_assert(it.first == it.second->name);
845 log_assert(!it.first.empty());
846 log_assert(it.second->width >= 0);
847 log_assert(it.second->size >= 0);
848 for (auto &it2 : it.second->attributes)
849 log_assert(!it2.first.empty());
850 }
851
852 for (auto &it : cells_) {
853 log_assert(this == it.second->module);
854 log_assert(it.first == it.second->name);
855 log_assert(!it.first.empty());
856 log_assert(!it.second->type.empty());
857 for (auto &it2 : it.second->connections()) {
858 log_assert(!it2.first.empty());
859 it2.second.check();
860 }
861 for (auto &it2 : it.second->attributes)
862 log_assert(!it2.first.empty());
863 for (auto &it2 : it.second->parameters)
864 log_assert(!it2.first.empty());
865 InternalCellChecker checker(this, it.second);
866 checker.check();
867 }
868
869 for (auto &it : processes) {
870 log_assert(it.first == it.second->name);
871 log_assert(!it.first.empty());
872 // FIXME: More checks here..
873 }
874
875 for (auto &it : connections_) {
876 log_assert(it.first.size() == it.second.size());
877 it.first.check();
878 it.second.check();
879 }
880
881 for (auto &it : attributes)
882 log_assert(!it.first.empty());
883 #endif
884 }
885
886 void RTLIL::Module::optimize()
887 {
888 }
889
890 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
891 {
892 log_assert(new_mod->refcount_wires_ == 0);
893 log_assert(new_mod->refcount_cells_ == 0);
894
895 new_mod->connections_ = connections_;
896 new_mod->attributes = attributes;
897
898 for (auto &it : wires_)
899 new_mod->addWire(it.first, it.second);
900
901 for (auto &it : memories)
902 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
903
904 for (auto &it : cells_)
905 new_mod->addCell(it.first, it.second);
906
907 for (auto &it : processes)
908 new_mod->processes[it.first] = it.second->clone();
909
910 struct RewriteSigSpecWorker
911 {
912 RTLIL::Module *mod;
913 void operator()(RTLIL::SigSpec &sig)
914 {
915 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
916 for (auto &c : chunks)
917 if (c.wire != NULL)
918 c.wire = mod->wires_.at(c.wire->name);
919 sig = chunks;
920 }
921 };
922
923 RewriteSigSpecWorker rewriteSigSpecWorker;
924 rewriteSigSpecWorker.mod = new_mod;
925 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
926 new_mod->fixup_ports();
927 }
928
929 RTLIL::Module *RTLIL::Module::clone() const
930 {
931 RTLIL::Module *new_mod = new RTLIL::Module;
932 new_mod->name = name;
933 cloneInto(new_mod);
934 return new_mod;
935 }
936
937 bool RTLIL::Module::has_memories() const
938 {
939 return !memories.empty();
940 }
941
942 bool RTLIL::Module::has_processes() const
943 {
944 return !processes.empty();
945 }
946
947 bool RTLIL::Module::has_memories_warn() const
948 {
949 if (!memories.empty())
950 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
951 return !memories.empty();
952 }
953
954 bool RTLIL::Module::has_processes_warn() const
955 {
956 if (!processes.empty())
957 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
958 return !processes.empty();
959 }
960
961 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
962 {
963 std::vector<RTLIL::Wire*> result;
964 result.reserve(wires_.size());
965 for (auto &it : wires_)
966 if (design->selected(this, it.second))
967 result.push_back(it.second);
968 return result;
969 }
970
971 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
972 {
973 std::vector<RTLIL::Cell*> result;
974 result.reserve(wires_.size());
975 for (auto &it : cells_)
976 if (design->selected(this, it.second))
977 result.push_back(it.second);
978 return result;
979 }
980
981 void RTLIL::Module::add(RTLIL::Wire *wire)
982 {
983 log_assert(!wire->name.empty());
984 log_assert(count_id(wire->name) == 0);
985 log_assert(refcount_wires_ == 0);
986 wires_[wire->name] = wire;
987 wire->module = this;
988 }
989
990 void RTLIL::Module::add(RTLIL::Cell *cell)
991 {
992 log_assert(!cell->name.empty());
993 log_assert(count_id(cell->name) == 0);
994 log_assert(refcount_cells_ == 0);
995 cells_[cell->name] = cell;
996 cell->module = this;
997 }
998
999 namespace {
1000 struct DeleteWireWorker
1001 {
1002 RTLIL::Module *module;
1003 const std::set<RTLIL::Wire*> *wires_p;
1004
1005 void operator()(RTLIL::SigSpec &sig) {
1006 std::vector<RTLIL::SigChunk> chunks = sig;
1007 for (auto &c : chunks)
1008 if (c.wire != NULL && wires_p->count(c.wire)) {
1009 c.wire = module->addWire(NEW_ID, c.width);
1010 c.offset = 0;
1011 }
1012 sig = chunks;
1013 }
1014 };
1015 }
1016
1017 #if 0
1018 void RTLIL::Module::remove(RTLIL::Wire *wire)
1019 {
1020 std::setPort<RTLIL::Wire*> wires_;
1021 wires_.insert(wire);
1022 remove(wires_);
1023 }
1024 #endif
1025
1026 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1027 {
1028 log_assert(refcount_wires_ == 0);
1029
1030 DeleteWireWorker delete_wire_worker;
1031 delete_wire_worker.module = this;
1032 delete_wire_worker.wires_p = &wires;
1033 rewrite_sigspecs(delete_wire_worker);
1034
1035 for (auto &it : wires) {
1036 log_assert(wires_.count(it->name) != 0);
1037 wires_.erase(it->name);
1038 delete it;
1039 }
1040 }
1041
1042 void RTLIL::Module::remove(RTLIL::Cell *cell)
1043 {
1044 log_assert(cells_.count(cell->name) != 0);
1045 log_assert(refcount_cells_ == 0);
1046 cells_.erase(cell->name);
1047 delete cell;
1048 }
1049
1050 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1051 {
1052 log_assert(wires_[wire->name] == wire);
1053 log_assert(refcount_wires_ == 0);
1054 wires_.erase(wire->name);
1055 wire->name = new_name;
1056 add(wire);
1057 }
1058
1059 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1060 {
1061 log_assert(cells_[cell->name] == cell);
1062 log_assert(refcount_wires_ == 0);
1063 cells_.erase(cell->name);
1064 cell->name = new_name;
1065 add(cell);
1066 }
1067
1068 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1069 {
1070 log_assert(count_id(old_name) != 0);
1071 if (wires_.count(old_name))
1072 rename(wires_.at(old_name), new_name);
1073 else if (cells_.count(old_name))
1074 rename(cells_.at(old_name), new_name);
1075 else
1076 log_abort();
1077 }
1078
1079 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1080 {
1081 log_assert(wires_[w1->name] == w1);
1082 log_assert(wires_[w2->name] == w2);
1083 log_assert(refcount_wires_ == 0);
1084
1085 wires_.erase(w1->name);
1086 wires_.erase(w2->name);
1087
1088 std::swap(w1->name, w2->name);
1089
1090 wires_[w1->name] = w1;
1091 wires_[w2->name] = w2;
1092 }
1093
1094 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1095 {
1096 log_assert(cells_[c1->name] == c1);
1097 log_assert(cells_[c2->name] == c2);
1098 log_assert(refcount_cells_ == 0);
1099
1100 cells_.erase(c1->name);
1101 cells_.erase(c2->name);
1102
1103 std::swap(c1->name, c2->name);
1104
1105 cells_[c1->name] = c1;
1106 cells_[c2->name] = c2;
1107 }
1108
1109 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1110 {
1111 int index = 0;
1112 return uniquify(name, index);
1113 }
1114
1115 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1116 {
1117 if (index == 0) {
1118 if (count_id(name) == 0)
1119 return name;
1120 index++;
1121 }
1122
1123 while (1) {
1124 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1125 if (count_id(new_name) == 0)
1126 return new_name;
1127 index++;
1128 }
1129 }
1130
1131 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1132 {
1133 if (a->port_id && !b->port_id)
1134 return true;
1135 if (!a->port_id && b->port_id)
1136 return false;
1137
1138 if (a->port_id == b->port_id)
1139 return a->name < b->name;
1140 return a->port_id < b->port_id;
1141 }
1142
1143 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1144 {
1145 for (auto mon : monitors)
1146 mon->notify_connect(this, conn);
1147
1148 if (design)
1149 for (auto mon : design->monitors)
1150 mon->notify_connect(this, conn);
1151
1152 connections_.push_back(conn);
1153 }
1154
1155 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1156 {
1157 connect(RTLIL::SigSig(lhs, rhs));
1158 }
1159
1160 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1161 {
1162 for (auto mon : monitors)
1163 mon->notify_connect(this, new_conn);
1164
1165 if (design)
1166 for (auto mon : design->monitors)
1167 mon->notify_connect(this, new_conn);
1168
1169 connections_ = new_conn;
1170 }
1171
1172 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1173 {
1174 return connections_;
1175 }
1176
1177 void RTLIL::Module::fixup_ports()
1178 {
1179 std::vector<RTLIL::Wire*> all_ports;
1180
1181 for (auto &w : wires_)
1182 if (w.second->port_input || w.second->port_output)
1183 all_ports.push_back(w.second);
1184 else
1185 w.second->port_id = 0;
1186
1187 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1188
1189 ports.clear();
1190 for (size_t i = 0; i < all_ports.size(); i++) {
1191 ports.push_back(all_ports[i]->name);
1192 all_ports[i]->port_id = i+1;
1193 }
1194 }
1195
1196 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1197 {
1198 RTLIL::Wire *wire = new RTLIL::Wire;
1199 wire->name = name;
1200 wire->width = width;
1201 add(wire);
1202 return wire;
1203 }
1204
1205 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1206 {
1207 RTLIL::Wire *wire = addWire(name);
1208 wire->width = other->width;
1209 wire->start_offset = other->start_offset;
1210 wire->port_id = other->port_id;
1211 wire->port_input = other->port_input;
1212 wire->port_output = other->port_output;
1213 wire->upto = other->upto;
1214 wire->attributes = other->attributes;
1215 return wire;
1216 }
1217
1218 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1219 {
1220 RTLIL::Cell *cell = new RTLIL::Cell;
1221 cell->name = name;
1222 cell->type = type;
1223 add(cell);
1224 return cell;
1225 }
1226
1227 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1228 {
1229 RTLIL::Cell *cell = addCell(name, other->type);
1230 cell->connections_ = other->connections_;
1231 cell->parameters = other->parameters;
1232 cell->attributes = other->attributes;
1233 return cell;
1234 }
1235
1236 #define DEF_METHOD(_func, _y_size, _type) \
1237 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1238 RTLIL::Cell *cell = addCell(name, _type); \
1239 cell->parameters["\\A_SIGNED"] = is_signed; \
1240 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1241 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1242 cell->setPort("\\A", sig_a); \
1243 cell->setPort("\\Y", sig_y); \
1244 return cell; \
1245 } \
1246 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1247 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1248 add ## _func(name, sig_a, sig_y, is_signed); \
1249 return sig_y; \
1250 }
1251 DEF_METHOD(Not, sig_a.size(), "$not")
1252 DEF_METHOD(Pos, sig_a.size(), "$pos")
1253 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1254 DEF_METHOD(Neg, sig_a.size(), "$neg")
1255 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1256 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1257 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1258 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1259 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1260 DEF_METHOD(LogicNot, 1, "$logic_not")
1261 #undef DEF_METHOD
1262
1263 #define DEF_METHOD(_func, _y_size, _type) \
1264 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1265 RTLIL::Cell *cell = addCell(name, _type); \
1266 cell->parameters["\\A_SIGNED"] = is_signed; \
1267 cell->parameters["\\B_SIGNED"] = is_signed; \
1268 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1269 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1270 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1271 cell->setPort("\\A", sig_a); \
1272 cell->setPort("\\B", sig_b); \
1273 cell->setPort("\\Y", sig_y); \
1274 return cell; \
1275 } \
1276 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1277 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1278 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1279 return sig_y; \
1280 }
1281 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1282 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1283 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1284 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1285 DEF_METHOD(Shl, sig_a.size(), "$shl")
1286 DEF_METHOD(Shr, sig_a.size(), "$shr")
1287 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1288 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1289 DEF_METHOD(Shift, sig_a.size(), "$shift")
1290 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1291 DEF_METHOD(Lt, 1, "$lt")
1292 DEF_METHOD(Le, 1, "$le")
1293 DEF_METHOD(Eq, 1, "$eq")
1294 DEF_METHOD(Ne, 1, "$ne")
1295 DEF_METHOD(Eqx, 1, "$eqx")
1296 DEF_METHOD(Nex, 1, "$nex")
1297 DEF_METHOD(Ge, 1, "$ge")
1298 DEF_METHOD(Gt, 1, "$gt")
1299 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1300 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1301 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1302 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1303 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1304 DEF_METHOD(LogicAnd, 1, "$logic_and")
1305 DEF_METHOD(LogicOr, 1, "$logic_or")
1306 #undef DEF_METHOD
1307
1308 #define DEF_METHOD(_func, _type, _pmux) \
1309 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1310 RTLIL::Cell *cell = addCell(name, _type); \
1311 cell->parameters["\\WIDTH"] = sig_a.size(); \
1312 cell->parameters["\\WIDTH"] = sig_b.size(); \
1313 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1314 cell->setPort("\\A", sig_a); \
1315 cell->setPort("\\B", sig_b); \
1316 cell->setPort("\\S", sig_s); \
1317 cell->setPort("\\Y", sig_y); \
1318 return cell; \
1319 } \
1320 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1321 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1322 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1323 return sig_y; \
1324 }
1325 DEF_METHOD(Mux, "$mux", 0)
1326 DEF_METHOD(Pmux, "$pmux", 1)
1327 #undef DEF_METHOD
1328
1329 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1330 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1331 RTLIL::Cell *cell = addCell(name, _type); \
1332 cell->setPort("\\" #_P1, sig1); \
1333 cell->setPort("\\" #_P2, sig2); \
1334 return cell; \
1335 } \
1336 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1337 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1338 add ## _func(name, sig1, sig2); \
1339 return sig2; \
1340 }
1341 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1342 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1343 RTLIL::Cell *cell = addCell(name, _type); \
1344 cell->setPort("\\" #_P1, sig1); \
1345 cell->setPort("\\" #_P2, sig2); \
1346 cell->setPort("\\" #_P3, sig3); \
1347 return cell; \
1348 } \
1349 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1350 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1351 add ## _func(name, sig1, sig2, sig3); \
1352 return sig3; \
1353 }
1354 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1355 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1356 RTLIL::Cell *cell = addCell(name, _type); \
1357 cell->setPort("\\" #_P1, sig1); \
1358 cell->setPort("\\" #_P2, sig2); \
1359 cell->setPort("\\" #_P3, sig3); \
1360 cell->setPort("\\" #_P4, sig4); \
1361 return cell; \
1362 } \
1363 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1364 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1365 add ## _func(name, sig1, sig2, sig3, sig4); \
1366 return sig4; \
1367 }
1368 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1369 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1370 RTLIL::Cell *cell = addCell(name, _type); \
1371 cell->setPort("\\" #_P1, sig1); \
1372 cell->setPort("\\" #_P2, sig2); \
1373 cell->setPort("\\" #_P3, sig3); \
1374 cell->setPort("\\" #_P4, sig4); \
1375 cell->setPort("\\" #_P5, sig5); \
1376 return cell; \
1377 } \
1378 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1379 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1380 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1381 return sig5; \
1382 }
1383 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1384 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1385 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1386 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1387 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1388 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1389 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1390 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1391 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1392 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1393 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1394 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1395 #undef DEF_METHOD_2
1396 #undef DEF_METHOD_3
1397 #undef DEF_METHOD_4
1398 #undef DEF_METHOD_5
1399
1400 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1401 {
1402 RTLIL::Cell *cell = addCell(name, "$pow");
1403 cell->parameters["\\A_SIGNED"] = a_signed;
1404 cell->parameters["\\B_SIGNED"] = b_signed;
1405 cell->parameters["\\A_WIDTH"] = sig_a.size();
1406 cell->parameters["\\B_WIDTH"] = sig_b.size();
1407 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1408 cell->setPort("\\A", sig_a);
1409 cell->setPort("\\B", sig_b);
1410 cell->setPort("\\Y", sig_y);
1411 return cell;
1412 }
1413
1414 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1415 {
1416 RTLIL::Cell *cell = addCell(name, "$slice");
1417 cell->parameters["\\A_WIDTH"] = sig_a.size();
1418 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1419 cell->parameters["\\OFFSET"] = offset;
1420 cell->setPort("\\A", sig_a);
1421 cell->setPort("\\Y", sig_y);
1422 return cell;
1423 }
1424
1425 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1426 {
1427 RTLIL::Cell *cell = addCell(name, "$concat");
1428 cell->parameters["\\A_WIDTH"] = sig_a.size();
1429 cell->parameters["\\B_WIDTH"] = sig_b.size();
1430 cell->setPort("\\A", sig_a);
1431 cell->setPort("\\B", sig_b);
1432 cell->setPort("\\Y", sig_y);
1433 return cell;
1434 }
1435
1436 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1437 {
1438 RTLIL::Cell *cell = addCell(name, "$lut");
1439 cell->parameters["\\LUT"] = lut;
1440 cell->parameters["\\WIDTH"] = sig_i.size();
1441 cell->setPort("\\A", sig_i);
1442 cell->setPort("\\Y", sig_o);
1443 return cell;
1444 }
1445
1446 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1447 {
1448 RTLIL::Cell *cell = addCell(name, "$assert");
1449 cell->setPort("\\A", sig_a);
1450 cell->setPort("\\EN", sig_en);
1451 return cell;
1452 }
1453
1454 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1455 {
1456 RTLIL::Cell *cell = addCell(name, "$sr");
1457 cell->parameters["\\SET_POLARITY"] = set_polarity;
1458 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1459 cell->parameters["\\WIDTH"] = sig_q.size();
1460 cell->setPort("\\SET", sig_set);
1461 cell->setPort("\\CLR", sig_clr);
1462 cell->setPort("\\Q", sig_q);
1463 return cell;
1464 }
1465
1466 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1467 {
1468 RTLIL::Cell *cell = addCell(name, "$dff");
1469 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1470 cell->parameters["\\WIDTH"] = sig_q.size();
1471 cell->setPort("\\CLK", sig_clk);
1472 cell->setPort("\\D", sig_d);
1473 cell->setPort("\\Q", sig_q);
1474 return cell;
1475 }
1476
1477 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1478 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1479 {
1480 RTLIL::Cell *cell = addCell(name, "$dffsr");
1481 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1482 cell->parameters["\\SET_POLARITY"] = set_polarity;
1483 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1484 cell->parameters["\\WIDTH"] = sig_q.size();
1485 cell->setPort("\\CLK", sig_clk);
1486 cell->setPort("\\SET", sig_set);
1487 cell->setPort("\\CLR", sig_clr);
1488 cell->setPort("\\D", sig_d);
1489 cell->setPort("\\Q", sig_q);
1490 return cell;
1491 }
1492
1493 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1494 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1495 {
1496 RTLIL::Cell *cell = addCell(name, "$adff");
1497 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1498 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1499 cell->parameters["\\ARST_VALUE"] = arst_value;
1500 cell->parameters["\\WIDTH"] = sig_q.size();
1501 cell->setPort("\\CLK", sig_clk);
1502 cell->setPort("\\ARST", sig_arst);
1503 cell->setPort("\\D", sig_d);
1504 cell->setPort("\\Q", sig_q);
1505 return cell;
1506 }
1507
1508 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1509 {
1510 RTLIL::Cell *cell = addCell(name, "$dlatch");
1511 cell->parameters["\\EN_POLARITY"] = en_polarity;
1512 cell->parameters["\\WIDTH"] = sig_q.size();
1513 cell->setPort("\\EN", sig_en);
1514 cell->setPort("\\D", sig_d);
1515 cell->setPort("\\Q", sig_q);
1516 return cell;
1517 }
1518
1519 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1520 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1521 {
1522 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1523 cell->parameters["\\EN_POLARITY"] = en_polarity;
1524 cell->parameters["\\SET_POLARITY"] = set_polarity;
1525 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1526 cell->parameters["\\WIDTH"] = sig_q.size();
1527 cell->setPort("\\EN", sig_en);
1528 cell->setPort("\\SET", sig_set);
1529 cell->setPort("\\CLR", sig_clr);
1530 cell->setPort("\\D", sig_d);
1531 cell->setPort("\\Q", sig_q);
1532 return cell;
1533 }
1534
1535 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1536 {
1537 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1538 cell->setPort("\\C", sig_clk);
1539 cell->setPort("\\D", sig_d);
1540 cell->setPort("\\Q", sig_q);
1541 return cell;
1542 }
1543
1544 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1545 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1546 {
1547 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1548 cell->setPort("\\C", sig_clk);
1549 cell->setPort("\\S", sig_set);
1550 cell->setPort("\\R", sig_clr);
1551 cell->setPort("\\D", sig_d);
1552 cell->setPort("\\Q", sig_q);
1553 return cell;
1554 }
1555
1556 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1557 bool arst_value, bool clk_polarity, bool arst_polarity)
1558 {
1559 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1560 cell->setPort("\\C", sig_clk);
1561 cell->setPort("\\R", sig_arst);
1562 cell->setPort("\\D", sig_d);
1563 cell->setPort("\\Q", sig_q);
1564 return cell;
1565 }
1566
1567 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1568 {
1569 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1570 cell->setPort("\\E", sig_en);
1571 cell->setPort("\\D", sig_d);
1572 cell->setPort("\\Q", sig_q);
1573 return cell;
1574 }
1575
1576 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1577 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1578 {
1579 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1580 cell->setPort("\\E", sig_en);
1581 cell->setPort("\\S", sig_set);
1582 cell->setPort("\\R", sig_clr);
1583 cell->setPort("\\D", sig_d);
1584 cell->setPort("\\Q", sig_q);
1585 return cell;
1586 }
1587
1588
1589 RTLIL::Wire::Wire()
1590 {
1591 module = nullptr;
1592 width = 1;
1593 start_offset = 0;
1594 port_id = 0;
1595 port_input = false;
1596 port_output = false;
1597 upto = false;
1598 }
1599
1600 RTLIL::Memory::Memory()
1601 {
1602 width = 1;
1603 size = 0;
1604 }
1605
1606 RTLIL::Cell::Cell() : module(nullptr)
1607 {
1608 }
1609
1610 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1611 {
1612 return connections_.count(portname) != 0;
1613 }
1614
1615 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1616 {
1617 RTLIL::SigSpec signal;
1618 auto conn_it = connections_.find(portname);
1619
1620 if (conn_it != connections_.end())
1621 {
1622 for (auto mon : module->monitors)
1623 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1624
1625 if (module->design)
1626 for (auto mon : module->design->monitors)
1627 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1628
1629 connections_.erase(conn_it);
1630 }
1631 }
1632
1633 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1634 {
1635 auto conn_it = connections_.find(portname);
1636
1637 if (conn_it == connections_.end()) {
1638 connections_[portname] = RTLIL::SigSpec();
1639 conn_it = connections_.find(portname);
1640 log_assert(conn_it != connections_.end());
1641 }
1642
1643 for (auto mon : module->monitors)
1644 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1645
1646 if (module->design)
1647 for (auto mon : module->design->monitors)
1648 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1649
1650 conn_it->second = signal;
1651 }
1652
1653 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1654 {
1655 return connections_.at(portname);
1656 }
1657
1658 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1659 {
1660 return connections_;
1661 }
1662
1663 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1664 {
1665 return parameters.count(paramname);
1666 }
1667
1668 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1669 {
1670 parameters.erase(paramname);
1671 }
1672
1673 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1674 {
1675 parameters[paramname] = value;
1676 }
1677
1678 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1679 {
1680 return parameters.at(paramname);
1681 }
1682
1683 void RTLIL::Cell::check()
1684 {
1685 #ifndef NDEBUG
1686 InternalCellChecker checker(NULL, this);
1687 checker.check();
1688 #endif
1689 }
1690
1691 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1692 {
1693 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1694 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1695 return;
1696
1697 if (type == "$mux" || type == "$pmux")
1698 {
1699 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1700 if (type == "$pmux")
1701 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1702 check();
1703 return;
1704 }
1705
1706 bool signedness_ab = type != "$slice" && type != "$concat";
1707
1708 if (connections_.count("\\A")) {
1709 if (signedness_ab) {
1710 if (set_a_signed)
1711 parameters["\\A_SIGNED"] = true;
1712 else if (parameters.count("\\A_SIGNED") == 0)
1713 parameters["\\A_SIGNED"] = false;
1714 }
1715 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1716 }
1717
1718 if (connections_.count("\\B")) {
1719 if (signedness_ab) {
1720 if (set_b_signed)
1721 parameters["\\B_SIGNED"] = true;
1722 else if (parameters.count("\\B_SIGNED") == 0)
1723 parameters["\\B_SIGNED"] = false;
1724 }
1725 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1726 }
1727
1728 if (connections_.count("\\Y"))
1729 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1730
1731 check();
1732 }
1733
1734 RTLIL::SigChunk::SigChunk()
1735 {
1736 wire = NULL;
1737 width = 0;
1738 offset = 0;
1739 }
1740
1741 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1742 {
1743 wire = NULL;
1744 data = value;
1745 width = data.bits.size();
1746 offset = 0;
1747 }
1748
1749 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1750 {
1751 log_assert(wire != nullptr);
1752 this->wire = wire;
1753 this->width = wire->width;
1754 this->offset = 0;
1755 }
1756
1757 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1758 {
1759 log_assert(wire != nullptr);
1760 this->wire = wire;
1761 this->width = width;
1762 this->offset = offset;
1763 }
1764
1765 RTLIL::SigChunk::SigChunk(const std::string &str)
1766 {
1767 wire = NULL;
1768 data = RTLIL::Const(str);
1769 width = data.bits.size();
1770 offset = 0;
1771 }
1772
1773 RTLIL::SigChunk::SigChunk(int val, int width)
1774 {
1775 wire = NULL;
1776 data = RTLIL::Const(val, width);
1777 this->width = data.bits.size();
1778 offset = 0;
1779 }
1780
1781 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1782 {
1783 wire = NULL;
1784 data = RTLIL::Const(bit, width);
1785 this->width = data.bits.size();
1786 offset = 0;
1787 }
1788
1789 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1790 {
1791 wire = bit.wire;
1792 offset = 0;
1793 if (wire == NULL)
1794 data = RTLIL::Const(bit.data);
1795 else
1796 offset = bit.offset;
1797 width = 1;
1798 }
1799
1800 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1801 {
1802 RTLIL::SigChunk ret;
1803 if (wire) {
1804 ret.wire = wire;
1805 ret.offset = this->offset + offset;
1806 ret.width = length;
1807 } else {
1808 for (int i = 0; i < length; i++)
1809 ret.data.bits.push_back(data.bits[offset+i]);
1810 ret.width = length;
1811 }
1812 return ret;
1813 }
1814
1815 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1816 {
1817 if (wire && other.wire)
1818 if (wire->name != other.wire->name)
1819 return wire->name < other.wire->name;
1820
1821 if (wire != other.wire)
1822 return wire < other.wire;
1823
1824 if (offset != other.offset)
1825 return offset < other.offset;
1826
1827 if (width != other.width)
1828 return width < other.width;
1829
1830 return data.bits < other.data.bits;
1831 }
1832
1833 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1834 {
1835 if (wire != other.wire || width != other.width || offset != other.offset)
1836 return false;
1837 if (data.bits != other.data.bits)
1838 return false;
1839 return true;
1840 }
1841
1842 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1843 {
1844 if (*this == other)
1845 return false;
1846 return true;
1847 }
1848
1849 RTLIL::SigSpec::SigSpec()
1850 {
1851 width_ = 0;
1852 hash_ = 0;
1853 }
1854
1855 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1856 {
1857 *this = other;
1858 }
1859
1860 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1861 {
1862 cover("kernel.rtlil.sigspec.init.list");
1863
1864 width_ = 0;
1865 hash_ = 0;
1866
1867 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1868 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1869 append(*it);
1870 }
1871
1872 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1873 {
1874 cover("kernel.rtlil.sigspec.assign");
1875
1876 width_ = other.width_;
1877 hash_ = other.hash_;
1878 chunks_ = other.chunks_;
1879 bits_.clear();
1880
1881 if (!other.bits_.empty())
1882 {
1883 RTLIL::SigChunk *last = NULL;
1884 int last_end_offset = 0;
1885
1886 for (auto &bit : other.bits_) {
1887 if (last && bit.wire == last->wire) {
1888 if (bit.wire == NULL) {
1889 last->data.bits.push_back(bit.data);
1890 last->width++;
1891 continue;
1892 } else if (last_end_offset == bit.offset) {
1893 last_end_offset++;
1894 last->width++;
1895 continue;
1896 }
1897 }
1898 chunks_.push_back(bit);
1899 last = &chunks_.back();
1900 last_end_offset = bit.offset + 1;
1901 }
1902
1903 check();
1904 }
1905
1906 return *this;
1907 }
1908
1909 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1910 {
1911 cover("kernel.rtlil.sigspec.init.const");
1912
1913 chunks_.push_back(RTLIL::SigChunk(value));
1914 width_ = chunks_.back().width;
1915 hash_ = 0;
1916 check();
1917 }
1918
1919 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1920 {
1921 cover("kernel.rtlil.sigspec.init.chunk");
1922
1923 chunks_.push_back(chunk);
1924 width_ = chunks_.back().width;
1925 hash_ = 0;
1926 check();
1927 }
1928
1929 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1930 {
1931 cover("kernel.rtlil.sigspec.init.wire");
1932
1933 chunks_.push_back(RTLIL::SigChunk(wire));
1934 width_ = chunks_.back().width;
1935 hash_ = 0;
1936 check();
1937 }
1938
1939 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1940 {
1941 cover("kernel.rtlil.sigspec.init.wire_part");
1942
1943 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1944 width_ = chunks_.back().width;
1945 hash_ = 0;
1946 check();
1947 }
1948
1949 RTLIL::SigSpec::SigSpec(const std::string &str)
1950 {
1951 cover("kernel.rtlil.sigspec.init.str");
1952
1953 chunks_.push_back(RTLIL::SigChunk(str));
1954 width_ = chunks_.back().width;
1955 hash_ = 0;
1956 check();
1957 }
1958
1959 RTLIL::SigSpec::SigSpec(int val, int width)
1960 {
1961 cover("kernel.rtlil.sigspec.init.int");
1962
1963 chunks_.push_back(RTLIL::SigChunk(val, width));
1964 width_ = width;
1965 hash_ = 0;
1966 check();
1967 }
1968
1969 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1970 {
1971 cover("kernel.rtlil.sigspec.init.state");
1972
1973 chunks_.push_back(RTLIL::SigChunk(bit, width));
1974 width_ = width;
1975 hash_ = 0;
1976 check();
1977 }
1978
1979 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1980 {
1981 cover("kernel.rtlil.sigspec.init.bit");
1982
1983 if (bit.wire == NULL)
1984 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1985 else
1986 for (int i = 0; i < width; i++)
1987 chunks_.push_back(bit);
1988 width_ = width;
1989 hash_ = 0;
1990 check();
1991 }
1992
1993 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1994 {
1995 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1996
1997 width_ = 0;
1998 hash_ = 0;
1999 for (auto &c : chunks)
2000 append(c);
2001 check();
2002 }
2003
2004 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2005 {
2006 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2007
2008 width_ = 0;
2009 hash_ = 0;
2010 for (auto &bit : bits)
2011 append_bit(bit);
2012 check();
2013 }
2014
2015 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2016 {
2017 cover("kernel.rtlil.sigspec.init.stdset_bits");
2018
2019 width_ = 0;
2020 hash_ = 0;
2021 for (auto &bit : bits)
2022 append_bit(bit);
2023 check();
2024 }
2025
2026 void RTLIL::SigSpec::pack() const
2027 {
2028 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2029
2030 if (that->bits_.empty())
2031 return;
2032
2033 cover("kernel.rtlil.sigspec.convert.pack");
2034 log_assert(that->chunks_.empty());
2035
2036 std::vector<RTLIL::SigBit> old_bits;
2037 old_bits.swap(that->bits_);
2038
2039 RTLIL::SigChunk *last = NULL;
2040 int last_end_offset = 0;
2041
2042 for (auto &bit : old_bits) {
2043 if (last && bit.wire == last->wire) {
2044 if (bit.wire == NULL) {
2045 last->data.bits.push_back(bit.data);
2046 last->width++;
2047 continue;
2048 } else if (last_end_offset == bit.offset) {
2049 last_end_offset++;
2050 last->width++;
2051 continue;
2052 }
2053 }
2054 that->chunks_.push_back(bit);
2055 last = &that->chunks_.back();
2056 last_end_offset = bit.offset + 1;
2057 }
2058
2059 check();
2060 }
2061
2062 void RTLIL::SigSpec::unpack() const
2063 {
2064 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2065
2066 if (that->chunks_.empty())
2067 return;
2068
2069 cover("kernel.rtlil.sigspec.convert.unpack");
2070 log_assert(that->bits_.empty());
2071
2072 that->bits_.reserve(that->width_);
2073 for (auto &c : that->chunks_)
2074 for (int i = 0; i < c.width; i++)
2075 that->bits_.push_back(RTLIL::SigBit(c, i));
2076
2077 that->chunks_.clear();
2078 that->hash_ = 0;
2079 }
2080
2081 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2082
2083 void RTLIL::SigSpec::hash() const
2084 {
2085 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2086
2087 if (that->hash_ != 0)
2088 return;
2089
2090 cover("kernel.rtlil.sigspec.hash");
2091 that->pack();
2092
2093 that->hash_ = 5381;
2094 for (auto &c : that->chunks_)
2095 if (c.wire == NULL) {
2096 for (auto &v : c.data.bits)
2097 DJB2(that->hash_, v);
2098 } else {
2099 DJB2(that->hash_, c.wire->name.index_);
2100 DJB2(that->hash_, c.offset);
2101 DJB2(that->hash_, c.width);
2102 }
2103
2104 if (that->hash_ == 0)
2105 that->hash_ = 1;
2106 }
2107
2108 void RTLIL::SigSpec::sort()
2109 {
2110 unpack();
2111 cover("kernel.rtlil.sigspec.sort");
2112 std::sort(bits_.begin(), bits_.end());
2113 }
2114
2115 void RTLIL::SigSpec::sort_and_unify()
2116 {
2117 cover("kernel.rtlil.sigspec.sort_and_unify");
2118 *this = this->to_sigbit_set();
2119 }
2120
2121 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2122 {
2123 replace(pattern, with, this);
2124 }
2125
2126 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2127 {
2128 log_assert(pattern.width_ == with.width_);
2129
2130 pattern.unpack();
2131 with.unpack();
2132
2133 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2134
2135 for (int i = 0; i < SIZE(pattern.bits_); i++)
2136 if (pattern.bits_[i].wire != NULL)
2137 rules[pattern.bits_[i]] = with.bits_[i];
2138
2139 replace(rules, other);
2140 }
2141
2142 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2143 {
2144 replace(rules, this);
2145 }
2146
2147 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2148 {
2149 cover("kernel.rtlil.sigspec.replace");
2150
2151 log_assert(other != NULL);
2152 log_assert(width_ == other->width_);
2153
2154 unpack();
2155 other->unpack();
2156
2157 for (int i = 0; i < SIZE(bits_); i++) {
2158 auto it = rules.find(bits_[i]);
2159 if (it != rules.end())
2160 other->bits_[i] = it->second;
2161 }
2162
2163 other->check();
2164 }
2165
2166 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2167 {
2168 remove2(pattern, NULL);
2169 }
2170
2171 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2172 {
2173 RTLIL::SigSpec tmp = *this;
2174 tmp.remove2(pattern, other);
2175 }
2176
2177 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2178 {
2179 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2180 remove2(pattern_bits, other);
2181 }
2182
2183 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2184 {
2185 remove2(pattern, NULL);
2186 }
2187
2188 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2189 {
2190 RTLIL::SigSpec tmp = *this;
2191 tmp.remove2(pattern, other);
2192 }
2193
2194 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2195 {
2196 if (other)
2197 cover("kernel.rtlil.sigspec.remove_other");
2198 else
2199 cover("kernel.rtlil.sigspec.remove");
2200
2201 unpack();
2202
2203 if (other != NULL) {
2204 log_assert(width_ == other->width_);
2205 other->unpack();
2206 }
2207
2208 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2209
2210 new_bits.resize(SIZE(bits_));
2211 if (other != NULL)
2212 new_other_bits.resize(SIZE(bits_));
2213
2214 int k = 0;
2215 for (int i = 0; i < SIZE(bits_); i++) {
2216 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2217 continue;
2218 if (other != NULL)
2219 new_other_bits[k] = other->bits_[i];
2220 new_bits[k++] = bits_[i];
2221 }
2222
2223 new_bits.resize(k);
2224 if (other != NULL)
2225 new_other_bits.resize(k);
2226
2227 bits_.swap(new_bits);
2228 width_ = SIZE(bits_);
2229
2230 if (other != NULL) {
2231 other->bits_.swap(new_other_bits);
2232 other->width_ = SIZE(other->bits_);
2233 }
2234
2235 check();
2236 }
2237
2238 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2239 {
2240 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2241 return extract(pattern_bits, other);
2242 }
2243
2244 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2245 {
2246 if (other)
2247 cover("kernel.rtlil.sigspec.extract_other");
2248 else
2249 cover("kernel.rtlil.sigspec.extract");
2250
2251 log_assert(other == NULL || width_ == other->width_);
2252
2253 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2254 RTLIL::SigSpec ret;
2255
2256 if (other) {
2257 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2258 for (int i = 0; i < width_; i++)
2259 if (bits_match[i].wire && pattern.count(bits_match[i]))
2260 ret.append_bit(bits_other[i]);
2261 } else {
2262 for (int i = 0; i < width_; i++)
2263 if (bits_match[i].wire && pattern.count(bits_match[i]))
2264 ret.append_bit(bits_match[i]);
2265 }
2266
2267 ret.check();
2268 return ret;
2269 }
2270
2271 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2272 {
2273 cover("kernel.rtlil.sigspec.replace_pos");
2274
2275 unpack();
2276 with.unpack();
2277
2278 log_assert(offset >= 0);
2279 log_assert(with.width_ >= 0);
2280 log_assert(offset+with.width_ <= width_);
2281
2282 for (int i = 0; i < with.width_; i++)
2283 bits_.at(offset + i) = with.bits_.at(i);
2284
2285 check();
2286 }
2287
2288 void RTLIL::SigSpec::remove_const()
2289 {
2290 if (packed())
2291 {
2292 cover("kernel.rtlil.sigspec.remove_const.packed");
2293
2294 std::vector<RTLIL::SigChunk> new_chunks;
2295 new_chunks.reserve(SIZE(chunks_));
2296
2297 width_ = 0;
2298 for (auto &chunk : chunks_)
2299 if (chunk.wire != NULL) {
2300 new_chunks.push_back(chunk);
2301 width_ += chunk.width;
2302 }
2303
2304 chunks_.swap(new_chunks);
2305 }
2306 else
2307 {
2308 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2309
2310 std::vector<RTLIL::SigBit> new_bits;
2311 new_bits.reserve(width_);
2312
2313 for (auto &bit : bits_)
2314 if (bit.wire != NULL)
2315 new_bits.push_back(bit);
2316
2317 bits_.swap(new_bits);
2318 width_ = bits_.size();
2319 }
2320
2321 check();
2322 }
2323
2324 void RTLIL::SigSpec::remove(int offset, int length)
2325 {
2326 cover("kernel.rtlil.sigspec.remove_pos");
2327
2328 unpack();
2329
2330 log_assert(offset >= 0);
2331 log_assert(length >= 0);
2332 log_assert(offset + length <= width_);
2333
2334 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2335 width_ = bits_.size();
2336
2337 check();
2338 }
2339
2340 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2341 {
2342 unpack();
2343 cover("kernel.rtlil.sigspec.extract_pos");
2344 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2345 }
2346
2347 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2348 {
2349 if (signal.width_ == 0)
2350 return;
2351
2352 if (width_ == 0) {
2353 *this = signal;
2354 return;
2355 }
2356
2357 cover("kernel.rtlil.sigspec.append");
2358
2359 if (packed() != signal.packed()) {
2360 pack();
2361 signal.pack();
2362 }
2363
2364 if (packed())
2365 for (auto &other_c : signal.chunks_)
2366 {
2367 auto &my_last_c = chunks_.back();
2368 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2369 auto &this_data = my_last_c.data.bits;
2370 auto &other_data = other_c.data.bits;
2371 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2372 my_last_c.width += other_c.width;
2373 } else
2374 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2375 my_last_c.width += other_c.width;
2376 } else
2377 chunks_.push_back(other_c);
2378 }
2379 else
2380 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2381
2382 width_ += signal.width_;
2383 check();
2384 }
2385
2386 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2387 {
2388 if (packed())
2389 {
2390 cover("kernel.rtlil.sigspec.append_bit.packed");
2391
2392 if (chunks_.size() == 0)
2393 chunks_.push_back(bit);
2394 else
2395 if (bit.wire == NULL)
2396 if (chunks_.back().wire == NULL) {
2397 chunks_.back().data.bits.push_back(bit.data);
2398 chunks_.back().width++;
2399 } else
2400 chunks_.push_back(bit);
2401 else
2402 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2403 chunks_.back().width++;
2404 else
2405 chunks_.push_back(bit);
2406 }
2407 else
2408 {
2409 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2410 bits_.push_back(bit);
2411 }
2412
2413 width_++;
2414 check();
2415 }
2416
2417 void RTLIL::SigSpec::extend(int width, bool is_signed)
2418 {
2419 cover("kernel.rtlil.sigspec.extend");
2420
2421 pack();
2422
2423 if (width_ > width)
2424 remove(width, width_ - width);
2425
2426 if (width_ < width) {
2427 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2428 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2429 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2430 padding = RTLIL::SigSpec(RTLIL::State::S0);
2431 while (width_ < width)
2432 append(padding);
2433 }
2434 }
2435
2436 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2437 {
2438 cover("kernel.rtlil.sigspec.extend_u0");
2439
2440 pack();
2441
2442 if (width_ > width)
2443 remove(width, width_ - width);
2444
2445 if (width_ < width) {
2446 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2447 if (!is_signed)
2448 padding = RTLIL::SigSpec(RTLIL::State::S0);
2449 while (width_ < width)
2450 append(padding);
2451 }
2452
2453 }
2454
2455 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2456 {
2457 cover("kernel.rtlil.sigspec.repeat");
2458
2459 RTLIL::SigSpec sig;
2460 for (int i = 0; i < num; i++)
2461 sig.append(*this);
2462 return sig;
2463 }
2464
2465 #ifndef NDEBUG
2466 void RTLIL::SigSpec::check() const
2467 {
2468 if (width_ > 64)
2469 {
2470 cover("kernel.rtlil.sigspec.check.skip");
2471 }
2472 else if (packed())
2473 {
2474 cover("kernel.rtlil.sigspec.check.packed");
2475
2476 int w = 0;
2477 for (size_t i = 0; i < chunks_.size(); i++) {
2478 const RTLIL::SigChunk chunk = chunks_[i];
2479 if (chunk.wire == NULL) {
2480 if (i > 0)
2481 log_assert(chunks_[i-1].wire != NULL);
2482 log_assert(chunk.offset == 0);
2483 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2484 } else {
2485 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2486 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2487 log_assert(chunk.offset >= 0);
2488 log_assert(chunk.width >= 0);
2489 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2490 log_assert(chunk.data.bits.size() == 0);
2491 }
2492 w += chunk.width;
2493 }
2494 log_assert(w == width_);
2495 log_assert(bits_.empty());
2496 }
2497 else
2498 {
2499 cover("kernel.rtlil.sigspec.check.unpacked");
2500
2501 log_assert(width_ == SIZE(bits_));
2502 log_assert(chunks_.empty());
2503 }
2504 }
2505 #endif
2506
2507 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2508 {
2509 cover("kernel.rtlil.sigspec.comp_lt");
2510
2511 if (this == &other)
2512 return false;
2513
2514 if (width_ != other.width_)
2515 return width_ < other.width_;
2516
2517 pack();
2518 other.pack();
2519
2520 if (chunks_.size() != other.chunks_.size())
2521 return chunks_.size() < other.chunks_.size();
2522
2523 hash();
2524 other.hash();
2525
2526 if (hash_ != other.hash_)
2527 return hash_ < other.hash_;
2528
2529 for (size_t i = 0; i < chunks_.size(); i++)
2530 if (chunks_[i] != other.chunks_[i]) {
2531 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2532 return chunks_[i] < other.chunks_[i];
2533 }
2534
2535 cover("kernel.rtlil.sigspec.comp_lt.equal");
2536 return false;
2537 }
2538
2539 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2540 {
2541 cover("kernel.rtlil.sigspec.comp_eq");
2542
2543 if (this == &other)
2544 return true;
2545
2546 if (width_ != other.width_)
2547 return false;
2548
2549 pack();
2550 other.pack();
2551
2552 if (chunks_.size() != chunks_.size())
2553 return false;
2554
2555 hash();
2556 other.hash();
2557
2558 if (hash_ != other.hash_)
2559 return false;
2560
2561 for (size_t i = 0; i < chunks_.size(); i++)
2562 if (chunks_[i] != other.chunks_[i]) {
2563 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2564 return false;
2565 }
2566
2567 cover("kernel.rtlil.sigspec.comp_eq.equal");
2568 return true;
2569 }
2570
2571 bool RTLIL::SigSpec::is_wire() const
2572 {
2573 cover("kernel.rtlil.sigspec.is_wire");
2574
2575 pack();
2576 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2577 }
2578
2579 bool RTLIL::SigSpec::is_chunk() const
2580 {
2581 cover("kernel.rtlil.sigspec.is_chunk");
2582
2583 pack();
2584 return SIZE(chunks_) == 1;
2585 }
2586
2587 bool RTLIL::SigSpec::is_fully_const() const
2588 {
2589 cover("kernel.rtlil.sigspec.is_fully_const");
2590
2591 pack();
2592 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2593 if (it->width > 0 && it->wire != NULL)
2594 return false;
2595 return true;
2596 }
2597
2598 bool RTLIL::SigSpec::is_fully_def() const
2599 {
2600 cover("kernel.rtlil.sigspec.is_fully_def");
2601
2602 pack();
2603 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2604 if (it->width > 0 && it->wire != NULL)
2605 return false;
2606 for (size_t i = 0; i < it->data.bits.size(); i++)
2607 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2608 return false;
2609 }
2610 return true;
2611 }
2612
2613 bool RTLIL::SigSpec::is_fully_undef() const
2614 {
2615 cover("kernel.rtlil.sigspec.is_fully_undef");
2616
2617 pack();
2618 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2619 if (it->width > 0 && it->wire != NULL)
2620 return false;
2621 for (size_t i = 0; i < it->data.bits.size(); i++)
2622 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2623 return false;
2624 }
2625 return true;
2626 }
2627
2628 bool RTLIL::SigSpec::has_marked_bits() const
2629 {
2630 cover("kernel.rtlil.sigspec.has_marked_bits");
2631
2632 pack();
2633 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2634 if (it->width > 0 && it->wire == NULL) {
2635 for (size_t i = 0; i < it->data.bits.size(); i++)
2636 if (it->data.bits[i] == RTLIL::State::Sm)
2637 return true;
2638 }
2639 return false;
2640 }
2641
2642 bool RTLIL::SigSpec::as_bool() const
2643 {
2644 cover("kernel.rtlil.sigspec.as_bool");
2645
2646 pack();
2647 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2648 if (width_)
2649 return chunks_[0].data.as_bool();
2650 return false;
2651 }
2652
2653 int RTLIL::SigSpec::as_int(bool is_signed) const
2654 {
2655 cover("kernel.rtlil.sigspec.as_int");
2656
2657 pack();
2658 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2659 if (width_)
2660 return chunks_[0].data.as_int(is_signed);
2661 return 0;
2662 }
2663
2664 std::string RTLIL::SigSpec::as_string() const
2665 {
2666 cover("kernel.rtlil.sigspec.as_string");
2667
2668 pack();
2669 std::string str;
2670 for (size_t i = chunks_.size(); i > 0; i--) {
2671 const RTLIL::SigChunk &chunk = chunks_[i-1];
2672 if (chunk.wire != NULL)
2673 for (int j = 0; j < chunk.width; j++)
2674 str += "?";
2675 else
2676 str += chunk.data.as_string();
2677 }
2678 return str;
2679 }
2680
2681 RTLIL::Const RTLIL::SigSpec::as_const() const
2682 {
2683 cover("kernel.rtlil.sigspec.as_const");
2684
2685 pack();
2686 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2687 if (width_)
2688 return chunks_[0].data;
2689 return RTLIL::Const();
2690 }
2691
2692 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2693 {
2694 cover("kernel.rtlil.sigspec.as_wire");
2695
2696 pack();
2697 log_assert(is_wire());
2698 return chunks_[0].wire;
2699 }
2700
2701 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2702 {
2703 cover("kernel.rtlil.sigspec.as_chunk");
2704
2705 pack();
2706 log_assert(is_chunk());
2707 return chunks_[0];
2708 }
2709
2710 bool RTLIL::SigSpec::match(std::string pattern) const
2711 {
2712 cover("kernel.rtlil.sigspec.match");
2713
2714 pack();
2715 std::string str = as_string();
2716 log_assert(pattern.size() == str.size());
2717
2718 for (size_t i = 0; i < pattern.size(); i++) {
2719 if (pattern[i] == ' ')
2720 continue;
2721 if (pattern[i] == '*') {
2722 if (str[i] != 'z' && str[i] != 'x')
2723 return false;
2724 continue;
2725 }
2726 if (pattern[i] != str[i])
2727 return false;
2728 }
2729
2730 return true;
2731 }
2732
2733 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2734 {
2735 cover("kernel.rtlil.sigspec.to_sigbit_set");
2736
2737 pack();
2738 std::set<RTLIL::SigBit> sigbits;
2739 for (auto &c : chunks_)
2740 for (int i = 0; i < c.width; i++)
2741 sigbits.insert(RTLIL::SigBit(c, i));
2742 return sigbits;
2743 }
2744
2745 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2746 {
2747 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2748
2749 unpack();
2750 return bits_;
2751 }
2752
2753 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2754 {
2755 cover("kernel.rtlil.sigspec.to_sigbit_map");
2756
2757 unpack();
2758 other.unpack();
2759
2760 log_assert(width_ == other.width_);
2761
2762 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2763 for (int i = 0; i < width_; i++)
2764 new_map[bits_[i]] = other.bits_[i];
2765
2766 return new_map;
2767 }
2768
2769 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2770 {
2771 cover("kernel.rtlil.sigspec.to_single_sigbit");
2772
2773 pack();
2774 log_assert(width_ == 1);
2775 for (auto &c : chunks_)
2776 if (c.width)
2777 return RTLIL::SigBit(c);
2778 log_abort();
2779 }
2780
2781 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2782 {
2783 size_t start = 0, end = 0;
2784 while ((end = text.find(sep, start)) != std::string::npos) {
2785 tokens.push_back(text.substr(start, end - start));
2786 start = end + 1;
2787 }
2788 tokens.push_back(text.substr(start));
2789 }
2790
2791 static int sigspec_parse_get_dummy_line_num()
2792 {
2793 return 0;
2794 }
2795
2796 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2797 {
2798 cover("kernel.rtlil.sigspec.parse");
2799
2800 std::vector<std::string> tokens;
2801 sigspec_parse_split(tokens, str, ',');
2802
2803 sig = RTLIL::SigSpec();
2804 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2805 {
2806 std::string netname = tokens[tokidx];
2807 std::string indices;
2808
2809 if (netname.size() == 0)
2810 continue;
2811
2812 if ('0' <= netname[0] && netname[0] <= '9') {
2813 cover("kernel.rtlil.sigspec.parse.const");
2814 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2815 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2816 if (ast == NULL)
2817 return false;
2818 sig.append(RTLIL::Const(ast->bits));
2819 delete ast;
2820 continue;
2821 }
2822
2823 if (module == NULL)
2824 return false;
2825
2826 cover("kernel.rtlil.sigspec.parse.net");
2827
2828 if (netname[0] != '$' && netname[0] != '\\')
2829 netname = "\\" + netname;
2830
2831 if (module->wires_.count(netname) == 0) {
2832 size_t indices_pos = netname.size()-1;
2833 if (indices_pos > 2 && netname[indices_pos] == ']')
2834 {
2835 indices_pos--;
2836 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2837 if (indices_pos > 0 && netname[indices_pos] == ':') {
2838 indices_pos--;
2839 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2840 }
2841 if (indices_pos > 0 && netname[indices_pos] == '[') {
2842 indices = netname.substr(indices_pos);
2843 netname = netname.substr(0, indices_pos);
2844 }
2845 }
2846 }
2847
2848 if (module->wires_.count(netname) == 0)
2849 return false;
2850
2851 RTLIL::Wire *wire = module->wires_.at(netname);
2852 if (!indices.empty()) {
2853 std::vector<std::string> index_tokens;
2854 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2855 if (index_tokens.size() == 1) {
2856 cover("kernel.rtlil.sigspec.parse.bit_sel");
2857 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2858 } else {
2859 cover("kernel.rtlil.sigspec.parse.part_sel");
2860 int a = atoi(index_tokens.at(0).c_str());
2861 int b = atoi(index_tokens.at(1).c_str());
2862 if (a > b) {
2863 int tmp = a;
2864 a = b, b = tmp;
2865 }
2866 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2867 }
2868 } else
2869 sig.append(wire);
2870 }
2871
2872 return true;
2873 }
2874
2875 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2876 {
2877 if (str.empty() || str[0] != '@')
2878 return parse(sig, module, str);
2879
2880 cover("kernel.rtlil.sigspec.parse.sel");
2881
2882 str = RTLIL::escape_id(str.substr(1));
2883 if (design->selection_vars.count(str) == 0)
2884 return false;
2885
2886 sig = RTLIL::SigSpec();
2887 RTLIL::Selection &sel = design->selection_vars.at(str);
2888 for (auto &it : module->wires_)
2889 if (sel.selected_member(module->name, it.first))
2890 sig.append(it.second);
2891
2892 return true;
2893 }
2894
2895 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2896 {
2897 if (str == "0") {
2898 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2899 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2900 return true;
2901 }
2902
2903 if (str == "~0") {
2904 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2905 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2906 return true;
2907 }
2908
2909 if (lhs.chunks_.size() == 1) {
2910 char *p = (char*)str.c_str(), *endptr;
2911 long long int val = strtoll(p, &endptr, 10);
2912 if (endptr && endptr != p && *endptr == 0) {
2913 sig = RTLIL::SigSpec(val, lhs.width_);
2914 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2915 return true;
2916 }
2917 }
2918
2919 return parse(sig, module, str);
2920 }
2921
2922 RTLIL::CaseRule::~CaseRule()
2923 {
2924 for (auto it = switches.begin(); it != switches.end(); it++)
2925 delete *it;
2926 }
2927
2928 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2929 {
2930 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2931 new_caserule->compare = compare;
2932 new_caserule->actions = actions;
2933 for (auto &it : switches)
2934 new_caserule->switches.push_back(it->clone());
2935 return new_caserule;
2936 }
2937
2938 RTLIL::SwitchRule::~SwitchRule()
2939 {
2940 for (auto it = cases.begin(); it != cases.end(); it++)
2941 delete *it;
2942 }
2943
2944 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2945 {
2946 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2947 new_switchrule->signal = signal;
2948 new_switchrule->attributes = attributes;
2949 for (auto &it : cases)
2950 new_switchrule->cases.push_back(it->clone());
2951 return new_switchrule;
2952
2953 }
2954
2955 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2956 {
2957 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2958 new_syncrule->type = type;
2959 new_syncrule->signal = signal;
2960 new_syncrule->actions = actions;
2961 return new_syncrule;
2962 }
2963
2964 RTLIL::Process::~Process()
2965 {
2966 for (auto it = syncs.begin(); it != syncs.end(); it++)
2967 delete *it;
2968 }
2969
2970 RTLIL::Process *RTLIL::Process::clone() const
2971 {
2972 RTLIL::Process *new_proc = new RTLIL::Process;
2973
2974 new_proc->name = name;
2975 new_proc->attributes = attributes;
2976
2977 RTLIL::CaseRule *rc_ptr = root_case.clone();
2978 new_proc->root_case = *rc_ptr;
2979 rc_ptr->switches.clear();
2980 delete rc_ptr;
2981
2982 for (auto &it : syncs)
2983 new_proc->syncs.push_back(it->clone());
2984
2985 return new_proc;
2986 }
2987
2988 YOSYS_NAMESPACE_END
2989