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Added $lcu cell type
[yosys.git] / kernel / satgen.h
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #ifndef SATGEN_H
21 #define SATGEN_H
22
23 #include "kernel/rtlil.h"
24 #include "kernel/sigtools.h"
25 #include "kernel/celltypes.h"
26 #include "kernel/macc.h"
27
28 #include "libs/ezsat/ezminisat.h"
29 typedef ezMiniSAT ezDefaultSAT;
30
31 struct SatGen
32 {
33 ezSAT *ez;
34 SigMap *sigmap;
35 std::string prefix;
36 SigPool initial_state;
37 std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
38 bool ignore_div_by_zero;
39 bool model_undef;
40
41 SatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :
42 ez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)
43 {
44 }
45
46 void setContext(SigMap *sigmap, std::string prefix = std::string())
47 {
48 this->sigmap = sigmap;
49 this->prefix = prefix;
50 }
51
52 std::vector<int> importSigSpecWorker(RTLIL::SigSpec &sig, std::string &pf, bool undef_mode, bool dup_undef)
53 {
54 log_assert(!undef_mode || model_undef);
55 sigmap->apply(sig);
56
57 std::vector<int> vec;
58 vec.reserve(SIZE(sig));
59
60 for (auto &bit : sig)
61 if (bit.wire == NULL) {
62 if (model_undef && dup_undef && bit == RTLIL::State::Sx)
63 vec.push_back(ez->frozen_literal());
64 else
65 vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE);
66 } else {
67 std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset);
68 vec.push_back(ez->frozen_literal(name));
69 }
70 return vec;
71 }
72
73 std::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)
74 {
75 log_assert(timestep != 0);
76 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
77 return importSigSpecWorker(sig, pf, false, false);
78 }
79
80 std::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)
81 {
82 log_assert(timestep != 0);
83 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
84 return importSigSpecWorker(sig, pf, false, true);
85 }
86
87 std::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)
88 {
89 log_assert(timestep != 0);
90 std::string pf = "undef:" + prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
91 return importSigSpecWorker(sig, pf, true, false);
92 }
93
94 void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)
95 {
96 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
97 sig_a = asserts_a[pf];
98 sig_en = asserts_en[pf];
99 }
100
101 int importAsserts(int timestep = -1)
102 {
103 std::vector<int> check_bits, enable_bits;
104 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
105 if (model_undef) {
106 check_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));
107 enable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));
108 } else {
109 check_bits = importDefSigSpec(asserts_a[pf], timestep);
110 enable_bits = importDefSigSpec(asserts_en[pf], timestep);
111 }
112 return ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));
113 }
114
115 int signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)
116 {
117 if (timestep_rhs < 0)
118 timestep_rhs = timestep_lhs;
119
120 log_assert(lhs.size() == rhs.size());
121
122 std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);
123 std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);
124
125 if (!model_undef)
126 return ez->vec_eq(vec_lhs, vec_rhs);
127
128 std::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);
129 std::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);
130
131 std::vector<int> eq_bits;
132 for (int i = 0; i < lhs.size(); i++)
133 eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),
134 ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));
135 return ez->expression(ezSAT::OpAnd, eq_bits);
136 }
137
138 void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
139 {
140 bool is_signed = forced_signed;
141 if (!forced_signed && cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0)
142 is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
143 while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
144 vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
145 while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
146 vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->FALSE);
147 }
148
149 void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
150 {
151 extendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);
152 while (vec_y.size() < vec_a.size())
153 vec_y.push_back(ez->literal());
154 }
155
156 void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
157 {
158 bool is_signed = forced_signed || (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool());
159 while (vec_a.size() < vec_y.size())
160 vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
161 while (vec_y.size() < vec_a.size())
162 vec_y.push_back(ez->literal());
163 }
164
165 void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)
166 {
167 log_assert(model_undef);
168 log_assert(vec_y.size() == vec_yy.size());
169 if (vec_y.size() > vec_undef.size()) {
170 std::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());
171 std::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());
172 ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));
173 } else {
174 log_assert(vec_y.size() == vec_undef.size());
175 ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));
176 }
177 }
178
179 void undefGating(int y, int yy, int undef)
180 {
181 ez->assume(ez->OR(undef, ez->IFF(y, yy)));
182 }
183
184 bool importCell(RTLIL::Cell *cell, int timestep = -1)
185 {
186 bool arith_undef_handled = false;
187 bool is_arith_compare = cell->type.in("$lt", "$le", "$ge", "$gt");
188
189 if (model_undef && (cell->type.in("$add", "$sub", "$mul", "$div", "$mod") || is_arith_compare))
190 {
191 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
192 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
193 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
194 if (is_arith_compare)
195 extendSignalWidth(undef_a, undef_b, cell, true);
196 else
197 extendSignalWidth(undef_a, undef_b, undef_y, cell, true);
198
199 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
200 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
201 int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
202
203 if (cell->type == "$div" || cell->type == "$mod") {
204 std::vector<int> b = importSigSpec(cell->getPort("\\B"), timestep);
205 undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
206 }
207
208 if (is_arith_compare) {
209 for (size_t i = 1; i < undef_y.size(); i++)
210 ez->SET(ez->FALSE, undef_y.at(i));
211 ez->SET(undef_y_bit, undef_y.at(0));
212 } else {
213 std::vector<int> undef_y_bits(undef_y.size(), undef_y_bit);
214 ez->assume(ez->vec_eq(undef_y_bits, undef_y));
215 }
216
217 arith_undef_handled = true;
218 }
219
220 if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_",
221 "$and", "$or", "$xor", "$xnor", "$add", "$sub"))
222 {
223 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
224 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
225 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
226 extendSignalWidth(a, b, y, cell);
227
228 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
229
230 if (cell->type == "$and" || cell->type == "$_AND_")
231 ez->assume(ez->vec_eq(ez->vec_and(a, b), yy));
232 if (cell->type == "$_NAND_")
233 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy));
234 if (cell->type == "$or" || cell->type == "$_OR_")
235 ez->assume(ez->vec_eq(ez->vec_or(a, b), yy));
236 if (cell->type == "$_NOR_")
237 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy));
238 if (cell->type == "$xor" || cell->type == "$_XOR_")
239 ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy));
240 if (cell->type == "$xnor" || cell->type == "$_XNOR_")
241 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy));
242 if (cell->type == "$add")
243 ez->assume(ez->vec_eq(ez->vec_add(a, b), yy));
244 if (cell->type == "$sub")
245 ez->assume(ez->vec_eq(ez->vec_sub(a, b), yy));
246
247 if (model_undef && !arith_undef_handled)
248 {
249 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
250 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
251 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
252 extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
253
254 if (cell->type.in("$and", "$_AND_", "$_NAND_")) {
255 std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));
256 std::vector<int> b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b));
257 std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0)));
258 ez->assume(ez->vec_eq(yX, undef_y));
259 }
260 else if (cell->type.in("$or", "$_OR_", "$_NOR_")) {
261 std::vector<int> a1 = ez->vec_and(a, ez->vec_not(undef_a));
262 std::vector<int> b1 = ez->vec_and(b, ez->vec_not(undef_b));
263 std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b1)));
264 ez->assume(ez->vec_eq(yX, undef_y));
265 }
266 else if (cell->type.in("$xor", "$xnor", "$_XOR_", "$_XNOR_")) {
267 std::vector<int> yX = ez->vec_or(undef_a, undef_b);
268 ez->assume(ez->vec_eq(yX, undef_y));
269 }
270 else
271 log_abort();
272
273 undefGating(y, yy, undef_y);
274 }
275 else if (model_undef)
276 {
277 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
278 undefGating(y, yy, undef_y);
279 }
280 return true;
281 }
282
283 if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
284 {
285 bool aoi_mode = cell->type.in("$_AOI3_", "$_AOI4_");
286 bool three_mode = cell->type.in("$_AOI3_", "$_OAI3_");
287
288 int a = importDefSigSpec(cell->getPort("\\A"), timestep).at(0);
289 int b = importDefSigSpec(cell->getPort("\\B"), timestep).at(0);
290 int c = importDefSigSpec(cell->getPort("\\C"), timestep).at(0);
291 int d = three_mode ? (aoi_mode ? ez->TRUE : ez->FALSE) : importDefSigSpec(cell->getPort("\\D"), timestep).at(0);
292 int y = importDefSigSpec(cell->getPort("\\Y"), timestep).at(0);
293 int yy = model_undef ? ez->literal() : y;
294
295 if (cell->type.in("$_AOI3_", "$_AOI4_"))
296 ez->assume(ez->IFF(ez->NOT(ez->OR(ez->AND(a, b), ez->AND(c, d))), yy));
297 else
298 ez->assume(ez->IFF(ez->NOT(ez->AND(ez->OR(a, b), ez->OR(c, d))), yy));
299
300 if (model_undef)
301 {
302 int undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep).at(0);
303 int undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep).at(0);
304 int undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep).at(0);
305 int undef_d = three_mode ? ez->FALSE : importUndefSigSpec(cell->getPort("\\D"), timestep).at(0);
306 int undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep).at(0);
307
308 if (aoi_mode)
309 {
310 int a0 = ez->AND(ez->NOT(a), ez->NOT(undef_a));
311 int b0 = ez->AND(ez->NOT(b), ez->NOT(undef_b));
312 int c0 = ez->AND(ez->NOT(c), ez->NOT(undef_c));
313 int d0 = ez->AND(ez->NOT(d), ez->NOT(undef_d));
314
315 int ab = ez->AND(a, b), cd = ez->AND(c, d);
316 int undef_ab = ez->AND(ez->OR(undef_a, undef_b), ez->NOT(ez->OR(a0, b0)));
317 int undef_cd = ez->AND(ez->OR(undef_c, undef_d), ez->NOT(ez->OR(c0, d0)));
318
319 int ab1 = ez->AND(ab, ez->NOT(undef_ab));
320 int cd1 = ez->AND(cd, ez->NOT(undef_cd));
321 int yX = ez->AND(ez->OR(undef_ab, undef_cd), ez->NOT(ez->OR(ab1, cd1)));
322
323 ez->assume(ez->IFF(yX, undef_y));
324 }
325 else
326 {
327 int a1 = ez->AND(a, ez->NOT(undef_a));
328 int b1 = ez->AND(b, ez->NOT(undef_b));
329 int c1 = ez->AND(c, ez->NOT(undef_c));
330 int d1 = ez->AND(d, ez->NOT(undef_d));
331
332 int ab = ez->OR(a, b), cd = ez->OR(c, d);
333 int undef_ab = ez->AND(ez->OR(undef_a, undef_b), ez->NOT(ez->OR(a1, b1)));
334 int undef_cd = ez->AND(ez->OR(undef_c, undef_d), ez->NOT(ez->OR(c1, d1)));
335
336 int ab0 = ez->AND(ez->NOT(ab), ez->NOT(undef_ab));
337 int cd0 = ez->AND(ez->NOT(cd), ez->NOT(undef_cd));
338 int yX = ez->AND(ez->OR(undef_ab, undef_cd), ez->NOT(ez->OR(ab0, cd0)));
339
340 ez->assume(ez->IFF(yX, undef_y));
341 }
342
343 undefGating(y, yy, undef_y);
344 }
345
346 return true;
347 }
348
349 if (cell->type == "$_NOT_" || cell->type == "$not")
350 {
351 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
352 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
353 extendSignalWidthUnary(a, y, cell);
354
355 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
356 ez->assume(ez->vec_eq(ez->vec_not(a), yy));
357
358 if (model_undef) {
359 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
360 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
361 extendSignalWidthUnary(undef_a, undef_y, cell, false);
362 ez->assume(ez->vec_eq(undef_a, undef_y));
363 undefGating(y, yy, undef_y);
364 }
365 return true;
366 }
367
368 if (cell->type == "$_MUX_" || cell->type == "$mux")
369 {
370 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
371 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
372 std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
373 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
374
375 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
376 ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
377
378 if (model_undef)
379 {
380 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
381 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
382 std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
383 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
384
385 std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
386 std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
387 std::vector<int> yX = ez->vec_ite(undef_s.at(0), undef_ab, ez->vec_ite(s.at(0), undef_b, undef_a));
388 ez->assume(ez->vec_eq(yX, undef_y));
389 undefGating(y, yy, undef_y);
390 }
391 return true;
392 }
393
394 if (cell->type == "$pmux")
395 {
396 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
397 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
398 std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
399 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
400
401 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
402
403 std::vector<int> tmp = a;
404 for (size_t i = 0; i < s.size(); i++) {
405 std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
406 tmp = ez->vec_ite(s.at(i), part_of_b, tmp);
407 }
408 ez->assume(ez->vec_eq(tmp, yy));
409
410 if (model_undef)
411 {
412 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
413 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
414 std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
415 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
416
417 int maybe_one_hot = ez->FALSE;
418 int maybe_many_hot = ez->FALSE;
419
420 int sure_one_hot = ez->FALSE;
421 int sure_many_hot = ez->FALSE;
422
423 std::vector<int> bits_set = std::vector<int>(undef_y.size(), ez->FALSE);
424 std::vector<int> bits_clr = std::vector<int>(undef_y.size(), ez->FALSE);
425
426 for (size_t i = 0; i < s.size(); i++)
427 {
428 std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
429 std::vector<int> part_of_undef_b(undef_b.begin()+i*a.size(), undef_b.begin()+(i+1)*a.size());
430
431 int maybe_s = ez->OR(s.at(i), undef_s.at(i));
432 int sure_s = ez->AND(s.at(i), ez->NOT(undef_s.at(i)));
433
434 maybe_one_hot = ez->OR(maybe_one_hot, maybe_s);
435 maybe_many_hot = ez->OR(maybe_many_hot, ez->AND(maybe_one_hot, maybe_s));
436
437 sure_one_hot = ez->OR(sure_one_hot, sure_s);
438 sure_many_hot = ez->OR(sure_many_hot, ez->AND(sure_one_hot, sure_s));
439
440 bits_set = ez->vec_ite(maybe_s, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(part_of_b, part_of_undef_b))), bits_set);
441 bits_clr = ez->vec_ite(maybe_s, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(part_of_b), part_of_undef_b))), bits_clr);
442 }
443
444 int maybe_a = ez->NOT(maybe_one_hot);
445
446 bits_set = ez->vec_ite(maybe_a, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(a, undef_a))), bits_set);
447 bits_clr = ez->vec_ite(maybe_a, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(a), undef_a))), bits_clr);
448
449 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(bits_set, bits_clr)), undef_y));
450 undefGating(y, yy, undef_y);
451 }
452 return true;
453 }
454
455 if (cell->type == "$pos" || cell->type == "$neg")
456 {
457 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
458 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
459 extendSignalWidthUnary(a, y, cell);
460
461 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
462
463 if (cell->type == "$pos") {
464 ez->assume(ez->vec_eq(a, yy));
465 } else {
466 std::vector<int> zero(a.size(), ez->FALSE);
467 ez->assume(ez->vec_eq(ez->vec_sub(zero, a), yy));
468 }
469
470 if (model_undef)
471 {
472 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
473 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
474 extendSignalWidthUnary(undef_a, undef_y, cell);
475
476 if (cell->type == "$pos") {
477 ez->assume(ez->vec_eq(undef_a, undef_y));
478 } else {
479 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
480 std::vector<int> undef_y_bits(undef_y.size(), undef_any_a);
481 ez->assume(ez->vec_eq(undef_y_bits, undef_y));
482 }
483
484 undefGating(y, yy, undef_y);
485 }
486 return true;
487 }
488
489 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
490 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not")
491 {
492 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
493 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
494
495 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
496
497 if (cell->type == "$reduce_and")
498 ez->SET(ez->expression(ez->OpAnd, a), yy.at(0));
499 if (cell->type == "$reduce_or" || cell->type == "$reduce_bool")
500 ez->SET(ez->expression(ez->OpOr, a), yy.at(0));
501 if (cell->type == "$reduce_xor")
502 ez->SET(ez->expression(ez->OpXor, a), yy.at(0));
503 if (cell->type == "$reduce_xnor")
504 ez->SET(ez->NOT(ez->expression(ez->OpXor, a)), yy.at(0));
505 if (cell->type == "$logic_not")
506 ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), yy.at(0));
507 for (size_t i = 1; i < y.size(); i++)
508 ez->SET(ez->FALSE, yy.at(i));
509
510 if (model_undef)
511 {
512 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
513 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
514 int aX = ez->expression(ezSAT::OpOr, undef_a);
515
516 if (cell->type == "$reduce_and") {
517 int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)));
518 ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0)));
519 }
520 else if (cell->type == "$reduce_or" || cell->type == "$reduce_bool" || cell->type == "$logic_not") {
521 int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a)));
522 ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0)));
523 }
524 else if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
525 ez->assume(ez->IFF(aX, undef_y.at(0)));
526 } else
527 log_abort();
528
529 for (size_t i = 1; i < undef_y.size(); i++)
530 ez->SET(ez->FALSE, undef_y.at(i));
531
532 undefGating(y, yy, undef_y);
533 }
534 return true;
535 }
536
537 if (cell->type == "$logic_and" || cell->type == "$logic_or")
538 {
539 std::vector<int> vec_a = importDefSigSpec(cell->getPort("\\A"), timestep);
540 std::vector<int> vec_b = importDefSigSpec(cell->getPort("\\B"), timestep);
541
542 int a = ez->expression(ez->OpOr, vec_a);
543 int b = ez->expression(ez->OpOr, vec_b);
544 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
545
546 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
547
548 if (cell->type == "$logic_and")
549 ez->SET(ez->expression(ez->OpAnd, a, b), yy.at(0));
550 else
551 ez->SET(ez->expression(ez->OpOr, a, b), yy.at(0));
552 for (size_t i = 1; i < y.size(); i++)
553 ez->SET(ez->FALSE, yy.at(i));
554
555 if (model_undef)
556 {
557 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
558 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
559 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
560
561 int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
562 int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
563 int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(vec_a, ez->vec_not(undef_a)));
564 int b1 = ez->expression(ezSAT::OpOr, ez->vec_and(vec_b, ez->vec_not(undef_b)));
565 int aX = ez->expression(ezSAT::OpOr, undef_a);
566 int bX = ez->expression(ezSAT::OpOr, undef_b);
567
568 if (cell->type == "$logic_and")
569 ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a1, b1)), ez->NOT(a0), ez->NOT(b0)), undef_y.at(0));
570 else if (cell->type == "$logic_or")
571 ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a0, b0)), ez->NOT(a1), ez->NOT(b1)), undef_y.at(0));
572 else
573 log_abort();
574
575 for (size_t i = 1; i < undef_y.size(); i++)
576 ez->SET(ez->FALSE, undef_y.at(i));
577
578 undefGating(y, yy, undef_y);
579 }
580 return true;
581 }
582
583 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt")
584 {
585 bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
586 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
587 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
588 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
589 extendSignalWidth(a, b, cell);
590
591 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
592
593 if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
594 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
595 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
596 extendSignalWidth(undef_a, undef_b, cell, true);
597 a = ez->vec_or(a, undef_a);
598 b = ez->vec_or(b, undef_b);
599 }
600
601 if (cell->type == "$lt")
602 ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0));
603 if (cell->type == "$le")
604 ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0));
605 if (cell->type == "$eq" || cell->type == "$eqx")
606 ez->SET(ez->vec_eq(a, b), yy.at(0));
607 if (cell->type == "$ne" || cell->type == "$nex")
608 ez->SET(ez->vec_ne(a, b), yy.at(0));
609 if (cell->type == "$ge")
610 ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0));
611 if (cell->type == "$gt")
612 ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), yy.at(0));
613 for (size_t i = 1; i < y.size(); i++)
614 ez->SET(ez->FALSE, yy.at(i));
615
616 if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
617 {
618 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
619 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
620 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
621 extendSignalWidth(undef_a, undef_b, cell, true);
622
623 if (cell->type == "$eqx")
624 yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b));
625 else
626 yy.at(0) = ez->OR(yy.at(0), ez->vec_ne(undef_a, undef_b));
627
628 for (size_t i = 0; i < y.size(); i++)
629 ez->SET(ez->FALSE, undef_y.at(i));
630
631 ez->assume(ez->vec_eq(y, yy));
632 }
633 else if (model_undef && (cell->type == "$eq" || cell->type == "$ne"))
634 {
635 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
636 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
637 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
638 extendSignalWidth(undef_a, undef_b, cell, true);
639
640 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
641 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
642 int undef_any = ez->OR(undef_any_a, undef_any_b);
643
644 std::vector<int> masked_a_bits = ez->vec_or(a, ez->vec_or(undef_a, undef_b));
645 std::vector<int> masked_b_bits = ez->vec_or(b, ez->vec_or(undef_a, undef_b));
646
647 int masked_ne = ez->vec_ne(masked_a_bits, masked_b_bits);
648 int undef_y_bit = ez->AND(undef_any, ez->NOT(masked_ne));
649
650 for (size_t i = 1; i < undef_y.size(); i++)
651 ez->SET(ez->FALSE, undef_y.at(i));
652 ez->SET(undef_y_bit, undef_y.at(0));
653
654 undefGating(y, yy, undef_y);
655 }
656 else
657 {
658 if (model_undef) {
659 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
660 undefGating(y, yy, undef_y);
661 }
662 log_assert(!model_undef || arith_undef_handled);
663 }
664 return true;
665 }
666
667 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
668 {
669 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
670 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
671 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
672
673 int extend_bit = ez->FALSE;
674
675 if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool())
676 extend_bit = a.back();
677
678 while (y.size() < a.size())
679 y.push_back(ez->literal());
680 while (y.size() > a.size())
681 a.push_back(extend_bit);
682
683 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
684 std::vector<int> shifted_a;
685
686 if (cell->type == "$shl" || cell->type == "$sshl")
687 shifted_a = ez->vec_shift_left(a, b, false, ez->FALSE, ez->FALSE);
688
689 if (cell->type == "$shr")
690 shifted_a = ez->vec_shift_right(a, b, false, ez->FALSE, ez->FALSE);
691
692 if (cell->type == "$sshr")
693 shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE, ez->FALSE);
694
695 if (cell->type == "$shift" || cell->type == "$shiftx")
696 shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
697
698 ez->assume(ez->vec_eq(shifted_a, yy));
699
700 if (model_undef)
701 {
702 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
703 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
704 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
705 std::vector<int> undef_a_shifted;
706
707 extend_bit = cell->type == "$shiftx" ? ez->TRUE : ez->FALSE;
708 if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool())
709 extend_bit = undef_a.back();
710
711 while (undef_y.size() < undef_a.size())
712 undef_y.push_back(ez->literal());
713 while (undef_y.size() > undef_a.size())
714 undef_a.push_back(extend_bit);
715
716 if (cell->type == "$shl" || cell->type == "$sshl")
717 undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->FALSE, ez->FALSE);
718
719 if (cell->type == "$shr")
720 undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->FALSE, ez->FALSE);
721
722 if (cell->type == "$sshr")
723 undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE, ez->FALSE);
724
725 if (cell->type == "$shift")
726 undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
727
728 if (cell->type == "$shiftx")
729 undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->TRUE, ez->TRUE);
730
731 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
732 std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
733 ez->assume(ez->vec_eq(ez->vec_or(undef_a_shifted, undef_all_y_bits), undef_y));
734 undefGating(y, yy, undef_y);
735 }
736 return true;
737 }
738
739 if (cell->type == "$mul")
740 {
741 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
742 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
743 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
744 extendSignalWidth(a, b, y, cell);
745
746 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
747
748 std::vector<int> tmp(a.size(), ez->FALSE);
749 for (int i = 0; i < int(a.size()); i++)
750 {
751 std::vector<int> shifted_a(a.size(), ez->FALSE);
752 for (int j = i; j < int(a.size()); j++)
753 shifted_a.at(j) = a.at(j-i);
754 tmp = ez->vec_ite(b.at(i), ez->vec_add(tmp, shifted_a), tmp);
755 }
756 ez->assume(ez->vec_eq(tmp, yy));
757
758 if (model_undef) {
759 log_assert(arith_undef_handled);
760 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
761 undefGating(y, yy, undef_y);
762 }
763 return true;
764 }
765
766 if (cell->type == "$macc")
767 {
768 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
769 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
770 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
771
772 Macc macc;
773 macc.from_cell(cell);
774
775 std::vector<int> tmp(SIZE(y), ez->FALSE);
776
777 for (auto &port : macc.ports)
778 {
779 std::vector<int> in_a = importDefSigSpec(port.in_a, timestep);
780 std::vector<int> in_b = importDefSigSpec(port.in_b, timestep);
781
782 while (SIZE(in_a) < SIZE(y))
783 in_a.push_back(port.is_signed && !in_a.empty() ? in_a.back() : ez->FALSE);
784 in_a.resize(SIZE(y));
785
786 if (SIZE(in_b))
787 {
788 while (SIZE(in_b) < SIZE(y))
789 in_b.push_back(port.is_signed && !in_b.empty() ? in_b.back() : ez->FALSE);
790 in_b.resize(SIZE(y));
791
792 for (int i = 0; i < SIZE(in_b); i++) {
793 std::vector<int> shifted_a(in_a.size(), ez->FALSE);
794 for (int j = i; j < int(in_a.size()); j++)
795 shifted_a.at(j) = in_a.at(j-i);
796 if (port.do_subtract)
797 tmp = ez->vec_ite(in_b.at(i), ez->vec_sub(tmp, shifted_a), tmp);
798 else
799 tmp = ez->vec_ite(in_b.at(i), ez->vec_add(tmp, shifted_a), tmp);
800 }
801 }
802 else
803 {
804 if (port.do_subtract)
805 tmp = ez->vec_sub(tmp, in_a);
806 else
807 tmp = ez->vec_add(tmp, in_a);
808 }
809 }
810
811 for (int i = 0; i < SIZE(b); i++) {
812 std::vector<int> val(SIZE(y), ez->FALSE);
813 val.at(0) = b.at(i);
814 tmp = ez->vec_add(tmp, val);
815 }
816
817 if (model_undef)
818 {
819 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
820 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
821
822 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
823 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
824
825 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
826 ez->assume(ez->vec_eq(undef_y, std::vector<int>(SIZE(y), ez->OR(undef_any_a, undef_any_b))));
827
828 undefGating(y, tmp, undef_y);
829 }
830 else
831 ez->assume(ez->vec_eq(y, tmp));
832
833 return true;
834 }
835
836 if (cell->type == "$div" || cell->type == "$mod")
837 {
838 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
839 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
840 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
841 extendSignalWidth(a, b, y, cell);
842
843 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
844
845 std::vector<int> a_u, b_u;
846 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) {
847 a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a);
848 b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b);
849 } else {
850 a_u = a;
851 b_u = b;
852 }
853
854 std::vector<int> chain_buf = a_u;
855 std::vector<int> y_u(a_u.size(), ez->FALSE);
856 for (int i = int(a.size())-1; i >= 0; i--)
857 {
858 chain_buf.insert(chain_buf.end(), chain_buf.size(), ez->FALSE);
859
860 std::vector<int> b_shl(i, ez->FALSE);
861 b_shl.insert(b_shl.end(), b_u.begin(), b_u.end());
862 b_shl.insert(b_shl.end(), chain_buf.size()-b_shl.size(), ez->FALSE);
863
864 y_u.at(i) = ez->vec_ge_unsigned(chain_buf, b_shl);
865 chain_buf = ez->vec_ite(y_u.at(i), ez->vec_sub(chain_buf, b_shl), chain_buf);
866
867 chain_buf.erase(chain_buf.begin() + a_u.size(), chain_buf.end());
868 }
869
870 std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
871 if (cell->type == "$div") {
872 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
873 ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
874 else
875 ez->assume(ez->vec_eq(y_tmp, y_u));
876 } else {
877 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
878 ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
879 else
880 ez->assume(ez->vec_eq(y_tmp, chain_buf));
881 }
882
883 if (ignore_div_by_zero) {
884 ez->assume(ez->expression(ezSAT::OpOr, b));
885 } else {
886 std::vector<int> div_zero_result;
887 if (cell->type == "$div") {
888 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) {
889 std::vector<int> all_ones(y.size(), ez->TRUE);
890 std::vector<int> only_first_one(y.size(), ez->FALSE);
891 only_first_one.at(0) = ez->TRUE;
892 div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
893 } else {
894 div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->TRUE);
895 div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
896 }
897 } else {
898 int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
899 div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
900 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
901 div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
902 else
903 div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
904 }
905 ez->assume(ez->vec_eq(yy, ez->vec_ite(ez->expression(ezSAT::OpOr, b), y_tmp, div_zero_result)));
906 }
907
908 if (model_undef) {
909 log_assert(arith_undef_handled);
910 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
911 undefGating(y, yy, undef_y);
912 }
913 return true;
914 }
915
916 if (cell->type == "$lut")
917 {
918 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
919 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
920
921 std::vector<int> lut;
922 for (auto bit : cell->getParam("\\LUT").bits)
923 lut.push_back(bit == RTLIL::S1 ? ez->TRUE : ez->FALSE);
924 while (SIZE(lut) < (1 << SIZE(a)))
925 lut.push_back(ez->FALSE);
926 lut.resize(1 << SIZE(a));
927
928 if (model_undef)
929 {
930 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
931 std::vector<int> t(lut), u(SIZE(t), ez->FALSE);
932
933 for (int i = SIZE(a)-1; i >= 0; i--)
934 {
935 std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
936 std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
937
938 std::vector<int> u0(u.begin(), u.begin() + SIZE(u)/2);
939 std::vector<int> u1(u.begin() + SIZE(u)/2, u.end());
940
941 t = ez->vec_ite(a[i], t1, t0);
942 u = ez->vec_ite(undef_a[i], ez->vec_or(ez->vec_xor(t0, t1), ez->vec_or(u0, u1)), ez->vec_ite(a[i], u1, u0));
943 }
944
945 log_assert(SIZE(t) == 1);
946 log_assert(SIZE(u) == 1);
947 undefGating(y, t, u);
948 ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort("\\Y"), timestep), u));
949 }
950 else
951 {
952 std::vector<int> t = lut;
953 for (int i = SIZE(a)-1; i >= 0; i--)
954 {
955 std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
956 std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
957 t = ez->vec_ite(a[i], t1, t0);
958 }
959
960 log_assert(SIZE(t) == 1);
961 ez->assume(ez->vec_eq(y, t));
962 }
963 return true;
964 }
965
966 if (cell->type == "$fa")
967 {
968 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
969 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
970 std::vector<int> c = importDefSigSpec(cell->getPort("\\C"), timestep);
971 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
972 std::vector<int> x = importDefSigSpec(cell->getPort("\\X"), timestep);
973
974 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
975 std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
976
977 std::vector<int> t1 = ez->vec_xor(a, b);
978 ez->assume(ez->vec_eq(yy, ez->vec_xor(t1, c)));
979
980 std::vector<int> t2 = ez->vec_and(a, b);
981 std::vector<int> t3 = ez->vec_and(c, t1);
982 ez->assume(ez->vec_eq(xx, ez->vec_or(t2, t3)));
983
984 if (model_undef)
985 {
986 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
987 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
988 std::vector<int> undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep);
989
990 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
991 std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
992
993 ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
994
995 std::vector<int> undef_t1 = ez->vec_or(undef_a, undef_b);
996
997 std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));
998 std::vector<int> b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b));
999 std::vector<int> undef_t2 = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0)));
1000
1001 std::vector<int> c0 = ez->vec_and(ez->vec_not(c), ez->vec_not(undef_c));
1002 std::vector<int> t10 = ez->vec_and(ez->vec_not(t1), ez->vec_not(undef_t1));
1003 std::vector<int> undef_t3 = ez->vec_and(ez->vec_or(undef_c, undef_t1), ez->vec_not(ez->vec_or(c0, t10)));
1004
1005 std::vector<int> t21 = ez->vec_and(t2, ez->vec_not(undef_t2));
1006 std::vector<int> t31 = ez->vec_and(t3, ez->vec_not(undef_t3));
1007 ez->assume(ez->vec_eq(undef_x, ez->vec_and(ez->vec_or(undef_t2, undef_t3), ez->vec_not(ez->vec_or(t21, t31)))));
1008
1009 undefGating(y, yy, undef_y);
1010 undefGating(x, xx, undef_x);
1011 }
1012 return true;
1013 }
1014
1015 if (cell->type == "$lcu")
1016 {
1017 std::vector<int> p = importDefSigSpec(cell->getPort("\\P"), timestep);
1018 std::vector<int> g = importDefSigSpec(cell->getPort("\\G"), timestep);
1019 std::vector<int> ci = importDefSigSpec(cell->getPort("\\CI"), timestep);
1020 std::vector<int> co = importDefSigSpec(cell->getPort("\\CO"), timestep);
1021
1022 std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
1023
1024 for (int i = 0; i < SIZE(co); i++)
1025 ez->SET(yy[i], ez->OR(g[i], ez->AND(p[i], i ? yy[i-1] : ci[0])));
1026
1027 if (model_undef)
1028 {
1029 std::vector<int> undef_p = importUndefSigSpec(cell->getPort("\\P"), timestep);
1030 std::vector<int> undef_g = importUndefSigSpec(cell->getPort("\\G"), timestep);
1031 std::vector<int> undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep);
1032 std::vector<int> undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep);
1033
1034 int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
1035 int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
1036 int undef_any_ci = ez->expression(ezSAT::OpOr, undef_ci);
1037 int undef_co_bit = ez->OR(undef_any_p, undef_any_g, undef_any_ci);
1038
1039 std::vector<int> undef_co_bits(undef_co.size(), undef_co_bit);
1040 ez->assume(ez->vec_eq(undef_co_bits, undef_co));
1041
1042 undefGating(co, yy, undef_co);
1043 }
1044 return true;
1045 }
1046
1047 if (cell->type == "$alu")
1048 {
1049 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
1050 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
1051 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
1052 std::vector<int> x = importDefSigSpec(cell->getPort("\\X"), timestep);
1053 std::vector<int> ci = importDefSigSpec(cell->getPort("\\CI"), timestep);
1054 std::vector<int> bi = importDefSigSpec(cell->getPort("\\BI"), timestep);
1055 std::vector<int> co = importDefSigSpec(cell->getPort("\\CO"), timestep);
1056
1057 extendSignalWidth(a, b, y, cell);
1058 extendSignalWidth(a, b, x, cell);
1059 extendSignalWidth(a, b, co, cell);
1060
1061 std::vector<int> def_y = model_undef ? ez->vec_var(y.size()) : y;
1062 std::vector<int> def_x = model_undef ? ez->vec_var(x.size()) : x;
1063 std::vector<int> def_co = model_undef ? ez->vec_var(co.size()) : co;
1064
1065 log_assert(SIZE(y) == SIZE(x));
1066 log_assert(SIZE(y) == SIZE(co));
1067 log_assert(SIZE(ci) == 1);
1068 log_assert(SIZE(bi) == 1);
1069
1070 for (int i = 0; i < SIZE(y); i++)
1071 {
1072 int s1 = a.at(i), s2 = ez->XOR(b.at(i), bi.at(0)), s3 = i ? co.at(i-1) : ci.at(0);
1073 ez->SET(def_x.at(i), ez->XOR(s1, s2));
1074 ez->SET(def_y.at(i), ez->XOR(def_x.at(i), s3));
1075 ez->SET(def_co.at(i), ez->OR(ez->AND(s1, s2), ez->AND(s1, s3), ez->AND(s2, s3)));
1076 }
1077
1078 if (model_undef)
1079 {
1080 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
1081 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
1082 std::vector<int> undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep);
1083 std::vector<int> undef_bi = importUndefSigSpec(cell->getPort("\\BI"), timestep);
1084
1085 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
1086 std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
1087 std::vector<int> undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep);
1088
1089 extendSignalWidth(undef_a, undef_b, undef_y, cell);
1090 extendSignalWidth(undef_a, undef_b, undef_x, cell);
1091 extendSignalWidth(undef_a, undef_b, undef_co, cell);
1092
1093 std::vector<int> all_inputs_undef;
1094 all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end());
1095 all_inputs_undef.insert(all_inputs_undef.end(), undef_b.begin(), undef_b.end());
1096 all_inputs_undef.insert(all_inputs_undef.end(), undef_ci.begin(), undef_ci.end());
1097 all_inputs_undef.insert(all_inputs_undef.end(), undef_bi.begin(), undef_bi.end());
1098 int undef_any = ez->expression(ezSAT::OpOr, all_inputs_undef);
1099
1100 for (int i = 0; i < SIZE(undef_y); i++) {
1101 ez->SET(undef_y.at(i), undef_any);
1102 ez->SET(undef_x.at(i), ez->OR(undef_a.at(i), undef_b.at(i), undef_bi.at(0)));
1103 ez->SET(undef_co.at(i), undef_any);
1104 }
1105
1106 undefGating(y, def_y, undef_y);
1107 undefGating(x, def_x, undef_x);
1108 undefGating(co, def_co, undef_co);
1109 }
1110 return true;
1111 }
1112
1113 if (cell->type == "$slice")
1114 {
1115 RTLIL::SigSpec a = cell->getPort("\\A");
1116 RTLIL::SigSpec y = cell->getPort("\\Y");
1117 ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
1118 return true;
1119 }
1120
1121 if (cell->type == "$concat")
1122 {
1123 RTLIL::SigSpec a = cell->getPort("\\A");
1124 RTLIL::SigSpec b = cell->getPort("\\B");
1125 RTLIL::SigSpec y = cell->getPort("\\Y");
1126
1127 RTLIL::SigSpec ab = a;
1128 ab.append(b);
1129
1130 ez->assume(signals_eq(ab, y, timestep));
1131 return true;
1132 }
1133
1134 if (timestep > 0 && (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_"))
1135 {
1136 if (timestep == 1)
1137 {
1138 initial_state.add((*sigmap)(cell->getPort("\\Q")));
1139 }
1140 else
1141 {
1142 std::vector<int> d = importDefSigSpec(cell->getPort("\\D"), timestep-1);
1143 std::vector<int> q = importDefSigSpec(cell->getPort("\\Q"), timestep);
1144
1145 std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
1146 ez->assume(ez->vec_eq(d, qq));
1147
1148 if (model_undef)
1149 {
1150 std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1);
1151 std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep);
1152
1153 ez->assume(ez->vec_eq(undef_d, undef_q));
1154 undefGating(q, qq, undef_q);
1155 }
1156 }
1157 return true;
1158 }
1159
1160 if (cell->type == "$assert")
1161 {
1162 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
1163 asserts_a[pf].append((*sigmap)(cell->getPort("\\A")));
1164 asserts_en[pf].append((*sigmap)(cell->getPort("\\EN")));
1165 return true;
1166 }
1167
1168 // Unsupported internal cell types: $pow $lut
1169 // .. and all sequential cells except $dff and $_DFF_[NP]_
1170 return false;
1171 }
1172 };
1173
1174 #endif