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Added SAT model for $alu cells
[yosys.git] / kernel / satgen.h
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #ifndef SATGEN_H
21 #define SATGEN_H
22
23 #include "kernel/rtlil.h"
24 #include "kernel/sigtools.h"
25 #include "kernel/celltypes.h"
26
27 #include "libs/ezsat/ezminisat.h"
28 typedef ezMiniSAT ezDefaultSAT;
29
30 struct SatGen
31 {
32 ezSAT *ez;
33 SigMap *sigmap;
34 std::string prefix;
35 SigPool initial_state;
36 std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
37 bool ignore_div_by_zero;
38 bool model_undef;
39
40 SatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :
41 ez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)
42 {
43 }
44
45 void setContext(SigMap *sigmap, std::string prefix = std::string())
46 {
47 this->sigmap = sigmap;
48 this->prefix = prefix;
49 }
50
51 std::vector<int> importSigSpecWorker(RTLIL::SigSpec &sig, std::string &pf, bool undef_mode, bool dup_undef)
52 {
53 log_assert(!undef_mode || model_undef);
54 sigmap->apply(sig);
55
56 std::vector<int> vec;
57 vec.reserve(SIZE(sig));
58
59 for (auto &bit : sig)
60 if (bit.wire == NULL) {
61 if (model_undef && dup_undef && bit == RTLIL::State::Sx)
62 vec.push_back(ez->frozen_literal());
63 else
64 vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE);
65 } else {
66 std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset);
67 vec.push_back(ez->frozen_literal(name));
68 }
69 return vec;
70 }
71
72 std::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)
73 {
74 log_assert(timestep != 0);
75 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
76 return importSigSpecWorker(sig, pf, false, false);
77 }
78
79 std::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)
80 {
81 log_assert(timestep != 0);
82 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
83 return importSigSpecWorker(sig, pf, false, true);
84 }
85
86 std::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)
87 {
88 log_assert(timestep != 0);
89 std::string pf = "undef:" + prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
90 return importSigSpecWorker(sig, pf, true, false);
91 }
92
93 void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)
94 {
95 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
96 sig_a = asserts_a[pf];
97 sig_en = asserts_en[pf];
98 }
99
100 int importAsserts(int timestep = -1)
101 {
102 std::vector<int> check_bits, enable_bits;
103 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
104 if (model_undef) {
105 check_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));
106 enable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));
107 } else {
108 check_bits = importDefSigSpec(asserts_a[pf], timestep);
109 enable_bits = importDefSigSpec(asserts_en[pf], timestep);
110 }
111 return ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));
112 }
113
114 int signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)
115 {
116 if (timestep_rhs < 0)
117 timestep_rhs = timestep_lhs;
118
119 log_assert(lhs.size() == rhs.size());
120
121 std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);
122 std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);
123
124 if (!model_undef)
125 return ez->vec_eq(vec_lhs, vec_rhs);
126
127 std::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);
128 std::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);
129
130 std::vector<int> eq_bits;
131 for (int i = 0; i < lhs.size(); i++)
132 eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),
133 ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));
134 return ez->expression(ezSAT::OpAnd, eq_bits);
135 }
136
137 void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
138 {
139 bool is_signed = forced_signed;
140 if (!forced_signed && cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0)
141 is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
142 while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
143 vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
144 while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
145 vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->FALSE);
146 }
147
148 void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
149 {
150 extendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);
151 while (vec_y.size() < vec_a.size())
152 vec_y.push_back(ez->literal());
153 }
154
155 void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
156 {
157 bool is_signed = forced_signed || (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool());
158 while (vec_a.size() < vec_y.size())
159 vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
160 while (vec_y.size() < vec_a.size())
161 vec_y.push_back(ez->literal());
162 }
163
164 void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)
165 {
166 log_assert(model_undef);
167 log_assert(vec_y.size() == vec_yy.size());
168 if (vec_y.size() > vec_undef.size()) {
169 std::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());
170 std::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());
171 ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));
172 } else {
173 log_assert(vec_y.size() == vec_undef.size());
174 ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));
175 }
176 }
177
178 void undefGating(int y, int yy, int undef)
179 {
180 ez->assume(ez->OR(undef, ez->IFF(y, yy)));
181 }
182
183 bool importCell(RTLIL::Cell *cell, int timestep = -1)
184 {
185 bool arith_undef_handled = false;
186 bool is_arith_compare = cell->type.in("$lt", "$le", "$ge", "$gt");
187
188 if (model_undef && (cell->type.in("$add", "$sub", "$mul", "$div", "$mod") || is_arith_compare))
189 {
190 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
191 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
192 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
193 if (is_arith_compare)
194 extendSignalWidth(undef_a, undef_b, cell, true);
195 else
196 extendSignalWidth(undef_a, undef_b, undef_y, cell, true);
197
198 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
199 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
200 int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
201
202 if (cell->type == "$div" || cell->type == "$mod") {
203 std::vector<int> b = importSigSpec(cell->getPort("\\B"), timestep);
204 undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
205 }
206
207 if (is_arith_compare) {
208 for (size_t i = 1; i < undef_y.size(); i++)
209 ez->SET(ez->FALSE, undef_y.at(i));
210 ez->SET(undef_y_bit, undef_y.at(0));
211 } else {
212 std::vector<int> undef_y_bits(undef_y.size(), undef_y_bit);
213 ez->assume(ez->vec_eq(undef_y_bits, undef_y));
214 }
215
216 arith_undef_handled = true;
217 }
218
219 if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_",
220 "$and", "$or", "$xor", "$xnor", "$add", "$sub"))
221 {
222 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
223 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
224 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
225 extendSignalWidth(a, b, y, cell);
226
227 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
228
229 if (cell->type == "$and" || cell->type == "$_AND_")
230 ez->assume(ez->vec_eq(ez->vec_and(a, b), yy));
231 if (cell->type == "$_NAND_")
232 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy));
233 if (cell->type == "$or" || cell->type == "$_OR_")
234 ez->assume(ez->vec_eq(ez->vec_or(a, b), yy));
235 if (cell->type == "$_NOR_")
236 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy));
237 if (cell->type == "$xor" || cell->type == "$_XOR_")
238 ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy));
239 if (cell->type == "$xnor" || cell->type == "$_XNOR_")
240 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy));
241 if (cell->type == "$add")
242 ez->assume(ez->vec_eq(ez->vec_add(a, b), yy));
243 if (cell->type == "$sub")
244 ez->assume(ez->vec_eq(ez->vec_sub(a, b), yy));
245
246 if (model_undef && !arith_undef_handled)
247 {
248 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
249 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
250 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
251 extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
252
253 if (cell->type.in("$and", "$_AND_", "$_NAND_")) {
254 std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));
255 std::vector<int> b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b));
256 std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0)));
257 ez->assume(ez->vec_eq(yX, undef_y));
258 }
259 else if (cell->type.in("$or", "$_OR_", "$_NOR_")) {
260 std::vector<int> a1 = ez->vec_and(a, ez->vec_not(undef_a));
261 std::vector<int> b1 = ez->vec_and(b, ez->vec_not(undef_b));
262 std::vector<int> yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b1)));
263 ez->assume(ez->vec_eq(yX, undef_y));
264 }
265 else if (cell->type.in("$xor", "$xnor", "$_XOR_", "$_XNOR_")) {
266 std::vector<int> yX = ez->vec_or(undef_a, undef_b);
267 ez->assume(ez->vec_eq(yX, undef_y));
268 }
269 else
270 log_abort();
271
272 undefGating(y, yy, undef_y);
273 }
274 else if (model_undef)
275 {
276 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
277 undefGating(y, yy, undef_y);
278 }
279 return true;
280 }
281
282 if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
283 {
284 bool aoi_mode = cell->type.in("$_AOI3_", "$_AOI4_");
285 bool three_mode = cell->type.in("$_AOI3_", "$_OAI3_");
286
287 int a = importDefSigSpec(cell->getPort("\\A"), timestep).at(0);
288 int b = importDefSigSpec(cell->getPort("\\B"), timestep).at(0);
289 int c = importDefSigSpec(cell->getPort("\\C"), timestep).at(0);
290 int d = three_mode ? (aoi_mode ? ez->TRUE : ez->FALSE) : importDefSigSpec(cell->getPort("\\D"), timestep).at(0);
291 int y = importDefSigSpec(cell->getPort("\\Y"), timestep).at(0);
292 int yy = model_undef ? ez->literal() : y;
293
294 if (cell->type.in("$_AOI3_", "$_AOI4_"))
295 ez->assume(ez->IFF(ez->NOT(ez->OR(ez->AND(a, b), ez->AND(c, d))), yy));
296 else
297 ez->assume(ez->IFF(ez->NOT(ez->AND(ez->OR(a, b), ez->OR(c, d))), yy));
298
299 if (model_undef)
300 {
301 int undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep).at(0);
302 int undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep).at(0);
303 int undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep).at(0);
304 int undef_d = three_mode ? ez->FALSE : importUndefSigSpec(cell->getPort("\\D"), timestep).at(0);
305 int undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep).at(0);
306
307 if (aoi_mode)
308 {
309 int a0 = ez->AND(ez->NOT(a), ez->NOT(undef_a));
310 int b0 = ez->AND(ez->NOT(b), ez->NOT(undef_b));
311 int c0 = ez->AND(ez->NOT(c), ez->NOT(undef_c));
312 int d0 = ez->AND(ez->NOT(d), ez->NOT(undef_d));
313
314 int ab = ez->AND(a, b), cd = ez->AND(c, d);
315 int undef_ab = ez->AND(ez->OR(undef_a, undef_b), ez->NOT(ez->OR(a0, b0)));
316 int undef_cd = ez->AND(ez->OR(undef_c, undef_d), ez->NOT(ez->OR(c0, d0)));
317
318 int ab1 = ez->AND(ab, ez->NOT(undef_ab));
319 int cd1 = ez->AND(cd, ez->NOT(undef_cd));
320 int yX = ez->AND(ez->OR(undef_ab, undef_cd), ez->NOT(ez->OR(ab1, cd1)));
321
322 ez->assume(ez->IFF(yX, undef_y));
323 }
324 else
325 {
326 int a1 = ez->AND(a, ez->NOT(undef_a));
327 int b1 = ez->AND(b, ez->NOT(undef_b));
328 int c1 = ez->AND(c, ez->NOT(undef_c));
329 int d1 = ez->AND(d, ez->NOT(undef_d));
330
331 int ab = ez->OR(a, b), cd = ez->OR(c, d);
332 int undef_ab = ez->AND(ez->OR(undef_a, undef_b), ez->NOT(ez->OR(a1, b1)));
333 int undef_cd = ez->AND(ez->OR(undef_c, undef_d), ez->NOT(ez->OR(c1, d1)));
334
335 int ab0 = ez->AND(ez->NOT(ab), ez->NOT(undef_ab));
336 int cd0 = ez->AND(ez->NOT(cd), ez->NOT(undef_cd));
337 int yX = ez->AND(ez->OR(undef_ab, undef_cd), ez->NOT(ez->OR(ab0, cd0)));
338
339 ez->assume(ez->IFF(yX, undef_y));
340 }
341
342 undefGating(y, yy, undef_y);
343 }
344
345 return true;
346 }
347
348 if (cell->type == "$_NOT_" || cell->type == "$not")
349 {
350 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
351 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
352 extendSignalWidthUnary(a, y, cell);
353
354 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
355 ez->assume(ez->vec_eq(ez->vec_not(a), yy));
356
357 if (model_undef) {
358 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
359 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
360 extendSignalWidthUnary(undef_a, undef_y, cell, true);
361 ez->assume(ez->vec_eq(undef_a, undef_y));
362 undefGating(y, yy, undef_y);
363 }
364 return true;
365 }
366
367 if (cell->type == "$_MUX_" || cell->type == "$mux")
368 {
369 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
370 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
371 std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
372 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
373
374 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
375 ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
376
377 if (model_undef)
378 {
379 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
380 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
381 std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
382 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
383
384 std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
385 std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
386 std::vector<int> yX = ez->vec_ite(undef_s.at(0), undef_ab, ez->vec_ite(s.at(0), undef_b, undef_a));
387 ez->assume(ez->vec_eq(yX, undef_y));
388 undefGating(y, yy, undef_y);
389 }
390 return true;
391 }
392
393 if (cell->type == "$pmux")
394 {
395 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
396 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
397 std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
398 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
399
400 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
401
402 std::vector<int> tmp = a;
403 for (size_t i = 0; i < s.size(); i++) {
404 std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
405 tmp = ez->vec_ite(s.at(i), part_of_b, tmp);
406 }
407 ez->assume(ez->vec_eq(tmp, yy));
408
409 if (model_undef)
410 {
411 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
412 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
413 std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
414 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
415
416 int maybe_one_hot = ez->FALSE;
417 int maybe_many_hot = ez->FALSE;
418
419 int sure_one_hot = ez->FALSE;
420 int sure_many_hot = ez->FALSE;
421
422 std::vector<int> bits_set = std::vector<int>(undef_y.size(), ez->FALSE);
423 std::vector<int> bits_clr = std::vector<int>(undef_y.size(), ez->FALSE);
424
425 for (size_t i = 0; i < s.size(); i++)
426 {
427 std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
428 std::vector<int> part_of_undef_b(undef_b.begin()+i*a.size(), undef_b.begin()+(i+1)*a.size());
429
430 int maybe_s = ez->OR(s.at(i), undef_s.at(i));
431 int sure_s = ez->AND(s.at(i), ez->NOT(undef_s.at(i)));
432
433 maybe_one_hot = ez->OR(maybe_one_hot, maybe_s);
434 maybe_many_hot = ez->OR(maybe_many_hot, ez->AND(maybe_one_hot, maybe_s));
435
436 sure_one_hot = ez->OR(sure_one_hot, sure_s);
437 sure_many_hot = ez->OR(sure_many_hot, ez->AND(sure_one_hot, sure_s));
438
439 bits_set = ez->vec_ite(maybe_s, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(part_of_b, part_of_undef_b))), bits_set);
440 bits_clr = ez->vec_ite(maybe_s, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(part_of_b), part_of_undef_b))), bits_clr);
441 }
442
443 int maybe_a = ez->NOT(maybe_one_hot);
444
445 bits_set = ez->vec_ite(maybe_a, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(a, undef_a))), bits_set);
446 bits_clr = ez->vec_ite(maybe_a, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(a), undef_a))), bits_clr);
447
448 ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(bits_set, bits_clr)), undef_y));
449 undefGating(y, yy, undef_y);
450 }
451 return true;
452 }
453
454 if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
455 {
456 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
457 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
458 extendSignalWidthUnary(a, y, cell);
459
460 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
461
462 if (cell->type == "$pos" || cell->type == "$bu0") {
463 ez->assume(ez->vec_eq(a, yy));
464 } else {
465 std::vector<int> zero(a.size(), ez->FALSE);
466 ez->assume(ez->vec_eq(ez->vec_sub(zero, a), yy));
467 }
468
469 if (model_undef)
470 {
471 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
472 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
473 extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
474
475 if (cell->type == "$pos" || cell->type == "$bu0") {
476 ez->assume(ez->vec_eq(undef_a, undef_y));
477 } else {
478 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
479 std::vector<int> undef_y_bits(undef_y.size(), undef_any_a);
480 ez->assume(ez->vec_eq(undef_y_bits, undef_y));
481 }
482
483 undefGating(y, yy, undef_y);
484 }
485 return true;
486 }
487
488 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
489 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not")
490 {
491 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
492 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
493
494 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
495
496 if (cell->type == "$reduce_and")
497 ez->SET(ez->expression(ez->OpAnd, a), yy.at(0));
498 if (cell->type == "$reduce_or" || cell->type == "$reduce_bool")
499 ez->SET(ez->expression(ez->OpOr, a), yy.at(0));
500 if (cell->type == "$reduce_xor")
501 ez->SET(ez->expression(ez->OpXor, a), yy.at(0));
502 if (cell->type == "$reduce_xnor")
503 ez->SET(ez->NOT(ez->expression(ez->OpXor, a)), yy.at(0));
504 if (cell->type == "$logic_not")
505 ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), yy.at(0));
506 for (size_t i = 1; i < y.size(); i++)
507 ez->SET(ez->FALSE, yy.at(i));
508
509 if (model_undef)
510 {
511 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
512 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
513 int aX = ez->expression(ezSAT::OpOr, undef_a);
514
515 if (cell->type == "$reduce_and") {
516 int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)));
517 ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0)));
518 }
519 else if (cell->type == "$reduce_or" || cell->type == "$reduce_bool" || cell->type == "$logic_not") {
520 int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a)));
521 ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0)));
522 }
523 else if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
524 ez->assume(ez->IFF(aX, undef_y.at(0)));
525 } else
526 log_abort();
527
528 for (size_t i = 1; i < undef_y.size(); i++)
529 ez->SET(ez->FALSE, undef_y.at(i));
530
531 undefGating(y, yy, undef_y);
532 }
533 return true;
534 }
535
536 if (cell->type == "$logic_and" || cell->type == "$logic_or")
537 {
538 std::vector<int> vec_a = importDefSigSpec(cell->getPort("\\A"), timestep);
539 std::vector<int> vec_b = importDefSigSpec(cell->getPort("\\B"), timestep);
540
541 int a = ez->expression(ez->OpOr, vec_a);
542 int b = ez->expression(ez->OpOr, vec_b);
543 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
544
545 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
546
547 if (cell->type == "$logic_and")
548 ez->SET(ez->expression(ez->OpAnd, a, b), yy.at(0));
549 else
550 ez->SET(ez->expression(ez->OpOr, a, b), yy.at(0));
551 for (size_t i = 1; i < y.size(); i++)
552 ez->SET(ez->FALSE, yy.at(i));
553
554 if (model_undef)
555 {
556 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
557 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
558 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
559
560 int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
561 int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
562 int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(vec_a, ez->vec_not(undef_a)));
563 int b1 = ez->expression(ezSAT::OpOr, ez->vec_and(vec_b, ez->vec_not(undef_b)));
564 int aX = ez->expression(ezSAT::OpOr, undef_a);
565 int bX = ez->expression(ezSAT::OpOr, undef_b);
566
567 if (cell->type == "$logic_and")
568 ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a1, b1)), ez->NOT(a0), ez->NOT(b0)), undef_y.at(0));
569 else if (cell->type == "$logic_or")
570 ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a0, b0)), ez->NOT(a1), ez->NOT(b1)), undef_y.at(0));
571 else
572 log_abort();
573
574 for (size_t i = 1; i < undef_y.size(); i++)
575 ez->SET(ez->FALSE, undef_y.at(i));
576
577 undefGating(y, yy, undef_y);
578 }
579 return true;
580 }
581
582 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt")
583 {
584 bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
585 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
586 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
587 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
588 extendSignalWidth(a, b, cell);
589
590 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
591
592 if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
593 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
594 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
595 extendSignalWidth(undef_a, undef_b, cell, true);
596 a = ez->vec_or(a, undef_a);
597 b = ez->vec_or(b, undef_b);
598 }
599
600 if (cell->type == "$lt")
601 ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0));
602 if (cell->type == "$le")
603 ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0));
604 if (cell->type == "$eq" || cell->type == "$eqx")
605 ez->SET(ez->vec_eq(a, b), yy.at(0));
606 if (cell->type == "$ne" || cell->type == "$nex")
607 ez->SET(ez->vec_ne(a, b), yy.at(0));
608 if (cell->type == "$ge")
609 ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0));
610 if (cell->type == "$gt")
611 ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), yy.at(0));
612 for (size_t i = 1; i < y.size(); i++)
613 ez->SET(ez->FALSE, yy.at(i));
614
615 if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
616 {
617 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
618 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
619 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
620 extendSignalWidth(undef_a, undef_b, cell, true);
621
622 if (cell->type == "$eqx")
623 yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b));
624 else
625 yy.at(0) = ez->OR(yy.at(0), ez->vec_ne(undef_a, undef_b));
626
627 for (size_t i = 0; i < y.size(); i++)
628 ez->SET(ez->FALSE, undef_y.at(i));
629
630 ez->assume(ez->vec_eq(y, yy));
631 }
632 else if (model_undef && (cell->type == "$eq" || cell->type == "$ne"))
633 {
634 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
635 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
636 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
637 extendSignalWidth(undef_a, undef_b, cell, true);
638
639 int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
640 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
641 int undef_any = ez->OR(undef_any_a, undef_any_b);
642
643 std::vector<int> masked_a_bits = ez->vec_or(a, ez->vec_or(undef_a, undef_b));
644 std::vector<int> masked_b_bits = ez->vec_or(b, ez->vec_or(undef_a, undef_b));
645
646 int masked_ne = ez->vec_ne(masked_a_bits, masked_b_bits);
647 int undef_y_bit = ez->AND(undef_any, ez->NOT(masked_ne));
648
649 for (size_t i = 1; i < undef_y.size(); i++)
650 ez->SET(ez->FALSE, undef_y.at(i));
651 ez->SET(undef_y_bit, undef_y.at(0));
652
653 undefGating(y, yy, undef_y);
654 }
655 else
656 {
657 if (model_undef) {
658 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
659 undefGating(y, yy, undef_y);
660 }
661 log_assert(!model_undef || arith_undef_handled);
662 }
663 return true;
664 }
665
666 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
667 {
668 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
669 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
670 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
671
672 int extend_bit = ez->FALSE;
673
674 if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
675 extend_bit = a.back();
676
677 while (y.size() < a.size())
678 y.push_back(ez->literal());
679 while (y.size() > a.size())
680 a.push_back(extend_bit);
681
682 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
683 std::vector<int> shifted_a;
684
685 if (cell->type == "$shl" || cell->type == "$sshl")
686 shifted_a = ez->vec_shift_left(a, b, false, ez->FALSE, ez->FALSE);
687
688 if (cell->type == "$shr")
689 shifted_a = ez->vec_shift_right(a, b, false, ez->FALSE, ez->FALSE);
690
691 if (cell->type == "$sshr")
692 shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE, ez->FALSE);
693
694 if (cell->type == "$shift" || cell->type == "$shiftx")
695 shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
696
697 ez->assume(ez->vec_eq(shifted_a, yy));
698
699 if (model_undef)
700 {
701 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
702 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
703 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
704 std::vector<int> undef_a_shifted;
705
706 if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
707 extend_bit = undef_a.back();
708
709 while (undef_y.size() < undef_a.size())
710 undef_y.push_back(ez->literal());
711 while (undef_y.size() > undef_a.size())
712 undef_a.push_back(extend_bit);
713
714 if (cell->type == "$shl" || cell->type == "$sshl")
715 undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->FALSE, ez->FALSE);
716
717 if (cell->type == "$shr")
718 undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->FALSE, ez->FALSE);
719
720 if (cell->type == "$sshr")
721 undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE, ez->FALSE);
722
723 if (cell->type == "$shift")
724 undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
725
726 if (cell->type == "$shiftx")
727 undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->TRUE, ez->TRUE);
728
729 int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
730 std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
731 ez->assume(ez->vec_eq(ez->vec_or(undef_a_shifted, undef_all_y_bits), undef_y));
732 undefGating(y, yy, undef_y);
733 }
734 return true;
735 }
736
737 if (cell->type == "$mul")
738 {
739 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
740 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
741 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
742 extendSignalWidth(a, b, y, cell);
743
744 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
745
746 std::vector<int> tmp(a.size(), ez->FALSE);
747 for (int i = 0; i < int(a.size()); i++)
748 {
749 std::vector<int> shifted_a(a.size(), ez->FALSE);
750 for (int j = i; j < int(a.size()); j++)
751 shifted_a.at(j) = a.at(j-i);
752 tmp = ez->vec_ite(b.at(i), ez->vec_add(tmp, shifted_a), tmp);
753 }
754 ez->assume(ez->vec_eq(tmp, yy));
755
756 if (model_undef) {
757 log_assert(arith_undef_handled);
758 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
759 undefGating(y, yy, undef_y);
760 }
761 return true;
762 }
763
764 if (cell->type == "$div" || cell->type == "$mod")
765 {
766 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
767 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
768 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
769 extendSignalWidth(a, b, y, cell);
770
771 std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
772
773 std::vector<int> a_u, b_u;
774 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) {
775 a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a);
776 b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b);
777 } else {
778 a_u = a;
779 b_u = b;
780 }
781
782 std::vector<int> chain_buf = a_u;
783 std::vector<int> y_u(a_u.size(), ez->FALSE);
784 for (int i = int(a.size())-1; i >= 0; i--)
785 {
786 chain_buf.insert(chain_buf.end(), chain_buf.size(), ez->FALSE);
787
788 std::vector<int> b_shl(i, ez->FALSE);
789 b_shl.insert(b_shl.end(), b_u.begin(), b_u.end());
790 b_shl.insert(b_shl.end(), chain_buf.size()-b_shl.size(), ez->FALSE);
791
792 y_u.at(i) = ez->vec_ge_unsigned(chain_buf, b_shl);
793 chain_buf = ez->vec_ite(y_u.at(i), ez->vec_sub(chain_buf, b_shl), chain_buf);
794
795 chain_buf.erase(chain_buf.begin() + a_u.size(), chain_buf.end());
796 }
797
798 std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
799 if (cell->type == "$div") {
800 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
801 ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
802 else
803 ez->assume(ez->vec_eq(y_tmp, y_u));
804 } else {
805 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
806 ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
807 else
808 ez->assume(ez->vec_eq(y_tmp, chain_buf));
809 }
810
811 if (ignore_div_by_zero) {
812 ez->assume(ez->expression(ezSAT::OpOr, b));
813 } else {
814 std::vector<int> div_zero_result;
815 if (cell->type == "$div") {
816 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) {
817 std::vector<int> all_ones(y.size(), ez->TRUE);
818 std::vector<int> only_first_one(y.size(), ez->FALSE);
819 only_first_one.at(0) = ez->TRUE;
820 div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
821 } else {
822 div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->TRUE);
823 div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
824 }
825 } else {
826 int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
827 div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
828 if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
829 div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
830 else
831 div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
832 }
833 ez->assume(ez->vec_eq(yy, ez->vec_ite(ez->expression(ezSAT::OpOr, b), y_tmp, div_zero_result)));
834 }
835
836 if (model_undef) {
837 log_assert(arith_undef_handled);
838 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
839 undefGating(y, yy, undef_y);
840 }
841 return true;
842 }
843
844 if (cell->type == "$lut")
845 {
846 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
847 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
848
849 std::vector<int> lut;
850 for (auto bit : cell->getParam("\\LUT").bits)
851 lut.push_back(bit == RTLIL::S1 ? ez->TRUE : ez->FALSE);
852 while (SIZE(lut) < (1 << SIZE(a)))
853 lut.push_back(ez->FALSE);
854 lut.resize(1 << SIZE(a));
855
856 if (model_undef)
857 {
858 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
859 std::vector<int> t(lut), u(SIZE(t), ez->FALSE);
860
861 for (int i = SIZE(a)-1; i >= 0; i--)
862 {
863 std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
864 std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
865
866 std::vector<int> u0(u.begin(), u.begin() + SIZE(u)/2);
867 std::vector<int> u1(u.begin() + SIZE(u)/2, u.end());
868
869 t = ez->vec_ite(a[i], t1, t0);
870 u = ez->vec_ite(undef_a[i], ez->vec_or(ez->vec_xor(t0, t1), ez->vec_or(u0, u1)), ez->vec_ite(a[i], u1, u0));
871 }
872
873 log_assert(SIZE(t) == 1);
874 log_assert(SIZE(u) == 1);
875 undefGating(y, t, u);
876 ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort("\\Y"), timestep), u));
877 }
878 else
879 {
880 std::vector<int> t = lut;
881 for (int i = SIZE(a)-1; i >= 0; i--)
882 {
883 std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
884 std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
885 t = ez->vec_ite(a[i], t1, t0);
886 }
887
888 log_assert(SIZE(t) == 1);
889 ez->assume(ez->vec_eq(y, t));
890 }
891 return true;
892 }
893
894 if (cell->type == "$alu")
895 {
896 std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
897 std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
898 std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
899 std::vector<int> x = importDefSigSpec(cell->getPort("\\X"), timestep);
900 std::vector<int> ci = importDefSigSpec(cell->getPort("\\CI"), timestep);
901 std::vector<int> bi = importDefSigSpec(cell->getPort("\\BI"), timestep);
902 std::vector<int> co = importDefSigSpec(cell->getPort("\\CO"), timestep);
903
904 extendSignalWidth(a, b, y, cell);
905 extendSignalWidth(a, b, x, cell);
906 extendSignalWidth(a, b, co, cell);
907
908 std::vector<int> def_y = model_undef ? ez->vec_var(y.size()) : y;
909 std::vector<int> def_x = model_undef ? ez->vec_var(x.size()) : x;
910 std::vector<int> def_co = model_undef ? ez->vec_var(co.size()) : co;
911
912 log_assert(SIZE(y) == SIZE(x));
913 log_assert(SIZE(y) == SIZE(co));
914 log_assert(SIZE(ci) == 1);
915 log_assert(SIZE(bi) == 1);
916
917 for (int i = 0; i < SIZE(y); i++)
918 {
919 int s1 = a.at(i), s2 = ez->XOR(b.at(i), bi.at(0)), s3 = i ? co.at(i-1) : ci.at(0);
920 ez->SET(def_x.at(i), ez->XOR(s1, s2));
921 ez->SET(def_y.at(i), ez->XOR(def_x.at(i), s3));
922 ez->SET(def_co.at(i), ez->OR(ez->AND(s1, s2), ez->AND(s1, s3), ez->AND(s2, s3)));
923 }
924
925 if (model_undef)
926 {
927 std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
928 std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
929 std::vector<int> undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep);
930 std::vector<int> undef_bi = importUndefSigSpec(cell->getPort("\\BI"), timestep);
931
932 std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
933 std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
934 std::vector<int> undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep);
935
936 extendSignalWidth(undef_a, undef_b, undef_y, cell, true);
937 extendSignalWidth(undef_a, undef_b, undef_x, cell, true);
938 extendSignalWidth(undef_a, undef_b, undef_co, cell, true);
939
940 std::vector<int> all_inputs_undef;
941 all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end());
942 all_inputs_undef.insert(all_inputs_undef.end(), undef_b.begin(), undef_b.end());
943 all_inputs_undef.insert(all_inputs_undef.end(), undef_ci.begin(), undef_ci.end());
944 all_inputs_undef.insert(all_inputs_undef.end(), undef_bi.begin(), undef_bi.end());
945 int undef_any = ez->expression(ezSAT::OpOr, all_inputs_undef);
946
947 for (int i = 0; i < SIZE(undef_y); i++) {
948 ez->SET(undef_y.at(i), undef_any);
949 ez->SET(undef_x.at(i), ez->OR(undef_a.at(i), undef_b.at(i), undef_bi.at(0)));
950 ez->SET(undef_co.at(i), undef_any);
951 }
952
953 undefGating(y, def_y, undef_y);
954 undefGating(x, def_x, undef_x);
955 undefGating(co, def_co, undef_co);
956 }
957 log_ping();
958 return true;
959 }
960
961 if (cell->type == "$slice")
962 {
963 RTLIL::SigSpec a = cell->getPort("\\A");
964 RTLIL::SigSpec y = cell->getPort("\\Y");
965 ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
966 return true;
967 }
968
969 if (cell->type == "$concat")
970 {
971 RTLIL::SigSpec a = cell->getPort("\\A");
972 RTLIL::SigSpec b = cell->getPort("\\B");
973 RTLIL::SigSpec y = cell->getPort("\\Y");
974
975 RTLIL::SigSpec ab = a;
976 ab.append(b);
977
978 ez->assume(signals_eq(ab, y, timestep));
979 return true;
980 }
981
982 if (timestep > 0 && (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_"))
983 {
984 if (timestep == 1)
985 {
986 initial_state.add((*sigmap)(cell->getPort("\\Q")));
987 }
988 else
989 {
990 std::vector<int> d = importDefSigSpec(cell->getPort("\\D"), timestep-1);
991 std::vector<int> q = importDefSigSpec(cell->getPort("\\Q"), timestep);
992
993 std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
994 ez->assume(ez->vec_eq(d, qq));
995
996 if (model_undef)
997 {
998 std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1);
999 std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep);
1000
1001 ez->assume(ez->vec_eq(undef_d, undef_q));
1002 undefGating(q, qq, undef_q);
1003 }
1004 }
1005 return true;
1006 }
1007
1008 if (cell->type == "$assert")
1009 {
1010 std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
1011 asserts_a[pf].append((*sigmap)(cell->getPort("\\A")));
1012 asserts_en[pf].append((*sigmap)(cell->getPort("\\EN")));
1013 return true;
1014 }
1015
1016 // Unsupported internal cell types: $pow $lut
1017 // .. and all sequential cells except $dff and $_DFF_[NP]_
1018 return false;
1019 }
1020 };
1021
1022 #endif