2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "kernel/yosys.h"
29 struct bitDef_t
: public std::pair
<RTLIL::Wire
*, int> {
30 bitDef_t() : std::pair
<RTLIL::Wire
*, int>(NULL
, 0) { }
31 bitDef_t(const RTLIL::SigBit
&bit
) : std::pair
<RTLIL::Wire
*, int>(bit
.wire
, bit
.offset
) { }
32 unsigned int hash() const { return first
->name
.hash() + second
; }
42 void add(RTLIL::SigSpec sig
)
49 void add(const SigPool
&other
)
51 for (auto &bit
: other
.bits
)
55 void del(RTLIL::SigSpec sig
)
62 void del(const SigPool
&other
)
64 for (auto &bit
: other
.bits
)
68 void expand(RTLIL::SigSpec from
, RTLIL::SigSpec to
)
70 log_assert(GetSize(from
) == GetSize(to
));
71 for (int i
= 0; i
< GetSize(from
); i
++) {
72 bitDef_t
bit_from(from
[i
]), bit_to(to
[i
]);
73 if (bit_from
.first
!= NULL
&& bit_to
.first
!= NULL
&& bits
.count(bit_from
) > 0)
78 RTLIL::SigSpec
extract(RTLIL::SigSpec sig
)
80 RTLIL::SigSpec result
;
82 if (bit
.wire
!= NULL
&& bits
.count(bit
))
83 result
.append_bit(bit
);
87 RTLIL::SigSpec
remove(RTLIL::SigSpec sig
)
89 RTLIL::SigSpec result
;
91 if (bit
.wire
!= NULL
&& bits
.count(bit
) == 0)
96 bool check(RTLIL::SigBit bit
)
98 return bit
.wire
!= NULL
&& bits
.count(bit
);
101 bool check_any(RTLIL::SigSpec sig
)
103 for (auto &bit
: sig
)
104 if (bit
.wire
!= NULL
&& bits
.count(bit
))
109 bool check_all(RTLIL::SigSpec sig
)
111 for (auto &bit
: sig
)
112 if (bit
.wire
!= NULL
&& bits
.count(bit
) == 0)
117 RTLIL::SigSpec
export_one()
119 for (auto &bit
: bits
)
120 return RTLIL::SigSpec(bit
.first
, bit
.second
);
121 return RTLIL::SigSpec();
124 RTLIL::SigSpec
export_all()
126 pool
<RTLIL::SigBit
> sig
;
127 for (auto &bit
: bits
)
128 sig
.insert(RTLIL::SigBit(bit
.first
, bit
.second
));
138 template <typename T
, class Compare
= std::less
<T
>>
141 struct bitDef_t
: public std::pair
<RTLIL::Wire
*, int> {
142 bitDef_t() : std::pair
<RTLIL::Wire
*, int>(NULL
, 0) { }
143 bitDef_t(const RTLIL::SigBit
&bit
) : std::pair
<RTLIL::Wire
*, int>(bit
.wire
, bit
.offset
) { }
144 unsigned int hash() const { return first
->name
.hash() + second
; }
147 dict
<bitDef_t
, std::set
<T
, Compare
>> bits
;
154 void insert(RTLIL::SigSpec sig
, T data
)
156 for (auto &bit
: sig
)
157 if (bit
.wire
!= NULL
)
158 bits
[bit
].insert(data
);
161 void insert(RTLIL::SigSpec sig
, const std::set
<T
> &data
)
163 for (auto &bit
: sig
)
164 if (bit
.wire
!= NULL
)
165 bits
[bit
].insert(data
.begin(), data
.end());
168 void erase(RTLIL::SigSpec sig
)
170 for (auto &bit
: sig
)
171 if (bit
.wire
!= NULL
)
175 void erase(RTLIL::SigSpec sig
, T data
)
177 for (auto &bit
: sig
)
178 if (bit
.wire
!= NULL
)
179 bits
[bit
].erase(data
);
182 void erase(RTLIL::SigSpec sig
, const std::set
<T
> &data
)
184 for (auto &bit
: sig
)
185 if (bit
.wire
!= NULL
)
186 bits
[bit
].erase(data
.begin(), data
.end());
189 void find(RTLIL::SigSpec sig
, std::set
<T
> &result
)
191 for (auto &bit
: sig
)
192 if (bit
.wire
!= NULL
) {
193 auto &data
= bits
[bit
];
194 result
.insert(data
.begin(), data
.end());
198 void find(RTLIL::SigSpec sig
, pool
<T
> &result
)
200 for (auto &bit
: sig
)
201 if (bit
.wire
!= NULL
) {
202 auto &data
= bits
[bit
];
203 result
.insert(data
.begin(), data
.end());
207 std::set
<T
> find(RTLIL::SigSpec sig
)
214 bool has(RTLIL::SigSpec sig
)
216 for (auto &bit
: sig
)
217 if (bit
.wire
!= NULL
&& bits
.count(bit
))
225 mfp
<SigBit
> database
;
227 SigMap(RTLIL::Module
*module
= NULL
)
233 void swap(SigMap
&other
)
235 database
.swap(other
.database
);
243 void set(RTLIL::Module
*module
)
246 for (auto &it
: module
->connections())
247 bitcount
+= it
.first
.size();
250 database
.reserve(bitcount
);
252 for (auto &it
: module
->connections())
253 add(it
.first
, it
.second
);
256 void add(RTLIL::SigSpec from
, RTLIL::SigSpec to
)
258 log_assert(GetSize(from
) == GetSize(to
));
260 for (int i
= 0; i
< GetSize(from
); i
++)
262 int bfi
= database
.lookup(from
[i
]);
263 int bti
= database
.lookup(to
[i
]);
265 const RTLIL::SigBit
&bf
= database
[bfi
];
266 const RTLIL::SigBit
&bt
= database
[bti
];
268 if (bf
.wire
|| bt
.wire
)
270 database
.imerge(bfi
, bti
);
272 if (bf
.wire
== nullptr)
273 database
.ipromote(bfi
);
275 if (bt
.wire
== nullptr)
276 database
.ipromote(bti
);
281 void add(RTLIL::SigSpec sig
)
283 for (auto &bit
: sig
) {
284 RTLIL::SigBit b
= database
.find(bit
);
285 if (b
.wire
!= nullptr)
286 database
.promote(bit
);
290 void apply(RTLIL::SigBit
&bit
) const
292 bit
= database
.find(bit
);
295 void apply(RTLIL::SigSpec
&sig
) const
297 for (auto &bit
: sig
)
301 RTLIL::SigBit
operator()(RTLIL::SigBit bit
) const
307 RTLIL::SigSpec
operator()(RTLIL::SigSpec sig
) const
313 RTLIL::SigSpec
operator()(RTLIL::Wire
*wire
) const
320 RTLIL::SigSpec
allbits() const
323 for (auto &bit
: database
)
324 if (bit
.wire
!= nullptr)
332 #endif /* SIGTOOLS_H */