2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * (C) 2020 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 #include "kernel/yosys.h"
34 NameBit() : offset(0) {}
35 NameBit(const RTLIL::IdString name
, int offset
) : name(name
), offset(offset
) {}
36 explicit NameBit(const RTLIL::SigBit
&b
) : name(b
.wire
->name
), offset(b
.offset
) {}
37 bool operator==(const NameBit
& nb
) const { return nb
.name
== name
&& nb
.offset
== offset
; }
38 bool operator!=(const NameBit
& nb
) const { return !operator==(nb
); }
39 unsigned int hash() const { return mkhash_add(name
.hash(), offset
); }
43 NameBit first
, second
;
44 BitBit(const NameBit
&first
, const NameBit
&second
) : first(first
), second(second
) {}
45 BitBit(const SigBit
&first
, const SigBit
&second
) : first(first
), second(second
) {}
46 bool operator==(const BitBit
& bb
) const { return bb
.first
== first
&& bb
.second
== second
; }
47 unsigned int hash() const { return mkhash_add(first
.hash(), second
.hash()); }
53 dict
<BitBit
, int> comb
;
54 dict
<NameBit
, int> arrival
, required
;
57 dict
<RTLIL::IdString
, ModuleTiming
> data
;
63 TimingInfo(RTLIL::Design
*design
)
68 void setup(RTLIL::Design
*design
)
70 for (auto module
: design
->modules()) {
71 if (!module
->get_blackbox_attribute())
77 const ModuleTiming
& setup_module(RTLIL::Module
*module
)
79 auto r
= data
.insert(module
->name
);
81 auto &t
= r
.first
->second
;
83 for (auto cell
: module
->cells()) {
84 if (cell
->type
== ID($specify2
)) {
85 auto src
= cell
->getPort(ID(SRC
));
86 auto dst
= cell
->getPort(ID(DST
));
87 for (const auto &c
: src
.chunks())
88 if (!c
.wire
->port_input
)
89 log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module
), log_id(cell
), log_signal(src
));
90 for (const auto &c
: dst
.chunks())
91 if (!c
.wire
->port_output
)
92 log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module
), log_id(cell
), log_signal(dst
));
93 int rise_max
= cell
->getParam(ID(T_RISE_MAX
)).as_int();
94 int fall_max
= cell
->getParam(ID(T_FALL_MAX
)).as_int();
95 int max
= std::max(rise_max
,fall_max
);
97 log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module
), log_id(cell
));
98 if (cell
->getParam(ID(FULL
)).as_bool()) {
99 for (const auto &s
: src
)
100 for (const auto &d
: dst
) {
101 auto r
= t
.comb
.insert(BitBit(s
,d
));
103 log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module
), log_signal(s
), log_signal(d
));
104 r
.first
->second
= max
;
108 log_assert(GetSize(src
) == GetSize(dst
));
109 for (auto i
= 0; i
< GetSize(src
); i
++) {
110 const auto &s
= src
[i
];
111 const auto &d
= dst
[i
];
112 auto r
= t
.comb
.insert(BitBit(s
,d
));
114 log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module
), log_signal(s
), log_signal(d
));
115 r
.first
->second
= max
;
119 else if (cell
->type
== ID($specify3
)) {
120 auto src
= cell
->getPort(ID(SRC
));
121 auto dst
= cell
->getPort(ID(DST
));
122 for (const auto &c
: src
.chunks())
123 if (!c
.wire
->port_input
)
124 log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module
), log_id(cell
), log_signal(src
));
125 for (const auto &c
: dst
.chunks())
126 if (!c
.wire
->port_output
)
127 log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module
), log_id(cell
), log_signal(dst
));
128 int rise_max
= cell
->getParam(ID(T_RISE_MAX
)).as_int();
129 int fall_max
= cell
->getParam(ID(T_FALL_MAX
)).as_int();
130 int max
= std::max(rise_max
,fall_max
);
132 log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module
), log_id(cell
));
134 log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module
), log_id(cell
));
137 for (const auto &d
: dst
) {
138 auto &v
= t
.arrival
[NameBit(d
)];
139 v
= std::max(v
, max
);
142 else if (cell
->type
== ID($specrule
)) {
143 auto type
= cell
->getParam(ID(TYPE
)).decode_string();
144 if (type
!= "$setup" && type
!= "$setuphold")
146 auto src
= cell
->getPort(ID(SRC
));
147 auto dst
= cell
->getPort(ID(DST
));
148 for (const auto &c
: src
.chunks())
149 if (!c
.wire
->port_input
)
150 log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module
), log_id(cell
), log_signal(src
));
151 for (const auto &c
: dst
.chunks())
152 if (!c
.wire
->port_input
)
153 log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module
), log_id(cell
), log_signal(dst
));
154 int max
= cell
->getParam(ID(T_LIMIT_MAX
)).as_int();
156 log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module
), log_id(cell
));
158 log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module
), log_id(cell
));
161 for (const auto &s
: src
) {
162 auto &v
= t
.required
[NameBit(s
)];
163 v
= std::max(v
, max
);
171 decltype(data
)::const_iterator
find(RTLIL::IdString module_name
) const { return data
.find(module_name
); }
172 decltype(data
)::const_iterator
end() const { return data
.end(); }
173 int count(RTLIL::IdString module_name
) const { return data
.count(module_name
); }
174 const ModuleTiming
& at(RTLIL::IdString module_name
) const { return data
.at(module_name
); }