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[litex.git] / lib / sata / k7sataphy / gtx.py
1 from migen.fhdl.std import *
2 from migen.genlib.cdc import *
3
4 from lib.sata.k7sataphy.std import *
5
6 class _PulseSynchronizer(PulseSynchronizer):
7 def __init__(self, i, idomain, o, odomain):
8 PulseSynchronizer.__init__(self, idomain, odomain)
9 self.comb += [
10 self.i.eq(i),
11 o.eq(self.o)
12 ]
13
14 class K7SATAPHYGTX(Module):
15 def __init__(self, pads, default_speed):
16 # Interface
17 self.drp = DRPBus()
18
19 # Channel - Ref Clock Ports
20 self.gtrefclk0 = Signal()
21
22 # Channel PLL
23 self.cplllock = Signal()
24 self.cpllreset = Signal()
25
26 # Receive Ports
27 self.rxuserrdy = Signal()
28 self.rxalign = Signal()
29
30 # Receive Ports - 8b10b Decoder
31 self.rxcharisk = Signal(2)
32 self.rxdisperr = Signal(2)
33
34 # Receive Ports - RX Data Path interface
35 self.gtrxreset = Signal()
36 self.rxdata = Signal(16)
37 self.rxoutclk = Signal()
38 self.rxusrclk = Signal()
39 self.rxusrclk2 = Signal()
40
41 # Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
42 self.rxelecidle = Signal()
43
44 # Receive Ports - RX Elastic Buffer and Phase Alignment Ports
45 self.rxdlyen = Signal()
46 self.rxdlysreset = Signal()
47 self.rxdlysresetdone = Signal()
48 self.rxphalign = Signal()
49 self.rxphaligndone = Signal()
50 self.rxphalignen = Signal()
51 self.rxphdlyreset = Signal()
52
53 # Receive Ports - RX PLL Ports
54 self.rxresetdone = Signal()
55
56 # Receive Ports - RX Ports for SATA
57 self.rxcominitdet = Signal()
58 self.rxcomwakedet = Signal()
59
60 # Transmit Ports
61 self.txuserrdy = Signal()
62
63 # Transmit Ports - 8b10b Encoder Control Ports
64 self.txcharisk = Signal(2)
65
66 # Transmit Ports - TX Buffer and Phase Alignment Ports
67 self.txdlyen = Signal()
68 self.txdlysreset = Signal()
69 self.txdlysresetdone = Signal()
70 self.txphalign = Signal()
71 self.txphaligndone = Signal()
72 self.txphalignen = Signal()
73 self.txphdlyreset = Signal()
74 self.txphinit = Signal()
75 self.txphinitdone = Signal()
76
77 # Transmit Ports - TX Data Path interface
78 self.gttxreset = Signal()
79 self.txdata = Signal(16)
80 self.txoutclk = Signal()
81 self.txusrclk = Signal()
82 self.txusrclk2 = Signal()
83
84 # Transmit Ports - TX PLL Ports
85 self.txresetdone = Signal()
86
87 # Transmit Ports - TX Ports for PCI Express
88 self.txelecidle = Signal(reset=1)
89
90 # Transmit Ports - TX Ports for SATA
91 self.txcomfinish = Signal()
92 self.txcominit = Signal()
93 self.txcomwake = Signal()
94 self.rxrate = Signal(3)
95 self.rxratedone = Signal()
96 self.txrate = Signal(3)
97 self.txratedone = Signal()
98
99 # Config at startup
100 div_config = {
101 "SATA1" : 4,
102 "SATA2" : 2,
103 "SATA3" : 1
104 }
105 rxout_div = div_config[default_speed]
106 txout_div = div_config[default_speed]
107
108 cdr_config = {
109 "SATA1" : 0x0380008BFF40100008,
110 "SATA2" : 0x0380008BFF40200008,
111 "SATA3" : 0X0380008BFF20200010
112 }
113 rxcdr_cfg = cdr_config[default_speed]
114
115 # Internals and clock domain crossing
116 # sys_clk --> sata_tx clk
117 txuserrdy = Signal()
118 txdlyen = Signal()
119 txdlysreset = Signal()
120 txphalign = Signal()
121 txphalignen = Signal()
122 txphdlyreset = Signal()
123 txphinit = Signal()
124 txelecidle = Signal(reset=1)
125 txcominit = Signal()
126 txcomwake = Signal()
127 txrate = Signal(3)
128
129 self.specials += [
130 MultiReg(self.txuserrdy, txuserrdy, "sata_tx"),
131 MultiReg(self.txdlyen, txdlyen, "sata_tx"),
132 MultiReg(self.txdlysreset, txdlysreset, "sata_tx"),
133 MultiReg(self.txphalign, txphalign, "sata_tx"),
134 MultiReg(self.txphalignen, txphalignen, "sata_tx"),
135 MultiReg(self.txphdlyreset, txphdlyreset, "sata_tx"),
136 MultiReg(self.txelecidle, txelecidle, "sata_tx"),
137 MultiReg(self.txrate, txrate, "sata_tx")
138 ]
139 self.submodules += [
140 _PulseSynchronizer(self.txcominit, "sys", txcominit, "sata_tx"),
141 _PulseSynchronizer(self.txcomwake, "sys", txcomwake, "sata_tx"),
142 ]
143
144 # sata_tx clk --> sys clk
145 txdlysresetdone = Signal()
146 txphaligndone = Signal()
147 txphinitdone = Signal()
148 txresetdone = Signal()
149 txratedone = Signal()
150 txcomfinish = Signal()
151
152 self.specials += [
153 MultiReg(txdlysresetdone, self.txdlysresetdone, "sys"),
154 MultiReg(txphaligndone, self.txphaligndone, "sys"),
155 MultiReg(txphinitdone, self.txphinitdone, "sys"),
156 MultiReg(txresetdone, self.txresetdone, "sys"),
157 MultiReg(txratedone, self.txratedone, "sys"),
158 ]
159
160 self.submodules += [
161 _PulseSynchronizer(txcomfinish, "sata_tx", self.txcomfinish, "sys"),
162 ]
163
164 # sys clk --> sata_rx clk
165 rxuserrdy = Signal()
166 rxelecidle = Signal()
167 rxdlyen = Signal()
168 rxdlysreset = Signal()
169 rxphalign = Signal()
170 rxphalignen = Signal()
171 rxphdlyreset = Signal()
172 rxrate = Signal(3)
173 rxalign = Signal()
174
175 self.specials += [
176 MultiReg(self.rxuserrdy, rxuserrdy, "sata_rx"),
177 MultiReg(self.rxelecidle, rxelecidle, "sata_rx"),
178 MultiReg(self.rxdlyen, rxdlyen, "sata_rx"),
179 MultiReg(self.rxdlysreset, rxdlysreset, "sata_rx"),
180 MultiReg(self.rxphalign, rxphalign, "sata_rx"),
181 MultiReg(self.rxphalignen, rxphalignen, "sata_rx"),
182 MultiReg(self.rxphdlyreset, rxphdlyreset, "sata_rx"),
183 MultiReg(self.rxrate, rxrate, "sata_rx"),
184 MultiReg(self.rxalign, rxalign, "sata_rx"),
185 ]
186
187
188 # sata_rx clk --> sys clk
189 rxdlysresetdone = Signal()
190 rxphaligndone = Signal()
191 rxresetdone = Signal()
192 rxcominitdet = Signal()
193 rxcomwakedet = Signal()
194 rxratedone = Signal()
195
196 self.specials += [
197 MultiReg(rxdlysresetdone, self.rxdlysresetdone, "sys"),
198 MultiReg(rxphaligndone, self.rxphaligndone, "sys"),
199 MultiReg(rxresetdone, self.rxresetdone, "sys"),
200 MultiReg(rxratedone, self.rxratedone, "sys")
201 ]
202
203 self.submodules += [
204 _PulseSynchronizer(rxcominitdet, "sata_rx", self.rxcominitdet, "sys"),
205 _PulseSynchronizer(rxcomwakedet, "sata_rx", self.rxcomwakedet, "sys"),
206 ]
207
208
209 self.rxbyteisaligned = Signal()
210 self.rxbyterealign = Signal()
211 self.rxcommadet = Signal()
212
213 # Bypass TX buffer
214 self.comb += [
215 self.txphdlyreset.eq(0),
216 self.txphalignen.eq(0),
217 self.txdlyen.eq(0),
218 self.txphalign.eq(0),
219 self.txphinit.eq(0)
220 ]
221
222 # Bypass RX buffer
223 self.comb += [
224 self.rxphdlyreset.eq(0),
225 self.rxdlyen.eq(0),
226 self.rxphalign.eq(0),
227 self.rxphalignen.eq(0),
228 ]
229
230 # Instance
231 gtxe2_channel_parameters = {
232 # Simulation-Only Attributes
233 "p_SIM_RECEIVER_DETECT_PASS":"TRUE",
234 "p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
235 "p_SIM_RESET_SPEEDUP":"TRUE",
236 "p_SIM_CPLLREFCLK_SEL":0b001,
237 "p_SIM_VERSION":"4.0",
238
239 # RX Byte and Word Alignment Attributes
240 "p_ALIGN_COMMA_DOUBLE":"FALSE",
241 "p_ALIGN_COMMA_ENABLE":ones(10),
242 "p_ALIGN_COMMA_WORD":2,
243 "p_ALIGN_MCOMMA_DET":"TRUE",
244 "p_ALIGN_MCOMMA_VALUE":0b1010000011,
245 "p_ALIGN_PCOMMA_DET":"TRUE",
246 "p_ALIGN_PCOMMA_VALUE":0b0101111100,
247 "p_SHOW_REALIGN_COMMA":"FALSE",
248 "p_RXSLIDE_AUTO_WAIT":7,
249 "p_RXSLIDE_MODE":"OFF",
250 "p_RX_SIG_VALID_DLY":10,
251
252 # RX 8B/10B Decoder Attributes
253 "p_RX_DISPERR_SEQ_MATCH":"TRUE",
254 "p_DEC_MCOMMA_DETECT":"TRUE",
255 "p_DEC_PCOMMA_DETECT":"TRUE",
256 "p_DEC_VALID_COMMA_ONLY":"TRUE",
257
258 # RX Clock Correction Attributes
259 "p_CBCC_DATA_SOURCE_SEL":"DECODED",
260 "p_CLK_COR_SEQ_2_USE":"FALSE",
261 "p_CLK_COR_KEEP_IDLE":"FALSE",
262 "p_CLK_COR_MAX_LAT":9,
263 "p_CLK_COR_MIN_LAT":7,
264 "p_CLK_COR_PRECEDENCE":"TRUE",
265 "p_CLK_COR_REPEAT_WAIT":0,
266 "p_CLK_COR_SEQ_LEN":1,
267 "p_CLK_COR_SEQ_1_ENABLE":ones(4),
268 "p_CLK_COR_SEQ_1_ENABLE":0,
269 "p_CLK_COR_SEQ_1_1":0,
270 "p_CLK_COR_SEQ_1_1":0,
271 "p_CLK_COR_SEQ_1_2":0,
272 "p_CLK_COR_SEQ_1_3":0,
273 "p_CLK_COR_SEQ_1_4":0,
274 "p_CLK_CORRECT_USE":"FALSE",
275 "p_CLK_COR_SEQ_2_ENABLE":ones(4),
276 "p_CLK_COR_SEQ_2_1":0,
277 "p_CLK_COR_SEQ_2_2":0,
278 "p_CLK_COR_SEQ_2_3":0,
279 "p_CLK_COR_SEQ_2_4":0,
280
281 # RX Channel Bonding Attributes
282 "p_CHAN_BOND_KEEP_ALIGN":"FALSE",
283 "p_CHAN_BOND_MAX_SKEW":1,
284 "p_CHAN_BOND_SEQ_LEN":1,
285 "p_CHAN_BOND_SEQ_1_1":0,
286 "p_CHAN_BOND_SEQ_1_1":0,
287 "p_CHAN_BOND_SEQ_1_2":0,
288 "p_CHAN_BOND_SEQ_1_3":0,
289 "p_CHAN_BOND_SEQ_1_4":0,
290 "p_CHAN_BOND_SEQ_1_ENABLE":ones(4),
291 "p_CHAN_BOND_SEQ_2_1":0,
292 "p_CHAN_BOND_SEQ_2_2":0,
293 "p_CHAN_BOND_SEQ_2_3":0,
294 "p_CHAN_BOND_SEQ_2_4":0,
295 "p_CHAN_BOND_SEQ_2_ENABLE":ones(4),
296 "p_CHAN_BOND_SEQ_2_USE":"FALSE",
297 "p_FTS_DESKEW_SEQ_ENABLE":ones(4),
298 "p_FTS_LANE_DESKEW_CFG":ones(4),
299 "p_FTS_LANE_DESKEW_EN":"FALSE",
300
301 # RX Margin Analysis Attributes
302 "p_ES_CONTROL":0,
303 "p_ES_ERRDET_EN":"FALSE",
304 "p_ES_EYE_SCAN_EN":"TRUE",
305 "p_ES_HORZ_OFFSET":0,
306 "p_ES_PMA_CFG":0,
307 "p_ES_PRESCALE":0,
308 "p_ES_QUALIFIER":0,
309 "p_ES_QUAL_MASK":0,
310 "p_ES_SDATA_MASK":0,
311 "p_ES_VERT_OFFSET":0,
312
313 # FPGA RX Interface Attributes
314 "p_RX_DATA_WIDTH":20,
315
316 # PMA Attributes
317 "p_OUTREFCLK_SEL_INV":0b11,
318 "p_PMA_RSV":0x00018480,
319 "p_PMA_RSV2":0x2050,
320 "p_PMA_RSV3":0,
321 "p_PMA_RSV4":0,
322 "p_RX_BIAS_CFG":0b100,
323 "p_DMONITOR_CFG":0xA00,
324 "p_RX_CM_SEL":0b11,
325 "p_RX_CM_TRIM":0b010,
326 "p_RX_DEBUG_CFG":0,
327 "p_RX_OS_CFG":0b10000000,
328 "p_TERM_RCAL_CFG":0,
329 "p_TERM_RCAL_OVRD":0,
330 "p_TST_RSV":0,
331 "p_RX_CLK25_DIV":6,
332 "p_TX_CLK25_DIV":6,
333 "p_UCODEER_CLR":0,
334
335 # PCI Express Attributes
336 "p_PCS_PCIE_EN":"FALSE",
337
338 # PCS Attributes
339 "p_PCS_RSVD_ATTR":0x100,
340
341 # RX Buffer Attributes
342 "p_RXBUF_ADDR_MODE":"FAST",
343 "p_RXBUF_EIDLE_HI_CNT":0b1000,
344 "p_RXBUF_EIDLE_LO_CNT":0,
345 "p_RXBUF_EN":"FALSE",
346 "p_RX_BUFFER_CFG":0,
347 "p_RXBUF_RESET_ON_CB_CHANGE":"TRUE",
348 "p_RXBUF_RESET_ON_COMMAALIGN":"FALSE",
349 "p_RXBUF_RESET_ON_EIDLE":"FALSE",
350 "p_RXBUF_RESET_ON_RATE_CHANGE":"TRUE",
351 "p_RXBUFRESET_TIME":1,
352 "p_RXBUF_THRESH_OVFLW":61,
353 "p_RXBUF_THRESH_OVRD":"FALSE",
354 "p_RXBUF_THRESH_UNDFLW":4,
355 "p_RXDLY_CFG":0x1f,
356 "p_RXDLY_LCFG":0x30,
357 "p_RXDLY_TAP_CFG":0,
358 "p_RXPH_CFG":0,
359 "p_RXPHDLY_CFG":0x084820,
360 "p_RXPH_MONITOR_SEL":0,
361 "p_RX_XCLK_SEL":"RXUSR",
362 "p_RX_DDI_SEL":0,
363 "p_RX_DEFER_RESET_BUF_EN":"TRUE",
364
365 #CDR Attributes
366 "p_RXCDR_CFG":rxcdr_cfg,
367 "p_RXCDR_FR_RESET_ON_EIDLE":0,
368 "p_RXCDR_HOLD_DURING_EIDLE":0,
369 "p_RXCDR_PH_RESET_ON_EIDLE":0,
370 "p_RXCDR_LOCK_CFG":0b010101,
371
372 # RX Initialization and Reset Attributes
373 "p_RXCDRFREQRESET_TIME":1,
374 "p_RXCDRPHRESET_TIME":1,
375 "p_RXISCANRESET_TIME":1,
376 "p_RXPCSRESET_TIME":1,
377 "p_RXPMARESET_TIME":3,
378
379 # RX OOB Signaling Attributes
380 "p_RXOOB_CFG":0b0000110,
381
382 # RX Gearbox Attributes
383 "p_RXGEARBOX_EN":"FALSE",
384 "p_GEARBOX_MODE":0,
385
386 # PRBS Detection Attribute
387 "p_RXPRBS_ERR_LOOPBACK":0,
388
389 # Power-Down Attributes
390 "p_PD_TRANS_TIME_FROM_P2":0x03c,
391 "p_PD_TRANS_TIME_NONE_P2":0x3c,
392 "p_PD_TRANS_TIME_TO_P2":0x64,
393
394 # RX OOB Signaling Attributes
395 "p_SAS_MAX_COM":64,
396 "p_SAS_MIN_COM":36,
397 "p_SATA_BURST_SEQ_LEN":0b0101,
398 "p_SATA_BURST_VAL":0b100,
399 "p_SATA_EIDLE_VAL":0b100,
400 "p_SATA_MAX_BURST":8,
401 "p_SATA_MAX_INIT":21,
402 "p_SATA_MAX_WAKE":7,
403 "p_SATA_MIN_BURST":4,
404 "p_SATA_MIN_INIT":12,
405 "p_SATA_MIN_WAKE":4,
406
407 # RX Fabric Clock Output Control Attributes
408 "p_TRANS_TIME_RATE":0x0e,
409
410 # TX Buffer Attributes
411 "p_TXBUF_EN":"FALSE",
412 "p_TXBUF_RESET_ON_RATE_CHANGE":"FALSE",
413 "p_TXDLY_CFG":0x1f,
414 "p_TXDLY_LCFG":0x030,
415 "p_TXDLY_TAP_CFG":0,
416 "p_TXPH_CFG":0x0780,
417 "p_TXPHDLY_CFG":0x084020,
418 "p_TXPH_MONITOR_SEL":0,
419 "p_TX_XCLK_SEL":"TXUSR",
420
421 # FPGA TX Interface Attributes
422 "p_TX_DATA_WIDTH":20,
423
424 # TX Configurable Driver Attributes
425 "p_TX_DEEMPH0":0,
426 "p_TX_DEEMPH1":0,
427 "p_TX_EIDLE_ASSERT_DELAY":0b110,
428 "p_TX_EIDLE_DEASSERT_DELAY":0b100,
429 "p_TX_LOOPBACK_DRIVE_HIZ":"FALSE",
430 "p_TX_MAINCURSOR_SEL":0,
431 "p_TX_DRIVE_MODE":"DIRECT",
432 "p_TX_MARGIN_FULL_0":0b1001110,
433 "p_TX_MARGIN_FULL_1":0b1001001,
434 "p_TX_MARGIN_FULL_2":0b1000101,
435 "p_TX_MARGIN_FULL_3":0b1000010,
436 "p_TX_MARGIN_FULL_4":0b1000000,
437 "p_TX_MARGIN_LOW_0":0b1000110,
438 "p_TX_MARGIN_LOW_1":0b1000100,
439 "p_TX_MARGIN_LOW_2":0b1000010,
440 "p_TX_MARGIN_LOW_3":0b1000000,
441 "p_TX_MARGIN_LOW_4":0b1000000,
442
443 # TX Gearbox Attributes
444 "p_TXGEARBOX_EN":"FALSE",
445
446 # TX Initialization and Reset Attributes
447 "p_TXPCSRESET_TIME":1,
448 "p_TXPMARESET_TIME":1,
449
450 # TX Receiver Detection Attributes
451 "p_TX_RXDETECT_CFG":0x1832,
452 "p_TX_RXDETECT_REF":0b100,
453
454 # CPLL Attributes
455 "p_CPLL_CFG":0xBC07DC,
456 "p_CPLL_FBDIV":4,
457 "p_CPLL_FBDIV_45":5,
458 "p_CPLL_INIT_CFG":0x00001e,
459 "p_CPLL_LOCK_CFG":0x01e8,
460 "p_CPLL_REFCLK_DIV":1,
461 "p_RXOUT_DIV":rxout_div,
462 "p_TXOUT_DIV":txout_div,
463 "p_SATA_CPLL_CFG":"VCO_3000MHZ",
464
465 # RX Initialization and Reset Attributes
466 "p_RXDFELPMRESET_TIME":0b0001111,
467
468 # RX Equalizer Attributes
469 "p_RXLPM_HF_CFG":0b00000011110000,
470 "p_RXLPM_LF_CFG":0b00000011110000,
471 "p_RX_DFE_GAIN_CFG":0x020fea,
472 "p_RX_DFE_H2_CFG":0b000000000000,
473 "p_RX_DFE_H3_CFG":0b000001000000,
474 "p_RX_DFE_H4_CFG":0b00011110000,
475 "p_RX_DFE_H5_CFG":0b00011100000,
476 "p_RX_DFE_KL_CFG":0b0000011111110,
477 "p_RX_DFE_LPM_CFG":0x0954,
478 "p_RX_DFE_LPM_HOLD_DURING_EIDLE":1,
479 "p_RX_DFE_UT_CFG":0b10001111000000000,
480 "p_RX_DFE_VP_CFG":0b00011111100000011,
481
482 # Power-Down Attributes
483 "p_RX_CLKMUX_PD":1,
484 "p_TX_CLKMUX_PD":1,
485
486 # FPGA RX Interface Attribute
487 "p_RX_INT_DATAWIDTH":0,
488
489 # FPGA TX Interface Attribute
490 "p_TX_INT_DATAWIDTH":0,
491
492 # TX Configurable Driver Attributes
493 "p_TX_QPI_STATUS_EN":0,
494
495 # RX Equalizer Attributes
496 "p_RX_DFE_KL_CFG2":0b00110011000100000001100000001100,
497 "p_RX_DFE_XYD_CFG":0b0000000000000,
498
499 # TX Configurable Driver Attributes
500 "p_TX_PREDRIVER_MODE":0,
501 }
502
503 self.specials += \
504 Instance("GTXE2_CHANNEL",
505 # CPLL Ports
506 #o_CPLLFBCLKLOST=,
507 o_CPLLLOCK=self.cplllock,
508 i_CPLLLOCKDETCLK=0,
509 i_CPLLLOCKEN=1,
510 i_CPLLPD=0,
511 #o_CPLLREFCLKLOST=0,
512 i_CPLLREFCLKSEL=0b001,
513 i_CPLLRESET=self.cpllreset,
514 i_GTRSVD=0,
515 i_PCSRSVDIN=0,
516 i_PCSRSVDIN2=0,
517 i_PMARSVDIN=0,
518 i_PMARSVDIN2=0,
519 i_TSTIN=ones(20),
520 #o_TSTOUT=,
521
522 # Channel
523 i_CLKRSVD=0,
524
525 # Channel - Clocking Ports
526 i_GTGREFCLK=0,
527 i_GTNORTHREFCLK0=0,
528 i_GTNORTHREFCLK1=0,
529 i_GTREFCLK0=self.gtrefclk0,
530 i_GTREFCLK1=0,
531 i_GTSOUTHREFCLK0=0,
532 i_GTSOUTHREFCLK1=0,
533
534 # Channel - DRP Ports
535 i_DRPADDR=self.drp.addr,
536 i_DRPCLK=self.drp.clk,
537 i_DRPDI=self.drp.di,
538 o_DRPDO=self.drp.do,
539 i_DRPEN=self.drp.en,
540 o_DRPRDY=self.drp.rdy,
541 i_DRPWE=self.drp.we,
542
543 # Clocking Ports
544 #o_GTREFCLKMONITOR=,
545 i_QPLLCLK=0,
546 i_QPLLREFCLK=0,
547 i_RXSYSCLKSEL=0b00,
548 i_TXSYSCLKSEL=0b00,
549
550 # Digital Monitor Ports
551 #o_DMONITOROUT=,
552
553 # FPGA TX Interface Datapath Configuration
554 i_TX8B10BEN=1,
555
556 # Loopback Ports
557 i_LOOPBACK=0,
558
559 # PCI Express Ports
560 #o_PHYSTATUS=,
561 i_RXRATE=rxrate,
562 #o_RXVALID=,
563
564 # Power-Down Ports
565 i_RXPD=0b00,
566 i_TXPD=0b00,
567
568 # RX 8B/10B Decoder Ports
569 i_SETERRSTATUS=0,
570
571 # RX Initialization and Reset Ports
572 i_EYESCANRESET=0,
573 i_RXUSERRDY=rxuserrdy,
574
575 # RX Margin Analysis Ports
576 #o_EYESCANDATAERROR=,
577 i_EYESCANMODE=0,
578 i_EYESCANTRIGGER=0,
579
580 # Receive Ports - CDR Ports
581 i_RXCDRFREQRESET=0,
582 i_RXCDRHOLD=0,
583 #o_RXCDRLOCK=,
584 i_RXCDROVRDEN=0,
585 i_RXCDRRESET=0,
586 i_RXCDRRESETRSV=0,
587
588 # Receive Ports - Clock Correction Ports
589 #o_RXCLKCORCNT=,
590
591 # Receive Ports - FPGA RX Interface Datapath Configuration
592 i_RX8B10BEN=1,
593
594 # Receive Ports - FPGA RX Interface Ports
595 i_RXUSRCLK=self.rxusrclk,
596 i_RXUSRCLK2=self.rxusrclk2,
597
598 # Receive Ports - FPGA RX interface Ports
599 o_RXDATA=self.rxdata,
600
601 # Receive Ports - Pattern Checker Ports
602 #o_RXPRBSERR=,
603 i_RXPRBSSEL=0,
604
605 # Receive Ports - Pattern Checker ports
606 i_RXPRBSCNTRESET=0,
607
608 # Receive Ports - RX Equalizer Ports
609 i_RXDFEXYDEN=0,
610 i_RXDFEXYDHOLD=0,
611 i_RXDFEXYDOVRDEN=0,
612
613 # Receive Ports - RX 8B/10B Decoder Ports
614 #o_RXDISPERR=,
615 #o_RXNOTINTABLE=,
616
617 # Receive Ports - RX AFE
618 i_GTXRXP=pads.rxp,
619 i_GTXRXN=pads.rxn,
620
621 # Receive Ports - RX Buffer Bypass Ports
622 i_RXBUFRESET=0,
623 #o_RXBUFSTATUS=,
624 i_RXDDIEN=1,
625 i_RXDLYBYPASS=0,
626 i_RXDLYEN=rxdlyen,
627 i_RXDLYOVRDEN=0,
628 i_RXDLYSRESET=rxdlysreset,
629 o_RXDLYSRESETDONE=rxdlysresetdone,
630 i_RXPHALIGN=rxphalign,
631 o_RXPHALIGNDONE=rxphaligndone,
632 i_RXPHALIGNEN=rxphalignen,
633 i_RXPHDLYPD=0,
634 i_RXPHDLYRESET=rxphdlyreset,
635 #o_RXPHMONITOR=,
636 i_RXPHOVRDEN=0,
637 #o_RXPHSLIPMONITOR=,
638 #o_RXSTATUS=,
639
640 # Receive Ports - RX Byte and Word Alignment Ports
641 o_RXBYTEISALIGNED=self.rxbyteisaligned,
642 o_RXBYTEREALIGN=self.rxbyterealign,
643 o_RXCOMMADET=self.rxcommadet,
644 i_RXCOMMADETEN=1,
645 i_RXMCOMMAALIGNEN=rxalign,
646 i_RXPCOMMAALIGNEN=rxalign,
647
648 # Receive Ports - RX Channel Bonding Ports
649 #o_RXCHANBONDSEQ=,
650 i_RXCHBONDEN=0,
651 i_RXCHBONDLEVEL=0,
652 i_RXCHBONDMASTER=0,
653 #o_RXCHBONDO=,
654 i_RXCHBONDSLAVE=0,
655
656 # Receive Ports - RX Channel Bonding Ports
657 #o_RXCHANISALIGNED=,
658 #o_RXCHANREALIGN=,
659
660 # Receive Ports - RX Equalizer Ports
661 i_RXDFEAGCHOLD=0,
662 i_RXDFEAGCOVRDEN=0,
663 i_RXDFECM1EN=0,
664 i_RXDFELFHOLD=0,
665 i_RXDFELFOVRDEN=1,
666 i_RXDFELPMRESET=0,
667 i_RXDFETAP2HOLD=0,
668 i_RXDFETAP2OVRDEN=0,
669 i_RXDFETAP3HOLD=0,
670 i_RXDFETAP3OVRDEN=0,
671 i_RXDFETAP4HOLD=0,
672 i_RXDFETAP4OVRDEN=0,
673 i_RXDFETAP5HOLD=0,
674 i_RXDFETAP5OVRDEN=0,
675 i_RXDFEUTHOLD=0,
676 i_RXDFEUTOVRDEN=0,
677 i_RXDFEVPHOLD=0,
678 i_RXDFEVPOVRDEN=0,
679 i_RXDFEVSEN=0,
680 i_RXLPMLFKLOVRDEN=0,
681 #o_RXMONITOROUT=,
682 i_RXMONITORSEL=0b00,
683 i_RXOSHOLD=0,
684 i_RXOSOVRDEN=0,
685
686 # Receive Ports - RX Equilizer Ports
687 i_RXLPMHFHOLD=0,
688 i_RXLPMHFOVRDEN=0,
689 i_RXLPMLFHOLD=0,
690
691 # Receive Ports - RX Fabric ClocK Output Control Ports
692 o_RXRATEDONE=rxratedone,
693
694 # Receive Ports - RX Fabric Output Control Ports
695 o_RXOUTCLK=self.rxoutclk,
696 #o_RXOUTCLKFABRIC=,
697 #o_RXOUTCLKPCS=,
698 i_RXOUTCLKSEL=0b010,
699
700 # Receive Ports - RX Gearbox Ports
701 #o_RXDATAVALID=,
702 #o_RXHEADER=,
703 #o_RXHEADERVALID=,
704 #o_RXSTARTOFSEQ=,
705
706 # Receive Ports - RX Gearbox Ports
707 i_RXGEARBOXSLIP=0,
708
709 # Receive Ports - RX Initialization and Reset Ports
710 i_GTRXRESET=self.gtrxreset,
711 i_RXOOBRESET=0,
712 i_RXPCSRESET=0,
713 i_RXPMARESET=0,
714
715 # Receive Ports - RX Margin Analysis ports
716 i_RXLPMEN=0,
717
718 # Receive Ports - RX OOB Signaling ports
719 #o_RXCOMSASDET=,
720 o_RXCOMWAKEDET=rxcomwakedet,
721
722 # Receive Ports - RX OOB Signaling ports
723 o_RXCOMINITDET=rxcominitdet,
724
725 # Receive Ports - RX OOB signalling Ports
726 o_RXELECIDLE=rxelecidle,
727 i_RXELECIDLEMODE=0b00,
728
729 # Receive Ports - RX Polarity Control Ports
730 i_RXPOLARITY=0,
731
732 # Receive Ports - RX gearbox ports
733 i_RXSLIDE=0,
734
735 # Receive Ports - RX8B/10B Decoder Ports
736 #o_RXCHARISCOMMA=,
737 o_RXCHARISK=self.rxcharisk,
738
739 # Receive Ports - Rx Channel Bonding Ports
740 i_RXCHBONDI=0,
741
742 # Receive Ports -RX Initialization and Reset Ports
743 o_RXRESETDONE=rxresetdone,
744
745 # Rx AFE Ports
746 i_RXQPIEN=0,
747 #o_RXQPISENN=,
748 #o_RXQPISENP=,
749
750 # TX Buffer Bypass Ports
751 i_TXPHDLYTSTCLK=0,
752
753 # TX Configurable Driver Ports
754 i_TXPOSTCURSOR=0,
755 i_TXPOSTCURSORINV=0,
756 i_TXPRECURSOR=0,
757 i_TXPRECURSORINV=0,
758 i_TXQPIBIASEN=0,
759 i_TXQPISTRONGPDOWN=0,
760 i_TXQPIWEAKPUP=0,
761
762 # TX Initialization and Reset Ports
763 i_CFGRESET=0,
764 i_GTTXRESET=self.gttxreset,
765 #o_PCSRSVDOUT=,
766 i_TXUSERRDY=txuserrdy,
767
768 # Transceiver Reset Mode Operation
769 i_GTRESETSEL=0,
770 i_RESETOVRD=0,
771
772 # Transmit Ports - 8b10b Encoder Control Ports
773 i_TXCHARDISPMODE=0,
774 i_TXCHARDISPVAL=0,
775
776 # Transmit Ports - FPGA TX Interface Ports
777 i_TXUSRCLK=self.txusrclk,
778 i_TXUSRCLK2=self.txusrclk2,
779
780 # Transmit Ports - PCI Express Ports
781 i_TXELECIDLE=txelecidle,
782 i_TXMARGIN=0,
783 i_TXRATE=txrate,
784 i_TXSWING=0,
785
786 # Transmit Ports - Pattern Generator Ports
787 i_TXPRBSFORCEERR=0,
788
789 # Transmit Ports - TX Buffer Bypass Ports
790 i_TXDLYBYPASS=0,
791 i_TXDLYEN=txdlyen,
792 i_TXDLYHOLD=0,
793 i_TXDLYOVRDEN=0,
794 i_TXDLYSRESET=txdlysreset,
795 o_TXDLYSRESETDONE=txdlysresetdone,
796 i_TXDLYUPDOWN=0,
797 i_TXPHALIGN=txphalign,
798 o_TXPHALIGNDONE=txphaligndone,
799 i_TXPHALIGNEN=txphalignen,
800 i_TXPHDLYPD=0,
801 i_TXPHDLYRESET=txphdlyreset,
802 i_TXPHINIT=txphinit,
803 o_TXPHINITDONE=txphinitdone,
804 i_TXPHOVRDEN=0,
805
806 # Transmit Ports - TX Buffer Ports
807 #o_TXBUFSTATUS=,
808
809 # Transmit Ports - TX Configurable Driver Ports
810 i_TXBUFDIFFCTRL=0b100,
811 i_TXDEEMPH=0,
812 i_TXDIFFCTRL=0b1000,
813 i_TXDIFFPD=0,
814 i_TXINHIBIT=0,
815 i_TXMAINCURSOR=0,
816 i_TXPISOPD=0,
817
818 # Transmit Ports - TX Data Path interface
819 i_TXDATA=self.txdata,
820
821 # Transmit Ports - TX Driver and OOB signaling
822 o_GTXTXP=pads.txp,
823 o_GTXTXN=pads.txn,
824
825 # Transmit Ports - TX Fabric Clock Output Control Ports
826 o_TXOUTCLK=self.txoutclk,
827 #o_TXOUTCLKFABRIC=,
828 #o_TXOUTCLKPCS=,
829 i_TXOUTCLKSEL=0b11,
830 o_TXRATEDONE=txratedone,
831 # Transmit Ports - TX Gearbox Ports
832 i_TXCHARISK=self.txcharisk,
833 #o_TXGEARBOXREADY=,
834 i_TXHEADER=0,
835 i_TXSEQUENCE=0,
836 i_TXSTARTSEQ=0,
837
838 # Transmit Ports - TX Initialization and Reset Ports
839 i_TXPCSRESET=0,
840 i_TXPMARESET=0,
841 o_TXRESETDONE=txresetdone,
842
843 # Transmit Ports - TX OOB signalling Ports
844 o_TXCOMFINISH=txcomfinish,
845 i_TXCOMINIT=txcominit,
846 i_TXCOMSAS=0,
847 i_TXCOMWAKE=txcomwake,
848 i_TXPDELECIDLEMODE=0,
849
850 # Transmit Ports - TX Polarity Control Ports
851 i_TXPOLARITY=0,
852
853 # Transmit Ports - TX Receiver Detection Ports
854 i_TXDETECTRX=0,
855
856 # Transmit Ports - TX8b/10b Encoder Ports
857 i_TX8B10BBYPASS=0,
858
859 # Transmit Ports - pattern Generator Ports
860 i_TXPRBSSEL=0,
861
862 # Tx Configurable Driver Ports
863 #o_TXQPISENN=,
864 #o_TXQPISENP=,
865
866 **gtxe2_channel_parameters
867 )