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084266fd8a94ff3bc27b4e5d3a42284a83219363
[litex.git] / lib / sata / phy / k7sataphy / gtx.py
1 from migen.fhdl.std import *
2 from migen.genlib.cdc import *
3
4 from lib.sata.common import *
5
6 def ones(width):
7 return 2**width-1
8
9 class _PulseSynchronizer(PulseSynchronizer):
10 def __init__(self, i, idomain, o, odomain):
11 PulseSynchronizer.__init__(self, idomain, odomain)
12 self.comb += [
13 self.i.eq(i),
14 o.eq(self.o)
15 ]
16
17 class K7SATAPHYGTX(Module):
18 def __init__(self, pads, default_speed):
19 # Interface
20 # Channel - Ref Clock Ports
21 self.gtrefclk0 = Signal()
22
23 # Channel PLL
24 self.cplllock = Signal()
25 self.cpllreset = Signal()
26
27 # Receive Ports
28 self.rxuserrdy = Signal()
29 self.rxalign = Signal()
30
31 # Receive Ports - 8b10b Decoder
32 self.rxcharisk = Signal(2)
33 self.rxdisperr = Signal(2)
34
35 # Receive Ports - RX Data Path interface
36 self.gtrxreset = Signal()
37 self.pmarxreset = Signal()
38 self.rxdata = Signal(16)
39 self.rxoutclk = Signal()
40 self.rxusrclk = Signal()
41 self.rxusrclk2 = Signal()
42
43 # Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
44 self.rxelecidle = Signal()
45
46 # Receive Ports - RX PLL Ports
47 self.rxresetdone = Signal()
48
49 # Receive Ports - RX Ports for SATA
50 self.rxcominitdet = Signal()
51 self.rxcomwakedet = Signal()
52
53 # Transmit Ports
54 self.txuserrdy = Signal()
55
56 # Transmit Ports - 8b10b Encoder Control Ports
57 self.txcharisk = Signal(2)
58
59 # Transmit Ports - TX Data Path interface
60 self.gttxreset = Signal()
61 self.txdata = Signal(16)
62 self.txoutclk = Signal()
63 self.txusrclk = Signal()
64 self.txusrclk2 = Signal()
65
66 # Transmit Ports - TX PLL Ports
67 self.txresetdone = Signal()
68
69 # Transmit Ports - TX Ports for PCI Express
70 self.txelecidle = Signal(reset=1)
71
72 # Transmit Ports - TX Ports for SATA
73 self.txcomfinish = Signal()
74 self.txcominit = Signal()
75 self.txcomwake = Signal()
76 self.txrate = Signal(3)
77 self.rxcdrlock = Signal()
78
79 # Config at startup
80 div_config = {
81 "SATA1" : 4,
82 "SATA2" : 2,
83 "SATA3" : 1
84 }
85 rxout_div = div_config[default_speed]
86 txout_div = div_config[default_speed]
87
88 cdr_config = {
89 "SATA1" : 0x0380008BFF40100008,
90 "SATA2" : 0x0388008BFF40200008,
91 "SATA3" : 0X0380008BFF10200010
92 }
93 rxcdr_cfg = cdr_config[default_speed]
94
95 # Internals and clock domain crossing
96 # sys_clk --> sata_tx clk
97 txuserrdy = Signal()
98 txelecidle = Signal(reset=1)
99 txcominit = Signal()
100 txcomwake = Signal()
101 txrate = Signal(3)
102
103 self.specials += [
104 MultiReg(self.txuserrdy, txuserrdy, "sata_tx"),
105 MultiReg(self.txelecidle, txelecidle, "sata_tx"),
106 MultiReg(self.txrate, txrate, "sata_tx")
107 ]
108 self.submodules += [
109 _PulseSynchronizer(self.txcominit, "sys", txcominit, "sata_tx"),
110 _PulseSynchronizer(self.txcomwake, "sys", txcomwake, "sata_tx"),
111 ]
112
113 # sata_tx clk --> sys clk
114 txresetdone = Signal()
115 txcomfinish = Signal()
116
117 self.specials += [
118 MultiReg(txresetdone, self.txresetdone, "sys"),
119 ]
120
121 self.submodules += [
122 _PulseSynchronizer(txcomfinish, "sata_tx", self.txcomfinish, "sys"),
123 ]
124
125 # sys clk --> sata_rx clk
126 rxuserrdy = Signal()
127
128 self.specials += [
129 MultiReg(self.rxuserrdy, rxuserrdy, "sata_rx"),
130 ]
131
132 # sata_rx clk --> sys clk
133 rxelecidle = Signal()
134 rxelecidle_i = Signal()
135 rxelecidle_cnt_i = Signal(9)
136 rxresetdone = Signal()
137 rxcominitdet = Signal()
138 rxcomwakedet = Signal()
139 rxratedone = Signal()
140 rxcdrlock = Signal()
141
142 self.specials += [
143 MultiReg(rxelecidle, rxelecidle_i, "sys"),
144 MultiReg(rxresetdone, self.rxresetdone, "sys"),
145 MultiReg(rxcominitdet, self.rxcominitdet, "sys"),
146 MultiReg(rxcomwakedet, self.rxcomwakedet, "sys"),
147 MultiReg(rxcdrlock, self.rxcdrlock, "sys"),
148 ]
149
150 self.sync += [
151 If(rxelecidle_i != self.rxelecidle,
152 If(rxelecidle_cnt_i == 0,
153 self.rxelecidle.eq(rxelecidle_i),
154 rxelecidle_cnt_i.eq(255)
155 ).Else(
156 rxelecidle_cnt_i.eq(rxelecidle_cnt_i-1)
157 )
158 ).Else(
159 rxelecidle_cnt_i.eq(255)
160 )
161 ]
162
163 self.rxbyteisaligned = Signal()
164
165 # QPLL input clock
166 self.qpllclk = Signal()
167 self.qpllrefclk = Signal()
168
169 # Instance
170 gtxe2_channel_parameters = {
171 # Simulation-Only Attributes
172 "p_SIM_RECEIVER_DETECT_PASS":"TRUE",
173 "p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
174 "p_SIM_RESET_SPEEDUP":"TRUE",
175 "p_SIM_CPLLREFCLK_SEL":0b001,
176 "p_SIM_VERSION":"4.0",
177
178 # RX Byte and Word Alignment Attributes
179 "p_ALIGN_COMMA_DOUBLE":"FALSE",
180 "p_ALIGN_COMMA_ENABLE":ones(10),
181 "p_ALIGN_COMMA_WORD":2,
182 "p_ALIGN_MCOMMA_DET":"TRUE",
183 "p_ALIGN_MCOMMA_VALUE":0b1010000011,
184 "p_ALIGN_PCOMMA_DET":"TRUE",
185 "p_ALIGN_PCOMMA_VALUE":0b0101111100,
186 "p_SHOW_REALIGN_COMMA":"FALSE",
187 "p_RXSLIDE_AUTO_WAIT":7,
188 "p_RXSLIDE_MODE":"PCS",
189 "p_RX_SIG_VALID_DLY":10,
190
191 # RX 8B/10B Decoder Attributes
192 "p_RX_DISPERR_SEQ_MATCH":"TRUE",
193 "p_DEC_MCOMMA_DETECT":"TRUE",
194 "p_DEC_PCOMMA_DETECT":"TRUE",
195 "p_DEC_VALID_COMMA_ONLY":"FALSE",
196
197 # RX Clock Correction Attributes
198 "p_CBCC_DATA_SOURCE_SEL":"DECODED",
199 "p_CLK_COR_SEQ_2_USE":"FALSE",
200 "p_CLK_COR_KEEP_IDLE":"FALSE",
201 "p_CLK_COR_MAX_LAT":9,
202 "p_CLK_COR_MIN_LAT":7,
203 "p_CLK_COR_PRECEDENCE":"TRUE",
204 "p_CLK_COR_REPEAT_WAIT":0,
205 "p_CLK_COR_SEQ_LEN":1,
206 "p_CLK_COR_SEQ_1_ENABLE":ones(4),
207 "p_CLK_COR_SEQ_1_1":0b0100000000,
208 "p_CLK_COR_SEQ_1_2":0b0000000000,
209 "p_CLK_COR_SEQ_1_3":0b0000000000,
210 "p_CLK_COR_SEQ_1_4":0b0000000000,
211 "p_CLK_CORRECT_USE":"FALSE",
212 "p_CLK_COR_SEQ_2_ENABLE":ones(4),
213 "p_CLK_COR_SEQ_2_1":0b0100000000,
214 "p_CLK_COR_SEQ_2_2":0,
215 "p_CLK_COR_SEQ_2_3":0,
216 "p_CLK_COR_SEQ_2_4":0,
217
218 # RX Channel Bonding Attributes
219 "p_CHAN_BOND_KEEP_ALIGN":"FALSE",
220 "p_CHAN_BOND_MAX_SKEW":1,
221 "p_CHAN_BOND_SEQ_LEN":1,
222 "p_CHAN_BOND_SEQ_1_1":0,
223 "p_CHAN_BOND_SEQ_1_1":0,
224 "p_CHAN_BOND_SEQ_1_2":0,
225 "p_CHAN_BOND_SEQ_1_3":0,
226 "p_CHAN_BOND_SEQ_1_4":0,
227 "p_CHAN_BOND_SEQ_1_ENABLE":ones(4),
228 "p_CHAN_BOND_SEQ_2_1":0,
229 "p_CHAN_BOND_SEQ_2_2":0,
230 "p_CHAN_BOND_SEQ_2_3":0,
231 "p_CHAN_BOND_SEQ_2_4":0,
232 "p_CHAN_BOND_SEQ_2_ENABLE":ones(4),
233 "p_CHAN_BOND_SEQ_2_USE":"FALSE",
234 "p_FTS_DESKEW_SEQ_ENABLE":ones(4),
235 "p_FTS_LANE_DESKEW_CFG":ones(4),
236 "p_FTS_LANE_DESKEW_EN":"FALSE",
237
238 # RX Margin Analysis Attributes
239 "p_ES_CONTROL":0,
240 "p_ES_ERRDET_EN":"FALSE",
241 "p_ES_EYE_SCAN_EN":"TRUE",
242 "p_ES_HORZ_OFFSET":0,
243 "p_ES_PMA_CFG":0,
244 "p_ES_PRESCALE":0,
245 "p_ES_QUALIFIER":0,
246 "p_ES_QUAL_MASK":0,
247 "p_ES_SDATA_MASK":0,
248 "p_ES_VERT_OFFSET":0,
249
250 # FPGA RX Interface Attributes
251 "p_RX_DATA_WIDTH":20,
252
253 # PMA Attributes
254 "p_OUTREFCLK_SEL_INV":0b11,
255 "p_PMA_RSV":0x00018480,
256 "p_PMA_RSV2":0x2050,
257 "p_PMA_RSV3":0,
258 "p_PMA_RSV4":0,
259 "p_RX_BIAS_CFG":0b100,
260 "p_DMONITOR_CFG":0xA00,
261 "p_RX_CM_SEL":0b11,
262 "p_RX_CM_TRIM":0b010,
263 "p_RX_DEBUG_CFG":0,
264 "p_RX_OS_CFG":0b10000000,
265 "p_TERM_RCAL_CFG":0,
266 "p_TERM_RCAL_OVRD":0,
267 "p_TST_RSV":0,
268 "p_RX_CLK25_DIV":6,
269 "p_TX_CLK25_DIV":6,
270 "p_UCODEER_CLR":0,
271
272 # PCI Express Attributes
273 "p_PCS_PCIE_EN":"FALSE",
274
275 # PCS Attributes
276 "p_PCS_RSVD_ATTR":0x100,
277
278 # RX Buffer Attributes
279 "p_RXBUF_ADDR_MODE":"FAST",
280 "p_RXBUF_EIDLE_HI_CNT":0b1000,
281 "p_RXBUF_EIDLE_LO_CNT":0,
282 "p_RXBUF_EN":"TRUE",
283 "p_RX_BUFFER_CFG":0,
284 "p_RXBUF_RESET_ON_CB_CHANGE":"TRUE",
285 "p_RXBUF_RESET_ON_COMMAALIGN":"FALSE",
286 "p_RXBUF_RESET_ON_EIDLE":"FALSE",
287 "p_RXBUF_RESET_ON_RATE_CHANGE":"TRUE",
288 "p_RXBUFRESET_TIME":1,
289 "p_RXBUF_THRESH_OVFLW":61,
290 "p_RXBUF_THRESH_OVRD":"FALSE",
291 "p_RXBUF_THRESH_UNDFLW":4,
292 "p_RXDLY_CFG":0x1f,
293 "p_RXDLY_LCFG":0x30,
294 "p_RXDLY_TAP_CFG":0,
295 "p_RXPH_CFG":0,
296 "p_RXPHDLY_CFG":0x084820,
297 "p_RXPH_MONITOR_SEL":0,
298 "p_RX_XCLK_SEL":"RXUSR",
299 "p_RX_DDI_SEL":0,
300 "p_RX_DEFER_RESET_BUF_EN":"TRUE",
301
302 #CDR Attributes
303 "p_RXCDR_CFG":rxcdr_cfg,
304 "p_RXCDR_FR_RESET_ON_EIDLE":0,
305 "p_RXCDR_HOLD_DURING_EIDLE":0,
306 "p_RXCDR_PH_RESET_ON_EIDLE":0,
307 "p_RXCDR_LOCK_CFG":0b010101,
308
309 # RX Initialization and Reset Attributes
310 "p_RXCDRFREQRESET_TIME":1,
311 "p_RXCDRPHRESET_TIME":1,
312 "p_RXISCANRESET_TIME":1,
313 "p_RXPCSRESET_TIME":1,
314 "p_RXPMARESET_TIME":3,
315
316 # RX OOB Signaling Attributes
317 "p_RXOOB_CFG":0b0000110,
318
319 # RX Gearbox Attributes
320 "p_RXGEARBOX_EN":"FALSE",
321 "p_GEARBOX_MODE":0,
322
323 # PRBS Detection Attribute
324 "p_RXPRBS_ERR_LOOPBACK":0,
325
326 # Power-Down Attributes
327 "p_PD_TRANS_TIME_FROM_P2":0x03c,
328 "p_PD_TRANS_TIME_NONE_P2":0x3c,
329 "p_PD_TRANS_TIME_TO_P2":0x64,
330
331 # RX OOB Signaling Attributes
332 "p_SAS_MAX_COM":64,
333 "p_SAS_MIN_COM":36,
334 "p_SATA_BURST_SEQ_LEN":0b0101,
335 "p_SATA_BURST_VAL":0b100,
336 "p_SATA_EIDLE_VAL":0b100,
337 "p_SATA_MAX_BURST":8,
338 "p_SATA_MAX_INIT":21,
339 "p_SATA_MAX_WAKE":7,
340 "p_SATA_MIN_BURST":4,
341 "p_SATA_MIN_INIT":12,
342 "p_SATA_MIN_WAKE":4,
343
344 # RX Fabric Clock Output Control Attributes
345 "p_TRANS_TIME_RATE":0x0e,
346
347 # TX Buffer Attributes
348 "p_TXBUF_EN":"TRUE",
349 "p_TXBUF_RESET_ON_RATE_CHANGE":"TRUE",
350 "p_TXDLY_CFG":0x1f,
351 "p_TXDLY_LCFG":0x030,
352 "p_TXDLY_TAP_CFG":0,
353 "p_TXPH_CFG":0x0780,
354 "p_TXPHDLY_CFG":0x084020,
355 "p_TXPH_MONITOR_SEL":0,
356 "p_TX_XCLK_SEL":"TXOUT",
357
358 # FPGA TX Interface Attributes
359 "p_TX_DATA_WIDTH":20,
360
361 # TX Configurable Driver Attributes
362 "p_TX_DEEMPH0":0,
363 "p_TX_DEEMPH1":0,
364 "p_TX_EIDLE_ASSERT_DELAY":0b110,
365 "p_TX_EIDLE_DEASSERT_DELAY":0b100,
366 "p_TX_LOOPBACK_DRIVE_HIZ":"FALSE",
367 "p_TX_MAINCURSOR_SEL":0,
368 "p_TX_DRIVE_MODE":"DIRECT",
369 "p_TX_MARGIN_FULL_0":0b1001110,
370 "p_TX_MARGIN_FULL_1":0b1001001,
371 "p_TX_MARGIN_FULL_2":0b1000101,
372 "p_TX_MARGIN_FULL_3":0b1000010,
373 "p_TX_MARGIN_FULL_4":0b1000000,
374 "p_TX_MARGIN_LOW_0":0b1000110,
375 "p_TX_MARGIN_LOW_1":0b1000100,
376 "p_TX_MARGIN_LOW_2":0b1000010,
377 "p_TX_MARGIN_LOW_3":0b1000000,
378 "p_TX_MARGIN_LOW_4":0b1000000,
379
380 # TX Gearbox Attributes
381 "p_TXGEARBOX_EN":"FALSE",
382
383 # TX Initialization and Reset Attributes
384 "p_TXPCSRESET_TIME":1,
385 "p_TXPMARESET_TIME":1,
386
387 # TX Receiver Detection Attributes
388 "p_TX_RXDETECT_CFG":0x1832,
389 "p_TX_RXDETECT_REF":0b100,
390
391 # CPLL Attributes
392 "p_CPLL_CFG":0xBC07DC,
393 "p_CPLL_FBDIV":4,
394 "p_CPLL_FBDIV_45":5,
395 "p_CPLL_INIT_CFG":0x00001e,
396 "p_CPLL_LOCK_CFG":0x01e8,
397 "p_CPLL_REFCLK_DIV":1,
398 "p_RXOUT_DIV":rxout_div,
399 "p_TXOUT_DIV":txout_div,
400 "p_SATA_CPLL_CFG":"VCO_3000MHZ",
401
402 # RX Initialization and Reset Attributes
403 "p_RXDFELPMRESET_TIME":0b0001111,
404
405 # RX Equalizer Attributes
406 "p_RXLPM_HF_CFG":0b00000011110000,
407 "p_RXLPM_LF_CFG":0b00000011110000,
408 "p_RX_DFE_GAIN_CFG":0x020fea,
409 "p_RX_DFE_H2_CFG":0b000000000000,
410 "p_RX_DFE_H3_CFG":0b000001000000,
411 "p_RX_DFE_H4_CFG":0b00011110000,
412 "p_RX_DFE_H5_CFG":0b00011100000,
413 "p_RX_DFE_KL_CFG":0b0000011111110,
414 "p_RX_DFE_LPM_CFG":0x0954,
415 "p_RX_DFE_LPM_HOLD_DURING_EIDLE":0,
416 "p_RX_DFE_UT_CFG":0b10001111000000000,
417 "p_RX_DFE_VP_CFG":0b00011111100000011,
418
419 # Power-Down Attributes
420 "p_RX_CLKMUX_PD":1,
421 "p_TX_CLKMUX_PD":1,
422
423 # FPGA RX Interface Attribute
424 "p_RX_INT_DATAWIDTH":0,
425
426 # FPGA TX Interface Attribute
427 "p_TX_INT_DATAWIDTH":0,
428
429 # TX Configurable Driver Attributes
430 "p_TX_QPI_STATUS_EN":0,
431
432 # RX Equalizer Attributes
433 "p_RX_DFE_KL_CFG2":0b00110011000100000001100000001100,
434 "p_RX_DFE_XYD_CFG":0b0000000000000,
435
436 # TX Configurable Driver Attributes
437 "p_TX_PREDRIVER_MODE":0,
438 }
439
440 self.specials += \
441 Instance("GTXE2_CHANNEL",
442 # CPLL Ports
443 #o_CPLLFBCLKLOST=,
444 o_CPLLLOCK=self.cplllock,
445 i_CPLLLOCKDETCLK=0,
446 i_CPLLLOCKEN=1,
447 i_CPLLPD=0,
448 #o_CPLLREFCLKLOST=0,
449 i_CPLLREFCLKSEL=0b001,
450 i_CPLLRESET=self.cpllreset,
451 i_GTRSVD=0,
452 i_PCSRSVDIN=0,
453 i_PCSRSVDIN2=0,
454 i_PMARSVDIN=0,
455 i_PMARSVDIN2=0,
456 i_TSTIN=ones(20),
457 #o_TSTOUT=,
458
459 # Channel
460 i_CLKRSVD=0,
461
462 # Channel - Clocking Ports
463 i_GTGREFCLK=0,
464 i_GTNORTHREFCLK0=0,
465 i_GTNORTHREFCLK1=0,
466 i_GTREFCLK0=self.gtrefclk0,
467 i_GTREFCLK1=0,
468 i_GTSOUTHREFCLK0=0,
469 i_GTSOUTHREFCLK1=0,
470
471 # Channel - DRP Ports
472 i_DRPADDR=0,
473 i_DRPCLK=0,
474 i_DRPDI=0,
475 #o_DRPDO=,
476 i_DRPEN=0,
477 #o_DRPRDY=,
478 i_DRPWE=0,
479
480 # Clocking Ports
481 #o_GTREFCLKMONITOR=,
482 i_QPLLCLK=self.qpllclk,
483 i_QPLLREFCLK=self.qpllrefclk,
484 i_RXSYSCLKSEL=0b00,
485 i_TXSYSCLKSEL=0b00,
486
487 # Digital Monitor Ports
488 #o_DMONITOROUT=,
489
490 # FPGA TX Interface Datapath Configuration
491 i_TX8B10BEN=1,
492
493 # Loopback Ports
494 i_LOOPBACK=0,
495
496 # PCI Express Ports
497 #o_PHYSTATUS=,
498 i_RXRATE=0,
499 #o_RXVALID=,
500
501 # Power-Down Ports
502 i_RXPD=0b00,
503 i_TXPD=0b00,
504
505 # RX 8B/10B Decoder Ports
506 i_SETERRSTATUS=0,
507
508 # RX Initialization and Reset Ports
509 i_EYESCANRESET=0,
510 i_RXUSERRDY=rxuserrdy,
511
512 # RX Margin Analysis Ports
513 #o_EYESCANDATAERROR=,
514 i_EYESCANMODE=0,
515 i_EYESCANTRIGGER=0,
516
517 # Receive Ports - CDR Ports
518 i_RXCDRFREQRESET=0,
519 i_RXCDRHOLD=0,
520 o_RXCDRLOCK=rxcdrlock,
521 i_RXCDROVRDEN=0,
522 i_RXCDRRESET=0,
523 i_RXCDRRESETRSV=0,
524
525 # Receive Ports - Clock Correction Ports
526 #o_RXCLKCORCNT=,
527
528 # Receive Ports - FPGA RX Interface Datapath Configuration
529 i_RX8B10BEN=1,
530
531 # Receive Ports - FPGA RX Interface Ports
532 i_RXUSRCLK=self.rxusrclk,
533 i_RXUSRCLK2=self.rxusrclk2,
534
535 # Receive Ports - FPGA RX interface Ports
536 o_RXDATA=self.rxdata,
537
538 # Receive Ports - Pattern Checker Ports
539 #o_RXPRBSERR=,
540 i_RXPRBSSEL=0,
541
542 # Receive Ports - Pattern Checker ports
543 i_RXPRBSCNTRESET=0,
544
545 # Receive Ports - RX Equalizer Ports
546 i_RXDFEXYDEN=0,
547 i_RXDFEXYDHOLD=0,
548 i_RXDFEXYDOVRDEN=0,
549
550 # Receive Ports - RX 8B/10B Decoder Ports
551 #o_RXDISPERR=,
552 #o_RXNOTINTABLE=,
553
554 # Receive Ports - RX AFE
555 i_GTXRXP=pads.rxp,
556 i_GTXRXN=pads.rxn,
557
558 # Receive Ports - RX Buffer Bypass Ports
559 i_RXBUFRESET=0,
560 #o_RXBUFSTATUS=,
561 i_RXDDIEN=0,
562 i_RXDLYBYPASS=1,
563 i_RXDLYEN=0,
564 i_RXDLYOVRDEN=0,
565 i_RXDLYSRESET=0,
566 #o_RXDLYSRESETDONE=0,
567 i_RXPHALIGN=0,
568 #o_RXPHALIGNDONE=,
569 i_RXPHALIGNEN=0,
570 i_RXPHDLYPD=0,
571 i_RXPHDLYRESET=0,
572 #o_RXPHMONITOR=,
573 i_RXPHOVRDEN=0,
574 #o_RXPHSLIPMONITOR=,
575 #o_RXSTATUS=,
576
577 # Receive Ports - RX Byte and Word Alignment Ports
578 o_RXBYTEISALIGNED=self.rxbyteisaligned,
579 #o_RXBYTEREALIGN=,
580 #o_RXCOMMADET=,
581 i_RXCOMMADETEN=1,
582 i_RXMCOMMAALIGNEN=1,
583 i_RXPCOMMAALIGNEN=1,
584
585 # Receive Ports - RX Channel Bonding Ports
586 #o_RXCHANBONDSEQ=,
587 i_RXCHBONDEN=0,
588 i_RXCHBONDLEVEL=0,
589 i_RXCHBONDMASTER=0,
590 #o_RXCHBONDO=,
591 i_RXCHBONDSLAVE=0,
592
593 # Receive Ports - RX Channel Bonding Ports
594 #o_RXCHANISALIGNED=,
595 #o_RXCHANREALIGN=,
596
597 # Receive Ports - RX Equalizer Ports
598 i_RXDFEAGCHOLD=0,
599 i_RXDFEAGCOVRDEN=0,
600 i_RXDFECM1EN=0,
601 i_RXDFELFHOLD=0,
602 i_RXDFELFOVRDEN=1,
603 i_RXDFELPMRESET=0,
604 i_RXDFETAP2HOLD=0,
605 i_RXDFETAP2OVRDEN=0,
606 i_RXDFETAP3HOLD=0,
607 i_RXDFETAP3OVRDEN=0,
608 i_RXDFETAP4HOLD=0,
609 i_RXDFETAP4OVRDEN=0,
610 i_RXDFETAP5HOLD=0,
611 i_RXDFETAP5OVRDEN=0,
612 i_RXDFEUTHOLD=0,
613 i_RXDFEUTOVRDEN=0,
614 i_RXDFEVPHOLD=0,
615 i_RXDFEVPOVRDEN=0,
616 i_RXDFEVSEN=0,
617 i_RXLPMLFKLOVRDEN=0,
618 #o_RXMONITOROUT=,
619 i_RXMONITORSEL=0b00,
620 i_RXOSHOLD=0,
621 i_RXOSOVRDEN=0,
622
623 # Receive Ports - RX Equilizer Ports
624 i_RXLPMHFHOLD=0,
625 i_RXLPMHFOVRDEN=0,
626 i_RXLPMLFHOLD=0,
627
628 # Receive Ports - RX Fabric ClocK Output Control Ports
629 #o_RXRATEDONE=,
630
631 # Receive Ports - RX Fabric Output Control Ports
632 o_RXOUTCLK=self.rxoutclk,
633 #o_RXOUTCLKFABRIC=,
634 #o_RXOUTCLKPCS=,
635 i_RXOUTCLKSEL=0b010,
636
637 # Receive Ports - RX Gearbox Ports
638 #o_RXDATAVALID=,
639 #o_RXHEADER=,
640 #o_RXHEADERVALID=,
641 #o_RXSTARTOFSEQ=,
642
643 # Receive Ports - RX Gearbox Ports
644 i_RXGEARBOXSLIP=0,
645
646 # Receive Ports - RX Initialization and Reset Ports
647 i_GTRXRESET=self.gtrxreset,
648 i_RXOOBRESET=0,
649 i_RXPCSRESET=0,
650 i_RXPMARESET=self.pmarxreset,
651
652 # Receive Ports - RX Margin Analysis ports
653 i_RXLPMEN=0,
654
655 # Receive Ports - RX OOB Signaling ports
656 #o_RXCOMSASDET=,
657 o_RXCOMWAKEDET=rxcomwakedet,
658
659 # Receive Ports - RX OOB Signaling ports
660 o_RXCOMINITDET=rxcominitdet,
661
662 # Receive Ports - RX OOB signalling Ports
663 o_RXELECIDLE=rxelecidle,
664 i_RXELECIDLEMODE=0b00,
665
666 # Receive Ports - RX Polarity Control Ports
667 i_RXPOLARITY=0,
668
669 # Receive Ports - RX gearbox ports
670 i_RXSLIDE=0,
671
672 # Receive Ports - RX8B/10B Decoder Ports
673 #o_RXCHARISCOMMA=,
674 o_RXCHARISK=self.rxcharisk,
675
676 # Receive Ports - Rx Channel Bonding Ports
677 i_RXCHBONDI=0,
678
679 # Receive Ports -RX Initialization and Reset Ports
680 o_RXRESETDONE=rxresetdone,
681
682 # Rx AFE Ports
683 i_RXQPIEN=0,
684 #o_RXQPISENN=,
685 #o_RXQPISENP=,
686
687 # TX Buffer Bypass Ports
688 i_TXPHDLYTSTCLK=0,
689
690 # TX Configurable Driver Ports
691 i_TXPOSTCURSOR=0,
692 i_TXPOSTCURSORINV=0,
693 i_TXPRECURSOR=0,
694 i_TXPRECURSORINV=0,
695 i_TXQPIBIASEN=0,
696 i_TXQPISTRONGPDOWN=0,
697 i_TXQPIWEAKPUP=0,
698
699 # TX Initialization and Reset Ports
700 i_CFGRESET=0,
701 i_GTTXRESET=self.gttxreset,
702 #o_PCSRSVDOUT=,
703 i_TXUSERRDY=txuserrdy,
704
705 # Transceiver Reset Mode Operation
706 i_GTRESETSEL=0,
707 i_RESETOVRD=0,
708
709 # Transmit Ports - 8b10b Encoder Control Ports
710 i_TXCHARDISPMODE=0,
711 i_TXCHARDISPVAL=0,
712
713 # Transmit Ports - FPGA TX Interface Ports
714 i_TXUSRCLK=self.txusrclk,
715 i_TXUSRCLK2=self.txusrclk2,
716
717 # Transmit Ports - PCI Express Ports
718 i_TXELECIDLE=txelecidle,
719 i_TXMARGIN=0,
720 i_TXRATE=txrate,
721 i_TXSWING=0,
722
723 # Transmit Ports - Pattern Generator Ports
724 i_TXPRBSFORCEERR=0,
725
726 # Transmit Ports - TX Buffer Bypass Ports
727 i_TXDLYBYPASS=1,
728 i_TXDLYEN=0,
729 i_TXDLYHOLD=0,
730 i_TXDLYOVRDEN=0,
731 i_TXDLYSRESET=0,
732 #o_TXDLYSRESETDONE=,
733 i_TXDLYUPDOWN=0,
734 i_TXPHALIGN=0,
735 #o_TXPHALIGNDONE=txphaligndone,
736 i_TXPHALIGNEN=0,
737 i_TXPHDLYPD=0,
738 i_TXPHDLYRESET=0,
739 i_TXPHINIT=0,
740 #o_TXPHINITDONE=,
741 i_TXPHOVRDEN=0,
742
743 # Transmit Ports - TX Buffer Ports
744 #o_TXBUFSTATUS=,
745
746 # Transmit Ports - TX Configurable Driver Ports
747 i_TXBUFDIFFCTRL=0b100,
748 i_TXDEEMPH=0,
749 i_TXDIFFCTRL=0b1000,
750 i_TXDIFFPD=0,
751 i_TXINHIBIT=0,
752 i_TXMAINCURSOR=0,
753 i_TXPISOPD=0,
754
755 # Transmit Ports - TX Data Path interface
756 i_TXDATA=self.txdata,
757
758 # Transmit Ports - TX Driver and OOB signaling
759 o_GTXTXP=pads.txp,
760 o_GTXTXN=pads.txn,
761
762 # Transmit Ports - TX Fabric Clock Output Control Ports
763 o_TXOUTCLK=self.txoutclk,
764 #o_TXOUTCLKFABRIC=,
765 #o_TXOUTCLKPCS=,
766 i_TXOUTCLKSEL=0b11, #??
767 #o_TXRATEDONE=,
768 # Transmit Ports - TX Gearbox Ports
769 i_TXCHARISK=self.txcharisk,
770 #o_TXGEARBOXREADY=,
771 i_TXHEADER=0,
772 i_TXSEQUENCE=0,
773 i_TXSTARTSEQ=0,
774
775 # Transmit Ports - TX Initialization and Reset Ports
776 i_TXPCSRESET=0,
777 i_TXPMARESET=0,
778 o_TXRESETDONE=txresetdone,
779
780 # Transmit Ports - TX OOB signalling Ports
781 o_TXCOMFINISH=txcomfinish,
782 i_TXCOMINIT=txcominit,
783 i_TXCOMSAS=0,
784 i_TXCOMWAKE=txcomwake,
785 i_TXPDELECIDLEMODE=0,
786
787 # Transmit Ports - TX Polarity Control Ports
788 i_TXPOLARITY=0,
789
790 # Transmit Ports - TX Receiver Detection Ports
791 i_TXDETECTRX=0,
792
793 # Transmit Ports - TX8b/10b Encoder Ports
794 i_TX8B10BBYPASS=0,
795
796 # Transmit Ports - pattern Generator Ports
797 i_TXPRBSSEL=0,
798
799 # Tx Configurable Driver Ports
800 #o_TXQPISENN=,
801 #o_TXQPISENP=,
802
803 **gtxe2_channel_parameters
804 )
805
806
807 class GTXE2_COMMON(Module):
808 def __init__(self, fbdiv=16):
809 self.refclk0 = Signal()
810
811 self.qpllclk = Signal()
812 self.qpllrefclk = Signal()
813
814 # fbdiv config
815 fbdiv_in_config = {
816 16 : 0b0000100000,
817 20 : 0b0000110000,
818 32 : 0b0001100000,
819 40 : 0b0010000000,
820 64 : 0b0011100000,
821 66 : 0b0101000000,
822 80 : 0b0100100000,
823 100 : 0b0101110000
824 }
825 fbdiv_in = fbdiv_in_config[fbdiv]
826
827 fbdiv_ratio_config = {
828 16 : 0b1,
829 20 : 0b1,
830 32 : 0b1,
831 40 : 0b1,
832 64 : 0b1,
833 66 : 0b0,
834 80 : 0b1,
835 100 : 0b1
836 }
837 fbdiv_ratio = fbdiv_ratio_config[fbdiv]
838
839 self.specials += \
840 Instance("GTXE2_COMMON",
841 # Simulation attributes
842 p_SIM_RESET_SPEEDUP="TRUE",
843 p_SIM_QPLLREFCLK_SEL=0b001,
844 p_SIM_VERSION="4.0",
845
846 # Common block attributes
847 p_BIAS_CFG=0x0000040000001000,
848 p_COMMON_CFG=0,
849 p_QPLL_CFG=0x06801c1,
850 p_QPLL_CLKOUT_CFG=0,
851 p_QPLL_COARSE_FREQ_OVRD=0b010000,
852 p_QPLL_COARSE_FREQ_OVRD_EN=0,
853 p_QPLL_CP=0b0000011111,
854 p_QPLL_CP_MONITOR_EN=0,
855 p_QPLL_DMONITOR_SEL=0,
856 p_QPLL_FBDIV=fbdiv_in,
857 p_QPLL_FBDIV_MONITOR_EN=0,
858 p_QPLL_FBDIV_RATIO=fbdiv_ratio,
859 p_QPLL_INIT_CFG=0x000006,
860 p_QPLL_LOCK_CFG=0x21e9,
861 p_QPLL_LPF=0b1111,
862 p_QPLL_REFCLK_DIV=1,
863
864 # Common block - Dynamic Reconfiguration Port (DRP)
865 i_DRPADDR=0,
866 i_DRPCLK=0,
867 i_DRPDI=0,
868 #o_DRPDO=,
869 i_DRPEN=0,
870 #o_DRPRDY=,
871 i_DRPWE=0,
872
873 # Common block - Ref Clock Ports
874 i_GTGREFCLK=0,
875 i_GTNORTHREFCLK0=0,
876 i_GTNORTHREFCLK1=0,
877 i_GTREFCLK0=self.refclk0,
878 i_GTREFCLK1=0,
879 i_GTSOUTHREFCLK0=0,
880 i_GTSOUTHREFCLK1=0,
881
882 # Common block - QPLL Ports
883 #o_QPLLDMONITOR=,
884 #o_QPLLFBCLKLOST=,
885 #o_QPLLLOCK=,
886 i_QPLLLOCKDETCLK=0,
887 i_QPLLLOCKEN=1,
888 o_QPLLOUTCLK=self.qpllclk,
889 o_QPLLOUTREFCLK=self.qpllrefclk,
890 i_QPLLOUTRESET=0,
891 i_QPLLPD=0,
892 #o_QPLLREFCLKLOST=,
893 i_QPLLREFCLKSEL=0b001,
894 i_QPLLRESET=0,
895 i_QPLLRSVD1=0,
896 i_QPLLRSVD2=ones(5),
897 #o_REFCLKOUTMONITOR=,
898
899 # Common block Ports
900 i_BGBYPASSB=1,
901 i_BGMONITORENB=1,
902 i_BGPDB=1,
903 i_BGRCALOVRD=0,
904 i_PMARSVD=0,
905 i_RCALENB=1
906 )