Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
[yosys.git] / libs / subcircuit / Makefile
1
2 CONFIG := clang-debug
3 # CONFIG := gcc-debug
4 # CONFIG := profile
5 # CONFIG := release
6
7 CC = clang
8 CXX = clang
9 CXXFLAGS = -MD -Wall -Wextra -ggdb
10 LDLIBS = -lstdc++
11
12 ifeq ($(CONFIG),clang-debug)
13 CXXFLAGS += -std=c++11 -O0
14 endif
15
16 ifeq ($(CONFIG),gcc-debug)
17 CC = gcc
18 CXX = gcc
19 CXXFLAGS += -std=gnu++0x -O0
20 endif
21
22 ifeq ($(CONFIG),profile)
23 CC = gcc
24 CXX = gcc
25 CXXFLAGS += -std=gnu++0x -Os -DNDEBUG
26 endif
27
28 ifeq ($(CONFIG),release)
29 CC = gcc
30 CXX = gcc
31 CXXFLAGS += -std=gnu++0x -march=native -O3 -DNDEBUG
32 endif
33
34 all: demo scshell
35
36 demo: demo.o subcircuit.o
37
38 scshell: scshell.o subcircuit.o
39
40 test: scshell
41 ./scshell < test_macc22.txt
42 ./scshell < test_mine.txt
43 perl test_perm.pl | ./scshell
44 splrun test_shorts.spl | ./scshell
45 splrun test_large.spl | ./scshell
46
47 clean:
48 rm -f demo scshell *.o *.d
49
50 .PHONY: all test clean
51
52 -include *.d
53