3 // Test procedure for matching Gates with shorted inputs, as suggested in
4 // "SubCircuit Extraction with SubGraph Isomorphism. Zong Ling, Ph. D. IBM
5 // Almaden Research Center -- EDA Shape Processing zling@us.ibm.com.":
7 // Four NAND gates and a NOR gate. One NAND gate (G1) has no shorted inputs,
8 // one (G2) has an input shorted to VSS, one (G3) has an input shorted to VDD,
9 // and one (G4) has both inputs shorted together. Th last gate (G5) is a NOR
16 net["${id}_VDD"] = "${id}_pa S";
17 net["${id}_VSS"] = "${id}_nb S";
19 net["${id}_A"] = "${id}_pa G";
20 net["${id}_B"] = "${id}_pb G";
21 net["${id}_Y"] = "${id}_pb D";
24 : node ${id}_pa pmos S 1 D 1 G 1
25 : node ${id}_pb pmos S 1 D 1 G 1
26 : node ${id}_na nmos S 1 D 1 G 1
27 : node ${id}_nb nmos S 1 D 1 G 1
28 : connect ${id}_pa S ${id}_pb S
29 : connect ${id}_pa D ${id}_pb D
30 : connect ${id}_pa D ${id}_na D
31 : connect ${id}_na S ${id}_nb D
32 : connect ${id}_pa G ${id}_na G
33 : connect ${id}_pb G ${id}_nb G
39 net["${id}_VDD"] = "${id}_pa S";
40 net["${id}_VSS"] = "${id}_nb S";
42 net["${id}_A"] = "${id}_pa G";
43 net["${id}_B"] = "${id}_pb G";
44 net["${id}_Y"] = "${id}_pb D";
47 : node ${id}_pa pmos S 1 D 1 G 1
48 : node ${id}_pb pmos S 1 D 1 G 1
49 : node ${id}_na nmos S 1 D 1 G 1
50 : node ${id}_nb nmos S 1 D 1 G 1
51 : connect ${id}_pa D ${id}_pb S
52 : connect ${id}_pb D ${id}_na D
53 : connect ${id}_pb D ${id}_nb D
54 : connect ${id}_na S ${id}_nb S
55 : connect ${id}_pa G ${id}_na G
56 : connect ${id}_pb G ${id}_nb G
63 : extern ${net["G0_VDD"]}
64 : extern ${net["G0_VSS"]}
65 : extern ${net["G0_A"]}
66 : extern ${net["G0_B"]}
67 : extern ${net["G0_Y"]}
72 : extern ${net["G0_VDD"]}
73 : extern ${net["G0_VSS"]}
74 : extern ${net["G0_A"]}
75 : extern ${net["G0_B"]}
76 : extern ${net["G0_Y"]}
86 : node vdd vsupply V 1
87 : connect vdd V ${net["G1_VDD"]}
88 : connect vdd V ${net["G2_VDD"]}
89 : connect vdd V ${net["G3_VDD"]}
90 : connect vdd V ${net["G4_VDD"]}
91 : connect vdd V ${net["G5_VDD"]}
93 : node vss vsupply V 1
94 : connect vss V ${net["G1_VSS"]}
95 : connect vss V ${net["G2_VSS"]}
96 : connect vss V ${net["G3_VSS"]}
97 : connect vss V ${net["G4_VSS"]}
98 : connect vss V ${net["G5_VSS"]}
100 : connect ${net["G2_A"]} ${net["G1_A"]}
101 : connect ${net["G2_B"]} ${net["G2_VSS"]}
103 : connect ${net["G3_A"]} ${net["G1_VDD"]}
104 : connect ${net["G3_B"]} ${net["G2_Y"]}
106 : connect ${net["G4_A"]} ${net["G1_Y"]}
107 : connect ${net["G4_B"]} ${net["G1_Y"]}
109 : connect ${net["G5_A"]} ${net["G3_Y"]}
110 : connect ${net["G5_B"]} ${net["G4_Y"]}
113 : solve nand haystack false
117 : solve nor haystack false