liteeth/core/etherbone/wishbone.py

   1 from liteeth.common import *
   2 from migen.bus import wishbone
   3
   4 class LiteEthEtherboneWishboneMaster(Module):
   5         def __init__(self):
   6                 self.wr_sink = wr_sink = Sink(eth_etherbone_mmap_description(32))
   7                 self.rd_sink = rd_sink = Sink(eth_etherbone_mmap_description(32))
   8                 self.wr_source = wr_source = Source(eth_etherbone_mmap_description(32))
   9                 self.rd_source = rd_source = Source(eth_etherbone_mmap_description(32))
  10                 self.bus = bus = wishbone.Interface()
  11                 ###s
  12
  13                 data = FlipFlop(32)
  14                 self.submodules += data
  15                 self.comb += data.d.eq(bus.dat_r)
  16
  17                 self.submodules.fsm = fsm = FSM(reset_state="IDLE")
  18                 fsm.act("IDLE",
  19                         wr_sink.ack.eq(1),
  20                         rd_sink.ack.eq(1),
  21                         If(wr_sink.stb & wr_sink.sop,
  22                                 wr_sink.ack.eq(0),
  23                                 NextState("WRITE_DATA")
  24                         ).Elif(rd_sink.stb & rd_sink.sop,
  25                                 rd_sink.ack.eq(0),
  26                                 NextState("READ_DATA")
  27                         )
  28                 )
  29                 fsm.act("WRITE_DATA",
  30                         bus.adr.eq(wr_sink.addr),
  31                         bus.dat_w.eq(wr_sink.data),
  32                         bus.sel.eq(wr_sink.be),
  33                         bus.stb.eq(wr_sink.stb),
  34                         bus.we.eq(1),
  35                         bus.cyc.eq(1),
  36                         If(bus.stb & bus.ack,
  37                                 wr_sink.ack.eq(1),
  38                                 If(wr_sink.eop,
  39                                         NextState("IDLE")
  40                                 )
  41                         )
  42                 )
  43                 fsm.act("READ_DATA",
  44                         bus.adr.eq(rd_sink.addr),
  45                         bus.sel.eq(rd_sink.be),
  46                         bus.stb.eq(rd_sink.stb),
  47                         bus.cyc.eq(1),
  48                         If(bus.stb & bus.ack,
  49                                 data.ce.eq(1),
  50                                 NextState("SEND_DATA")
  51                         )
  52                 )
  53                 fsm.act("SEND_DATA",
  54                         wr_source.stb.eq(rd_sink.stb),
  55                         wr_source.sop.eq(rd_sink.sop),
  56                         wr_source.eop.eq(rd_sink.eop),
  57                         wr_source.base_addr.eq(rd_sink.base_addr),
  58                         wr_source.addr.eq(rd_sink.addr),
  59                         wr_source.count.eq(rd_sink.count),
  60                         wr_source.be.eq(rd_sink.be),
  61                         wr_source.data.eq(data.q),
  62                         If(wr_source.stb & wr_source.ack,
  63                                 rd_sink.ack.eq(1),
  64                                 If(wr_source.eop,
  65                                         NextState("IDLE")
  66                                 ).Else(
  67                                         NextState("READ_DATA")
  68                                 )
  69                         )
  70                 )