1 from liteeth
.common
import *
2 from liteeth
.generic
.depacketizer
import LiteEthDepacketizer
3 from liteeth
.generic
.packetizer
import LiteEthPacketizer
4 from liteeth
.mac
.core
import LiteEthMACCore
5 from liteeth
.mac
.frontend
.wishbone
import LiteEthMACWishboneInterface
6 from liteeth
.mac
.frontend
.crossbar
import LiteEthMACCrossbar
8 class LiteEthMACDepacketizer(LiteEthDepacketizer
):
10 LiteEthDepacketizer
.__init
__(self
,
11 eth_phy_description(8),
12 eth_mac_description(8),
16 class LiteEthMACPacketizer(LiteEthPacketizer
):
18 LiteEthPacketizer
.__init
__(self
,
19 eth_mac_description(8),
20 eth_phy_description(8),
24 class LiteEthMAC(Module
, AutoCSR
):
25 def __init__(self
, phy
, dw
, interface
="crossbar", endianness
="be",
26 with_hw_preamble_crc
=True):
27 self
.submodules
.core
= LiteEthMACCore(phy
, dw
, endianness
, with_hw_preamble_crc
)
29 if interface
== "crossbar":
30 self
.submodules
.crossbar
= LiteEthMACCrossbar()
31 self
.submodules
.packetizer
= LiteEthMACPacketizer()
32 self
.submodules
.depacketizer
= LiteEthMACDepacketizer()
34 Record
.connect(self
.crossbar
.master
.source
, self
.packetizer
.sink
),
35 Record
.connect(self
.packetizer
.source
, self
.core
.sink
),
36 Record
.connect(self
.core
.source
, self
.depacketizer
.sink
),
37 Record
.connect(self
.depacketizer
.source
, self
.crossbar
.master
.sink
)
39 elif interface
== "wishbone":
40 self
.submodules
.interface
= wishbone
.LiteEthMACWishboneInterface(dw
, 2, 2)
42 Record
.connect(self
.interface
.source
, self
.core
.sink
),
43 Record
.connect(self
.core
.source
, self
.interface
.sink
)
45 self
.ev
, self
.bus
= self
.interface
.sram
.ev
, self
.interface
.bus
46 self
.csrs
= self
.interface
.get_csrs()
47 elif interface
== "dma":
48 raise NotImplementedError
50 raise ValueError(interface
+ " not supported by LiteEthMac!")