liteeth/mac/frontend/wishbone.py

   1 from liteeth.common import *
   2 from liteeth.mac.common import *
   3 from liteeth.mac.frontend import sram
   4
   5 from migen.bus import wishbone
   6 from migen.fhdl.simplify import FullMemoryWE
   7
   8 class LiteEthMACWishboneInterface(Module, AutoCSR):
   9         def __init__(self, dw, nrxslots=2, ntxslots=2):
  10                 self.sink = Sink(eth_phy_description(dw))
  11                 self.source = Source(eth_phy_description(dw))
  12                 self.bus = wishbone.Interface()
  13                 ###
  14                 # storage in SRAM
  15                 sram_depth = buffer_depth//(dw//8)
  16                 self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
  17                 self.comb += [
  18                         Record.connect(self.sink, self.sram.sink),
  19                         Record.connect(self.sram.source, self.source)
  20                 ]
  21
  22                 # Wishbone interface
  23                 wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
  24                         for n in range(nrxslots)]
  25                 # TODO: FullMemoryWE should move to Mibuild
  26                 wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
  27                         for n in range(ntxslots)]
  28                 wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
  29
  30                 wb_slaves = []
  31                 decoderoffset = log2_int(sram_depth)
  32                 decoderbits = log2_int(len(wb_sram_ifs))
  33                 for n, wb_sram_if in enumerate(wb_sram_ifs):
  34                         def slave_filter(a, v=n):
  35                                 return a[decoderoffset:decoderoffset+decoderbits] == v
  36                         wb_slaves.append((slave_filter, wb_sram_if.bus))
  37                         self.submodules += wb_sram_if
  38                 wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
  39                 self.submodules += wb_con