89f6fe9cf9aff7e6337c31b963d7c13002a93be6
[litex.git] / liteeth / test / arp_tb.py
1 from migen.fhdl.std import *
2 from migen.bus import wishbone
3 from migen.bus.transactions import *
4 from migen.sim.generic import run_simulation
5
6 from liteeth.common import *
7 from liteeth.mac import LiteEthMAC
8 from liteeth.arp import LiteEthARP
9
10 from liteeth.test.common import *
11 from liteeth.test.model import phy, mac, arp
12
13 ip_address = 0x12345678
14 mac_address = 0x12345678abcd
15
16 class TB(Module):
17 def __init__(self):
18 self.submodules.phy_model = phy.PHY(8, debug=True)
19 self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
20 self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
21
22 self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_hw_preamble_crc=True)
23 self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address)
24
25 # use sys_clk for each clock_domain
26 self.clock_domains.cd_eth_rx = ClockDomain()
27 self.clock_domains.cd_eth_tx = ClockDomain()
28 self.comb += [
29 self.cd_eth_rx.clk.eq(ClockSignal()),
30 self.cd_eth_rx.rst.eq(ResetSignal()),
31 self.cd_eth_tx.clk.eq(ClockSignal()),
32 self.cd_eth_tx.rst.eq(ResetSignal()),
33 ]
34
35 def gen_simulation(self, selfp):
36 selfp.cd_eth_rx.rst = 1
37 selfp.cd_eth_tx.rst = 1
38 yield
39 selfp.cd_eth_rx.rst = 0
40 selfp.cd_eth_tx.rst = 0
41
42 for i in range(100):
43 yield
44
45 while selfp.arp.table.request.ack != 1:
46 selfp.arp.table.request.stb = 1
47 selfp.arp.table.request.ip_address = 0x12345678
48 yield
49 selfp.arp.table.request.stb = 0
50 while selfp.arp.table.response.stb != 1:
51 selfp.arp.table.response.ack = 1
52 yield
53 print("Model MAC : 0x%12x" %selfp.arp.table.response.mac_address)
54
55
56 if __name__ == "__main__":
57 run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)