b4629c8937dffe72457c9243a34ae2161558c421
1 from migen
.fhdl
.std
import *
2 from migen
.bus
import wishbone
3 from migen
.bus
.transactions
import *
4 from migen
.sim
.generic
import run_simulation
6 from liteeth
.common
import *
7 from liteeth
.mac
import LiteEthMAC
8 from liteeth
.arp
import LiteEthARP
10 from liteeth
.test
.common
import *
11 from liteeth
.test
.model
import phy
, mac
, arp
13 ip_address
= 0x12345678
14 mac_address
= 0x12345678abcd
18 self
.submodules
.phy_model
= phy
.PHY(8, debug
=True)
19 self
.submodules
.mac_model
= mac
.MAC(self
.phy_model
, debug
=True, loopback
=False)
20 self
.submodules
.arp_model
= arp
.ARP(self
.mac_model
, mac_address
, ip_address
, debug
=True)
22 self
.submodules
.core
= LiteEthMAC(phy
=self
.phy_model
, dw
=8, with_hw_preamble_crc
=True)
23 self
.submodules
.arp
= LiteEthARP(mac_address
, ip_address
)
25 # use sys_clk for each clock_domain
26 self
.clock_domains
.cd_eth_rx
= ClockDomain()
27 self
.clock_domains
.cd_eth_tx
= ClockDomain()
29 self
.cd_eth_rx
.clk
.eq(ClockSignal()),
30 self
.cd_eth_rx
.rst
.eq(ResetSignal()),
31 self
.cd_eth_tx
.clk
.eq(ClockSignal()),
32 self
.cd_eth_tx
.rst
.eq(ResetSignal()),
36 Record
.connect(self
.arp
.source
, self
.core
.sink
),
37 Record
.connect(self
.core
.source
, self
.arp
.sink
)
40 def gen_simulation(self
, selfp
):
41 selfp
.cd_eth_rx
.rst
= 1
42 selfp
.cd_eth_tx
.rst
= 1
44 selfp
.cd_eth_rx
.rst
= 0
45 selfp
.cd_eth_tx
.rst
= 0
50 selfp
.arp
.table
.request
.ip_address
= 0x12345678
51 selfp
.arp
.table
.request
.stb
= 1
53 if __name__
== "__main__":
54 run_simulation(TB(), ncycles
=256, vcd_name
="my.vcd", keep_files
=True)