liteeth/test/etherbone_tb.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3 from migen.bus.transactions import *
   4 from migen.sim.generic import run_simulation
   5
   6 from liteeth.common import *
   7 from liteeth.core import LiteEthUDPIPCore
   8 from liteeth.core.etherbone import LiteEthEtherbone
   9
  10 from liteeth.test.common import *
  11 from liteeth.test.model import phy, mac, arp, ip, udp, etherbone
  12
  13 ip_address = 0x12345678
  14 mac_address = 0x12345678abcd
  15
  16 class TB(Module):
  17         def __init__(self):
  18                 self.submodules.phy_model = phy.PHY(8, debug=True)
  19                 self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
  20                 self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
  21                 self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
  22                 self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=True, loopback=False)
  23                 self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=True)
  24
  25                 self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
  26                 self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
  27
  28                 self.submodules.sram = wishbone.SRAM(1024)
  29                 self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.wishbone.bus, self.sram.bus)
  30
  31
  32
  33                 # use sys_clk for each clock_domain
  34                 self.clock_domains.cd_eth_rx = ClockDomain()
  35                 self.clock_domains.cd_eth_tx = ClockDomain()
  36                 self.comb += [
  37                         self.cd_eth_rx.clk.eq(ClockSignal()),
  38                         self.cd_eth_rx.rst.eq(ResetSignal()),
  39                         self.cd_eth_tx.clk.eq(ClockSignal()),
  40                         self.cd_eth_tx.rst.eq(ResetSignal()),
  41                 ]
  42
  43         def gen_simulation(self, selfp):
  44                 selfp.cd_eth_rx.rst = 1
  45                 selfp.cd_eth_tx.rst = 1
  46                 yield
  47                 selfp.cd_eth_rx.rst = 0
  48                 selfp.cd_eth_tx.rst = 0
  49
  50                 for i in range(100):
  51                         yield
  52
  53                 # test probe
  54                 #packet = etherbone.EtherbonePacket()
  55                 #packet.pf = 1
  56                 #self.etherbone_model.send(packet)
  57
  58                 # test writes
  59                 writes = etherbone.EtherboneWrites(base_addr=0x1000)
  60                 for i in range(16):
  61                         writes.add(etherbone.EtherboneWrite(i))
  62                 record = etherbone.EtherboneRecord()
  63                 record.writes = writes
  64                 record.reads = None
  65                 record.bca = 0
  66                 record.rca = 0
  67                 record.rff = 0
  68                 record.cyc = 0
  69                 record.wca = 0
  70                 record.wff = 0
  71                 record.byte_enable = 0
  72                 record.wcount = 16
  73                 record.rcount = 0
  74
  75                 packet = etherbone.EtherbonePacket()
  76                 packet.records = [record]
  77                 print(packet)
  78
  79                 self.etherbone_model.send(packet)
  80
  81
  82
  83 if __name__ == "__main__":
  84         run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)