dff6a28faf0e07dca442d038b96ec32da4509976
1 from litesata
.common
import *
2 from litesata
.core
.link
.scrambler
import Scrambler
4 class LiteSATACONTInserter(Module
):
5 def __init__(self
, description
):
6 self
.sink
= sink
= Sink(description
)
7 self
.source
= source
= Source(description
)
11 self
.counter
= counter
= Counter(max=4)
17 self
.comb
+= is_data
.eq(sink
.charisk
== 0)
19 last_data
= Signal(32)
20 last_primitive
= Signal(32)
21 last_charisk
= Signal(4)
23 If(sink
.stb
& source
.ack
,
24 last_data
.eq(sink
.data
),
25 last_charisk
.eq(sink
.charisk
),
27 last_primitive
.eq(sink
.data
),
30 was_hold
.eq(last_primitive
== primitives
["HOLD"])
33 self
.comb
+= change
.eq(
34 (sink
.data
!= last_data
) |
35 (sink
.charisk
!= last_charisk
) |
40 self
.scrambler
= scrambler
= InsertReset(Scrambler())
44 Record
.connect(sink
, source
),
47 counter
.ce
.eq(sink
.ack
& (counter
.value
!=2)),
49 If(counter
.value
== 1,
50 source
.charisk
.eq(0b0001),
51 source
.data
.eq(primitives
["CONT"])
52 # insert scrambled data for EMI
53 ).Elif(counter
.value
== 2,
54 scrambler
.ce
.eq(sink
.ack
),
55 source
.charisk
.eq(0b0000),
56 source
.data
.eq(scrambler
.value
)
59 counter
.reset
.eq(source
.ack
),
60 If(counter
.value
== 2,
61 # Reinsert last primitive
62 If(is_data |
(~is_data
& was_hold
),
65 source
.charisk
.eq(0b0001),
66 source
.data
.eq(last_primitive
)
73 class LiteSATACONTRemover(Module
):
74 def __init__(self
, description
):
75 self
.sink
= sink
= Sink(description
)
76 self
.source
= source
= Source(description
)
83 cont_ongoing
= Signal()
86 is_data
.eq(sink
.charisk
== 0),
87 is_cont
.eq(~is_data
& (sink
.data
== primitives
["CONT"]))
90 If(sink
.stb
& sink
.ack
,
97 self
.comb
+= cont_ongoing
.eq(is_cont |
(in_cont
& is_data
))
100 last_primitive
= Signal(32)
102 If(sink
.stb
& sink
.ack
,
103 If(~is_data
& ~is_cont
,
104 last_primitive
.eq(sink
.data
)
109 Record
.connect(sink
, source
),
111 source
.charisk
.eq(0b0001),
112 source
.data
.eq(last_primitive
)