litesata/test/crc_tb.py

   1 import subprocess
   2
   3 from litesata.common import *
   4 from litesata.core.link.crc import *
   5
   6 from litesata.test.common import *
   7
   8 class TB(Module):
   9         def __init__(self, length, random):
  10                 self.crc = LiteSATACRC()
  11                 self.length = length
  12                 self.random = random
  13
  14         def get_c_crc(self, datas):
  15                 stdin = ""
  16                 for data in datas:
  17                         stdin += "0x%08x " %data
  18                 stdin += "exit"
  19                 with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
  20                         process.stdin.write(stdin.encode("ASCII"))
  21                         out, err = process.communicate()
  22                 return int(out.decode("ASCII"), 16)
  23
  24         def gen_simulation(self, selfp):
  25                 # init CRC
  26                 selfp.crc.d = 0
  27                 selfp.crc.ce = 1
  28                 selfp.crc.reset = 1
  29                 yield
  30                 selfp.crc.reset = 0
  31
  32                 # feed CRC with datas
  33                 datas = []
  34                 for i in range(self.length):
  35                         data = seed_to_data(i, self.random)
  36                         datas.append(data)
  37                         selfp.crc.d = data
  38                         yield
  39
  40                 # log results
  41                 yield
  42                 sim_crc = selfp.crc.value
  43
  44                 # stop
  45                 selfp.crc.ce = 0
  46                 for i in range(32):
  47                         yield
  48
  49                 # get C core reference
  50                 c_crc = self.get_c_crc(datas)
  51
  52                 # check results
  53                 s, l, e = check(c_crc, sim_crc)
  54                 print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
  55
  56 if __name__ == "__main__":
  57         from migen.sim.generic import run_simulation
  58         length = 8192
  59         run_simulation(TB(length, True), ncycles=length+100, vcd_name="my.vcd")