6f228ce15b78467e8f43f0b6d46ce64cb7b2d0bd
1 from litex
.build
.generic_platform
import *
2 from litex
.build
.xilinx
import XilinxPlatform
, VivadoProgrammer
6 ("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
7 ("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
8 ("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
9 ("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
10 ("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
11 ("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
12 ("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
13 ("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
16 Subsignal("p", Pins("G10"), IOStandard("LVDS")),
17 Subsignal("n", Pins("F10"), IOStandard("LVDS"))
21 Subsignal("cts", Pins("L23")),
22 Subsignal("rts", Pins("K27")),
23 Subsignal("tx", Pins("K26")),
24 Subsignal("rx", Pins("G25")),
25 IOStandard("LVCMOS18")
29 Subsignal("p", Pins("D23"), IOStandard("LVDS")),
30 Subsignal("n", Pins("C23"), IOStandard("LVDS"))
110 "GBTCLK1_M2C_P": "E25",
111 "GBTCLK1_M2C_N": "D25",
112 "GBTCLK0_M2C_P": "H12",
113 "GBTCLK0_M2C_N": "G12",
141 "PRSNT_M2C_B": "H24",
183 class Platform(XilinxPlatform
):
184 default_clk_name
= "clk125"
185 default_clk_period
= 8.0
188 XilinxPlatform
.__init
__(self
, "xcku040-ffva1156-2-e", _io
, _connectors
,
191 def create_programmer(self
):
192 return VivadoProgrammer()