litex/boards/platforms/netv2.py

   1 # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   6
   7 # IOs ----------------------------------------------------------------------------------------------
   8
   9 _io = [
  10     # clock
  11     ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
  12
  13     # leds
  14     ("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
  15     ("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
  16     ("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
  17     ("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
  18     ("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
  19     ("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
  20
  21     # spiflash
  22     ("flash", 0,
  23         Subsignal("cs_n", Pins("T19")),
  24         Subsignal("mosi", Pins("P22")),
  25         Subsignal("miso", Pins("R22")),
  26         Subsignal("vpp", Pins("P21")),
  27         Subsignal("hold", Pins("R21")),
  28         IOStandard("LVCMOS33")
  29     ),
  30
  31     # spiflash4x
  32     ("spiflash4x", 0,
  33         Subsignal("cs_n", Pins("T19")),
  34         Subsignal("dq", Pins("P22 R22 P21 R21")),
  35         IOStandard("LVCMOS33")
  36     ),
  37
  38     # serial
  39     ("serial", 0,
  40         Subsignal("tx", Pins("E14")),
  41         Subsignal("rx", Pins("E13")),
  42         IOStandard("LVCMOS33"),
  43     ),
  44
  45     # dram
  46     ("ddram", 0,
  47         Subsignal("a", Pins(
  48             "U6 V4 W5 V5 AA1 Y2 AB1 AB3",
  49             "AB2 Y3 W6 Y1 V2 AA3"),
  50             IOStandard("SSTL15_R")),
  51         Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")),
  52         Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15_R")),
  53         Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15_R")),
  54         Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")),
  55         Subsignal("dm", Pins("G1 H4 M5 L3"), IOStandard("SSTL15_R")),
  56         Subsignal("dq", Pins(
  57             "C2 F1 B1 F3 A1 D2 B2 E2",
  58             "J5 H3 K1 H2 J1 G2 H5 G3",
  59             "N2 M6 P1 N5 P2 N4 R1 P6",
  60             "K3 M2 K4 M3 J6 L5 J4 K6"),
  61             IOStandard("SSTL15_R"),
  62             Misc("IN_TERM=UNTUNED_SPLIT_40")),
  63         Subsignal("dqs_p", Pins("E1 K2 P5 M1"), IOStandard("DIFF_SSTL15_R")),
  64         Subsignal("dqs_n", Pins("D1 J2 P4 L1"), IOStandard("DIFF_SSTL15_R")),
  65         Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15_R")),
  66         Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15_R")),
  67         Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")),
  68         Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")),
  69         Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
  70         Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15_R")),
  71         Misc("SLEW=FAST"),
  72     ),
  73
  74     # ethernet
  75     ("eth_clocks", 0,
  76         Subsignal("ref_clk", Pins("D17")),
  77         IOStandard("LVCMOS33"),
  78     ),
  79
  80     ("eth", 0,
  81         Subsignal("rst_n", Pins("F16")),
  82         Subsignal("rx_data", Pins("A20 B18")),
  83         Subsignal("crs_dv", Pins("C20")),
  84         Subsignal("tx_en", Pins("A19")),
  85         Subsignal("tx_data", Pins("C18 C19")),
  86         Subsignal("mdc", Pins("F14")),
  87         Subsignal("mdio", Pins("F13")),
  88         Subsignal("rx_er", Pins("B20")),
  89         Subsignal("int_n", Pins("D21")),
  90         IOStandard("LVCMOS33")
  91      ),
  92
  93      # sdcard
  94      ("sdcard", 0,
  95         Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
  96         Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
  97         Subsignal("clk", Pins("K18")),
  98         IOStandard("LVCMOS33"), Misc("SLEW=FAST")
  99     ),
 100
 101     # hdmi in
 102     ("hdmi_in", 0,
 103         Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()),
 104         Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()),
 105         Subsignal("data0_p", Pins("K21"), IOStandard("TMDS_33"), Inverted()),
 106         Subsignal("data0_n", Pins("K22"), IOStandard("TMDS_33"), Inverted()),
 107         Subsignal("data1_p", Pins("J20"), IOStandard("TMDS_33"), Inverted()),
 108         Subsignal("data1_n", Pins("J21"), IOStandard("TMDS_33"), Inverted()),
 109         Subsignal("data2_p", Pins("J22"), IOStandard("TMDS_33"), Inverted()),
 110         Subsignal("data2_n", Pins("H22"), IOStandard("TMDS_33"), Inverted()),
 111         Subsignal("scl", Pins("T18"), IOStandard("LVCMOS33")),
 112         Subsignal("sda", Pins("V18"), IOStandard("LVCMOS33")),
 113     ),
 114
 115     ("hdmi_in", 1,
 116         Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()),
 117         Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()),
 118         Subsignal("data0_p", Pins("AA18"), IOStandard("TMDS_33")),
 119         Subsignal("data0_n", Pins("AB18"), IOStandard("TMDS_33")),
 120         Subsignal("data1_p", Pins("AA19"), IOStandard("TMDS_33"), Inverted()),
 121         Subsignal("data1_n", Pins("AB20"), IOStandard("TMDS_33"), Inverted()),
 122         Subsignal("data2_p", Pins("AB21"), IOStandard("TMDS_33"), Inverted()),
 123         Subsignal("data2_n", Pins("AB22"), IOStandard("TMDS_33"), Inverted()),
 124         Subsignal("scl", Pins("W17"), IOStandard("LVCMOS33"), Inverted()),
 125         Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")),
 126     ),
 127
 128     # hdmi out
 129     ("hdmi_out", 0,
 130         Subsignal("clk_p", Pins("W19"), Inverted(), IOStandard("TMDS_33")),
 131         Subsignal("clk_n", Pins("W20"), Inverted(), IOStandard("TMDS_33")),
 132         Subsignal("data0_p", Pins("W21"), IOStandard("TMDS_33")),
 133         Subsignal("data0_n", Pins("W22"), IOStandard("TMDS_33")),
 134         Subsignal("data1_p", Pins("U20"), IOStandard("TMDS_33")),
 135         Subsignal("data1_n", Pins("V20"), IOStandard("TMDS_33")),
 136         Subsignal("data2_p", Pins("T21"), IOStandard("TMDS_33")),
 137         Subsignal("data2_n", Pins("U21"), IOStandard("TMDS_33"))
 138     ),
 139
 140     ("hdmi_out", 1,
 141         Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()),
 142         Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()),
 143         Subsignal("data0_p", Pins("E22"), IOStandard("TMDS_33"), Inverted()),
 144         Subsignal("data0_n", Pins("D22"), IOStandard("TMDS_33"), Inverted()),
 145         Subsignal("data1_p", Pins("C22"), IOStandard("TMDS_33"), Inverted()),
 146         Subsignal("data1_n", Pins("B22"), IOStandard("TMDS_33"), Inverted()),
 147         Subsignal("data2_p", Pins("B21"), IOStandard("TMDS_33"), Inverted()),
 148         Subsignal("data2_n", Pins("A21"), IOStandard("TMDS_33"), Inverted()),
 149     ),
 150
 151 ]
 152
 153 # Platform -----------------------------------------------------------------------------------------
 154
 155 class Platform(XilinxPlatform):
 156     default_clk_name = "clk50"
 157     default_clk_period = 1e9/50e6
 158
 159     def __init__(self):
 160         XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")