litex/boards/platforms/nexys_video.py

   1 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   6 from litex.build.openocd import OpenOCD
   7
   8 # IOs ----------------------------------------------------------------------------------------------
   9
  10 _io = [
  11     ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
  12     ("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
  13     ("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
  14     ("user_led", 3, Pins("U16"), IOStandard("LVCMOS25")),
  15     ("user_led", 4, Pins("V15"), IOStandard("LVCMOS25")),
  16     ("user_led", 5, Pins("W16"), IOStandard("LVCMOS25")),
  17     ("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")),
  18     ("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")),
  19
  20     ("user_sw", 0, Pins("E22"), IOStandard("LVCMOS25")),
  21     ("user_sw", 1, Pins("F21"), IOStandard("LVCMOS25")),
  22     ("user_sw", 2, Pins("G21"), IOStandard("LVCMOS25")),
  23     ("user_sw", 3, Pins("G22"), IOStandard("LVCMOS25")),
  24     ("user_sw", 4, Pins("H17"), IOStandard("LVCMOS25")),
  25     ("user_sw", 5, Pins("J16"), IOStandard("LVCMOS25")),
  26     ("user_sw", 6, Pins("K13"), IOStandard("LVCMOS25")),
  27     ("user_sw", 7, Pins("M17"), IOStandard("LVCMOS25")),
  28
  29
  30     ("user_btn", 0, Pins("B22"), IOStandard("LVCMOS25")),
  31     ("user_btn", 1, Pins("D22"), IOStandard("LVCMOS25")),
  32     ("user_btn", 2, Pins("C22"), IOStandard("LVCMOS25")),
  33     ("user_btn", 3, Pins("D14"), IOStandard("LVCMOS25")),
  34     ("user_btn", 4, Pins("F15"), IOStandard("LVCMOS25")),
  35     ("user_btn", 5, Pins("G4"),  IOStandard("LVCMOS25")),
  36
  37     ("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")),
  38
  39     ("oled", 0,
  40         Subsignal("dc",   Pins("W22")),
  41         Subsignal("res",  Pins("U21")),
  42         Subsignal("sclk", Pins("W21")),
  43         Subsignal("sdin", Pins("Y22")),
  44         Subsignal("vbat", Pins("P20")),
  45         Subsignal("vdd",  Pins("V22")),
  46         IOStandard("LVCMOS33")
  47     ),
  48
  49     ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
  50
  51     ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
  52
  53     ("serial", 0,
  54         Subsignal("tx", Pins("AA19")),
  55         Subsignal("rx", Pins("V18")),
  56         IOStandard("LVCMOS33"),
  57     ),
  58
  59     ("ddram", 0,
  60         Subsignal("a", Pins(
  61             "M2 M5 M3 M1 L6 P1 N3 N2",
  62             "M6 R1 L5 N5 N4 P2 P6"),
  63             IOStandard("SSTL15")),
  64         Subsignal("ba",    Pins("L3 K6 L4"), IOStandard("SSTL15")),
  65         Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
  66         Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
  67         Subsignal("we_n",  Pins("L1"), IOStandard("SSTL15")),
  68         Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
  69         Subsignal("dq", Pins(
  70             "G2 H4 H5 J1 K1 H3 H2 J5",
  71             "E3 B2 F3 D2 C2 A1 E2 B1"),
  72             IOStandard("SSTL15"),
  73             Misc("IN_TERM=UNTUNED_SPLIT_50")),
  74         Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
  75         Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
  76         Subsignal("clk_p", Pins("P5"),    IOStandard("DIFF_SSTL15")),
  77         Subsignal("clk_n", Pins("P4"),    IOStandard("DIFF_SSTL15")),
  78         Subsignal("cke",   Pins("J6"),    IOStandard("SSTL15")),
  79         Subsignal("odt",   Pins("K4"),    IOStandard("SSTL15")),
  80         Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
  81         Misc("SLEW=FAST"),
  82     ),
  83
  84     ("eth_clocks", 0,
  85         Subsignal("tx", Pins("AA14")),
  86         Subsignal("rx", Pins("V13")),
  87         IOStandard("LVCMOS25")
  88     ),
  89     ("eth", 0,
  90         Subsignal("rst_n",   Pins("U7"), IOStandard("LVCMOS33")),
  91         Subsignal("int_n",   Pins("Y14")),
  92         Subsignal("mdio",    Pins("Y16")),
  93         Subsignal("mdc",     Pins("AA16")),
  94         Subsignal("rx_ctl",  Pins("W10")),
  95         Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")),
  96         Subsignal("tx_ctl",  Pins("V10")),
  97         Subsignal("tx_data", Pins("Y12 W12 W11 Y11")),
  98         IOStandard("LVCMOS25")
  99     ),
 100
 101     ("hdmi_in", 0,
 102         Subsignal("clk_p",   Pins("V4"),   IOStandard("TMDS_33")),
 103         Subsignal("clk_n",   Pins("W4"),   IOStandard("TMDS_33")),
 104         Subsignal("data0_p", Pins("Y3"),   IOStandard("TMDS_33")),
 105         Subsignal("data0_n", Pins("AA3"),  IOStandard("TMDS_33")),
 106         Subsignal("data1_p", Pins("W2"),   IOStandard("TMDS_33")),
 107         Subsignal("data1_n", Pins("Y2"),   IOStandard("TMDS_33")),
 108         Subsignal("data2_p", Pins("U2"),   IOStandard("TMDS_33")),
 109         Subsignal("data2_n", Pins("V2"),   IOStandard("TMDS_33")),
 110         Subsignal("scl",     Pins("Y4"),   IOStandard("LVCMOS33")),
 111         Subsignal("sda",     Pins("AB5"),  IOStandard("LVCMOS33")),
 112         Subsignal("hpd_en",  Pins("AB12"), IOStandard("LVCMOS25")),
 113         Subsignal("cec",     Pins("AA5"),  IOStandard("LVCMOS33")), # FIXME
 114         Subsignal("txen",    Pins("R3"),   IOStandard("LVCMOS33")), # FIXME
 115     ),
 116
 117     ("hdmi_out", 0,
 118         Subsignal("clk_p",   Pins("T1"),   IOStandard("TMDS_33")),
 119         Subsignal("clk_n",   Pins("U1"),   IOStandard("TMDS_33")),
 120         Subsignal("data0_p", Pins("W1"),   IOStandard("TMDS_33")),
 121         Subsignal("data0_n", Pins("Y1"),   IOStandard("TMDS_33")),
 122         Subsignal("data1_p", Pins("AA1"),  IOStandard("TMDS_33")),
 123         Subsignal("data1_n", Pins("AB1"),  IOStandard("TMDS_33")),
 124         Subsignal("data2_p", Pins("AB3"),  IOStandard("TMDS_33")),
 125         Subsignal("data2_n", Pins("AB2"),  IOStandard("TMDS_33")),
 126         Subsignal("scl",     Pins("U3"),   IOStandard("LVCMOS33")),
 127         Subsignal("sda",     Pins("V3"),   IOStandard("LVCMOS33")),
 128         Subsignal("cec",     Pins("AA4"),  IOStandard("LVCMOS33")), # FIXME
 129         Subsignal("hdp",     Pins("AB13"), IOStandard("LVCMOS25")), # FIXME
 130     ),
 131 ]
 132
 133 # Connectors ---------------------------------------------------------------------------------------
 134
 135 _connectors = [
 136     ("LPC", {
 137         "DP0_C2M_P"     : "D7",
 138         "DP0_C2M_N"     : "C7",
 139         "DP0_M2C_P"     : "D9",
 140         "DP0_M2C_N"     : "C9",
 141         "GBTCLK0_M2C_P" : "F10",
 142         "GBTCLK0_M2C_N" : "E10",
 143         "LA01_CC_P"     : "J20",
 144         "LA01_CC_N"     : "J21",
 145         "LA05_P"        : "M21",
 146         "LA05_N"        : "L21",
 147         "LA09_P"        : "H20",
 148         "LA09_N"        : "G20",
 149         "LA13_P"        : "K17",
 150         "LA13_N"        : "J17",
 151         "LA17_CC_P"     : "B17",
 152         "LA17_CC_N"     : "B18",
 153         "LA23_P"        : "B21",
 154         "LA23_N"        : "A21",
 155         "LA26_P"        : "F18",
 156         "LA26_N"        : "E18",
 157         "CLK0_M2C_P"    : "J19",
 158         "CLK0_M2C_N"    : "A19",
 159         "LA02_P"        : "M18",
 160         "LA02_N"        : "L18",
 161         "LA04_P"        : "N20",
 162         "LA04_N"        : "M20",
 163         "LA07_P"        : "M13",
 164         "LA07_N"        : "L13",
 165         "LA11_P"        : "L14",
 166         "LA11_N"        : "L15",
 167         "LA15_P"        : "L16",
 168         "LA15_N"        : "K16",
 169         "LA19_P"        : "A18",
 170         "LA19_N"        : "A19",
 171         "LA21_P"        : "E19",
 172         "LA21_N"        : "D19",
 173         "LA24_P"        : "B15",
 174         "LA24_N"        : "B16",
 175         "LA28_P"        : "C13",
 176         "LA28_N"        : "B13",
 177         "LA30_P"        : "A13",
 178         "LA30_N"        : "A14",
 179         "LA32_P"        : "A15",
 180         "LA32_N"        : "A16",
 181         "LA06_P"        : "N22",
 182         "LA06_N"        : "M22",
 183         "LA10_P"        : "K21",
 184         "LA10_N"        : "K22",
 185         "LA14_P"        : "J22",
 186         "LA14_N"        : "H22",
 187         "LA18_CC_P"     : "D17",
 188         "LA18_CC_N"     : "C17",
 189         "LA27_P"        : "B20",
 190         "LA27_N"        : "A20",
 191         "CLK1_M2C_P"    : "C18",
 192         "CLK1_M2C_N"    : "C19",
 193         "LA00_CC_P"     : "K18",
 194         "LA00_CC_N"     : "K19",
 195         "LA03_P"        : "N18",
 196         "LA03_N"        : "N19",
 197         "LA08_P"        : "M15",
 198         "LA08_N"        : "M16",
 199         "LA12_P"        : "L19",
 200         "LA12_N"        : "L20",
 201         "LA16_P"        : "G17",
 202         "LA16_N"        : "G18",
 203         "LA20_P"        : "F19",
 204         "LA20_N"        : "F20",
 205         "LA22_P"        : "E21",
 206         "LA22_N"        : "D21",
 207         "LA25_P"        : "F16",
 208         "LA25_N"        : "E17",
 209         "LA29_P"        : "C14",
 210         "LA29_N"        : "C15",
 211         "LA31_P"        : "E13",
 212         "LA31_N"        : "E14",
 213         "LA33_P"        : "F13",
 214         "LA33_N"        : "F14",
 215         }
 216     )
 217 ]
 218
 219 # Platform -----------------------------------------------------------------------------------------
 220
 221 class Platform(XilinxPlatform):
 222     default_clk_name   = "clk100"
 223     default_clk_period = 1e9/100e6
 224
 225     def __init__(self):
 226         XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado")
 227         self.toolchain.bitstream_commands = \
 228             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 229         self.toolchain.additional_commands = \
 230             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
 231              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 232         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 233
 234     def create_programmer(self):
 235         return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
 236
 237     def do_finalize(self, fragment):
 238         XilinxPlatform.do_finalize(self, fragment)
 239         try:
 240             self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
 241         except ConstraintError:
 242             pass
 243
 244     def do_finalize(self, fragment):
 245         XilinxPlatform.do_finalize(self, fragment)
 246         self.add_period_constraint(self.lookup_request("clk100",        loose=True), 1e9/100e6)
 247         self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)