litex/boards/targets/arty.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6 from migen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import arty
   9
  10 from litex.soc.integration.soc_core import mem_decoder
  11 from litex.soc.integration.soc_sdram import *
  12 from litex.soc.integration.builder import *
  13
  14 from litedram.modules import MT41K128M16
  15 from litedram.phy import s7ddrphy
  16
  17 from liteeth.phy.mii import LiteEthPHYMII
  18 from liteeth.core.mac import LiteEthMAC
  19
  20
  21 class _CRG(Module):
  22     def __init__(self, platform):
  23         self.clock_domains.cd_sys = ClockDomain()
  24         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  25         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
  26         self.clock_domains.cd_clk200 = ClockDomain()
  27         self.clock_domains.cd_clk50 = ClockDomain()
  28
  29         clk100 = platform.request("clk100")
  30         rst = ~platform.request("cpu_reset")
  31
  32         pll_locked = Signal()
  33         pll_fb = Signal()
  34         pll_sys = Signal()
  35         pll_sys4x = Signal()
  36         pll_sys4x_dqs = Signal()
  37         pll_clk200 = Signal()
  38         pll_clk50 = Signal()
  39         self.specials += [
  40             Instance("PLLE2_BASE",
  41                      p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  42
  43                      # VCO @ 1600 MHz
  44                      p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
  45                      p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
  46                      i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  47
  48                      # 100 MHz
  49                      p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
  50                      o_CLKOUT0=pll_sys,
  51
  52                      # 400 MHz
  53                      p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
  54                      o_CLKOUT1=pll_sys4x,
  55
  56                      # 400 MHz dqs
  57                      p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0,
  58                      o_CLKOUT2=pll_sys4x_dqs,
  59
  60                      # 200 MHz
  61                      p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
  62                      o_CLKOUT3=pll_clk200,
  63
  64                      # 50MHz
  65                      p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0,
  66                      o_CLKOUT4=pll_clk50
  67             ),
  68             Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  69             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
  70             Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
  71             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
  72             Instance("BUFG", i_I=pll_clk50, o_O=self.cd_clk50.clk),
  73             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
  74             AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
  75             AsyncResetSynchronizer(self.cd_clk50, ~pll_locked | rst),
  76         ]
  77
  78         reset_counter = Signal(4, reset=15)
  79         ic_reset = Signal(reset=1)
  80         self.sync.clk200 += \
  81             If(reset_counter != 0,
  82                 reset_counter.eq(reset_counter - 1)
  83             ).Else(
  84                 ic_reset.eq(0)
  85             )
  86         self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
  87
  88         eth_clk = Signal()
  89         self.specials += [
  90             Instance("BUFR", p_BUFR_DIVIDE="4", i_CE=1, i_CLR=0, i_I=clk100, o_O=eth_clk),
  91             Instance("BUFG", i_I=eth_clk, o_O=platform.request("eth_ref_clk")),
  92         ]
  93
  94
  95 class BaseSoC(SoCSDRAM):
  96     csr_map = {
  97         "ddrphy":    16,
  98     }
  99     csr_map.update(SoCSDRAM.csr_map)
 100     def __init__(self, **kwargs):
 101         platform = arty.Platform()
 102         sys_clk_freq = int(100e6)
 103         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
 104                          integrated_rom_size=0x8000,
 105                          integrated_sram_size=0x8000,
 106                          **kwargs)
 107
 108         self.submodules.crg = _CRG(platform)
 109
 110         # sdram
 111         self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
 112         sdram_module = MT41K128M16(sys_clk_freq, "1:4")
 113         self.register_sdram(self.ddrphy,
 114                             sdram_module.geom_settings,
 115                             sdram_module.timing_settings)
 116
 117
 118 class EthernetSoC(BaseSoC):
 119     csr_map = {
 120         "ethphy": 18,
 121         "ethmac": 19
 122     }
 123     csr_map.update(BaseSoC.csr_map)
 124
 125     interrupt_map = {
 126         "ethmac": 3,
 127     }
 128     interrupt_map.update(BaseSoC.interrupt_map)
 129
 130     mem_map = {
 131         "ethmac": 0x30000000,  # (shadow @0xb0000000)
 132     }
 133     mem_map.update(BaseSoC.mem_map)
 134
 135     def __init__(self, **kwargs):
 136         BaseSoC.__init__(self, **kwargs)
 137
 138         self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
 139                                                self.platform.request("eth"))
 140         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
 141             interface="wishbone", endianness=self.cpu.endianness)
 142         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
 143         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 144
 145         self.crg.cd_sys.clk.attr.add("keep")
 146         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
 147         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
 148         self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
 149         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0)
 150         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0)
 151         self.platform.add_false_path_constraints(
 152             self.crg.cd_sys.clk,
 153             self.ethphy.crg.cd_eth_rx.clk,
 154             self.ethphy.crg.cd_eth_tx.clk)
 155
 156
 157 def main():
 158     parser = argparse.ArgumentParser(description="LiteX SoC port to Arty")
 159     builder_args(parser)
 160     soc_sdram_args(parser)
 161     parser.add_argument("--with-ethernet", action="store_true",
 162                         help="enable Ethernet support")
 163     args = parser.parse_args()
 164
 165     cls = EthernetSoC if args.with_ethernet else BaseSoC
 166     soc = cls(**soc_sdram_argdict(args))
 167     builder = Builder(soc, **builder_argdict(args))
 168     builder.build()
 169
 170
 171 if __name__ == "__main__":
 172     main()