litex/boards/targets/nexys_video.py

   1 #!/usr/bin/env python3
   2 import argparse
   3 import os
   4
   5 from litex.gen import *
   6 from litex.gen.genlib.resetsync import AsyncResetSynchronizer
   7
   8 from litex.boards.platforms import nexys_video
   9
  10 from litex.soc.integration.soc_core import *
  11 from litex.soc.integration.builder import *
  12
  13 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
  14 from liteeth.core.mac import LiteEthMAC
  15
  16
  17 class _CRG(Module):
  18     def __init__(self, platform):
  19         self.clock_domains.cd_sys = ClockDomain()
  20         self.clock_domains.cd_clk200 = ClockDomain()
  21
  22         clk100 = platform.request("clk100")
  23         rst = platform.request("cpu_reset")
  24
  25         pll_locked = Signal()
  26         pll_fb = Signal()
  27         pll_sys = Signal()
  28         pll_clk200 = Signal()
  29         self.specials += [
  30             Instance("PLLE2_BASE",
  31                      p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  32
  33                      # VCO @ 800 MHz
  34                      p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
  35                      p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
  36                      i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  37
  38                      # 100 MHz
  39                      p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
  40                      o_CLKOUT0=pll_sys,
  41
  42                      # 200 MHz
  43                      p_CLKOUT3_DIVIDE=4, p_CLKOUT3_PHASE=0.0,
  44                      o_CLKOUT3=pll_clk200
  45             ),
  46             Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  47             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
  48             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst),
  49             AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
  50         ]
  51
  52         reset_counter = Signal(4, reset=15)
  53         ic_reset = Signal(reset=1)
  54         self.sync.clk200 += \
  55             If(reset_counter != 0,
  56                 reset_counter.eq(reset_counter - 1)
  57             ).Else(
  58                 ic_reset.eq(0)
  59             )
  60         self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
  61
  62
  63 class BaseSoC(SoCCore):
  64     def __init__(self, **kwargs):
  65         platform = nexys_video.Platform()
  66         SoCCore.__init__(self, platform, clk_freq=100*1000000,
  67                          integrated_rom_size=0x8000,
  68                          integrated_sram_size=0x8000,
  69                          integrated_main_ram_size=0x10000,
  70                          **kwargs)
  71
  72         self.submodules.crg = _CRG(platform)
  73
  74
  75 class MiniSoC(BaseSoC):
  76     csr_map = {
  77         "ethphy": 18,
  78         "ethmac": 19
  79     }
  80     csr_map.update(BaseSoC.csr_map)
  81
  82     interrupt_map = {
  83         "ethmac": 2,
  84     }
  85     interrupt_map.update(BaseSoC.interrupt_map)
  86
  87     mem_map = {
  88         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  89     }
  90     mem_map.update(BaseSoC.mem_map)
  91
  92     def __init__(self, **kwargs):
  93         BaseSoC.__init__(self, **kwargs)
  94
  95         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
  96                                                  self.platform.request("eth"))
  97         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
  98         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  99         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 100
 101 def main():
 102     parser = argparse.ArgumentParser(description="LiteX SoC port to Nexys Video")
 103     builder_args(parser)
 104     soc_core_args(parser)
 105     parser.add_argument("--with-ethernet", action="store_true",
 106                         help="enable Ethernet support")
 107     parser.add_argument("--build", action="store_true",
 108                         help="build bitstream")
 109     parser.add_argument("--load", action="store_true",
 110                         help="load bitstream")
 111     args = parser.parse_args()
 112
 113     cls = MiniSoC if args.with_ethernet else BaseSoC
 114     soc = cls(**soc_core_argdict(args))
 115     builder = Builder(soc, **builder_argdict(args))
 116
 117     if args.build:
 118         builder.build()
 119
 120     if args.load:
 121         prog = soc.platform.create_programmer()
 122         prog.load_bitstream(os.path.join(builder.output_dir, "gateware", "top.bit"))
 123
 124
 125 if __name__ == "__main__":
 126     main()