0c30c8147e984294f3aaade766fb87f9d867ed31
2 from migen
.fhdl
import verilog
4 from functools
import reduce
5 from operator
import or_
9 s
= [Signal() for i
in range(n
)]
14 s
= [Signal(2) for i
in range(n
)]
27 self
.sigs
= gen_list(2)
30 class Example(Module
):
32 a
= [Bar() for x
in range(3)]
33 b
= [Foo() for x
in range(3)]
35 b
= [Bar() for x
in range(2)]
41 allsigs
.extend(obj
.sigs
)
42 self
.comb
+= output
.eq(reduce(or_
, allsigs
))
44 print(verilog
.convert(Example()))