litex/gen/examples/basic/record.py

   1 from migen import *
   2 from migen.fhdl import verilog
   3
   4
   5 L = [
   6     ("position", [
   7             ("x", 10, DIR_M_TO_S),
   8             ("y", 10, DIR_M_TO_S),
   9     ]),
  10     ("color", 32, DIR_M_TO_S),
  11     ("stb", 1, DIR_M_TO_S),
  12     ("ack", 1, DIR_S_TO_M)
  13 ]
  14
  15
  16 class Test(Module):
  17     def __init__(self):
  18         master = Record(L)
  19         slave = Record(L)
  20         self.comb += master.connect(slave)
  21
  22
  23 if __name__ == "__main__":
  24     print(verilog.convert(Test()))
  25     print(layout_len(L))
  26     print(layout_partial(L, "position/x", "color"))