litex/gen/genlib/io.py

   1 from litex.gen.fhdl.structure import *
   2 from litex.gen.fhdl.module import Module
   3 from litex.gen.fhdl.specials import Special
   4
   5
   6 class DifferentialInput(Special):
   7     def __init__(self, i_p, i_n, o):
   8         Special.__init__(self)
   9         self.i_p = wrap(i_p)
  10         self.i_n = wrap(i_n)
  11         self.o = wrap(o)
  12
  13     def iter_expressions(self):
  14         yield self, "i_p", SPECIAL_INPUT
  15         yield self, "i_n", SPECIAL_INPUT
  16         yield self, "o", SPECIAL_OUTPUT
  17
  18     @staticmethod
  19     def lower(dr):
  20         raise NotImplementedError("Attempted to use a differential input, but platform does not support them")
  21
  22
  23 class DifferentialOutput(Special):
  24     def __init__(self, i, o_p, o_n):
  25         Special.__init__(self)
  26         self.i = wrap(i)
  27         self.o_p = wrap(o_p)
  28         self.o_n = wrap(o_n)
  29
  30     def iter_expressions(self):
  31         yield self, "i", SPECIAL_INPUT
  32         yield self, "o_p", SPECIAL_OUTPUT
  33         yield self, "o_n", SPECIAL_OUTPUT
  34
  35     @staticmethod
  36     def lower(dr):
  37         raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
  38
  39
  40 class CRG(Module):
  41     """ Clock and Reset Generator """
  42
  43     def __init__(self, clk, rst=0):
  44         self.clock_domains.cd_sys = ClockDomain()
  45         self.clock_domains.cd_por = ClockDomain(reset_less=True)
  46
  47         if hasattr(clk, "p"):
  48             clk_se = Signal()
  49             self.specials += DifferentialInput(clk.p, clk.n, clk_se)
  50             clk = clk_se
  51
  52         # Power on Reset (vendor agnostic)
  53         int_rst = Signal(reset=1)
  54         self.sync.por += int_rst.eq(rst)
  55         self.comb += [
  56             self.cd_sys.clk.eq(clk),
  57             self.cd_por.clk.eq(clk),
  58             self.cd_sys.rst.eq(int_rst)
  59         ]
  60
  61
  62 class DDRInput(Special):
  63     def __init__(self, i, o1, o2, clk=ClockSignal()):
  64         Special.__init__(self)
  65         self.i = wrap(i)
  66         self.o1 = wrap(o1)
  67         self.o2 = wrap(o2)
  68         self.clk = wrap(clk)
  69
  70     def iter_expressions(self):
  71         yield self, "i", SPECIAL_INPUT
  72         yield self, "o1", SPECIAL_OUTPUT
  73         yield self, "o2", SPECIAL_OUTPUT
  74         yield self, "clk", SPECIAL_INPUT
  75
  76     @staticmethod
  77     def lower(dr):
  78         raise NotImplementedError("Attempted to use a DDR input, but platform does not support them")
  79
  80
  81 class DDROutput(Special):
  82     def __init__(self, i1, i2, o, clk=ClockSignal()):
  83         Special.__init__(self)
  84         self.i1 = i1
  85         self.i2 = i2
  86         self.o = o
  87         self.clk = clk
  88
  89     def iter_expressions(self):
  90         yield self, "i1", SPECIAL_INPUT
  91         yield self, "i2", SPECIAL_INPUT
  92         yield self, "o", SPECIAL_OUTPUT
  93         yield self, "clk", SPECIAL_INPUT
  94
  95     @staticmethod
  96     def lower(dr):
  97         raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
  98