litex/gen/migen/build/platforms/kc705.py

   1 from migen.build.generic_platform import *
   2 from migen.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
   3 from migen.build.xilinx.ise import XilinxISEToolchain
   4
   5
   6 _io = [
   7     ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
   8     ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
   9     ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
  10     ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
  11     ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
  12     ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
  13     ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
  14     ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
  15
  16     ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
  17
  18     ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
  19     ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
  20     ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
  21     ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
  22     ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
  23
  24     ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
  25     ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
  26     ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
  27     ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
  28
  29     ("user_sma_clock", 0,
  30         Subsignal("p", Pins("L25"), IOStandard("LVDS_25")),
  31         Subsignal("n", Pins("K25"), IOStandard("LVDS_25"))
  32     ),
  33     ("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")),
  34     ("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")),
  35
  36     ("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS33")),
  37     ("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS33")),
  38
  39     ("clk200", 0,
  40         Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
  41         Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
  42     ),
  43
  44     ("clk156", 0,
  45         Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
  46         Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
  47     ),
  48
  49     ("i2c", 0,
  50         Subsignal("scl", Pins("K21")),
  51         Subsignal("sda", Pins("L21")),
  52         IOStandard("LVCMOS25")),
  53
  54     ("serial", 0,
  55         Subsignal("cts", Pins("L27")),
  56         Subsignal("rts", Pins("K23")),
  57         Subsignal("tx", Pins("K24")),
  58         Subsignal("rx", Pins("M19")),
  59         IOStandard("LVCMOS25")),
  60
  61     ("spiflash", 0,  # clock needs to be accessed through STARTUPE2
  62         Subsignal("cs_n", Pins("U19")),
  63         Subsignal("dq", Pins("P24", "R25", "R20", "R21")),
  64         IOStandard("LVCMOS25")
  65     ),
  66
  67     ("mmc", 0,
  68         Subsignal("wp", Pins("Y21")),
  69         Subsignal("det", Pins("AA21")),
  70         Subsignal("cmd", Pins("AB22")),
  71         Subsignal("clk", Pins("AB23")),
  72         Subsignal("dat", Pins("AC20 AA23 AA22 AC21")),
  73         IOStandard("LVCMOS25")),
  74
  75     ("lcd", 0,
  76         Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
  77         Subsignal("e", Pins("AB10")),
  78         Subsignal("rs", Pins("Y11")),
  79         Subsignal("rw", Pins("AB13")),
  80         IOStandard("LVCMOS15")),
  81
  82     ("rotary", 0,
  83         Subsignal("a", Pins("Y26")),
  84         Subsignal("b", Pins("Y25")),
  85         Subsignal("push", Pins("AA26")),
  86         IOStandard("LVCMOS25")),
  87
  88     ("hdmi", 0,
  89         Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")),
  90         Subsignal("de", Pins("H17")),
  91         Subsignal("clk", Pins("K18")),
  92         Subsignal("vsync", Pins("H20")),
  93         Subsignal("hsync", Pins("J18")),
  94         Subsignal("int", Pins("AH24")),
  95         Subsignal("spdif", Pins("J17")),
  96         Subsignal("spdif_out", Pins("G20")),
  97         IOStandard("LVCMOS25")),
  98
  99     ("ddram", 0,
 100         Subsignal("a", Pins(
 101             "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
 102             "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
 103             IOStandard("SSTL15")),
 104         Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
 105         Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
 106         Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
 107         Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
 108         Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
 109         Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
 110             IOStandard("SSTL15")),
 111         Subsignal("dq", Pins(
 112             "AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
 113             "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
 114             "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
 115             "AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
 116             "AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
 117             "AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
 118             "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
 119             "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
 120             IOStandard("SSTL15_T_DCI")),
 121         Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
 122             IOStandard("DIFF_SSTL15")),
 123         Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
 124             IOStandard("DIFF_SSTL15")),
 125         Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")),
 126         Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")),
 127         Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
 128         Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")),
 129         Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
 130         Misc("SLEW=FAST"),
 131         Misc("VCCAUX_IO=HIGH")
 132     ),
 133
 134     ("eth_clocks", 0,
 135         Subsignal("tx", Pins("M28")),
 136         Subsignal("gtx", Pins("K30")),
 137         Subsignal("rx", Pins("U27")),
 138         IOStandard("LVCMOS25")
 139     ),
 140     ("eth", 0,
 141         Subsignal("rst_n", Pins("L20")),
 142         Subsignal("int_n", Pins("N30")),
 143         Subsignal("mdio", Pins("J21")),
 144         Subsignal("mdc", Pins("R23")),
 145         Subsignal("dv", Pins("R28")),
 146         Subsignal("rx_er", Pins("V26")),
 147         Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
 148         Subsignal("tx_en", Pins("M27")),
 149         Subsignal("tx_er", Pins("N29")),
 150         Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
 151         Subsignal("col", Pins("W19")),
 152         Subsignal("crs", Pins("R30")),
 153         IOStandard("LVCMOS25")
 154     ),
 155
 156     ("pcie_x1", 0,
 157         Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
 158         Subsignal("clk_p", Pins("U8")),
 159         Subsignal("clk_n", Pins("U7")),
 160         Subsignal("rx_p", Pins("M6")),
 161         Subsignal("rx_n", Pins("M5")),
 162         Subsignal("tx_p", Pins("L4")),
 163         Subsignal("tx_n", Pins("L3"))
 164     ),
 165     ("pcie_x2", 0,
 166         Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
 167         Subsignal("clk_p", Pins("U8")),
 168         Subsignal("clk_n", Pins("U7")),
 169         Subsignal("rx_p", Pins("M6 P6")),
 170         Subsignal("rx_n", Pins("M5 P5")),
 171         Subsignal("tx_p", Pins("L4 M2")),
 172         Subsignal("tx_n", Pins("L3 M1"))
 173     ),
 174     ("pcie_x4", 0,
 175         Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
 176         Subsignal("clk_p", Pins("U8")),
 177         Subsignal("clk_n", Pins("U7")),
 178         Subsignal("rx_p", Pins("M6 P6 R4 T6")),
 179         Subsignal("rx_n", Pins("M5 P5 R3 T5")),
 180         Subsignal("tx_p", Pins("L4 M2 N4 P2")),
 181         Subsignal("tx_n", Pins("L3 M1 N3 P1"))
 182     ),
 183     ("pcie_x8", 0,
 184         Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
 185         Subsignal("clk_p", Pins("U8")),
 186         Subsignal("clk_n", Pins("U7")),
 187         Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")),
 188         Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")),
 189         Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")),
 190         Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1"))
 191     )
 192 ]
 193
 194 _connectors = [
 195     ("HPC", {
 196         "DP1_M2C_P": "D6",
 197         "DP1_M2C_N": "D5",
 198         "DP2_M2C_P": "B6",
 199         "DP2_M2C_N": "B5",
 200         "DP3_M2C_P": "A8",
 201         "DP3_M2C_N": "A7",
 202         "DP1_C2M_P": "C4",
 203         "DP1_C2M_N": "C3",
 204         "DP2_C2M_P": "B2",
 205         "DP2_C2M_N": "B1",
 206         "DP3_C2M_P": "A4",
 207         "DP3_C2M_N": "A3",
 208         "DP0_C2M_P": "D2",
 209         "DP0_C2M_N": "D1",
 210         "DP0_M2C_P": "E4",
 211         "DP0_M2C_N": "E3",
 212         "LA06_P": "H30",
 213         "LA06_N": "G30",
 214         "LA10_P": "D29",
 215         "LA10_N": "C30",
 216         "LA14_P": "B28",
 217         "LA14_N": "A28",
 218         "LA18_CC_P": "F21",
 219         "LA18_CC_N": "E21",
 220         "LA27_P": "C19",
 221         "LA27_N": "B19",
 222         "HA01_CC_P": "H14",
 223         "HA01_CC_N": "G14",
 224         "HA05_P": "F15",
 225         "HA05_N": "E16",
 226         "HA09_P": "F12",
 227         "HA09_N": "E13",
 228         "HA13_P": "L16",
 229         "HA13_N": "K16",
 230         "HA16_P": "L15",
 231         "HA16_N": "K15",
 232         "HA20_P": "K13",
 233         "HA20_N": "J13",
 234         "CLK1_M2C_P": "D17",
 235         "CLK1_M2C_N": "D18",
 236         "LA00_CC_P": "C25",
 237         "LA00_CC_N": "B25",
 238         "LA03_P": "H26",
 239         "LA03_N": "H27",
 240         "LA08_P": "E29",
 241         "LA08_N": "E30",
 242         "LA12_P": "C29",
 243         "LA12_N": "B29",
 244         "LA16_P": "B27",
 245         "LA16_N": "A27",
 246         "LA20_P": "E19",
 247         "LA20_N": "D19",
 248         "LA22_P": "C20",
 249         "LA22_N": "B20",
 250         "LA25_P": "G17",
 251         "LA25_N": "F17",
 252         "LA29_P": "C17",
 253         "LA29_N": "B17",
 254         "LA31_P": "G22",
 255         "LA31_N": "F22",
 256         "LA33_P": "H21",
 257         "LA33_N": "H22",
 258         "HA03_P": "C12",
 259         "HA03_N": "B12",
 260         "HA07_P": "B14",
 261         "HA07_N": "A15",
 262         "HA11_P": "B13",
 263         "HA11_N": "A13",
 264         "HA14_P": "J16",
 265         "HA14_N": "H16",
 266         "HA18_P": "K14",
 267         "HA18_N": "J14",
 268         "HA22_P": "L11",
 269         "HA22_N": "K11",
 270         "GBTCLK1_M2C_P": "E8",
 271         "GBTCLK1_M2C_N": "E7",
 272         "GBTCLK0_M2C_P": "C8",
 273         "GBTCLK0_M2C_N": "C7",
 274         "LA01_CC_P": "D26",
 275         "LA01_CC_N": "C26",
 276         "LA05_P": "G29",
 277         "LA05_N": "F30",
 278         "LA09_P": "B30",
 279         "LA09_N": "A30",
 280         "LA13_P": "A25",
 281         "LA13_N": "A26",
 282         "LA17_CC_P": "F20",
 283         "LA17_CC_N": "E20",
 284         "LA23_P": "B22",
 285         "LA23_N": "A22",
 286         "LA26_P": "B18",
 287         "LA26_N": "A18",
 288         "PG_M2C": "J29",
 289         "HA00_CC_P": "D12",
 290         "HA00_CC_N": "D13",
 291         "HA04_P": "F11",
 292         "HA04_N": "E11",
 293         "HA08_P": "E14",
 294         "HA08_N": "E15",
 295         "HA12_P": "C15",
 296         "HA12_N": "B15",
 297         "HA15_P": "H15",
 298         "HA15_N": "G15",
 299         "HA19_P": "H11",
 300         "HA19_N": "H12",
 301         "PRSNT_M2C_B": "M20",
 302         "CLK0_M2C_P": "D27",
 303         "CLK0_M2C_N": "C27",
 304         "LA02_P": "H24",
 305         "LA02_N": "H25",
 306         "LA04_P": "G28",
 307         "LA04_N": "F28",
 308         "LA07_P": "E28",
 309         "LA07_N": "D28",
 310         "LA11_P": "G27",
 311         "LA11_N": "F27",
 312         "LA15_P": "C24",
 313         "LA15_N": "B24",
 314         "LA19_P": "G18",
 315         "LA19_N": "F18",
 316         "LA21_P": "A20",
 317         "LA21_N": "A21",
 318         "LA24_P": "A16",
 319         "LA24_N": "A17",
 320         "LA28_P": "D16",
 321         "LA28_N": "C16",
 322         "LA30_P": "D22",
 323         "LA30_N": "C22",
 324         "LA32_P": "D21",
 325         "LA32_N": "C21",
 326         "HA02_P": "D11",
 327         "HA02_N": "C11",
 328         "HA06_P": "D14",
 329         "HA06_N": "C14",
 330         "HA10_P": "A11",
 331         "HA10_N": "A12",
 332         "HA17_CC_P": "G13",
 333         "HA17_CC_N": "F13",
 334         "HA21_P": "J11",
 335         "HA21_N": "J12",
 336         "HA23_P": "L12",
 337         "HA23_N": "L13",
 338         }
 339     ),
 340     ("LPC", {
 341         "GBTCLK0_M2C_P": "N8",
 342         "GBTCLK0_M2C_N": "N7",
 343         "LA01_CC_P": "AE23",
 344         "LA01_CC_N": "AF23",
 345         "LA05_P": "AG22",
 346         "LA05_N": "AH22",
 347         "LA09_P": "AK23",
 348         "LA09_N": "AK24",
 349         "LA13_P": "AB24",
 350         "LA13_N": "AC25",
 351         "LA17_CC_P": "AB27",
 352         "LA17_CC_N": "AC27",
 353         "LA23_P": "AH26",
 354         "LA23_N": "AH27",
 355         "LA26_P": "AK29",
 356         "LA26_N": "AK30",
 357         "CLK0_M2C_P": "AF22",
 358         "CLK0_M2C_N": "AG23",
 359         "LA02_P": "AF20",
 360         "LA02_N": "AF21",
 361         "LA04_P": "AH21",
 362         "LA04_N": "AJ21",
 363         "LA07_P": "AG25",
 364         "LA07_N": "AH25",
 365         "LA11_P": "AE25",
 366         "LA11_N": "AF25",
 367         "LA15_P": "AC24",
 368         "LA15_N": "AD24",
 369         "LA19_P": "AJ26",
 370         "LA19_N": "AK26",
 371         "LA21_P": "AG27",
 372         "LA21_N": "AG28",
 373         "LA24_P": "AG30",
 374         "LA24_N": "AH30",
 375         "LA28_P": "AE30",
 376         "LA28_N": "AF30",
 377         "LA30_P": "AB29",
 378         "LA30_N": "AB30",
 379         "LA32_P": "Y30",
 380         "LA32_N": "AA30",
 381         "LA06_P": "AK20",
 382         "LA06_N": "AK21",
 383         "LA10_P": "AJ24",
 384         "LA10_N": "AK25",
 385         "LA14_P": "AD21",
 386         "LA14_N": "AE21",
 387         "LA18_CC_P": "AD27",
 388         "LA18_CC_N": "AD28",
 389         "LA27_P": "AJ28",
 390         "LA27_N": "AJ29",
 391         "CLK1_M2C_P": "AG29",
 392         "CLK1_M2C_N": "AH29",
 393         "LA00_CC_P": "AD23",
 394         "LA00_CC_N": "AE24",
 395         "LA03_P": "AG20",
 396         "LA03_N": "AH20",
 397         "LA08_P": "AJ22",
 398         "LA08_N": "AJ23",
 399         "LA12_P": "AA20",
 400         "LA12_N": "AB20",
 401         "LA16_P": "AC22",
 402         "LA16_N": "AD22",
 403         "LA20_P": "AF26",
 404         "LA20_N": "AF27",
 405         "LA22_P": "AJ27",
 406         "LA22_N": "AK28",
 407         "LA25_P": "AC26",
 408         "LA25_N": "AD26",
 409         "LA29_P": "AE28",
 410         "LA29_N": "AF28",
 411         "LA31_P": "AD29",
 412         "LA31_N": "AE29",
 413         "LA33_P": "AC29",
 414         "LA33_N": "AC30",
 415         }
 416     )
 417 ]
 418
 419
 420 class Platform(XilinxPlatform):
 421     identifier = 0x4B37
 422     default_clk_name = "clk156"
 423     default_clk_period = 6.4
 424
 425     def __init__(self, toolchain="vivado", programmer="xc3sprog"):
 426         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
 427             toolchain=toolchain)
 428         if toolchain == "ise":
 429             self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
 430         elif toolchain == "vivado":
 431             self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 432             self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 433         self.programmer = programmer
 434
 435     def create_programmer(self):
 436         if self.programmer == "xc3sprog":
 437             return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
 438         elif self.programmer == "vivado":
 439             return VivadoProgrammer()
 440         elif self.programmer == "impact":
 441             return iMPACT()
 442         else:
 443             raise ValueError("{} programmer is not supported".format(programmer))
 444
 445     def do_finalize(self, fragment):
 446         XilinxPlatform.do_finalize(self, fragment)
 447         try:
 448             self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
 449         except ConstraintError:
 450             pass
 451         try:
 452             self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
 453         except ConstraintError:
 454             pass
 455         if isinstance(self.toolchain, XilinxISEToolchain):
 456             self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
 457         else:
 458             self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")