litex/gen/migen/genlib/io.py

   1 from migen.fhdl.structure import *
   2 from migen.fhdl.module import Module
   3 from migen.fhdl.specials import Special
   4
   5
   6 class DifferentialInput(Special):
   7     def __init__(self, i_p, i_n, o):
   8         Special.__init__(self)
   9         self.i_p = wrap(i_p)
  10         self.i_n = wrap(i_n)
  11         self.o = wrap(o)
  12
  13     def iter_expressions(self):
  14         yield self, "i_p", SPECIAL_INPUT
  15         yield self, "i_n", SPECIAL_INPUT
  16         yield self, "o", SPECIAL_OUTPUT
  17
  18     @staticmethod
  19     def lower(dr):
  20         raise NotImplementedError("Attempted to use a differential input, but platform does not support them")
  21
  22
  23 class DifferentialOutput(Special):
  24     def __init__(self, i, o_p, o_n):
  25         Special.__init__(self)
  26         self.i = wrap(i)
  27         self.o_p = wrap(o_p)
  28         self.o_n = wrap(o_n)
  29
  30     def iter_expressions(self):
  31         yield self, "i", SPECIAL_INPUT
  32         yield self, "o_p", SPECIAL_OUTPUT
  33         yield self, "o_n", SPECIAL_OUTPUT
  34
  35     @staticmethod
  36     def lower(dr):
  37         raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
  38
  39
  40 class CRG(Module):
  41     def __init__(self, clk, rst=0):
  42         self.clock_domains.cd_sys = ClockDomain()
  43         self.clock_domains.cd_por = ClockDomain(reset_less=True)
  44
  45         if hasattr(clk, "p"):
  46             clk_se = Signal()
  47             self.specials += DifferentialInput(clk.p, clk.n, clk_se)
  48             clk = clk_se
  49
  50         # Power on Reset (vendor agnostic)
  51         int_rst = Signal(reset=1)
  52         self.sync.por += int_rst.eq(rst)
  53         self.comb += [
  54             self.cd_sys.clk.eq(clk),
  55             self.cd_por.clk.eq(clk),
  56             self.cd_sys.rst.eq(int_rst)
  57         ]
  58
  59
  60 class DDRInput(Special):
  61     def __init__(self, i, o1, o2, clk=ClockSignal()):
  62         Special.__init__(self)
  63         self.i = wrap(i)
  64         self.o1 = wrap(o1)
  65         self.o2 = wrap(o2)
  66         self.clk = wrap(clk)
  67
  68     def iter_expressions(self):
  69         yield self, "i", SPECIAL_INPUT
  70         yield self, "o1", SPECIAL_OUTPUT
  71         yield self, "o2", SPECIAL_OUTPUT
  72         yield self, "clk", SPECIAL_INPUT
  73
  74     @staticmethod
  75     def lower(dr):
  76         raise NotImplementedError("Attempted to use a DDR input, but platform does not support them")
  77
  78
  79 class DDROutput(Special):
  80     def __init__(self, i1, i2, o, clk=ClockSignal()):
  81         Special.__init__(self)
  82         self.i1 = i1
  83         self.i2 = i2
  84         self.o = o
  85         self.clk = clk
  86
  87     def iter_expressions(self):
  88         yield self, "i1", SPECIAL_INPUT
  89         yield self, "i2", SPECIAL_INPUT
  90         yield self, "o", SPECIAL_OUTPUT
  91         yield self, "clk", SPECIAL_INPUT
  92
  93     @staticmethod
  94     def lower(dr):
  95         raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
  96