litex/gen/migen/test/support.py

   1 from migen import *
   2 from migen.fhdl import verilog
   3
   4
   5 class SimCase:
   6     def setUp(self, *args, **kwargs):
   7         self.tb = self.TestBench(*args, **kwargs)
   8
   9     def test_to_verilog(self):
  10         verilog.convert(self.tb)
  11
  12     def run_with(self, generator):
  13         run_simulation(self.tb, generator)