litex/soc/cores/cpu/__init__.py

   1 # This file is Copyright (c) 2017-2018 Tim 'mithro' Ansell <me@mith.ro>
   2 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # License: BSD
   4
   5 from migen import *
   6
   7 # CPU ----------------------------------------------------------------------------------------------
   8
   9 class CPU(Module):
  10     name                 = None
  11     data_width           = None
  12     endianness           = None
  13     gcc_triple           = None
  14     gcc_flags            = None
  15     clang_triple         = None
  16     clang_flags          = None
  17     linker_output_format = None
  18     interrupts           = {}
  19     mem_map              = {}
  20     io_regions           = {}
  21     use_rom              = False
  22
  23     def __init__(self, *args, **kwargs):
  24         pass
  25
  26 class CPUNone(CPU):
  27     variants             = ["standard"]
  28     data_width           = 32
  29     endianness           = "little"
  30     reset_address        = 0x00000000
  31     io_regions           = {0x00000000: 0x100000000} # origin, length
  32     periph_buses         = []
  33     memory_buses         = []
  34     mem_map              = {"csr": 0x00000000}
  35
  36 CPU_GCC_TRIPLE_RISCV32 = (
  37     "riscv64-unknown-elf",
  38     "riscv32-unknown-elf",
  39     "riscv64-elf",
  40     "riscv32-elf",
  41     "riscv-none-embed",
  42     "riscv64-linux",
  43     "riscv64-linux-gnu-gcc",
  44     "riscv-sifive-elf",
  45     "riscv64-none-elf",
  46 )
  47
  48 CPU_GCC_TRIPLE_RISCV64 = (
  49     "riscv64-unknown-elf",
  50     "riscv64-elf",
  51     "riscv64-linux",
  52     "riscv64-linux-gnu-gcc",
  53     "riscv-sifive-elf",
  54     "riscv64-none-elf",
  55 )
  56
  57 # CPUS ---------------------------------------------------------------------------------------------
  58
  59 from litex.soc.cores.cpu.lm32 import LM32
  60 from litex.soc.cores.cpu.mor1kx import MOR1KX
  61 from litex.soc.cores.cpu.microwatt import Microwatt
  62 from litex.soc.cores.cpu.serv import SERV
  63 from litex.soc.cores.cpu.picorv32 import PicoRV32
  64 from litex.soc.cores.cpu.minerva import Minerva
  65 from litex.soc.cores.cpu.vexriscv import VexRiscv
  66 from litex.soc.cores.cpu.rocket import RocketRV64
  67 from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
  68 from litex.soc.cores.cpu.cv32e40p import CV32E40P
  69
  70 CPUS = {
  71     # None
  72     "None"        : CPUNone,
  73
  74     # LM32
  75     "lm32"        : LM32,
  76
  77     # OpenRisc
  78     "mor1kx"      : MOR1KX,
  79
  80     # Open Power
  81     "microwatt"   : Microwatt,
  82
  83     # RISC-V 32-bit
  84     "serv"        : SERV,
  85     "picorv32"    : PicoRV32,
  86     "minerva"     : Minerva,
  87     "vexriscv"    : VexRiscv,
  88     "cv32e40p"    : CV32E40P,
  89
  90     # RISC-V 64-bit
  91     "rocket"      : RocketRV64,
  92     "blackparrot" : BlackParrotRV64,
  93 }