litex/soc/cores/cpu/serv/core.py

   1 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # This file is Copyright (c) 2020 Greg Davill <greg.davill@gmail.com>
   3 # License: BSD
   4
   5 import os
   6
   7 from migen import *
   8
   9 from litex import get_data_mod
  10 from litex.soc.interconnect import wishbone
  11 from litex.soc.cores.cpu import CPU
  12
  13
  14 CPU_VARIANTS = ["standard"]
  15
  16
  17 class SERV(CPU):
  18     name                 = "serv"
  19     data_width           = 32
  20     endianness           = "little"
  21     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
  22                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
  23     linker_output_format = "elf32-littleriscv"
  24     io_regions           = {0x80000000: 0x80000000} # origin, length
  25
  26     @property
  27     def gcc_flags(self):
  28         flags =  "-march=rv32i "
  29         flags += "-mabi=ilp32 "
  30         flags += "-D__serv__ "
  31         return flags
  32
  33     def __init__(self, platform, variant="standard"):
  34         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
  35         self.platform     = platform
  36         self.variant      = variant
  37         self.reset        = Signal()
  38         self.ibus         = ibus = wishbone.Interface()
  39         self.dbus         = dbus = wishbone.Interface()
  40         self.periph_buses = [ibus, dbus]
  41         self.memory_buses = []
  42
  43         # # #
  44
  45         self.cpu_params = dict(
  46             # clock / reset
  47             i_clk   = ClockSignal(),
  48             i_i_rst = ResetSignal() | self.reset,
  49
  50             # timer irq
  51             i_i_timer_irq = 0,
  52
  53             # ibus
  54             o_o_ibus_adr = Cat(Signal(2), ibus.adr),
  55             o_o_ibus_cyc = ibus.cyc,
  56             i_i_ibus_rdt = ibus.dat_r,
  57             i_i_ibus_ack = ibus.ack,
  58
  59             # dbus
  60             o_o_dbus_adr = Cat(Signal(2), dbus.adr),
  61             o_o_dbus_dat = dbus.dat_w,
  62             o_o_dbus_sel = dbus.sel,
  63             o_o_dbus_we  = dbus.we,
  64             o_o_dbus_cyc = dbus.cyc,
  65             i_i_dbus_rdt = dbus.dat_r,
  66             i_i_dbus_ack = dbus.ack,
  67         )
  68         self.comb += [
  69             ibus.stb.eq(ibus.cyc),
  70             ibus.sel.eq(0xf),
  71             dbus.stb.eq(dbus.cyc),
  72         ]
  73
  74         # add verilog sources
  75         self.add_sources(platform)
  76
  77     def set_reset_address(self, reset_address):
  78         assert not hasattr(self, "reset_address")
  79         self.reset_address = reset_address
  80         self.cpu_params.update(p_RESET_PC=reset_address)
  81
  82     @staticmethod
  83     def add_sources(platform):
  84         vdir = get_data_mod("cpu", "serv").data_location
  85         platform.add_source_dir(os.path.join(vdir, "rtl"))
  86         platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
  87
  88     def do_finalize(self):
  89         assert hasattr(self, "reset_address")
  90         self.specials += Instance("serv_rf_top", **self.cpu_params)