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[litex.git] / litex / soc / integration / soc.py
1 # This file is Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
2 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
3 # This file is Copyright (c) 2019 Gabriel L. Somlo <somlo@cmu.edu>
4 # License: BSD
5
6 import logging
7 import time
8 import datetime
9 from math import log2, ceil
10
11 from migen import *
12
13 from litex.soc.cores import cpu
14 from litex.soc.cores.identifier import Identifier
15 from litex.soc.cores.timer import Timer
16 from litex.soc.cores.spi_flash import SpiFlash
17 from litex.soc.cores.spi import SPIMaster
18
19 from litex.soc.interconnect.csr import *
20 from litex.soc.interconnect import csr_bus
21 from litex.soc.interconnect import stream
22 from litex.soc.interconnect import wishbone
23 from litex.soc.interconnect import axi
24
25 logging.basicConfig(level=logging.INFO)
26
27 # Helpers ------------------------------------------------------------------------------------------
28
29 def auto_int(x):
30 return int(x, 0)
31
32 def colorer(s, color="bright"):
33 header = {
34 "bright": "\x1b[1m",
35 "green": "\x1b[32m",
36 "cyan": "\x1b[36m",
37 "red": "\x1b[31m",
38 "yellow": "\x1b[33m",
39 "underline": "\x1b[4m"}[color]
40 trailer = "\x1b[0m"
41 return header + str(s) + trailer
42
43 def build_time(with_time=True):
44 fmt = "%Y-%m-%d %H:%M:%S" if with_time else "%Y-%m-%d"
45 return datetime.datetime.fromtimestamp(time.time()).strftime(fmt)
46
47 # SoCConstant --------------------------------------------------------------------------------------
48
49 def SoCConstant(value):
50 return value
51
52 # SoCRegion ----------------------------------------------------------------------------------------
53
54 class SoCRegion:
55 def __init__(self, origin=None, size=None, mode="rw", cached=True, linker=False):
56 self.logger = logging.getLogger("SoCRegion")
57 self.origin = origin
58 self.size = size
59 if size != 2**log2_int(size, False):
60 self.logger.info("Region size {} internally from {} to {}.".format(
61 colorer("rounded", color="cyan"),
62 colorer("0x{:08x}".format(size)),
63 colorer("0x{:08x}".format(2**log2_int(size, False)))))
64 self.size_pow2 = 2**log2_int(size, False)
65 self.mode = mode
66 self.cached = cached
67 self.linker = linker
68
69 def decoder(self, bus):
70 origin = self.origin
71 size = self.size_pow2
72 if (origin & (size - 1)) != 0:
73 self.logger.error("Origin needs to be aligned on size:")
74 self.logger.error(self)
75 raise
76 origin >>= int(log2(bus.data_width//8)) # bytes to words aligned
77 size >>= int(log2(bus.data_width//8)) # bytes to words aligned
78 return lambda a: (a[log2_int(size):] == (origin >> log2_int(size)))
79
80 def __str__(self):
81 r = ""
82 if self.origin is not None:
83 r += "Origin: {}, ".format(colorer("0x{:08x}".format(self.origin)))
84 if self.size is not None:
85 r += "Size: {}, ".format(colorer("0x{:08x}".format(self.size)))
86 r += "Mode: {}, ".format(colorer(self.mode.upper()))
87 r += "Cached: {} ".format(colorer(self.cached))
88 r += "Linker: {}".format(colorer(self.linker))
89 return r
90
91 class SoCIORegion(SoCRegion): pass
92
93 # SoCCSRRegion -------------------------------------------------------------------------------------
94
95 class SoCCSRRegion:
96 def __init__(self, origin, busword, obj):
97 self.origin = origin
98 self.busword = busword
99 self.obj = obj
100
101 # SoCBusHandler ------------------------------------------------------------------------------------
102
103 class SoCBusHandler(Module):
104 supported_standard = ["wishbone"]
105 supported_data_width = [32, 64]
106 supported_address_width = [32]
107
108 # Creation -------------------------------------------------------------------------------------
109 def __init__(self, standard, data_width=32, address_width=32, timeout=1e6, reserved_regions={}):
110 self.logger = logging.getLogger("SoCBusHandler")
111 self.logger.info("Creating Bus Handler...")
112
113 # Check Standard
114 if standard not in self.supported_standard:
115 self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
116 colorer("Bus standard", color="red"),
117 colorer(standard),
118 colorer(", ".join(self.supported_standard))))
119 raise
120
121 # Check Data Width
122 if data_width not in self.supported_data_width:
123 self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
124 colorer("Data Width", color="red"),
125 colorer(data_width),
126 colorer(", ".join(str(x) for x in self.supported_data_width))))
127 raise
128
129 # Check Address Width
130 if address_width not in self.supported_address_width:
131 self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
132 colorer("Address Width", color="red"),
133 colorer(data_width),
134 colorer(", ".join(str(x) for x in self.supported_address_width))))
135 raise
136
137 # Create Bus
138 self.standard = standard
139 self.data_width = data_width
140 self.address_width = address_width
141 self.masters = {}
142 self.slaves = {}
143 self.regions = {}
144 self.io_regions = {}
145 self.timeout = timeout
146 self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
147 colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
148
149 # Adding reserved regions
150 self.logger.info("Adding {} Bus Regions...".format(colorer("reserved", color="cyan")))
151 for name, region in reserved_regions.items():
152 if isinstance(region, int):
153 region = SoCRegion(origin=region, size=0x1000000)
154 self.add_region(name, region)
155
156 self.logger.info("Bus Handler {}.".format(colorer("created", color="green")))
157
158 # Add/Allog/Check Regions ----------------------------------------------------------------------
159 def add_region(self, name, region):
160 allocated = False
161 if name in self.regions.keys() or name in self.io_regions.keys():
162 self.logger.error("{} already declared as Region:".format(colorer(name, color="red")))
163 self.logger.error(self)
164 raise
165 # Check if SoCIORegion
166 if isinstance(region, SoCIORegion):
167 self.io_regions[name] = region
168 overlap = self.check_regions_overlap(self.io_regions)
169 if overlap is not None:
170 self.logger.error("IO Region {} between {} and {}:".format(
171 colorer("overlap", color="red"),
172 colorer(overlap[0]),
173 colorer(overlap[1])))
174 self.logger.error(str(self.io_regions[overlap[0]]))
175 self.logger.error(str(self.io_regions[overlap[1]]))
176 raise
177 self.logger.info("{} Region {} at {}.".format(
178 colorer(name, color="underline"),
179 colorer("added", color="green"),
180 str(region)))
181 # Check if SoCRegion
182 elif isinstance(region, SoCRegion):
183 # If no origin specified, allocate region.
184 if region.origin is None:
185 allocated = True
186 region = self.alloc_region(name, region.size, region.cached)
187 self.regions[name] = region
188 # Else add region and check for overlaps.
189 else:
190 if not region.cached:
191 if not self.check_region_is_io(region):
192 self.logger.error("{} Region {}: {}.".format(
193 colorer(name),
194 colorer("not in IO region", color="red"),
195 str(region)))
196 self.logger.error(self)
197 raise
198 self.regions[name] = region
199 overlap = self.check_regions_overlap(self.regions)
200 if overlap is not None:
201 self.logger.error("Region {} between {} and {}:".format(
202 colorer("overlap", color="red"),
203 colorer(overlap[0]),
204 colorer(overlap[1])))
205 self.logger.error(str(self.regions[overlap[0]]))
206 self.logger.error(str(self.regions[overlap[1]]))
207 raise
208 self.logger.info("{} Region {} at {}.".format(
209 colorer(name, color="underline"),
210 colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
211 str(region)))
212 else:
213 self.logger.error("{} is not a supported Region.".format(colorer(name, color="red")))
214 raise
215
216 def alloc_region(self, name, size, cached=True):
217 self.logger.info("Allocating {} Region of size {}...".format(
218 colorer("Cached" if cached else "IO"),
219 colorer("0x{:08x}".format(size))))
220
221 # Limit Search Regions
222 if cached == False:
223 search_regions = self.io_regions
224 else:
225 search_regions = {"main": SoCRegion(origin=0x00000000, size=2**self.address_width-1)}
226
227 # Iterate on Search_Regions to find a Candidate
228 for _, search_region in search_regions.items():
229 origin = search_region.origin
230 while (origin + size) < (search_region.origin + search_region.size_pow2):
231 # Create a Candicate.
232 candidate = SoCRegion(origin=origin, size=size, cached=cached)
233 overlap = False
234 # Check Candidate does not overlap with allocated existing regions
235 for _, allocated in self.regions.items():
236 if self.check_regions_overlap({"0": allocated, "1": candidate}) is not None:
237 origin = allocated.origin + allocated.size_pow2
238 overlap = True
239 break
240 if not overlap:
241 # If no overlap, the Candidate is selected
242 return candidate
243
244 self.logger.error("Not enough Address Space to allocate Region.")
245 raise
246
247 def check_regions_overlap(self, regions, check_linker=False):
248 i = 0
249 while i < len(regions):
250 n0 = list(regions.keys())[i]
251 r0 = regions[n0]
252 for n1 in list(regions.keys())[i+1:]:
253 r1 = regions[n1]
254 if r0.linker or r1.linker:
255 if not check_linker:
256 continue
257 if r0.origin >= (r1.origin + r1.size_pow2):
258 continue
259 if r1.origin >= (r0.origin + r0.size_pow2):
260 continue
261 return (n0, n1)
262 i += 1
263 return None
264
265 def check_region_is_in(self, region, container):
266 is_in = True
267 if not (region.origin >= container.origin):
268 is_in = False
269 if not ((region.origin + region.size) < (container.origin + container.size)):
270 is_in = False
271 return is_in
272
273 def check_region_is_io(self, region):
274 is_io = False
275 for _, io_region in self.io_regions.items():
276 if self.check_region_is_in(region, io_region):
277 is_io = True
278 return is_io
279
280 # Add Master/Slave -----------------------------------------------------------------------------
281 def add_adapter(self, name, interface, direction="m2s"):
282 assert direction in ["m2s", "s2m"]
283
284 if isinstance(interface, wishbone.Interface):
285 new_interface = wishbone.Interface(data_width=self.data_width)
286 if direction == "m2s":
287 converter = wishbone.Converter(master=interface, slave=new_interface)
288 if direction == "s2m":
289 converter = wishbone.Converter(master=new_interface, slave=interface)
290 self.submodules += converter
291 elif isinstance(interface, axi.AXILiteInterface):
292 # Data width conversion
293 intermediate = axi.AXILiteInterface(data_width=self.data_width)
294 if direction == "m2s":
295 converter = axi.AXILiteConverter(master=interface, slave=intermediate)
296 if direction == "s2m":
297 converter = axi.AXILiteConverter(master=intermediate, slave=interface)
298 self.submodules += converter
299 # Bus type conversion
300 new_interface = wishbone.Interface(data_width=self.data_width)
301 if direction == "m2s":
302 converter = axi.AXILite2Wishbone(axi_lite=intermediate, wishbone=new_interface)
303 elif direction == "s2m":
304 converter = axi.Wishbone2AXILite(wishbone=new_interface, axi_lite=intermediate)
305 self.submodules += converter
306 else:
307 raise TypeError(interface)
308
309 fmt = "{name} Bus {converted} from {frombus} {frombits}-bit to {tobus} {tobits}-bit."
310 frombus = "Wishbone" if isinstance(interface, wishbone.Interface) else "AXILite"
311 tobus = "Wishbone" if isinstance(new_interface, wishbone.Interface) else "AXILite"
312 frombits = interface.data_width
313 tobits = new_interface.data_width
314 if frombus != tobus or frombits != tobits:
315 self.logger.info(fmt.format(
316 name = colorer(name),
317 converted = colorer("converted", color="cyan"),
318 frombus = colorer("Wishbone" if isinstance(interface, wishbone.Interface) else "AXILite"),
319 frombits = colorer(interface.data_width),
320 tobus = colorer("Wishbone" if isinstance(new_interface, wishbone.Interface) else "AXILite"),
321 tobits = colorer(new_interface.data_width)))
322 return new_interface
323
324 def add_master(self, name=None, master=None):
325 if name is None:
326 name = "master{:d}".format(len(self.masters))
327 if name in self.masters.keys():
328 self.logger.error("{} {} as Bus Master:".format(
329 colorer(name),
330 colorer("already declared", color="red")))
331 self.logger.error(self)
332 raise
333 master = self.add_adapter(name, master, "m2s")
334 self.masters[name] = master
335 self.logger.info("{} {} as Bus Master.".format(
336 colorer(name, color="underline"),
337 colorer("added", color="green")))
338
339 def add_slave(self, name=None, slave=None, region=None):
340 no_name = name is None
341 no_region = region is None
342 if no_name and no_region:
343 self.logger.error("Please {} {} or/and {} of Bus Slave.".format(
344 colorer("specify", color="red"),
345 colorer("name"),
346 colorer("region")))
347 raise
348 if no_name:
349 name = "slave{:d}".format(len(self.slaves))
350 if no_region:
351 region = self.regions.get(name, None)
352 if region is None:
353 self.logger.error("{} Region {}.".format(
354 colorer(name),
355 colorer("not found", color="red")))
356 raise
357 else:
358 self.add_region(name, region)
359 if name in self.slaves.keys():
360 self.logger.error("{} {} as Bus Slave:".format(
361 colorer(name),
362 colorer("already declared", color="red")))
363 self.logger.error(self)
364 raise
365 slave = self.add_adapter(name, slave, "s2m")
366 self.slaves[name] = slave
367 self.logger.info("{} {} as Bus Slave.".format(
368 colorer(name, color="underline"),
369 colorer("added", color="green")))
370
371 # Str ------------------------------------------------------------------------------------------
372 def __str__(self):
373 r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
374 colorer(self.data_width), colorer(self.standard), colorer(2**self.address_width/2**30))
375 r += "IO Regions: ({})\n".format(len(self.io_regions.keys())) if len(self.io_regions.keys()) else ""
376 io_regions = {k: v for k, v in sorted(self.io_regions.items(), key=lambda item: item[1].origin)}
377 for name, region in io_regions.items():
378 r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
379 r += "Bus Regions: ({})\n".format(len(self.regions.keys())) if len(self.regions.keys()) else ""
380 regions = {k: v for k, v in sorted(self.regions.items(), key=lambda item: item[1].origin)}
381 for name, region in regions.items():
382 r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
383 r += "Bus Masters: ({})\n".format(len(self.masters.keys())) if len(self.masters.keys()) else ""
384 for name in self.masters.keys():
385 r += "- {}\n".format(colorer(name, color="underline"))
386 r += "Bus Slaves: ({})\n".format(len(self.slaves.keys())) if len(self.slaves.keys()) else ""
387 for name in self.slaves.keys():
388 r += "- {}\n".format(colorer(name, color="underline"))
389 r = r[:-1]
390 return r
391
392 # SoCLocHandler --------------------------------------------------------------------------------------
393
394 class SoCLocHandler(Module):
395 # Creation -------------------------------------------------------------------------------------
396 def __init__(self, name, n_locs):
397 self.name = name
398 self.locs = {}
399 self.n_locs = n_locs
400
401 # Add ------------------------------------------------------------------------------------------
402 def add(self, name, n=None, use_loc_if_exists=False):
403 allocated = False
404 if not (use_loc_if_exists and name in self.locs.keys()):
405 if name in self.locs.keys():
406 self.logger.error("{} {} name {}.".format(
407 colorer(name), self.name, colorer("already used", color="red")))
408 self.logger.error(self)
409 raise
410 if n in self.locs.values():
411 self.logger.error("{} {} Location {}.".format(
412 colorer(n), self.name, colorer("already used", color="red")))
413 self.logger.error(self)
414 raise
415 if n is None:
416 allocated = True
417 n = self.alloc(name)
418 else:
419 if n < 0:
420 self.logger.error("{} {} Location should be {}.".format(
421 colorer(n),
422 self.name,
423 colorer("positive", color="red")))
424 raise
425 if n > self.n_locs:
426 self.logger.error("{} {} Location {} than maximum: {}.".format(
427 colorer(n),
428 self.name,
429 colorer("higher", color="red"),
430 colorer(self.n_locs)))
431 raise
432 self.locs[name] = n
433 else:
434 n = self.locs[name]
435 self.logger.info("{} {} {} at Location {}.".format(
436 colorer(name, color="underline"),
437 self.name,
438 colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
439 colorer(n)))
440
441 # Alloc ----------------------------------------------------------------------------------------
442 def alloc(self, name):
443 for n in range(self.n_locs):
444 if n not in self.locs.values():
445 return n
446 self.logger.error("Not enough Locations.")
447 self.logger.error(self)
448 raise
449
450 # Str ------------------------------------------------------------------------------------------
451 def __str__(self):
452 r = "{} Locations: ({})\n".format(self.name, len(self.locs.keys())) if len(self.locs.keys()) else ""
453 locs = {k: v for k, v in sorted(self.locs.items(), key=lambda item: item[1])}
454 length = 0
455 for name in locs.keys():
456 if len(name) > length: length = len(name)
457 for name in locs.keys():
458 r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(length + 1 - len(name)), colorer(self.locs[name]))
459 return r
460
461 # SoCCSRHandler ------------------------------------------------------------------------------------
462
463 class SoCCSRHandler(SoCLocHandler):
464 supported_data_width = [8, 32]
465 supported_address_width = [14+i for i in range(4)]
466 supported_alignment = [32]
467 supported_paging = [0x800*2**i for i in range(4)]
468
469 # Creation -------------------------------------------------------------------------------------
470 def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
471 SoCLocHandler.__init__(self, "CSR", n_locs=alignment//8*(2**address_width)//paging)
472 self.logger = logging.getLogger("SoCCSRHandler")
473 self.logger.info("Creating CSR Handler...")
474
475 # Check Data Width
476 if data_width not in self.supported_data_width:
477 self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
478 colorer("Data Width", color="red"),
479 colorer(data_width),
480 colorer(", ".join(str(x) for x in self.supported_data_width))))
481 raise
482
483 # Check Address Width
484 if address_width not in self.supported_address_width:
485 self.logger.error("Unsupported {} {} supporteds: {:s}".format(
486 colorer("Address Width", color="red"),
487 colorer(address_width),
488 colorer(", ".join(str(x) for x in self.supported_address_width))))
489 raise
490
491 # Check Alignment
492 if alignment not in self.supported_alignment:
493 self.logger.error("Unsupported {}: {} supporteds: {:s}".format(
494 colorer("Alignment", color="red"),
495 colorer(alignment),
496 colorer(", ".join(str(x) for x in self.supported_alignment))))
497 raise
498 if data_width > alignment:
499 self.logger.error("Alignment ({}) {} Data Width ({})".format(
500 colorer(alignment),
501 colorer("should be >=", color="red"),
502 colorer(data_width)))
503 raise
504
505 # Check Paging
506 if paging not in self.supported_paging:
507 self.logger.error("Unsupported {} 0x{}, supporteds: {:s}".format(
508 colorer("Paging", color="red"),
509 colorer("{:x}".format(paging)),
510 colorer(", ".join("0x{:x}".format(x) for x in self.supported_paging))))
511 raise
512
513 # Create CSR Handler
514 self.data_width = data_width
515 self.address_width = address_width
516 self.alignment = alignment
517 self.paging = paging
518 self.masters = {}
519 self.regions = {}
520 self.logger.info("{}-bit CSR Bus, {}-bit Aligned, {}KiB Address Space, {}B Paging (Up to {} Locations).".format(
521 colorer(self.data_width),
522 colorer(self.alignment),
523 colorer(2**self.address_width/2**10),
524 colorer(self.paging),
525 colorer(self.n_locs)))
526
527 # Adding reserved CSRs
528 self.logger.info("Adding {} CSRs...".format(colorer("reserved", color="cyan")))
529 for name, n in reserved_csrs.items():
530 self.add(name, n)
531
532 self.logger.info("CSR Handler {}.".format(colorer("created", color="green")))
533
534 # Add Master -----------------------------------------------------------------------------------
535 def add_master(self, name=None, master=None):
536 if name is None:
537 name = "master{:d}".format(len(self.masters))
538 if name in self.masters.keys():
539 self.logger.error("{} {} as CSR Master:".format(
540 colorer(name),
541 colorer("already declared", color="red")))
542 self.logger.error(self)
543 raise
544 if master.data_width != self.data_width:
545 self.logger.error("{} Master/Handler Data Width {} ({} vs {}).".format(
546 colorer(name),
547 colorer("missmatch", color="red"),
548 colorer(master.data_width),
549 colorer(self.data_width)))
550 raise
551 self.masters[name] = master
552 self.logger.info("{} {} as CSR Master.".format(
553 colorer(name, color="underline"),
554 colorer("added", color="green")))
555
556 # Add Region -----------------------------------------------------------------------------------
557 def add_region(self, name, region):
558 # FIXME: add checks
559 self.regions[name] = region
560
561 # Address map ----------------------------------------------------------------------------------
562 def address_map(self, name, memory):
563 if memory is not None:
564 name = name + "_" + memory.name_override
565 if self.locs.get(name, None) is None:
566 self.logger.error("CSR {} {}.".format(
567 colorer(name),
568 colorer("not found", color="red")))
569 self.logger.error(self)
570 raise
571 return self.locs[name]
572
573 # Str ------------------------------------------------------------------------------------------
574 def __str__(self):
575 r = "{}-bit CSR Bus, {}-bit Aligned, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
576 colorer(self.data_width),
577 colorer(self.alignment),
578 colorer(2**self.address_width/2**10),
579 colorer(self.paging),
580 colorer(self.n_locs))
581 r += SoCLocHandler.__str__(self)
582 r = r[:-1]
583 return r
584
585 # SoCIRQHandler ------------------------------------------------------------------------------------
586
587 class SoCIRQHandler(SoCLocHandler):
588 # Creation -------------------------------------------------------------------------------------
589 def __init__(self, n_irqs=32, reserved_irqs={}):
590 SoCLocHandler.__init__(self, "IRQ", n_locs=n_irqs)
591 self.logger = logging.getLogger("SoCIRQHandler")
592 self.logger.info("Creating IRQ Handler...")
593
594 # Check IRQ Number
595 if n_irqs > 32:
596 self.logger.error("Unsupported IRQs number: {} supporteds: {:s}".format(
597 colorer(n, color="red"), colorer("Up to 32", color="green")))
598 raise
599
600 # Create IRQ Handler
601 self.logger.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs)))
602
603 # Adding reserved IRQs
604 self.logger.info("Adding {} IRQs...".format(colorer("reserved", color="cyan")))
605 for name, n in reserved_irqs.items():
606 self.add(name, n)
607
608 self.logger.info("IRQ Handler {}.".format(colorer("created", color="green")))
609
610 # Str ------------------------------------------------------------------------------------------
611 def __str__(self):
612 r ="IRQ Handler (up to {} Locations).\n".format(colorer(self.n_locs))
613 r += SoCLocHandler.__str__(self)
614 r = r[:-1]
615 return r
616
617 # SoCController ------------------------------------------------------------------------------------
618
619 class SoCController(Module, AutoCSR):
620 def __init__(self,
621 with_reset = True,
622 with_scratch = True,
623 with_errors = True):
624
625 if with_reset:
626 self._reset = CSRStorage(1, description="""Write a ``1`` to this register to reset the SoC.""")
627 if with_scratch:
628 self._scratch = CSRStorage(32, reset=0x12345678, description="""
629 Use this register as a scratch space to verify that software read/write accesses
630 to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
631 can be used to verify endianness.""")
632 if with_errors:
633 self._bus_errors = CSRStatus(32, description="Total number of Wishbone bus errors (timeouts) since start.")
634
635 # # #
636
637 # Reset
638 if with_reset:
639 self.reset = Signal()
640 self.comb += self.reset.eq(self._reset.re)
641
642 # Errors
643 if with_errors:
644 self.bus_error = Signal()
645 bus_errors = Signal(32)
646 self.sync += [
647 If(bus_errors != (2**len(bus_errors)-1),
648 If(self.bus_error, bus_errors.eq(bus_errors + 1))
649 )
650 ]
651 self.comb += self._bus_errors.status.eq(bus_errors)
652
653 # SoC ----------------------------------------------------------------------------------------------
654
655 class SoC(Module):
656 mem_map = {}
657 def __init__(self, platform, sys_clk_freq,
658 bus_standard = "wishbone",
659 bus_data_width = 32,
660 bus_address_width = 32,
661 bus_timeout = 1e6,
662 bus_reserved_regions = {},
663
664 csr_data_width = 32,
665 csr_address_width = 14,
666 csr_paging = 0x800,
667 csr_reserved_csrs = {},
668
669 irq_n_irqs = 32,
670 irq_reserved_irqs = {},
671 ):
672
673 self.logger = logging.getLogger("SoC")
674 self.logger.info(colorer(" __ _ __ _ __ ", color="bright"))
675 self.logger.info(colorer(" / / (_) /____ | |/_/ ", color="bright"))
676 self.logger.info(colorer(" / /__/ / __/ -_)> < ", color="bright"))
677 self.logger.info(colorer(" /____/_/\\__/\\__/_/|_| ", color="bright"))
678 self.logger.info(colorer(" Build your hardware, easily!", color="bright"))
679
680 self.logger.info(colorer("-"*80, color="bright"))
681 self.logger.info(colorer("Creating SoC... ({})".format(build_time())))
682 self.logger.info(colorer("-"*80, color="bright"))
683 self.logger.info("FPGA device : {}.".format(platform.device))
684 self.logger.info("System clock: {:3.2f}MHz.".format(sys_clk_freq/1e6))
685
686 # SoC attributes ---------------------------------------------------------------------------
687 self.platform = platform
688 self.sys_clk_freq = sys_clk_freq
689 self.constants = {}
690 self.csr_regions = {}
691
692 # SoC Bus Handler --------------------------------------------------------------------------
693 self.submodules.bus = SoCBusHandler(
694 standard = bus_standard,
695 data_width = bus_data_width,
696 address_width = bus_address_width,
697 timeout = bus_timeout,
698 reserved_regions = bus_reserved_regions,
699 )
700
701 # SoC Bus Handler --------------------------------------------------------------------------
702 self.submodules.csr = SoCCSRHandler(
703 data_width = csr_data_width,
704 address_width = csr_address_width,
705 alignment = 32,
706 paging = csr_paging,
707 reserved_csrs = csr_reserved_csrs,
708 )
709
710 # SoC IRQ Handler --------------------------------------------------------------------------
711 self.submodules.irq = SoCIRQHandler(
712 n_irqs = irq_n_irqs,
713 reserved_irqs = irq_reserved_irqs
714 )
715
716 self.logger.info(colorer("-"*80, color="bright"))
717 self.logger.info(colorer("Initial SoC:"))
718 self.logger.info(colorer("-"*80, color="bright"))
719 self.logger.info(self.bus)
720 self.logger.info(self.csr)
721 self.logger.info(self.irq)
722 self.logger.info(colorer("-"*80, color="bright"))
723
724 self.add_config("CLOCK_FREQUENCY", int(sys_clk_freq))
725
726 # SoC Helpers ----------------------------------------------------------------------------------
727 def check_if_exists(self, name):
728 if hasattr(self, name):
729 self.logger.error("{} SubModule already {}.".format(
730 colorer(name),
731 colorer("declared", color="red")))
732 raise
733
734 def add_constant(self, name, value=None):
735 name = name.upper()
736 if name in self.constants.keys():
737 self.logger.error("{} Constant already {}.".format(
738 colorer(name),
739 colorer("declared", color="red")))
740 raise
741 self.constants[name] = SoCConstant(value)
742
743 def add_config(self, name, value=None):
744 name = "CONFIG_" + name
745 if isinstance(value, str):
746 self.add_constant(name + "_" + value)
747 else:
748 self.add_constant(name, value)
749
750 # SoC Main Components --------------------------------------------------------------------------
751 def add_controller(self, name="ctrl", **kwargs):
752 self.check_if_exists(name)
753 setattr(self.submodules, name, SoCController(**kwargs))
754 self.csr.add(name, use_loc_if_exists=True)
755
756 def add_ram(self, name, origin, size, contents=[], mode="rw", bus=None):
757 if bus is None:
758 bus = wishbone.Interface(data_width=self.bus.data_width)
759
760 if isinstance(bus, wishbone.Interface):
761 ram = wishbone.SRAM(size, bus=bus, init=contents, read_only=(mode == "r"))
762 elif isinstance(bus, axi.AXILiteInterface):
763 ram = axi.AXILiteSRAM(size, bus=bus, init=contents, read_only=(mode == "r"))
764 else:
765 raise TypeError(bus)
766
767 self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
768 self.check_if_exists(name)
769 self.logger.info("{} RAM {} {} {}.".format(
770 colorer("Wishbone" if isinstance(bus, wishbone.Interface) else "AXILite"),
771 colorer(name),
772 colorer("added", color="green"),
773 self.bus.regions[name]))
774 setattr(self.submodules, name, ram)
775
776 def add_rom(self, name, origin, size, contents=[], bus=None):
777 self.add_ram(name, origin, size, contents, mode="r", bus=bus)
778
779 def add_csr_bridge(self, origin):
780 self.submodules.csr_bridge = wishbone.Wishbone2CSR(
781 bus_csr = csr_bus.Interface(
782 address_width = self.csr.address_width,
783 data_width = self.csr.data_width))
784 csr_size = 2**(self.csr.address_width + 2)
785 csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
786 self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region)
787 self.csr.add_master(name="bridge", master=self.csr_bridge.csr)
788 self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
789 self.add_config("CSR_ALIGNMENT", self.csr.alignment)
790
791 def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None):
792 if name not in cpu.CPUS.keys():
793 self.logger.error("{} CPU {}, supporteds: {}.".format(
794 colorer(name),
795 colorer("not supported", color="red"),
796 colorer(", ".join(cpu.CPUS.keys()))))
797 raise
798 # Add CPU
799 cpu_cls = cls if cls is not None else cpu.CPUS[name]
800 if variant not in cpu_cls.variants:
801 self.logger.error("{} CPU variant {}, supporteds: {}.".format(
802 colorer(variant),
803 colorer("not supported", color="red"),
804 colorer(", ".join(cpu_cls.variants))))
805 raise
806 self.submodules.cpu = cpu_cls(self.platform, variant)
807 # Update SoC with CPU constraints
808 for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
809 self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
810 self.mem_map.update(self.cpu.mem_map) # FIXME
811 # Add Bus Masters/CSR/IRQs
812 if not isinstance(self.cpu, cpu.CPUNone):
813 if reset_address is None:
814 reset_address = self.mem_map["rom"]
815 self.cpu.set_reset_address(reset_address)
816 for n, cpu_bus in enumerate(self.cpu.periph_buses):
817 self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
818 self.csr.add("cpu", use_loc_if_exists=True)
819 if hasattr(self.cpu, "interrupt"):
820 for name, loc in self.cpu.interrupts.items():
821 self.irq.add(name, loc)
822 self.add_config("CPU_HAS_INTERRUPT")
823
824
825 if hasattr(self, "ctrl"):
826 if hasattr(self.ctrl, "reset"):
827 self.comb += self.cpu.reset.eq(self.ctrl.reset)
828 self.add_config("CPU_RESET_ADDR", reset_address)
829 # Add constants
830 self.add_config("CPU_TYPE", str(name))
831 self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
832 self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown"))
833 if hasattr(self.cpu, "nop"):
834 self.add_constant("CONFIG_CPU_NOP", self.cpu.nop)
835
836 def add_timer(self, name="timer0"):
837 self.check_if_exists(name)
838 setattr(self.submodules, name, Timer())
839 self.csr.add(name, use_loc_if_exists=True)
840 if hasattr(self.cpu, "interrupt"):
841 self.irq.add(name, use_loc_if_exists=True)
842
843 # SoC finalization -----------------------------------------------------------------------------
844 def do_finalize(self):
845 self.logger.info(colorer("-"*80, color="bright"))
846 self.logger.info(colorer("Finalized SoC:"))
847 self.logger.info(colorer("-"*80, color="bright"))
848 self.logger.info(self.bus)
849 self.logger.info(self.csr)
850 self.logger.info(self.irq)
851 self.logger.info(colorer("-"*80, color="bright"))
852
853 # SoC Bus Interconnect ---------------------------------------------------------------------
854 if len(self.bus.masters) and len(self.bus.slaves):
855 # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
856 if ((len(self.bus.masters) == 1) and
857 (len(self.bus.slaves) == 1) and
858 (next(iter(self.bus.regions.values())).origin == 0)):
859 self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint(
860 master = next(iter(self.bus.masters.values())),
861 slave = next(iter(self.bus.slaves.values())))
862 # Otherwise, use InterconnectShared.
863 else:
864 self.submodules.bus_interconnect = wishbone.InterconnectShared(
865 masters = self.bus.masters.values(),
866 slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()],
867 register = True,
868 timeout_cycles = self.bus.timeout)
869 if hasattr(self, "ctrl") and self.bus.timeout is not None:
870 if hasattr(self.ctrl, "bus_error"):
871 self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
872 self.bus.logger.info("Interconnect: {} ({} <-> {}).".format(
873 colorer(self.bus_interconnect.__class__.__name__),
874 colorer(len(self.bus.masters)),
875 colorer(len(self.bus.slaves))))
876 self.add_constant("CONFIG_BUS_STANDARD", self.bus.standard.upper())
877 self.add_constant("CONFIG_BUS_DATA_WIDTH", self.bus.data_width)
878 self.add_constant("CONFIG_BUS_ADDRESS_WIDTH", self.bus.address_width)
879
880 # SoC CSR Interconnect ---------------------------------------------------------------------
881 self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
882 address_map = self.csr.address_map,
883 data_width = self.csr.data_width,
884 address_width = self.csr.address_width,
885 alignment = self.csr.alignment,
886 paging = self.csr.paging,
887 soc_bus_data_width = self.bus.data_width)
888 if len(self.csr.masters):
889 self.submodules.csr_interconnect = csr_bus.InterconnectShared(
890 masters = list(self.csr.masters.values()),
891 slaves = self.csr_bankarray.get_buses())
892
893 # Add CSRs regions
894 for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
895 self.csr.add_region(name, SoCCSRRegion(
896 origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
897 busword = self.csr.data_width,
898 obj = csrs))
899
900 # Add Memory regions
901 for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
902 self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
903 origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
904 busword = self.csr.data_width,
905 obj = memory))
906
907 # Sort CSR regions by origin
908 self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
909
910 # Add CSRs / Config items to constants
911 for name, constant in self.csr_bankarray.constants:
912 self.add_constant(name + "_" + constant.name, constant.value.value)
913
914 # SoC CPU Check ----------------------------------------------------------------------------
915 if not isinstance(self.cpu, cpu.CPUNone):
916 if "sram" not in self.bus.regions.keys():
917 self.logger.error("CPU needs {} Region to be {} as Bus or Linker Region.".format(
918 colorer("sram"),
919 colorer("defined", color="red")))
920 self.logger.error(self.bus)
921 raise
922 cpu_reset_address_valid = False
923 for name, container in self.bus.regions.items():
924 if self.bus.check_region_is_in(
925 region = SoCRegion(origin=self.cpu.reset_address, size=self.bus.data_width//8),
926 container = container):
927 cpu_reset_address_valid = True
928 if name == "rom":
929 self.cpu.use_rom = True
930 if not cpu_reset_address_valid:
931 self.logger.error("CPU needs {} to be in a {} Region.".format(
932 colorer("reset address 0x{:08x}".format(self.cpu.reset_address)),
933 colorer("defined", color="red")))
934 self.logger.error(self.bus)
935 raise
936
937 # SoC IRQ Interconnect ---------------------------------------------------------------------
938 if hasattr(self, "cpu"):
939 if hasattr(self.cpu, "interrupt"):
940 for name, loc in sorted(self.irq.locs.items()):
941 if name in self.cpu.interrupts.keys():
942 continue
943 if hasattr(self, name):
944 module = getattr(self, name)
945 if not hasattr(module, "ev"):
946 self.logger.error("EventManager {} in {} SubModule.".format(
947 colorer("not found", color="red"),
948 colorer(name)))
949 raise
950 self.comb += self.cpu.interrupt[loc].eq(module.ev.irq)
951 self.add_constant(name + "_INTERRUPT", loc)
952
953 # SoC build ------------------------------------------------------------------------------------
954 def build(self, *args, **kwargs):
955 self.build_name = kwargs.pop("build_name", self.platform.name)
956 kwargs.update({"build_name": self.build_name})
957 return self.platform.build(self, *args, **kwargs)
958
959 # LiteXSoC -----------------------------------------------------------------------------------------
960
961 class LiteXSoC(SoC):
962 # Add Identifier -------------------------------------------------------------------------------
963 def add_identifier(self, name="identifier", identifier="LiteX SoC", with_build_time=True):
964 self.check_if_exists(name)
965 if with_build_time:
966 identifier += " " + build_time()
967 setattr(self.submodules, name, Identifier(identifier))
968 self.csr.add(name + "_mem", use_loc_if_exists=True)
969
970 # Add UART -------------------------------------------------------------------------------------
971 def add_uart(self, name, baudrate=115200, fifo_depth=16):
972 from litex.soc.cores import uart
973
974 # Stub / Stream
975 if name in ["stub", "stream"]:
976 self.submodules.uart = uart.UART(tx_fifo_depth=0, rx_fifo_depth=0)
977 if name == "stub":
978 self.comb += self.uart.sink.ready.eq(1)
979
980 # UARTBone / Bridge
981 elif name in ["uartbone", "bridge"]:
982 self.add_uartbone(baudrate=baudrate)
983
984 # Crossover
985 elif name in ["crossover"]:
986 self.submodules.uart = uart.UARTCrossover()
987
988 # Model/Sim
989 elif name in ["model", "sim"]:
990 self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
991 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
992 tx_fifo_depth = fifo_depth,
993 rx_fifo_depth = fifo_depth))
994
995 # JTAG Atlantic
996 elif name in ["jtag_atlantic"]:
997 from litex.soc.cores.jtag import JTAGAtlantic
998 self.submodules.uart_phy = JTAGAtlantic()
999 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
1000 tx_fifo_depth = fifo_depth,
1001 rx_fifo_depth = fifo_depth))
1002
1003 # JTAG UART
1004 elif name in ["jtag_uart"]:
1005 from litex.soc.cores.jtag import JTAGPHY
1006 self.submodules.uart_phy = JTAGPHY(device=self.platform.device)
1007 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
1008 tx_fifo_depth = fifo_depth,
1009 rx_fifo_depth = fifo_depth))
1010
1011 # USB ACM (with ValentyUSB core)
1012 elif name in ["usb_acm"]:
1013 import valentyusb.usbcore.io as usbio
1014 import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
1015 usb_pads = self.platform.request("usb")
1016 usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
1017 self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf)
1018
1019 # Classic UART
1020 else:
1021 self.submodules.uart_phy = uart.UARTPHY(
1022 pads = self.platform.request(name),
1023 clk_freq = self.sys_clk_freq,
1024 baudrate = baudrate)
1025 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
1026 tx_fifo_depth = fifo_depth,
1027 rx_fifo_depth = fifo_depth))
1028
1029 self.csr.add("uart_phy", use_loc_if_exists=True)
1030 self.csr.add("uart", use_loc_if_exists=True)
1031 if hasattr(self.cpu, "interrupt"):
1032 self.irq.add("uart", use_loc_if_exists=True)
1033 else:
1034 self.add_constant("UART_POLLING")
1035
1036 # Add UARTbone ---------------------------------------------------------------------------------
1037 def add_uartbone(self, name="serial", baudrate=115200):
1038 from litex.soc.cores import uart
1039 self.submodules.uartbone = uart.UARTBone(
1040 pads = self.platform.request(name),
1041 clk_freq = self.sys_clk_freq,
1042 baudrate = baudrate)
1043 self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
1044
1045 # Add SDRAM ------------------------------------------------------------------------------------
1046 def add_sdram(self, name, phy, module, origin, size=None, with_soc_interconnect=True,
1047 l2_cache_size = 8192,
1048 l2_cache_min_data_width = 128,
1049 l2_cache_reverse = True,
1050 l2_cache_full_memory_we = True,
1051 **kwargs):
1052
1053 # Imports
1054 from litedram.common import LiteDRAMNativePort
1055 from litedram.core import LiteDRAMCore
1056 from litedram.frontend.wishbone import LiteDRAMWishbone2Native
1057 from litedram.frontend.axi import LiteDRAMAXI2Native
1058
1059 # LiteDRAM core
1060 self.submodules.sdram = LiteDRAMCore(
1061 phy = phy,
1062 geom_settings = module.geom_settings,
1063 timing_settings = module.timing_settings,
1064 clk_freq = self.sys_clk_freq,
1065 **kwargs)
1066 self.csr.add("sdram")
1067
1068 # Save SPD data to be able to verify it at runtime
1069 if hasattr(module, "_spd_data"):
1070 # pack the data into words of bus width
1071 bytes_per_word = self.bus.data_width // 8
1072 mem = [0] * ceil(len(module._spd_data) / bytes_per_word)
1073 for i in range(len(mem)):
1074 for offset in range(bytes_per_word):
1075 mem[i] <<= 8
1076 if self.cpu.endianness == "little":
1077 offset = bytes_per_word - 1 - offset
1078 spd_byte = i * bytes_per_word + offset
1079 if spd_byte < len(module._spd_data):
1080 mem[i] |= module._spd_data[spd_byte]
1081 self.add_rom(
1082 name="spd",
1083 origin=self.mem_map.get("spd", None),
1084 size=len(module._spd_data),
1085 contents=mem,
1086 )
1087
1088 if not with_soc_interconnect: return
1089
1090 # Compute/Check SDRAM size
1091 sdram_size = 2**(module.geom_settings.bankbits +
1092 module.geom_settings.rowbits +
1093 module.geom_settings.colbits)*phy.settings.databits//8
1094 if size is not None:
1095 sdram_size = min(sdram_size, size)
1096
1097 # Add SDRAM region
1098 self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
1099
1100 # SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
1101 if len(self.cpu.memory_buses):
1102 # When CPU has at least a direct memory bus, connect them directly to LiteDRAM.
1103 for mem_bus in self.cpu.memory_buses:
1104 # Request a LiteDRAM native port.
1105 port = self.sdram.crossbar.get_port()
1106 port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
1107
1108 # Check if bus is an AXI bus and connect it.
1109 if isinstance(mem_bus, axi.AXIInterface):
1110 # If same data_width, connect it directly.
1111 if port.data_width == mem_bus.data_width:
1112 self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
1113 self.submodules += LiteDRAMAXI2Native(
1114 axi = self.cpu.mem_axi,
1115 port = port,
1116 base_address = self.bus.regions["main_ram"].origin)
1117 # If different data_width, do the adaptation and connect it via Wishbone.
1118 else:
1119 self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
1120 port.data_width,
1121 self.cpu.mem_axi.data_width))
1122 # FIXME: replace WB data-width converter with native AXI converter!!!
1123 mem_wb = wishbone.Interface(
1124 data_width = self.cpu.mem_axi.data_width,
1125 adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8))
1126 # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
1127 mem_a2w = ResetInserter()(axi.AXI2Wishbone(
1128 axi = self.cpu.mem_axi,
1129 wishbone = mem_wb,
1130 base_address = 0))
1131 self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
1132 self.submodules += mem_a2w
1133 litedram_wb = wishbone.Interface(port.data_width)
1134 self.submodules += LiteDRAMWishbone2Native(
1135 wishbone = litedram_wb,
1136 port = port,
1137 base_address = origin)
1138 self.submodules += wishbone.Converter(mem_wb, litedram_wb)
1139 # Check if bus is a Native bus and connect it.
1140 if isinstance(mem_bus, LiteDRAMNativePort):
1141 # If same data_width, connect it directly.
1142 if port.data_width == mem_bus.data_width:
1143 self.comb += mem_bus.cmd.connect(port.cmd)
1144 self.comb += mem_bus.wdata.connect(port.wdata)
1145 self.comb += port.rdata.connect(mem_bus.rdata)
1146 # Else raise Error.
1147 else:
1148 raise NotImplementedError
1149 else:
1150 # When CPU has no direct memory interface, create a Wishbone Slave interface to LiteDRAM.
1151
1152 # Request a LiteDRAM native port.
1153 port = self.sdram.crossbar.get_port()
1154 port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
1155
1156 # Create Wishbone Slave.
1157 wb_sdram = wishbone.Interface()
1158 self.bus.add_slave("main_ram", wb_sdram)
1159
1160 # L2 Cache
1161 if l2_cache_size != 0:
1162 # Insert L2 cache inbetween Wishbone bus and LiteDRAM
1163 l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
1164 l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
1165 l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
1166 l2_cache = wishbone.Cache(
1167 cachesize = l2_cache_size//4,
1168 master = wb_sdram,
1169 slave = wishbone.Interface(l2_cache_data_width),
1170 reverse = l2_cache_reverse)
1171 if l2_cache_full_memory_we:
1172 l2_cache = FullMemoryWE()(l2_cache)
1173 self.submodules.l2_cache = l2_cache
1174 litedram_wb = self.l2_cache.slave
1175 else:
1176 litedram_wb = wishbone.Interface(port.data_width)
1177 self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
1178 self.add_config("L2_SIZE", l2_cache_size)
1179
1180 # Wishbone Slave <--> LiteDRAM bridge
1181 self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
1182 base_address = self.bus.regions["main_ram"].origin)
1183
1184 # Add Ethernet ---------------------------------------------------------------------------------
1185 def add_ethernet(self, name="ethmac", phy=None):
1186 # Imports
1187 from liteeth.mac import LiteEthMAC
1188 # MAC
1189 ethmac = LiteEthMAC(
1190 phy = phy,
1191 dw = 32,
1192 interface = "wishbone",
1193 endianness = self.cpu.endianness)
1194 setattr(self.submodules, name, ethmac)
1195 ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False)
1196 self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
1197 self.add_csr(name)
1198 self.add_interrupt(name)
1199 # Timing constraints
1200 if hasattr(phy, "crg"):
1201 eth_rx_clk = phy.crg.cd_eth_rx.clk
1202 eth_tx_clk = phy.crg.cd_eth_tx.clk
1203 else:
1204 eth_rx_clk = phy.cd_eth_rx.clk
1205 eth_tx_clk = phy.cd_eth_tx.clk
1206 self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
1207 self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
1208 self.platform.add_false_path_constraints(
1209 self.crg.cd_sys.clk,
1210 eth_rx_clk,
1211 eth_tx_clk)
1212
1213 # Add Etherbone --------------------------------------------------------------------------------
1214 def add_etherbone(self, name="etherbone", phy=None,
1215 mac_address = 0x10e2d5000000,
1216 ip_address = "192.168.1.50",
1217 udp_port = 1234):
1218 # Imports
1219 from liteeth.core import LiteEthUDPIPCore
1220 from liteeth.frontend.etherbone import LiteEthEtherbone
1221 # Core
1222 ethcore = LiteEthUDPIPCore(
1223 phy = self.ethphy,
1224 mac_address = mac_address,
1225 ip_address = ip_address,
1226 clk_freq = self.clk_freq)
1227 ethcore = ClockDomainsRenamer("eth_tx")(ethcore)
1228 self.submodules += ethcore
1229
1230 # Clock domain renaming
1231 self.clock_domains.cd_etherbone = ClockDomain("etherbone")
1232 self.comb += self.cd_etherbone.clk.eq(ClockSignal("sys"))
1233 self.comb += self.cd_etherbone.rst.eq(ResetSignal("sys"))
1234
1235 # Etherbone
1236 etherbone = LiteEthEtherbone(ethcore.udp, udp_port, cd="etherbone")
1237 setattr(self.submodules, name, etherbone)
1238 self.add_wb_master(etherbone.wishbone.bus)
1239 # Timing constraints
1240 if hasattr(phy, "crg"):
1241 eth_rx_clk = phy.crg.cd_eth_rx.clk
1242 eth_tx_clk = phy.crg.cd_eth_tx.clk
1243 else:
1244 eth_rx_clk = phy.cd_eth_rx.clk
1245 eth_tx_clk = phy.cd_eth_tx.clk
1246 self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
1247 self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
1248 self.platform.add_false_path_constraints(
1249 self.crg.cd_sys.clk,
1250 eth_rx_clk,
1251 eth_tx_clk)
1252
1253 # Add SPI Flash --------------------------------------------------------------------------------
1254 def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):
1255 assert dummy_cycles is not None # FIXME: Get dummy_cycles from SPI Flash
1256 assert mode in ["1x", "4x"]
1257 if clk_freq is None: clk_freq = self.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash
1258 spiflash = SpiFlash(
1259 pads = self.platform.request(name if mode == "1x" else name + mode),
1260 dummy = dummy_cycles,
1261 div = ceil(self.clk_freq/clk_freq),
1262 with_bitbang = True,
1263 endianness = self.cpu.endianness)
1264 spiflash.add_clk_primitive(self.platform.device)
1265 setattr(self.submodules, name, spiflash)
1266 self.add_memory_region(name, self.mem_map[name], 0x1000000) # FIXME: Get size from SPI Flash
1267 self.add_wb_slave(self.mem_map[name], spiflash.bus)
1268 self.add_csr(name)
1269
1270 # Add SPI SDCard -------------------------------------------------------------------------------
1271 def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3):
1272 pads = self.platform.request(name)
1273 if hasattr(pads, "rst"):
1274 self.comb += pads.rst.eq(0)
1275 spisdcard = SPIMaster(pads, 32, self.sys_clk_freq, spi_clk_freq, mode="aligned")
1276 spisdcard.add_clk_divider()
1277 setattr(self.submodules, name, spisdcard)
1278 self.add_csr(name)
1279
1280 # Add SDCard -----------------------------------------------------------------------------------
1281 def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False):
1282 assert mode in ["read", "write", "read+write"]
1283 # Imports
1284 from litesdcard.emulator import SDEmulator
1285 from litesdcard.phy import SDPHY
1286 from litesdcard.core import SDCore
1287 from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
1288
1289 # Emulator / Pads
1290 if use_emulator:
1291 sdemulator = SDEmulator(self.platform)
1292 self.submodules += sdemulator
1293 sdcard_pads = sdemulator.pads
1294 else:
1295 sdcard_pads = self.platform.request(name)
1296
1297 # Core
1298 self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq)
1299 self.submodules.sdcore = SDCore(self.sdphy)
1300 self.add_csr("sdphy")
1301 self.add_csr("sdcore")
1302
1303 # Block2Mem DMA
1304 if "read" in mode:
1305 bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
1306 self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
1307 self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
1308 self.bus.add_master("sdblock2mem", master=bus)
1309 self.add_csr("sdblock2mem")
1310
1311 # Mem2Block DMA
1312 if "write" in mode:
1313 bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
1314 self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
1315 self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
1316 self.bus.add_master("sdmem2block", master=bus)
1317 self.add_csr("sdmem2block")